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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / niu / rxc_sat / vera / monitor / control_fifo_mon.vr
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: control_fifo_mon.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36
37#include "control_fifo_mon.vri"
38
39class control_fifo_mon{
40
41 integer RXC_ACK_MAX_DELAY = 1;
42 integer my_port;
43
44
45 local bit randomize_req_drv = 1'b1; // Enabled by default ?
46 local bit [15:0] start_delay = 16'h0; // Default is NO delay
47
48 task new(integer iport);
49
50 task drive_cfifo_port (dmc_zcp_drv_port port_bind);
51// task show_dfifo (dmc_zcp_drv_port port_bind);
52
53}
54
55task control_fifo_mon::new( integer iport ){
56
57 static bit[7:0] ports_used = 0;
58
59
60 if(iport > 3 ) {
61 error("ERROR: FAKE DMC_RXC I/F module: Port %0d is invalid.\n", iport);
62 return;
63 }
64
65 // Check if port already in use
66 if(ports_used[iport] == 1) {
67 error("\nERROR: FAKE DMC_RXC I/F module is already attached to port %0d"
68 ,iport);
69 my_port = -1;
70 terminate;
71 }
72 else my_port = iport;
73
74
75 fork
76 case (my_port) {
77
78 0: begin
79 drive_cfifo_port (dmc_zcp_drv0);
80 end
81 1: begin
82 drive_cfifo_port (dmc_zcp_drv1);
83 end
84 }
85
86 join none
87}
88
89
90task control_fifo_mon::drive_cfifo_port(dmc_zcp_drv_port port_bind){
91
92integer num_of_cycle = 0;
93
94 while (1) {
95 @(posedge port_bind.$clk);
96
97 if ((port_bind.$control_fifo_ack == 1'b1) && (num_of_cycle == 0)) {
98 printf("%0d: First Cycle Control fifo = %h\n",
99 {get_time(HI), get_time(LO)}, port_bind.$control_fifo_data[129:0]);
100 printf("Usr Data[39:16] = %0h\n", port_bind.$control_fifo_data[23:0]);
101 printf("Hash Val1 = %0h\n", port_bind.$control_fifo_data[43:24]);
102 printf("Hash Val2 = %0h\n", port_bind.$control_fifo_data[63:48]);
103 printf("Zflowid = %0h\n", port_bind.$control_fifo_data[75:64]);
104 printf("SE-bit = %0h\n", port_bind.$control_fifo_data[76]);
105 printf("Drop-pkt = %0h\n", port_bind.$control_fifo_data[77]);
106 printf("FFLP-hw-err = %0h\n", port_bind.$control_fifo_data[78]);
107 printf("MAC-promiscuous = %0h\n", port_bind.$control_fifo_data[79]);
108 printf("tt-err = %0h\n", port_bind.$control_fifo_data[86]);
109 printf("tt-succeed = %0h\n", port_bind.$control_fifo_data[87]);
110 printf("Hash-sub-index = %0h\n", port_bind.$control_fifo_data[90:88]);
111 printf("HZFVLD = %0h\n", port_bind.$control_fifo_data[91]);
112 printf("Exact = %0h\n", port_bind.$control_fifo_data[92]);
113 printf("Hash-hit = %0h\n", port_bind.$control_fifo_data[93]);
114 printf("Table-RDC[1:0] = %0h\n", port_bind.$control_fifo_data[95:94]);
115 printf("TCAM-M-index = %0h\n", port_bind.$control_fifo_data[103:96]);
116 printf("Table-RDC[4:2] = %0h\n", port_bind.$control_fifo_data[106:104]);
117 printf("Default-RDC = %0h\n", port_bind.$control_fifo_data[111:107]);
118 printf("TZFVLD = %0h\n", port_bind.$control_fifo_data[112]);
119 printf("TRES = %0h\n", port_bind.$control_fifo_data[114:113]);
120 printf("TCAM-Hit = %0h\n", port_bind.$control_fifo_data[115]);
121 printf("Bad-IP = %0h\n", port_bind.$control_fifo_data[116]);
122 printf("No-port = %0h\n", port_bind.$control_fifo_data[117]);
123 printf("LLC-SNAP = %0h\n", port_bind.$control_fifo_data[118]);
124 printf("VLAN = %0h\n", port_bind.$control_fifo_data[119]);
125 printf("CLASS = %0h\n", port_bind.$control_fifo_data[124:120]);
126 printf("MAC-check = %0h\n", port_bind.$control_fifo_data[125]);
127 printf("MAC-PORT = %0h\n", port_bind.$control_fifo_data[127:126]);
128 printf("SOP = %0h\n", port_bind.$control_fifo_data[128]);
129 printf("EOP = %0h\n", port_bind.$control_fifo_data[129]);
130
131 num_of_cycle = num_of_cycle + 1;
132
133 }
134
135 else {
136 if (port_bind.$control_fifo_ack == 1'b1) {
137 printf("%0d: Second Cycle Control fifo = %h\n",
138 {get_time(HI), get_time(LO)}, port_bind.$control_fifo_data[129:0]);
139 printf("TCP-sequence = %0h\n", port_bind.$control_fifo_data[71:40]);
140 printf("TCP-hdr-len = %0h\n", port_bind.$control_fifo_data[75:72]);
141 printf("Ipv4-hdr-len = %0h\n", port_bind.$control_fifo_data[79:76]);
142 printf("L3-pkt-len = %0h\n", port_bind.$control_fifo_data[95:80]);
143 printf("zc-RDC = %0h\n", port_bind.$control_fifo_data[100:96]);
144 printf("DMAW-type = %0h\n", port_bind.$control_fifo_data[102:101]);
145 printf("ULP-type = %0h\n", port_bind.$control_fifo_data[105:104]);
146 printf("Pkt-ID = %0h\n", port_bind.$control_fifo_data[109:106]);
147 printf("IP-ver = %0h\n", port_bind.$control_fifo_data[110]);
148 printf("Usr Data[15:0] = %0h\n", port_bind.$control_fifo_data[127:112]);
149 printf("SOP = %0h\n", port_bind.$control_fifo_data[128]);
150 printf("EOP = %0h\n", port_bind.$control_fifo_data[129]);
151
152 num_of_cycle = 0;
153 }
154 }
155
156
157 } // end of while
158
159} // end of task drive_cfifo_port
160
161
162//task control_fifo_mon::show_dfifo(dmc_zcp_drv_port port_bind){
163/*
164task control_fifo_mon::show_dfifo0(){
165 printf ( "IP cksum = %0h", zcp_rdmc_port.$control_fifo_data[15:0],
166 "L2 option = %0h", zcp_rdmc_port.$control_fifo_data[41:40],
167 "L3 version = %0h", zcp_rdmc_port.$control_fifo_data[43:42],
168 "L4 protocol = %0h", zcp_rdmc_port.$control_fifo_data[49:48],
169 "Pkt Length = %0h", zcp_rdmc_port.$control_fifo_data[101:88]);
170}
171*/
172
173
Full OpenSPARC design & verification tarball including full HDL.