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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / niu / test_utils / vera / niu_macintr_utils.vr
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_macintr_utils.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36#include "niu_int_dev.vrh"
37#include "niu_int_mgr.vrh"
38#include "mbox_class.vrh"
39#include "get_mbox_id.vrh"
40#include "neptune_memory_map.vri"
41#include "mac_defines.vri"
42#include "pio_driver.vrh"
43#include "mac_pio_class.vrh"
44#include "xmac_util.vrh"
45#include "bmac_util.vrh"
46#include "mac_shadow_class.vrh"
47#include "xmac_shadow_class.vrh"
48#include "vega_shadow_class.vrh"
49#include "cMesg.vrh"
50#include "mac_defines.vri"
51
52extern Mesg be_msg;
53extern niu_gen_pio gen_pio_drv;
54extern CNiuIntrMgr NiuIntrMgr;
55extern pio_drv pio_driver_class;
56extern mac_pio_cl mac_pio_class;
57extern shadow_cl shadow_class;
58extern mac_util_class mac_util;
59extern bmac_util_class bmac_util;
60extern hdl_task deassert_mdint(bit[2:0] id);
61extern hdl_task check_mdint_status(bit[2:0] id, var bit status);
62
63#define PCS_INT_MASK 6
64#define CSR_LANE_ALIGN 12
65#define CSR_LANE3_SYNC 3
66#define CSR_LANE2_SYNC 2
67#define CSR_LANE1_SYNC 1
68#define CSR_LANE0_SYNC 0
69#define CSR_FAULT 7
70#define CSR_RX_LINK_UP 2
71#define CSR_TX_FAULT 11
72#define CSR_RX_FAULT 10
73
74class CNiuIntrDevMAC extends CNiuIntrDev {
75 integer mac_id;
76 integer isr_count=0, lf_intr_cnt=0, rf_intr_cnt=0;
77 integer underrun_cnt=0, pkts_txmt_cnt=0, tx_xfer_err_cnt=0;
78 integer txfrm_cnt_int=0, txbyte_cnt_int=0;
79 event clear_crc_cnt, clear_broadcast_cnt, clear_frag_cnt, clear_hist1_cnt, clear_hist2_cnt, clear_hist3_cnt, clear_hist4_cnt, clear_hist5_cnt, clear_hist6_cnt, clear_hist7_cnt, clear_mpsz_cnt, clear_multicast_cnt, clear_byte_cnt, clear_link_fault_cnt;
80event clear_frame_cnt;
81 bit byte_cnt_int=0;
82 bit TxMacInNotPauseSt=0, TxMacInPauseSt=0, RxMacRcvPause=0; // FC
83 bit mdint_int=0;
84
85 task new(integer port_id, integer dev_id) {
86 super.new(dev_id);
87 mac_id = port_id;
88 }
89 task set_masks();
90 task set_rx_mask(bit[31:0] val);
91 task set_brx_mask(bit[31:0] val);
92 function integer isr( (bit[1:0] ldf_flags=0) );
93 task check_xpcs_int();
94 task check_pcs_int();
95 task check_XmacTX_int();
96 task check_XmacRX_int();
97 task check_XmacFC_int();
98 task check_BmacTX_int();
99 task check_BmacRX_int();
100 task check_BmacFC_int();
101}
102
103function integer CNiuIntrDevMAC::isr( (bit[1:0] ldf_flags=0) ) {
104 bit[31:0] rd_data, rd_status, rd_mask;
105 bit[39:0] base_addr;
106
107 isr_done = 0;
108 SetPendingFlag();
109
110 printf("Start macISR ISR id=%0d mac_id=%0d LDF_flags=%0d time=%0d\n", super.dev_id, mac_id, ldf_flags, get_time(LO));
111 if(ldf_flags!=2) printf("ERROR ldf_flags is not set to the correct value of 2\n");
112
113 if(mac_id==0 || mac_id==1) {
114 check_XmacRX_int();
115 check_XmacTX_int();
116 check_XmacFC_int();
117 //check_xpcs_int(); not tested yet
118 //check_pcs_int(); not tested yet
119 }
120 if(mac_id==2 || mac_id==3) {
121 check_BmacRX_int();
122 check_BmacTX_int();
123 check_BmacFC_int();
124 }
125
126 base_addr = mac_util.get_mac_reg_base(mac_id);
127 //mac_pio_class.xmac_pio_rd(base_addr + XMAC_C_S_MSK, rd_mask, 1'b0);
128 mac_pio_class.xmac_pio_rd(base_addr + XMAC_CTRL_STAT, rd_status, 1'b0);
129 printf("macISR CTRL id=%0d status=0x%0x\n", super.dev_id, rd_status);
130
131 ClrPendingFlag();
132 isr_done=1;
133}
134
135task CNiuIntrDevMAC::check_XmacFC_int() {
136 bit[31:0] rd_data, rd_status, rd_mask, active_int;
137 bit[39:0] base_addr;
138
139 base_addr = mac_util.get_mac_reg_base(mac_id);
140 mac_pio_class.xmac_pio_rd(base_addr + XMAC_C_S_MSK, rd_mask, 1'b0);
141 mac_pio_class.xmac_pio_rd(base_addr + XMAC_CTRL_STAT, rd_status, 1'b0);
142 active_int=rd_status & ~rd_mask;
143
144 printf("macISR xmac FC id=%0d status=0x%0x\n", super.dev_id, rd_status);
145 if(active_int[0]) {
146 printf("macISR rxxmac FC mac_id=%0d RxMacRcvPause Interrupt RxMacRcvPauseTime=%0h\n", mac_id, rd_status[31:16]);
147 RxMacRcvPause=1;
148 }
149 if(active_int[1]) {
150 printf("macISR rxxmac FC mac_id=%0d TxMacInPauseSt Interrupt\n", mac_id);
151 TxMacInPauseSt=1;
152 }
153 if(active_int[2]) {
154 printf("macISR rxxmac FC mac_id=%0d TxMacInNotPauseSt Interrupt\n", mac_id);
155 TxMacInNotPauseSt=1;
156 }
157}
158
159task CNiuIntrDevMAC::check_BmacFC_int() {
160 bit[31:0] rd_data, rd_status, rd_mask, active_int;
161 bit[39:0] base_addr;
162
163 base_addr = mac_util.get_mac_reg_base(mac_id);
164 mac_pio_class.xmac_pio_rd(base_addr + BMAC_C_S_MSK, rd_mask, 1'b0);
165 mac_pio_class.xmac_pio_rd(base_addr + BMAC_CTRL_STAT, rd_status, 1'b0);
166 active_int=rd_status & ~rd_mask;
167
168 printf("macISR xmac FC id=%0d status=0x%0x\n", super.dev_id, rd_status);
169 if(active_int[2]) {
170 printf("macISR rxbmac FC mac_id=%0d TxMacInNotPauseSt Interrupt\n", mac_id);
171 //Not_Paused_State=1;
172 TxMacInNotPauseSt=1;
173 }
174 if(active_int[1]) {
175 printf("macISR rxbmac FC mac_id=%0d TxMacInPauseSt Interrupt\n", mac_id);
176 //Paused_State=1;
177 TxMacInPauseSt=1;
178 }
179 if(active_int[0]) {
180 printf("macISR rxbmac FC mac_id=%0d RxMacRcvPause=1 Interrupt Pause_Time_Rcvd=%0h\n", mac_id, rd_status[31:16]);
181 //Pause_Received=1;
182 RxMacRcvPause=1;
183 }
184}
185
186task CNiuIntrDevMAC::check_BmacTX_int() {
187 bit[31:0] rd_data, rd_status, rd_mask, active_int;
188 bit[39:0] base_addr;
189
190 base_addr = mac_util.get_mac_reg_base(mac_id);
191 mac_pio_class.xmac_pio_rd(base_addr + BTxMAC_STATUS, rd_status, 1'b0);
192 mac_pio_class.xmac_pio_rd(base_addr + BTxMAC_STAT_MSK, rd_mask, 1'b0);
193 active_int=rd_status & ~rd_mask;
194
195 printf("macISR bmac TX id=%0d status=0x%0x mask=0x%0x active_int=0x%0x\n", super.dev_id, rd_status, rd_mask, active_int);
196 if(active_int[11]) {
197 //printf("macISR TX mac_id=%0d byte_cnt Interrupt\n", mac_id);
198 printf("macISR TX mac_id=%0d byte_cnt Interrupt (set mask)\n", mac_id);
199 rd_mask[11]=1;
200 mac_pio_class.xmac_pio_wr(base_addr + BTxMAC_STAT_MSK, rd_mask);
201 mac_pio_class.xmac_pio_rd(base_addr + TxMAC_FRM_CNT, rd_data, 1'b0);
202 txfrm_cnt_int++;
203 if(rd_data!=='hffffffff) printf("ERROR CNiuIntrDevMAC Interrupt TxMAC_FRM_CNT=0x%0x\n", rd_data);
204 //while(rd_data=='hffffffff) mac_pio_class.xmac_pio_rd(base_addr + TxMAC_FRM_CNT, rd_data, 1'b0);
205 }
206 if(active_int[10]) {
207 //printf("macISR TX mac_id=%0d byte_cnt Interrupt\n", mac_id);
208 printf("macISR TX mac_id=%0d byte_cnt Interrupt (set mask)\n", mac_id);
209 rd_mask[10]=1;
210 mac_pio_class.xmac_pio_wr(base_addr + BTxMAC_STAT_MSK, rd_mask);
211 mac_pio_class.xmac_pio_rd(base_addr + TxMAC_BYTE_CNT, rd_data, 1'b0);
212 txbyte_cnt_int++;
213 if(rd_data!=='hffffffff) printf("ERROR CNiuIntrDevMAC Interrupt TxMAC_BYTE_CNT=0x%0x\n", rd_data);
214 while(rd_data=='hffffffff) mac_pio_class.xmac_pio_rd(base_addr + TxMAC_BYTE_CNT, rd_data, 1'b0);
215 }
216 if(active_int[1]) {
217 printf("CNiuIntrDevMAC TX mac_id=%0d recived underrun_interrupt\n",mac_id);
218 underrun_cnt++;
219 }
220 if(active_int[0]) {
221 printf("CNiuIntrDevMAC TX mac_id=%0d recived Pkts_xmtd_interrupt\n",mac_id);
222 pkts_txmt_cnt++;
223 }
224}
225
226task CNiuIntrDevMAC::check_BmacRX_int() {
227 bit[31:0] rd_data, rd_status, rd_mask, active_int;
228 bit[39:0] base_addr;
229
230 base_addr = mac_util.get_mac_reg_base(mac_id);
231 mac_pio_class.xmac_pio_rd(base_addr + BRxMAC_STAT_MSK, rd_mask, 1'b0);
232 mac_pio_class.xmac_pio_rd(base_addr + BRxMAC_STATUS, rd_status, 1'b0);
233 active_int=rd_status & ~rd_mask;
234
235 printf("macISR bmac RX id=%0d status=0x%0x mask=0x%0x active_int=0x%0x\n", super.dev_id, rd_status, rd_mask, active_int);
236 if(active_int[7]) {
237 printf("macISR bmac RX mac_id=%0d byte_cnt Interrupt\n", mac_id);
238 //mac_pio_class.xmac_pio_rd(base_addr + BT, rd_data, 1'b0);
239 trigger(ONE_SHOT, clear_byte_cnt);
240 byte_cnt_int=1;
241 //if(rd_data!=='hffff) printf("ERROR macISR Interrupt BT=0x%0x\n", rd_data);
242 }
243 if(active_int[2]) {
244 printf("macISR bmac RX mac_id=%0d frame_cnt Interrupt\n", mac_id);
245 mac_pio_class.xmac_pio_rd(base_addr + BRxMAC_FRM_CNT, rd_data, 1'b0);
246 trigger(ONE_SHOT, clear_frame_cnt);
247 // sims show that bmac frm counter = 0 at interrupt
248 //if(rd_data!=='hffff) printf("ERROR macISR Interrupt BRxMAC_FRM_CNT=0x%0x\n", rd_data);
249 printf("macISR Interrupt BRxMAC_FRM_CNT=0x%0x\n", rd_data);
250 }
251 if(active_int[5]) {
252 printf("macISR bmac RX mac_id=%0d len_cnt Interrupt\n", mac_id);
253 mac_pio_class.xmac_pio_rd(base_addr + MAC_LEN_ER_CNT, rd_data, 1'b0);
254 trigger(ONE_SHOT, clear_mpsz_cnt);
255 printf("macISR Interrupt bMAC_LEN_ER_CNT=0x%0x\n", rd_data);
256 // sims show that bmac len counter = 0 at interrupt
257 //if(rd_data!=='hffff) printf("ERROR macISR Interrupt bMAC_LEN_ER_CNT=0x%0x\n", rd_data);
258 printf("macISR Interrupt bMAC_LEN_ER_CNT=0x%0x\n", rd_data);
259 }
260 if(active_int[4]) {
261 printf("macISR bmac RX mac_id=%0d crc_cnt Interrupt\n", mac_id);
262 mac_pio_class.xmac_pio_rd(base_addr + BMAC_CRC_ER_CNT, rd_data, 1'b0);
263 trigger(ONE_SHOT, clear_crc_cnt);
264 // sims show that bmac crc counter = 0 at interrupt
265 //if(rd_data!=='hffff) printf("ERROR macISR Interrupt BMAC_CRC_ER_CNT=0x%0x\n", rd_data);
266 printf("macISR Interrupt BMAC_CRC_ER_CNT=0x%0x\n", rd_data);
267 }
268}
269
270task CNiuIntrDevMAC::check_xpcs_int() {
271 bit[31:0] rd_data, rd_status, rd_mask;
272
273 mac_pio_class.xmac_pio_rd(XPCS0_BASE + XPCS_STATUS, rd_status, 1'b0);
274 printf("macISR XPCS0 id=%0d status=0x%0x\n", super.dev_id, rd_status);
275 //printf("macISR XPCS0 id=%0d status CSR_LANE_ALIGN=%b\n", super.dev_id, rd_status[CSR_LANE_ALIGN]);
276 //printf("macISR XPCS0 id=%0d status CSR_LANE3_SYNC=%b\n", super.dev_id, rd_status[CSR_LANE3_SYNC]);
277 //printf("macISR XPCS0 id=%0d status CSR_LANE2_SYNC=%b\n", super.dev_id, rd_status[CSR_LANE2_SYNC]);
278 //printf("macISR XPCS0 id=%0d status CSR_LANE1_SYNC=%b\n", super.dev_id, rd_status[CSR_LANE1_SYNC]);
279 //printf("macISR XPCS0 id=%0d status CSR_LANE0_SYNC=%b\n", super.dev_id, rd_status[CSR_LANE0_SYNC]);
280
281 mac_pio_class.xmac_pio_rd(XPCS0_BASE + XPCS_STATUS1, rd_status, 1'b0);
282 printf("macISR XPCS0 id=%0d status1=0x%0x\n", super.dev_id, rd_status);
283 //printf("macISR XPCS0 id=%0d status1 CSR_FAULT=%b\n", super.dev_id, rd_status[CSR_FAULT]);
284 //printf("macISR XPCS0 id=%0d status1 CSR_RX_LINK_UP=%b\n", super.dev_id, rd_status[CSR_RX_LINK_UP]);
285
286 mac_pio_class.xmac_pio_rd(XPCS0_BASE + XPCS_STATUS2, rd_status, 1'b0);
287 printf("macISR XPCS0 id=%0d status2=0x%0x\n", super.dev_id, rd_status);
288 //printf("macISR XPCS0 id=%0d status2 CSR_TX_FAULT=%b\n", super.dev_id, rd_status[CSR_TX_FAULT]);
289 //printf("macISR XPCS0 id=%0d status2 CSR_RX_FAULT=%b\n", super.dev_id, rd_status[CSR_RX_FAULT]);
290 if(rd_status[CSR_RX_FAULT]) {
291 printf(" macISR XPCS0 CSR_RX_FAULT Interrupt\n");
292 mac_pio_class.xmac_pio_rd(XPCS0_BASE + XPCS_STATUS1, rd_status, 1'b0);
293 printf(" macISR XPCS0 id=%0d status1 CSR_FAULT=%b\n", super.dev_id, rd_status[CSR_FAULT]);
294 mac_pio_class.xmac_pio_rd(XPCS0_BASE + XPCS_STATUS2, rd_status, 1'b0);
295 printf(" macISR XPCS0 id=%0d status2 CSR_RX_FAULT=%b\n", super.dev_id, rd_status[CSR_RX_FAULT]);
296 }
297 if(rd_status[CSR_TX_FAULT]) {
298 printf(" macISR XPCS0 CSR_TX_FAULT Interrupt\n");
299 }
300 mac_pio_class.xmac_pio_rd(XPCS1_BASE + XPCS_STATUS, rd_status, 1'b0);
301 printf("macISR XPCS1 id=%0d status=0x%0x\n", super.dev_id, rd_status);
302 //printf("macISR XPCS1 id=%0d status CSR_LANE_ALIGN=%b\n", super.dev_id, rd_status[CSR_LANE_ALIGN]);
303 //printf("macISR XPCS1 id=%0d status CSR_LANE3_SYNC=%b\n", super.dev_id, rd_status[CSR_LANE3_SYNC]);
304 //printf("macISR XPCS1 id=%0d status CSR_LANE2_SYNC=%b\n", super.dev_id, rd_status[CSR_LANE2_SYNC]);
305 //printf("macISR XPCS1 id=%0d status CSR_LANE1_SYNC=%b\n", super.dev_id, rd_status[CSR_LANE1_SYNC]);
306 //printf("macISR XPCS1 id=%0d status CSR_LANE0_SYNC=%b\n", super.dev_id, rd_status[CSR_LANE0_SYNC]);
307
308 mac_pio_class.xmac_pio_rd(XPCS1_BASE + XPCS_STATUS1, rd_status, 1'b0);
309 printf("macISR XPCS1 id=%0d status1=0x%0x\n", super.dev_id, rd_status);
310 //printf("macISR XPCS1 id=%0d status1 CSR_FAULT=%b\n", super.dev_id, rd_status[CSR_FAULT]);
311 //printf("macISR XPCS1 id=%0d status1 CSR_RX_LINK_UP=%b\n", super.dev_id, rd_status[CSR_RX_LINK_UP]);
312
313 mac_pio_class.xmac_pio_rd(XPCS1_BASE + XPCS_STATUS2, rd_status, 1'b0);
314 printf("macISR XPCS1 id=%0d status2=0x%0x\n", super.dev_id, rd_status);
315 //printf("macISR XPCS1 id=%0d status2 CSR_TX_FAULT=%b\n", super.dev_id, rd_status[CSR_TX_FAULT]);
316 //printf("macISR XPCS1 id=%0d status2 CSR_RX_FAULT=%b\n", super.dev_id, rd_status[CSR_RX_FAULT]);
317 if(rd_status[CSR_RX_FAULT]) {
318 printf(" macISR XPCS1 CSR_RX_FAULT Interrupt\n");
319 mac_pio_class.xmac_pio_rd(XPCS1_BASE + XPCS_STATUS1, rd_status, 1'b0);
320 printf(" macISR XPCS1 id=%0d status1 CSR_FAULT=%b\n", super.dev_id, rd_status[CSR_FAULT]);
321 mac_pio_class.xmac_pio_rd(XPCS1_BASE + XPCS_STATUS2, rd_status, 1'b0);
322 printf(" macISR XPCS1 id=%0d status2 CSR_RX_FAULT=%b\n", super.dev_id, rd_status[CSR_RX_FAULT]);
323 }
324 if(rd_status[CSR_TX_FAULT]) {
325 printf(" macISR XPCS1 CSR_TX_FAULT Interrupt\n");
326 }
327}
328
329task CNiuIntrDevMAC::check_pcs_int() {
330 bit[31:0] rd_data, rd_status, rd_mask;
331
332 mac_pio_class.xmac_pio_rd(PCS0_BASE + PCS_INTERRUPT_STATUS, rd_status, 1'b0);
333 printf("macISR PCS0 id=%0d status=0x%0x\n", super.dev_id, rd_status);
334 if(rd_status[2]) {
335 printf("macISR PCS0 link down Interrupt\n");
336 }
337 mac_pio_class.xmac_pio_rd(PCS1_BASE + PCS_INTERRUPT_STATUS, rd_status, 1'b0);
338 printf("macISR PCS1 id=%0d status=0x%0x\n", super.dev_id, rd_status);
339 if(rd_status[2]) {
340 printf("macISR PCS1 link down Interrupt\n");
341 }
342}
343
344task CNiuIntrDevMAC::check_XmacTX_int() {
345 bit[31:0] rd_data, rd_status, rd_mask, active_int;
346 bit[39:0] base_addr;
347
348 base_addr = mac_util.get_mac_reg_base(mac_id);
349 mac_pio_class.xmac_pio_rd(base_addr + XTxMAC_STAT_MSK, rd_mask, 1'b0);
350 mac_pio_class.xmac_pio_rd(base_addr + XTxMAC_STATUS, rd_status, 1'b0);
351 active_int=rd_status & ~rd_mask;
352
353 printf("macISR TX id=%0d status=0x%0x mask=0x%0x active_int=0x%0x\n", super.dev_id, rd_status, rd_mask, active_int);
354 if(active_int[11]) {
355 //printf("macISR TX mac_id=%0d frame_cnt Interrupt\n", mac_id);
356 printf("macISR TX mac_id=%0d frame_cnt Interrupt (set mask)\n", mac_id);
357 rd_mask[11]=1;
358 mac_pio_class.xmac_pio_wr(base_addr + XTxMAC_STAT_MSK, rd_mask);
359 mac_pio_class.xmac_pio_rd(base_addr + TxMAC_FRM_CNT, rd_data, 1'b0);
360 txfrm_cnt_int++;
361 if(rd_data!=='hffffffff) printf("ERROR macISR Interrupt TxMAC_FRM_CNT=0x%0x\n", rd_data);
362 //while(rd_data=='hffffffff) mac_pio_class.xmac_pio_rd(base_addr + TxMAC_FRM_CNT, rd_data, 1'b0);
363 }
364 if(active_int[10]) {
365 //printf("macISR TX mac_id=%0d byte_cnt Interrupt\n", mac_id);
366 printf("macISR TX mac_id=%0d byte_cnt Interrupt (set mask)\n", mac_id);
367 rd_mask[10]=1;
368 mac_pio_class.xmac_pio_wr(base_addr + XTxMAC_STAT_MSK, rd_mask);
369 mac_pio_class.xmac_pio_rd(base_addr + TxMAC_BYTE_CNT, rd_data, 1'b0);
370 txbyte_cnt_int++;
371 if(rd_data!=='hffffffff) printf("ERROR macISR Interrupt TxMAC_BYTE_CNT=0x%0x\n", rd_data);
372 //while(rd_data=='hffffffff) mac_pio_class.xmac_pio_rd(base_addr + TxMAC_BYTE_CNT, rd_data, 1'b0);
373 }
374 if(rd_status[4]) {
375 printf("CNiuIntrDevMAC TX mac_id=%0d recived tx_xfer_err_interrupt\n",mac_id);
376 tx_xfer_err_cnt++;
377 }
378 if(rd_status[1]) {
379 printf("CNiuIntrDevMAC TX mac_id=%0d recived underrun_interrupt\n",mac_id);
380 underrun_cnt++;
381 }
382 if(rd_status[0]) {
383 printf("CNiuIntrDevMAC TX mac_id=%0d recived Pkts_xmtd_interrupt\n",mac_id);
384 pkts_txmt_cnt++;
385 }
386}
387
388task CNiuIntrDevMAC::check_XmacRX_int() {
389 bit[31:0] rd_data, rd_status, rd_mask, active_int;
390 bit[39:0] base_addr;
391 bit mdint_status;
392
393 base_addr = mac_util.get_mac_reg_base(mac_id);
394 mac_pio_class.xmac_pio_rd(base_addr + XRxMAC_STAT_MSK, rd_mask, 1'b0);
395 mac_pio_class.xmac_pio_rd(base_addr + XRxMAC_STATUS, rd_status, 1'b0);
396 active_int=rd_status & ~rd_mask;
397
398 printf("macISR RX id=%0d mask=0x%0x status=0x%0x active_int=0x%0x\n", super.dev_id, rd_status, rd_mask, active_int);
399 if(active_int[0]) {
400 printf("macISR RX mac_id=%0d Frame Recieved Interrupt\n", mac_id);
401 }
402 if(active_int[1]) {
403 printf("macISR RX mac_id=%0d Overflow Interrupt\n", mac_id);
404 }
405 if(active_int[2]) {
406 printf("macISR RX mac_id=%0d Underflow Interrupt\n", mac_id);
407 }
408 if(active_int[3]) {
409 printf("macISR RX mac_id=%0d crc_cnt Interrupt (set mask)\n", mac_id);
410 rd_mask[3]=1;
411 mac_pio_class.xmac_pio_wr(base_addr + XRxMAC_STAT_MSK, rd_mask);
412 mac_pio_class.xmac_pio_rd(base_addr + MAC_CRC_ER_CNT, rd_data, 1'b0);
413 trigger(ONE_SHOT, clear_crc_cnt);
414 if(rd_data!=='hff) printf("ERROR macISR Interrupt MAC_CRC_ER_CNT=0x%0x\n", rd_data);
415 }
416 if(active_int[4]) {
417 printf("macISR RX mac_id=%0d mpsz Interrupt (set mask)\n", mac_id);
418 rd_mask[4]=1;
419 mac_pio_class.xmac_pio_wr(base_addr + XRxMAC_STAT_MSK, rd_mask);
420 mac_pio_class.xmac_pio_rd(base_addr + RxMAC_MPSZER_CNT, rd_data, 1'b0);
421 trigger(ONE_SHOT, clear_mpsz_cnt);
422 if(rd_data!=='hff) printf("ERROR macISR Interrupt MPSZER_CNT=0x%0x\n", rd_data);
423 }
424 if(active_int[5]) {
425 printf("macISR RX mac_id=%0d code viol Interrupt\n", mac_id);
426 }
427 if(active_int[6]) {
428 printf("macISR RX mac_id=%0d byte_cnt Interrupt (set mask)\n", mac_id);
429 rd_mask[6]=1;
430 mac_pio_class.xmac_pio_wr(base_addr + XRxMAC_STAT_MSK, rd_mask);
431 mac_pio_class.xmac_pio_rd(base_addr + RxMAC_BT_CNT, rd_data, 1'b0);
432 //trigger(ONE_BLAST, clear_byte_cnt);
433 trigger(ONE_SHOT, clear_byte_cnt);
434 byte_cnt_int=1;
435 printf("macISR Interrupt BT_CNT=0x%h time=%0d\n", rd_data, get_time(LO));
436 if(rd_data!=='hffffffff) printf("ERROR macISR Interrupt BT_CNT=0x%0x\n", rd_data);
437 //delay for byte cntr to clear
438 repeat(30) @(posedge CLOCK);
439 //read status again because int triggered
440 mac_pio_class.xmac_pio_rd(base_addr + XRxMAC_STATUS, rd_data, 1'b0);
441 printf("macISR RX id=%0d status=0x%0x\n", super.dev_id, rd_data);
442 }
443 if(active_int[7]) {
444 printf("macISR RX mac_id=%0d hist1 Interrupt (set mask)\n", mac_id);
445 rd_mask[7]=1;
446 mac_pio_class.xmac_pio_wr(base_addr + XRxMAC_STAT_MSK, rd_mask);
447 mac_pio_class.xmac_pio_rd(base_addr + RxMAC_HIST_CNT1, rd_data, 1'b0);
448 trigger(ONE_SHOT, clear_hist1_cnt);
449 if(rd_data!=='h1fffff) printf("ERROR macISR Interrupt HIST_CNT1=0x%0x (64)\n", rd_data);
450 }
451 if(active_int[8]) {
452 printf("macISR RX mac_id=%0d hist2 Interrupt (set mask)\n", mac_id);
453 rd_mask[8]=1;
454 mac_pio_class.xmac_pio_wr(base_addr + XRxMAC_STAT_MSK, rd_mask);
455 mac_pio_class.xmac_pio_rd(base_addr + RxMAC_HIST_CNT2, rd_data, 1'b0);
456 trigger(ONE_SHOT, clear_hist2_cnt);
457 if(rd_data!=='h1fffff) printf("ERROR macISR Interrupt HIST_CNT2=0x%0x (65-127)\n", rd_data);
458 }
459 if(active_int[9]) {
460 printf("macISR RX mac_id=%0d hist3 Interrupt (set mask)\n", mac_id);
461 rd_mask[9]=1;
462 mac_pio_class.xmac_pio_wr(base_addr + XRxMAC_STAT_MSK, rd_mask);
463 mac_pio_class.xmac_pio_rd(base_addr + RxMAC_HIST_CNT3, rd_data, 1'b0);
464 trigger(ONE_SHOT, clear_hist3_cnt);
465 if(rd_data!=='hfffff) printf("ERROR macISR Interrupt HIST_CNT3=0x%0x (128-255)\n", rd_data);
466 }
467 if(active_int[10]) {
468 printf("macISR RX mac_id=%0d hist4 Interrupt (set mask)\n", mac_id);
469 rd_mask[10]=1;
470 mac_pio_class.xmac_pio_wr(base_addr + XRxMAC_STAT_MSK, rd_mask);
471 mac_pio_class.xmac_pio_rd(base_addr + RxMAC_HIST_CNT4, rd_data, 1'b0);
472 trigger(ONE_SHOT, clear_hist4_cnt);
473 if(rd_data!=='h7ffff) printf("ERROR macISR Interrupt HIST_CNT4=0x%0x (256-511)\n", rd_data);
474 }
475 if(active_int[11]) {
476 printf("macISR RX mac_id=%0d hist5 Interrupt (set mask)\n", mac_id);
477 rd_mask[11]=1;
478 mac_pio_class.xmac_pio_wr(base_addr + XRxMAC_STAT_MSK, rd_mask);
479 mac_pio_class.xmac_pio_rd(base_addr + RxMAC_HIST_CNT5, rd_data, 1'b0);
480 trigger(ONE_SHOT, clear_hist5_cnt);
481 if(rd_data!=='h3ffff) printf("ERROR macISR Interrupt HIST_CNT5=0x%0x (512-1023)\n", rd_data);
482 }
483 if(active_int[12]) {
484 printf("macISR RX mac_id=%0d hist6 Interrupt (set mask)\n", mac_id);
485 rd_mask[12]=1;
486 mac_pio_class.xmac_pio_wr(base_addr + XRxMAC_STAT_MSK, rd_mask);
487 mac_pio_class.xmac_pio_rd(base_addr + RxMAC_HIST_CNT6, rd_data, 1'b0);
488 trigger(ONE_SHOT, clear_hist6_cnt);
489 if(rd_data!=='h1ffff) printf("ERROR macISR Interrupt HIST_CNT6=0x%0x\n (1024-1522)", rd_data);
490 }
491 if(active_int[13]) {
492 printf("macISR RX mac_id=%0d broadcast_cnt Interrupt (set mask)\n", mac_id);
493 rd_mask[13]=1;
494 mac_pio_class.xmac_pio_wr(base_addr + XRxMAC_STAT_MSK, rd_mask);
495 mac_pio_class.xmac_pio_rd(base_addr + RxMAC_BC_FRM_CNT, rd_data, 1'b0);
496 trigger(ONE_SHOT, clear_broadcast_cnt);
497 if(rd_data!=='h1fffff) printf("ERROR macISR Interrupt BC_FRM_CNT=0x%0x\n", rd_data);
498 }
499 if(active_int[14]) {
500 printf("macISR RX mac_id=%0d multicast_cnt Interrupt (set mask)\n", mac_id);
501 rd_mask[14]=1;
502 mac_pio_class.xmac_pio_wr(base_addr + XRxMAC_STAT_MSK, rd_mask);
503 mac_pio_class.xmac_pio_rd(base_addr + RxMAC_MC_FRM_CNT, rd_data, 1'b0);
504 trigger(ONE_SHOT, clear_multicast_cnt);
505 if(rd_data!=='h1fffff) printf("ERROR macISR Interrupt MC_FRM_CNT=0x%0x\n", rd_data);
506 }
507 if(active_int[15]) {
508 printf("macISR RX mac_id=%0d frag_cnt Interrupt (set mask)\n", mac_id);
509 rd_mask[15]=1;
510 mac_pio_class.xmac_pio_wr(base_addr + XRxMAC_STAT_MSK, rd_mask);
511 mac_pio_class.xmac_pio_rd(base_addr + RxMAC_FRAG_CNT, rd_data, 1'b0);
512 trigger(ONE_SHOT, clear_frag_cnt);
513 if(rd_data!=='h1fffff) printf("ERROR macISR Interrupt FRAG_CNT=0x%0x\n", rd_data);
514 }
515 if(active_int[16]) {
516`ifdef N2_FC
517`else
518 printf("macISR RX mac_id=%0d PHY_MDINT Interrupt time=%0d\n", mac_id, get_time(LO));
519 mdint_int=1;
520 check_mdint_status(mac_id, mdint_status);
521 if(mdint_status!==0) printf("macISR mac_id=%0d ERROR Interrupt PHY_MDINT signal not low.\n", mac_id);
522 deassert_mdint(mac_id);
523 delay(500);
524 check_mdint_status(mac_id, mdint_status);
525 if(mdint_status!==1) printf("macISR mac_id=%0d ERROR Interrupt PHY_MDINT signal not high after deassert time=%0d\n", mac_id, get_time(LO));
526`endif
527 }
528 if(active_int[17]) {
529 printf("macISR RX mac_id=%0d link_fault_count Interrupt\n", mac_id);
530 mac_pio_class.xmac_pio_rd(base_addr + LINK_FAULT_CNT, rd_data, 1'b0);
531 trigger(ONE_SHOT, clear_link_fault_cnt);
532 if(rd_data!=='hff) printf("ERROR macISR Interrupt LINK_FAULT_CNT=0x%0x\n", rd_data);
533 printf("macISR RX mac_id=%0d link_fault_count Interrupt\n", mac_id);
534 mac_pio_class.xmac_pio_rd(base_addr + LINK_FAULT_CNT, rd_data, 1'b0);
535 trigger(ONE_SHOT, clear_link_fault_cnt);
536 if(rd_data!=='h0) printf("ERROR macISR Interrupt LINK_FAULT_CNT=0x%0x\n", rd_data);
537 }
538 if(active_int[18]) {
539 rf_intr_cnt++;
540 printf("macISR RX mac_id=%0d remote_fault_detected Interrupt count=%0d\n", mac_id, rf_intr_cnt);
541 mac_pio_class.xmac_pio_rd(base_addr + XRxMAC_STATUS, rd_data, 1'b0);
542 if(rd_data[18]!=0) {
543 printf("INFO remote_fault_status interrupt not cleared,possible that a new remote fault event has happened\n");
544 rf_intr_cnt++;
545 }
546 }
547 if(active_int[19]) {
548 lf_intr_cnt++;
549 printf("macISR RX mac_id=%0d local_fault_detected Interrupt count=%0d\n", mac_id, lf_intr_cnt);
550 mac_pio_class.xmac_pio_rd(base_addr + XRxMAC_STATUS, rd_data, 1'b0);
551 if(rd_data[19]!=0) {
552 printf("INFO local_fault_status interrupt not cleared,possible that a new local fault event has happened\n");
553 lf_intr_cnt++;
554 }
555 }
556 if(active_int[20]) {
557 printf("macISR RX mac_id=%0d hist7 Interrupt (set mask)\n", mac_id);
558 rd_mask[20]=1;
559 mac_pio_class.xmac_pio_wr(base_addr + XRxMAC_STAT_MSK, rd_mask);
560 mac_pio_class.xmac_pio_rd(base_addr + RxMAC_HIST_CNT7, rd_data, 1'b0);
561 trigger(ONE_SHOT, clear_hist7_cnt);
562 if(rd_data!=='h1fffff) printf("ERROR macISR Interrupt HIST_CNT7=0x%0x\n", rd_data);
563 }
564}
565
566task CNiuIntrDevMAC::set_rx_mask(bit[31:0] val) {
567 if(mac_id==0 || mac_id==1)
568 mac_pio_class.xmac_pio_wr(mac_util.get_mac_reg_base(mac_id) + XRxMAC_STAT_MSK, val);
569}
570task CNiuIntrDevMAC::set_brx_mask(bit[31:0] val) {
571 if(mac_id==2 || mac_id==3)
572 mac_pio_class.xmac_pio_wr(mac_util.get_mac_reg_base(mac_id) + BRxMAC_STAT_MSK, val);
573}
574
575task CNiuIntrDevMAC::set_masks () {
576 bit[39:0] base_addr;
577 bit[31:0] rd_data;
578
579 printf("macISR setting masks=0 mac_id=%0d\n", mac_id);
580 base_addr = mac_util.get_mac_reg_base(mac_id);
581 if(mac_id==0 || mac_id==1) {
582 mac_pio_class.xmac_pio_wr(base_addr + XTxMAC_STAT_MSK, 32'h1); //keep frame_transmitted masked
583 mac_pio_class.xmac_pio_wr(base_addr + XRxMAC_STAT_MSK, 32'h1); //keep frame_receieved masked
584 mac_pio_class.xmac_pio_wr(base_addr + XMAC_C_S_MSK, 32'h0);
585
586 mac_pio_class.xmac_pio_wr(base_addr + XMAC_C_S_MSK, 32'b0);
587 mac_pio_class.xmac_pio_wr(base_addr + BMAC_C_S_MSK, 32'b0);
588
589 mac_pio_class.xmac_pio_rd(PCS0_BASE + PCS_MII_CONTROL, rd_data, 1'b0);
590 rd_data[PCS_INT_MASK]=0;
591 mac_pio_class.xmac_pio_wr(PCS0_BASE + PCS_MII_CONTROL, rd_data);
592
593 mac_pio_class.xmac_pio_rd(PCS1_BASE + PCS_MII_CONTROL, rd_data, 1'b0);
594 rd_data[PCS_INT_MASK]=0;
595 mac_pio_class.xmac_pio_wr(PCS1_BASE + PCS_MII_CONTROL, rd_data);
596
597 mac_pio_class.xmac_pio_wr(XPCS0_BASE + XPCS_MASK1, 0);
598 mac_pio_class.xmac_pio_wr(XPCS1_BASE + XPCS_MASK1, 0);
599 }
600 else {
601 mac_pio_class.xmac_pio_wr(base_addr + BRxMAC_STAT_MSK, 32'h1); //keep frame_receieved masked
602 mac_pio_class.xmac_pio_wr(base_addr + BTxMAC_STAT_MSK, 32'h1); //keep frame_transmitted masked
603 mac_pio_class.xmac_pio_wr(base_addr + BMAC_C_S_MSK, 32'h0);
604 }
605}
Full OpenSPARC design & verification tarball including full HDL.