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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / niu / vera / niu_pio / bmac_util.vr
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: bmac_util.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36#include "mac_defines.vri"
37#include "bmac_memory_map.vri"
38#include "pio_driver.vrh"
39#include "mac_pio_class.vrh"
40#include "xpcs_memory_map.vri"
41
42extern mac_pio_cl mac_pio_class;
43//extern pio_drv pio_driver_class;
44extern bit reset_complete;
45
46class bmac_util_class {
47 task new();
48 function bit check_cmd(bit [63:0]cmd, bit [63:0] opt);
49 task get_mac_debug_level(var integer mac_debug, var integer mac_quick,var integer mac_verbose );
50 task bmac_init(integer iport, bit [63:0] cmd);
51 task bmac_init_sub(integer iport, bit [63:0] cmd);
52 task tx_bmac_reset(integer iport, bit [39:0] base_addr, integer MAC_INIT_DEBUG);
53 task rx_bmac_reset(integer iport, bit [39:0] base_addr, integer MAC_INIT_DEBUG);
54 task init_all_reg(integer iport, bit[63:0] cmd, bit [39:0] base_addr);
55 task init_essential_reg_only(integer iport, bit[63:0] cmd, bit [39:0] base_addr);
56 task setup_reg(integer iport, bit[63:0] cmd, bit [39:0] addr, bit [31:0] data,bit [31:0] verify_mask);
57 task mac_pci_rd(bit [39:0] addr, var bit [31:0] exp_value);
58 task mac_pci_rd_cmp(bit [39:0] addr, bit [31:0] exp_value, bit [31:0] data_mask);
59 function bit[39:0] get_mac_reg_base(integer iport);
60 function bit[(16*12)-1:0] get_bmac_reg_name(integer id);
61 function bit[32:0] get_bmac_reg_adr(integer id);
62 function bit[32:0] bmac_reg_addr (integer sel);
63 function bit[31:0] bmac_reg_mask (integer sel);
64 function bit[31:0] bmac_reg_default (integer sel);
65 function integer flen(integer sel);
66 function integer flen_j(integer sel);
67 task set_host_info_1(integer mac_id,bit[31:0] ctrl_word);
68 task wr_ipp_mac_reg(integer mac_id,bit[39:0] addr, bit[31:0]wr_data);
69 task rd_ipp_mac_reg(integer mac_id,bit[39:0] addr, var bit[31:0]rd_data, bit compare);
70 task ipp_shadow_rd (bit[39:0] addr, var bit[31:0] rd_data,\
71 var bit[31:0] data_mask, var bit data_valid);
72 task rx_pkt_count_check(integer pkt_cnt);
73 task tx_pkt_count_check(integer pkt_cnt);
74 local function integer getPortID(bit [39:0] addr) {
75 case(addr[19:12]) {
76 8'h80:getPortID = 0;
77 8'h82:getPortID = 0;
78 8'h84:getPortID = 0;
79 8'h86:getPortID = 1;
80 8'h88:getPortID = 1;
81 8'h8a:getPortID = 1;
82 8'h8c:getPortID = 2;
83 8'h8e:getPortID = 2;
84 8'h90:getPortID = 3;
85 8'h92:getPortID = 3;
86 }
87 }
88}
89
90task bmac_util_class::new() { }
91
92function bit bmac_util_class :: check_cmd(bit [63:0]cmd, bit [63:0] opt){
93 if((cmd & opt) > 0) check_cmd=1;
94 else check_cmd=0;
95}
96
97task bmac_util_class::get_mac_debug_level(var integer mac_debug, var integer mac_quick, var integer mac_verbose) {
98 mac_debug = 0;
99 if( get_plus_arg( CHECK, "MAC_TEST_DEBUG") ) {
100 mac_debug = get_plus_arg(NUM, "MAC_TEST_DEBUG" );
101 }
102 mac_quick = get_plus_arg( CHECK, "MAC_QUICK_TEST");
103 mac_verbose = get_plus_arg( CHECK, "MAC_VERBOSE_TEST");
104}
105
106
107task bmac_util_class::bmac_init(integer iport, bit[63:0] cmd) {
108 integer mac_debug,mac_quick,mac_verbose;
109 integer MAC_INIT_DEBUG;
110 bit [31:0] data;
111 bit [39:0] base_addr;
112
113 get_mac_debug_level(mac_debug,mac_quick,mac_verbose);
114 MAC_INIT_DEBUG = check_cmd(cmd, MI_DEBUG) | mac_debug;
115
116 printf("bmac_init:MAC%0d Setting up registers\n", iport);
117 cmd[0] = 0; // RX_MAC_RESET
118 cmd[1] = 0; // TX_MAC_RESET
119
120 base_addr = get_mac_reg_base(iport);
121
122 //programming the PA size as not resetable by SW reset and so gate sims have a problem
123 setup_reg(iport, cmd, base_addr + MAC_PA_SIZE, 32'h0000_0007, 32'h0000_03ff );
124
125 if(check_cmd(cmd, MAC_CONF_1000)) data = 32'h0019;
126 if(check_cmd(cmd, MAC_CONF_100)) data = 32'h0091;
127 if(check_cmd(cmd, MAC_CONF_10)) data = 32'h0011;
128 data[1]=check_cmd(cmd, MAC_LOOPBACK);
129
130 //printf("bmac_init:MAC%0d Writing XIF_CONFIG Reg=0x%0h time=%0d\n", iport, data, get_time(LO));
131 setup_reg(iport, cmd, base_addr + MAC_XIF_CONFIG, data, 32'hffff_ffe6);
132
133 bmac_init_sub(iport, RX_MAC_RESET | TX_MAC_RESET | cmd);
134 setup_reg(iport, cmd, base_addr + BRxMAC_FRM_CNT, 32'h0000_0000, 32'h0000_ffff );
135 printf("bmac_init:MAC%0d DONE time=%0d\n", iport, get_time(LO));
136}
137
138
139task bmac_util_class::bmac_init_sub(integer iport, bit[63:0] cmd) {
140 bit [39:0] base_addr;
141 bit [31:0] data, data1,data2, rx_data, tx_data;
142 integer MAC_INIT_DEBUG;
143 integer mac_debug,mac_quick,mac_verbose;
144
145 get_mac_debug_level(mac_debug,mac_quick,mac_verbose);
146 base_addr = get_mac_reg_base(iport);
147 MAC_INIT_DEBUG = check_cmd(cmd,MI_DEBUG) | mac_debug;
148
149 //MAC RESET CODE
150 fork
151 if( check_cmd(cmd,TX_MAC_RESET) ) tx_bmac_reset(iport,base_addr,MAC_INIT_DEBUG);
152 if( check_cmd(cmd,RX_MAC_RESET) ) rx_bmac_reset(iport,base_addr,MAC_INIT_DEBUG);
153 join all
154
155 //MAC COUNTERS INITIALIZE
156 if( check_cmd(cmd,MAC_INIT_ALL_REG) ) {
157 if (get_plus_arg(CHECK, "ESSENTIAL_PIO_WRITES_ONLY"))
158 init_essential_reg_only(iport, cmd, base_addr);
159 else
160 init_all_reg(iport, cmd, base_addr);
161 }
162
163 //MAC CONFIG CODE
164 if( check_cmd(cmd,MAC_CONF_10) | check_cmd(cmd,MAC_CONF_100) | check_cmd(cmd,MAC_CONF_1000) ) {
165 bit [47:0] tmp48;
166
167 if( check_cmd(cmd, MAC_SHORT_PKT) ) {
168 setup_reg(iport, cmd, base_addr + BMAC_MIN, {4'h0,8'h7,10'h40,10'h17}, 32'hffff_ffff);
169 setup_reg(iport, cmd, base_addr + BMAC_MAX, {2'h0, 14'h0,2'h0,14'h0024}, 32'hffff_ffff);
170 }
171 else {
172#ifdef VEGA_CHIP_LEVEL
173 setup_reg(iport, cmd, base_addr + BMAC_MIN, {4'h0,8'h7,10'h40,10'h20}, 32'hffff_ffff);
174 if(get_plus_arg(CHECK,"JUMBO_FRAME_EN"))
175 setup_reg(iport, cmd, base_addr + BMAC_MAX, {2'h0,14'h0,2'h0,14'h3fff}, 32'hffff_ffff);
176 else
177 setup_reg(iport, cmd, base_addr + BMAC_MAX, {2'h0,14'h0,2'h0,14'h05EE}, 32'hffff_ffff);
178#else
179 setup_reg(iport, cmd, base_addr + BMAC_MIN, {4'h0,8'h7,10'h40,10'h20}, 32'hffff_ffff);
180 if(get_plus_arg(CHECK,"JUMBO_FRAME_EN"))
181 setup_reg(iport, cmd, base_addr + BMAC_MAX, {2'h0,14'h0,2'h0,14'h3FFF}, 32'hffff_ffff);
182 else
183 setup_reg(iport, cmd, base_addr + BMAC_MAX, {2'h0,14'h0,2'h0,14'h05EE}, 32'hffff_ffff);
184#endif
185 }
186
187 data = 32'h0000_0007;
188 setup_reg(iport, cmd, base_addr + TxMAC_CONFIG, data, 32'hffff_ffff);
189 printf("bmac_init:Waiting for MAC[%0d] Disable to complete ...\n",iport);
190
191 //mac_pci_rd(base_addr + TxMAC_CONFIG, data);
192 // while(data[0] == 1 ) {
193 // repeat(10) @(CLOCK);
194 // mac_pci_rd(base_addr + TxMAC_CONFIG, data);
195 // }
196
197 repeat(10) @(CLOCK);
198
199 data1 = 32'h0000_0009;
200 data1[9] = get_plus_arg(CHECK, "RX_DROP_PKT_CHECK");
201 data1[7] = check_cmd(cmd, MAC_ER_CK_EN) ? 0 : 1;
202 setup_reg(iport, cmd, base_addr + RxMAC_CONFIG, data1,32'hffff_ffff);
203
204 //mac_pci_rd(base_addr + RxMAC_CONFIG, data1);
205 // while(data[0] == 1 ) {
206 // repeat(10) @(CLOCK);
207 // mac_pci_rd(base_addr + RxMAC_CONFIG, data1);
208 //
209 // }
210
211 repeat(10) @(CLOCK);
212 }
213}
214
215////////////////////////////////////////////////////////////////////////////////
216// mac reset Tasks
217////////////////////////////////////////////////////////////////////////////////
218
219task bmac_util_class::tx_bmac_reset(integer iport, bit[39:0] base_addr, integer MAC_INIT_DEBUG) {
220 bit[31:0] tx_data;
221
222 // Assert Reset on TX
223 mac_pio_class.bmac_pio_wr(base_addr + BTxMAC_SW_RST, 32'h01);
224 printf("bmac_init:MAC%0d Writing BTxMAC_SW_RST=1 (%h)\n", iport, base_addr+BTxMAC_SW_RST);
225
226 repeat(10) @(CLOCK);
227 printf("bmac_init:Waiting for TX MAC%0d to reset. time=%0d\n", iport, get_time(LO));
228
229 // Wait for Reset on TX Mac to complete
230 mac_pio_class.mac_pio_rd(base_addr + BTxMAC_SW_RST, tx_data);
231 while(tx_data != 0) {
232 repeat(5) @(CLOCK);
233 mac_pio_class.mac_pio_rd(base_addr + BTxMAC_SW_RST, tx_data);
234 }
235
236 printf("bmac_init:TX MAC%0d reset complete.\n", iport);
237 repeat(10) @(CLOCK);
238}
239
240
241task bmac_util_class::rx_bmac_reset(integer iport, bit[39:0] base_addr, integer MAC_INIT_DEBUG) {
242 bit[31:0] rx_data;
243
244 // Assert Reset on RX Mac
245 mac_pio_class.bmac_pio_wr(base_addr + BRxMAC_SW_RST, 32'h01);
246 printf("bmac_init:MAC%0d Writing BRxMAC_SW_RST=1 (%h)\n", iport, base_addr+BRxMAC_SW_RST );
247
248 repeat(10) @(CLOCK);
249 printf("bmac_init:Waiting for RX MAC%0d to reset. time=%0d\n", iport, get_time(LO));
250
251 // Wait for Reset on RX Mac to complete
252 mac_pio_class.mac_pio_rd(base_addr + BRxMAC_SW_RST, rx_data);
253 while(rx_data != 0) {
254 repeat(5) @(CLOCK);
255 mac_pio_class.mac_pio_rd(base_addr + BRxMAC_SW_RST, rx_data);
256 }
257
258 printf("bmac_init:RX MAC%0d reset complete.\n", iport);
259 repeat(10) @(CLOCK);
260}
261
262
263////////////////////////////////////////////////////////////////////////////////
264// init_all_reg Task
265////////////////////////////////////////////////////////////////////////////////
266
267task bmac_util_class :: init_all_reg(integer iport, bit[63:0] cmd, bit [39:0] base_addr) {
268 bit [47:0] tmp48;
269
270 setup_reg(iport, cmd, base_addr + BTxMAC_STAT_MSK, 32'h0000_01ff,32'hffff_ffff);
271 setup_reg(iport, cmd, base_addr + BRxMAC_STAT_MSK,32'h0000_00ff, 32'hffff_ffff);
272 setup_reg(iport, cmd, base_addr + BMAC_C_S_MSK, 32'hffff_fff7, 32'hffff_ffff);
273 setup_reg(iport, cmd, base_addr + MAC_SEND_PAUSE, 32'h0000_1BF0, 32'h000f_ffff );
274 setup_reg(iport, cmd, base_addr + BMAC_MIN, 32'h0000_0040, 32'h0000_03ff );
275 if(get_plus_arg(CHECK,"JUMBO_FRAME_EN"))
276 setup_reg(iport, cmd, base_addr + BMAC_MAX, 32'h2000_3FFF, 32'hffff_ffff );
277 else
278 setup_reg(iport, cmd, base_addr + BMAC_MAX, 32'h2000_05EE, 32'hffff_ffff );
279 setup_reg(iport, cmd, base_addr + MAC_PA_SIZE, 32'h0000_0007, 32'h0000_03ff );
280 setup_reg(iport, cmd, base_addr + MAC_CTRL_TYPE, 32'h0000_8808, 32'h0000_ffff );
281
282
283 setup_reg(iport, cmd, base_addr + MAC_IPG0, 32'h0000_0000, 32'h0000_00ff );
284 setup_reg(iport, cmd, base_addr + MAC_IPG1, 32'h0000_0008, 32'h0000_00ff );
285 setup_reg(iport, cmd, base_addr + MAC_IPG2, 32'h0000_0004, 32'h0000_00ff );
286 setup_reg(iport, cmd, base_addr + MAC_SLOT_TIME, 32'h0000_0040, 32'h0000_03ff );
287 setup_reg(iport, cmd, base_addr + MAC_JAM_SIZE, 32'h0000_0004, 32'h0000_001f );
288 setup_reg(iport, cmd, base_addr + MAC_ATTMPT_LMT, 32'h0000_0010, 32'h0000_00ff );
289
290 setup_reg(iport, cmd, base_addr + BMAC_COL_CNT, 32'h0000_0000, 32'h0000_ffff );
291 setup_reg(iport, cmd, base_addr + BMAC_OA_COL_CNT,32'h0000_0000, 32'h0000_ffff );
292 setup_reg(iport, cmd, base_addr + BMAC_EX_COL_CNT,32'h0000_0000, 32'h0000_ffff );
293 setup_reg(iport, cmd, base_addr + BMAC_LT_COL_CNT,32'h0000_0000, 32'h0000_ffff );
294 setup_reg(iport, cmd, base_addr + MAC_DEF_TIMER,32'h0000_0000, 32'h0000_ffff );
295
296
297
298
299 setup_reg(iport, cmd, base_addr + BMAC_ADDR0, 32'h0000_0000, 32'h0000_ffff );
300 setup_reg(iport, cmd, base_addr + BMAC_ADDR1, 32'h0000_0000, 32'h0000_ffff );
301 setup_reg(iport, cmd, base_addr + BMAC_ADDR2, 32'h0000_0000, 32'h0000_ffff );
302 setup_reg(iport, cmd, base_addr + MAC_ADDR3, 32'h0000_0000, 32'h0000_ffff );
303 setup_reg(iport, cmd, base_addr + MAC_ADDR4, 32'h0000_0000, 32'h0000_ffff );
304 setup_reg(iport, cmd, base_addr + MAC_ADDR5, 32'h0000_0000, 32'h0000_ffff );
305 setup_reg(iport, cmd, base_addr + MAC_ADDR6, 32'h0000_0000, 32'h0000_ffff );
306 setup_reg(iport, cmd, base_addr + MAC_ADDR7, 32'h0000_0000, 32'h0000_ffff );
307 setup_reg(iport, cmd, base_addr + MAC_ADDR8, 32'h0000_0000, 32'h0000_ffff );
308 setup_reg(iport, cmd, base_addr + MAC_ADDR9, 32'h0000_0000, 32'h0000_ffff );
309 setup_reg(iport, cmd, base_addr + MAC_ADDR10, 32'h0000_0000, 32'h0000_ffff );
310 setup_reg(iport, cmd, base_addr + MAC_ADDR11, 32'h0000_0000, 32'h0000_ffff );
311 setup_reg(iport, cmd, base_addr + MAC_ADDR12, 32'h0000_0000, 32'h0000_ffff );
312 setup_reg(iport, cmd, base_addr + MAC_ADDR13, 32'h0000_0000, 32'h0000_ffff );
313 setup_reg(iport, cmd, base_addr + MAC_ADDR14, 32'h0000_0000, 32'h0000_ffff );
314 setup_reg(iport, cmd, base_addr + MAC_ADDR15, 32'h0000_0000, 32'h0000_ffff );
315 setup_reg(iport, cmd, base_addr + MAC_ADDR16, 32'h0000_0000, 32'h0000_ffff );
316 setup_reg(iport, cmd, base_addr + MAC_ADDR17, 32'h0000_0000, 32'h0000_ffff );
317 setup_reg(iport, cmd, base_addr + MAC_ADDR18, 32'h0000_0000, 32'h0000_ffff );
318 setup_reg(iport, cmd, base_addr + MAC_ADDR19, 32'h0000_0000, 32'h0000_ffff );
319 setup_reg(iport, cmd, base_addr + MAC_ADDR20, 32'h0000_0000, 32'h0000_ffff );
320 setup_reg(iport, cmd, base_addr + MAC_ADDR21, 32'h0000_0000, 32'h0000_ffff );
321 setup_reg(iport, cmd, base_addr + MAC_ADDR22, 32'h0000_0000, 32'h0000_ffff );
322 setup_reg(iport, cmd, base_addr + MAC_ADDR23, 32'h0000_0000, 32'h0000_ffff );
323
324 setup_reg(iport, cmd, base_addr + MAC_FC_ADDR0, 32'h0000_0001, 32'h0000_ffff );
325 setup_reg(iport, cmd, base_addr + MAC_FC_ADDR1, 32'h0000_C200, 32'h0000_ffff );
326 setup_reg(iport, cmd, base_addr + MAC_FC_ADDR2, 32'h0000_0180, 32'h0000_ffff );
327
328 setup_reg(iport, cmd, base_addr + MAC_ADD_FILT0, 32'h0000_0000, 32'h0000_ffff );
329 setup_reg(iport, cmd, base_addr + MAC_ADD_FILT1, 32'h0000_0000, 32'h0000_ffff );
330 setup_reg(iport, cmd, base_addr + MAC_ADD_FILT2, 32'h0000_0000, 32'h0000_ffff );
331 setup_reg(iport, cmd, base_addr + MAC_ADD_FILT12_MASK, 32'h0000_0000, 32'h0000_ffff );
332 setup_reg(iport, cmd, base_addr + MAC_ADD_FILT00_MASK, 32'h0000_0000, 32'h0000_ffff );
333
334 setup_reg(iport, cmd, base_addr + MAC_HASH_TBL0, 32'h0000_0000, 32'h0000_ffff );
335 setup_reg(iport, cmd, base_addr + MAC_HASH_TBL1, 32'h0000_0000, 32'h0000_ffff );
336 setup_reg(iport, cmd, base_addr + MAC_HASH_TBL2, 32'h0000_0000, 32'h0000_ffff );
337 setup_reg(iport, cmd, base_addr + MAC_HASH_TBL3, 32'h0000_0000, 32'h0000_ffff );
338 setup_reg(iport, cmd, base_addr + MAC_HASH_TBL4, 32'h0000_0000, 32'h0000_ffff );
339 setup_reg(iport, cmd, base_addr + MAC_HASH_TBL5, 32'h0000_0000, 32'h0000_ffff );
340 setup_reg(iport, cmd, base_addr + MAC_HASH_TBL6, 32'h0000_0000, 32'h0000_ffff );
341 setup_reg(iport, cmd, base_addr + MAC_HASH_TBL7, 32'h0000_0000, 32'h0000_ffff );
342 setup_reg(iport, cmd, base_addr + MAC_HASH_TBL8, 32'h0000_0000, 32'h0000_ffff );
343 setup_reg(iport, cmd, base_addr + MAC_HASH_TBL9, 32'h0000_0000, 32'h0000_ffff );
344 setup_reg(iport, cmd, base_addr + MAC_HASH_TBL10, 32'h0000_0000,32'h0000_ffff );
345 setup_reg(iport, cmd, base_addr + MAC_HASH_TBL11, 32'h0000_0000,32'h0000_ffff );
346 setup_reg(iport, cmd, base_addr + MAC_HASH_TBL12, 32'h0000_0000,32'h0000_ffff );
347 setup_reg(iport, cmd, base_addr + MAC_HASH_TBL13, 32'h0000_0000,32'h0000_ffff );
348 setup_reg(iport, cmd, base_addr + MAC_HASH_TBL14, 32'h0000_0000,32'h0000_ffff );
349 setup_reg(iport, cmd, base_addr + MAC_HASH_TBL15, 32'h0000_0000,32'h0000_ffff );
350
351 setup_reg(iport, cmd, base_addr + BRxMAC_FRM_CNT, 32'h0000_0000, 32'h0000_ffff );
352 setup_reg(iport, cmd, base_addr + MAC_LEN_ER_CNT, 32'h0000_0000, 32'h0000_ffff );
353 setup_reg(iport, cmd, base_addr + BMAC_AL_ER_CNT, 32'h0000_0000, 32'h0000_ffff );
354 setup_reg(iport, cmd, base_addr + BMAC_CRC_ER_CNT, 32'h0000_0000, 32'h0000_00ff );
355 setup_reg(iport, cmd, base_addr + BMAC_CD_VIO_CNT, 32'h0000_0000, 32'h0000_00ff );
356}
357
358
359////////////////////////////////////////////////////////////////////////////////
360//
361// init_essential_reg_only Task
362//
363////////////////////////////////////////////////////////////////////////////////
364
365task bmac_util_class :: init_essential_reg_only(integer iport, bit[63:0] cmd, bit [39:0] base_addr) {
366 bit [47:0] tmp48;
367
368 setup_reg(iport, cmd, base_addr + BTxMAC_STAT_MSK, 32'h0000_01ff,32'hffff_ffff);
369 setup_reg(iport, cmd, base_addr + BRxMAC_STAT_MSK,32'h0000_00ff, 32'hffff_ffff);
370 setup_reg(iport, cmd, base_addr + BMAC_C_S_MSK, 32'hffff_fff7, 32'hffff_ffff);
371 setup_reg(iport, cmd, base_addr + MAC_SEND_PAUSE, 32'h0000_1BF0, 32'h000f_ffff );
372 setup_reg(iport, cmd, base_addr + BMAC_MIN, 32'h0000_0040, 32'h0000_03ff );
373 if(get_plus_arg(CHECK,"JUMBO_FRAME_EN"))
374 setup_reg(iport, cmd, base_addr + BMAC_MAX, 32'h2000_3FFF, 32'hffff_ffff );
375 else
376 setup_reg(iport, cmd, base_addr + BMAC_MAX, 32'h2000_05EE, 32'hffff_ffff );
377 setup_reg(iport, cmd, base_addr + MAC_PA_SIZE, 32'h0000_0007, 32'h0000_03ff );
378 setup_reg(iport, cmd, base_addr + MAC_CTRL_TYPE, 32'h0000_8808, 32'h0000_ffff );
379
380
381 setup_reg(iport, cmd, base_addr + MAC_IPG0, 32'h0000_0000, 32'h0000_00ff );
382 setup_reg(iport, cmd, base_addr + MAC_IPG1, 32'h0000_0008, 32'h0000_00ff );
383 setup_reg(iport, cmd, base_addr + MAC_IPG2, 32'h0000_0004, 32'h0000_00ff );
384 setup_reg(iport, cmd, base_addr + MAC_SLOT_TIME, 32'h0000_0040, 32'h0000_03ff );
385 setup_reg(iport, cmd, base_addr + MAC_JAM_SIZE, 32'h0000_0004, 32'h0000_001f );
386 setup_reg(iport, cmd, base_addr + MAC_ATTMPT_LMT, 32'h0000_0010, 32'h0000_00ff );
387
388 setup_reg(iport, cmd, base_addr + BMAC_COL_CNT, 32'h0000_0000, 32'h0000_ffff );
389 setup_reg(iport, cmd, base_addr + BMAC_OA_COL_CNT,32'h0000_0000, 32'h0000_ffff );
390 setup_reg(iport, cmd, base_addr + BMAC_EX_COL_CNT,32'h0000_0000, 32'h0000_ffff );
391 setup_reg(iport, cmd, base_addr + BMAC_LT_COL_CNT,32'h0000_0000, 32'h0000_ffff );
392 setup_reg(iport, cmd, base_addr + MAC_DEF_TIMER,32'h0000_0000, 32'h0000_ffff );
393
394
395 setup_reg(iport, cmd, base_addr + MAC_FC_ADDR0, 32'h0000_0001, 32'h0000_ffff );
396 setup_reg(iport, cmd, base_addr + MAC_FC_ADDR1, 32'h0000_C200, 32'h0000_ffff );
397 setup_reg(iport, cmd, base_addr + MAC_FC_ADDR2, 32'h0000_0180, 32'h0000_ffff );
398
399 setup_reg(iport, cmd, base_addr + MAC_ADD_FILT0, 32'h0000_0000, 32'h0000_ffff );
400 setup_reg(iport, cmd, base_addr + MAC_ADD_FILT1, 32'h0000_0000, 32'h0000_ffff );
401 setup_reg(iport, cmd, base_addr + MAC_ADD_FILT2, 32'h0000_0000, 32'h0000_ffff );
402 setup_reg(iport, cmd, base_addr + MAC_ADD_FILT12_MASK, 32'h0000_0000, 32'h0000_ffff );
403 setup_reg(iport, cmd, base_addr + MAC_ADD_FILT00_MASK, 32'h0000_0000, 32'h0000_ffff );
404
405 setup_reg(iport, cmd, base_addr + BRxMAC_FRM_CNT, 32'h0000_0000, 32'h0000_ffff );
406 setup_reg(iport, cmd, base_addr + MAC_LEN_ER_CNT, 32'h0000_0000, 32'h0000_ffff );
407 setup_reg(iport, cmd, base_addr + BMAC_AL_ER_CNT, 32'h0000_0000, 32'h0000_ffff );
408 setup_reg(iport, cmd, base_addr + BMAC_CRC_ER_CNT, 32'h0000_0000, 32'h0000_00ff );
409 setup_reg(iport, cmd, base_addr + BMAC_CD_VIO_CNT, 32'h0000_0000, 32'h0000_00ff );
410}
411
412////////////////////////////////////////////////////////////////////////////////
413//
414// setup_reg Task
415//
416////////////////////////////////////////////////////////////////////////////////
417
418task bmac_util_class :: setup_reg(integer iport, bit[63:0] cmd, bit [39:0] addr, bit [31:0] data, bit [31:0] verify_mask) {
419 bit [31:0] data2;
420
421 if(check_cmd(cmd, MI_DEBUG))
422 printf("bmac_init:MAC%0d Writing %s Reg=0x%0h (%h) time=%0d\n", iport, get_bmac_reg_name(addr[11:0]), data, addr, get_time(LO));
423
424 mac_pio_class.bmac_pio_wr(addr, data);
425
426 if(check_cmd(cmd,MAC_REG_VERIFY)) { // This is just for basic SANITY testing
427 mac_pio_class.mac_pio_rd(addr, data2);
428 if((data & verify_mask) != (data2 & verify_mask))
429 printf("Error: bmac_init: Register Write Verify: Register %s (%h), Wrote: %h Read: %h Mask: %h\n",
430 get_bmac_reg_name(addr[11:0]),addr,data,data2,verify_mask);
431 }
432}
433
434task bmac_util_class :: set_host_info_1 (integer mac_id,bit[31:0] ctrl_word ) {
435
436 bit [39:0] base_addr;
437
438 base_addr = get_mac_reg_base(mac_id);
439 if(get_plus_arg( CHECK, "RX_DROP_PKT_CHECK"))
440 mac_pio_class.bmac_pio_wr(base_addr + RxMAC_CONFIG, 32'h0000_0201);
441 else
442 mac_pio_class.bmac_pio_wr(base_addr + RxMAC_CONFIG, 32'h0000_0001);
443
444 mac_pio_class.bmac_pio_wr(base_addr + BMAC_ALTAD_CMPEN, 32'h0000_FFFF);
445
446 mac_pio_class.bmac_pio_wr(base_addr + BMAC_HOST_INF1, ctrl_word);
447
448
449}
450
451task bmac_util_class :: wr_ipp_mac_reg(integer mac_id, bit[39:0] addr, bit[31:0] wr_data) {
452 bit [39:0] base_addr;
453 base_addr = get_mac_reg_base(mac_id);
454 mac_pio_class.bmac_pio_wr(base_addr + addr, wr_data);
455}
456
457task bmac_util_class :: rd_ipp_mac_reg(integer mac_id,bit[39:0] addr, \
458 var bit[31:0]rd_data, bit compare) {
459
460 bit [39:0] base_addr;
461 base_addr = get_mac_reg_base(mac_id);
462
463
464 mac_pio_class.bmac_pio_rd(base_addr + addr, rd_data, compare);
465
466
467}
468task bmac_util_class :: ipp_shadow_rd (bit[39:0] addr, var bit[31:0] rd_data,\
469 var bit[31:0] data_mask, var bit data_valid) {
470 integer port_id;
471 port_id = getPortID(addr);
472
473 mac_pio_class.mac_shadow_class[port_id].get_data(addr,rd_data,data_mask,data_valid);
474}
475
476////////////////////////////////////////////////////////////////////////////////
477//
478// mac_pci_rd Task
479//
480////////////////////////////////////////////////////////////////////////////////
481
482task bmac_util_class :: mac_pci_rd(bit [39:0] addr, var bit [31:0] exp_value) {
483 semaphore_get(WAIT, mac_pio_class.pio_drv_mac.pio_access, 1);
484 mac_pio_class.pio_drv_mac.address = addr;
485 mac_pio_class.pio_drv_mac.rd_wr = 1'b1;
486 mac_pio_class.pio_drv_mac.cfg_access = 1'b0;
487 //pio_driver.exp_data = exp_value;
488 //pio_driver.data_mask = 0;
489 //pio_driver.data_mask = 32'hffff_ffff;
490 //pio_driver.exp_data_valid = 1'b1;
491 trigger(ONE_SHOT, mac_pio_class.pio_drv_mac.pio_start);
492 sync(ALL, mac_pio_class.pio_drv_mac.pio_complete);
493 exp_value = mac_pio_class.pio_drv_mac.rd_data;
494 semaphore_put(mac_pio_class.pio_drv_mac.pio_access, 1);
495}
496
497
498
499task bmac_util_class :: mac_pci_rd_cmp(bit [39:0] addr, bit [31:0] exp_value, bit [31:0] data_mask) {
500 semaphore_get(WAIT, mac_pio_class.pio_drv_mac.pio_access, 1);
501 mac_pio_class.pio_drv_mac.address = addr;
502 mac_pio_class.pio_drv_mac.rd_wr = 1'b1;
503 mac_pio_class.pio_drv_mac.cfg_access = 1'b0;
504 //pio_driver_class.exp_data = exp_value;
505 //pio_driver_class.data_mask = data_mask;
506 //pio_driver_class.exp_data_valid = 1'b1;
507 trigger(ONE_SHOT, mac_pio_class.pio_drv_mac.pio_start);
508 sync(ALL, mac_pio_class.pio_drv_mac.pio_complete);
509
510 /****
511 if ((pio_driver.rd_data & pio_driver.data_mask) !== (pio_driver.exp_data & pio_driver.data_mask)) {
512 printf("Error: Register %s (%h) data mismatch: \n",get_bmac_reg_name(addr[11:0]),addr);
513 printf(" Expected: %h Got: %h Mask: %h\n",pio_driver.exp_data,
514 pio_driver.rd_data, pio_driver.data_mask);
515 printf("\n");
516 }
517 *****/
518
519 semaphore_put(mac_pio_class.pio_drv_mac.pio_access, 1);
520}
521
522function bit[39:0] bmac_util_class :: get_mac_reg_base(integer iport) {
523
524 case(iport) {
525 0: get_mac_reg_base = MAC0_BASE;
526 1: get_mac_reg_base = MAC1_BASE;
527 2: get_mac_reg_base = MAC2_BASE;
528 3: get_mac_reg_base = MAC3_BASE;
529 default: error("Error: Invalid PORT (%0d) for get_mac_reg_base task.\n",iport);
530 }
531
532}
533
534function bit[(16*12)-1:0] bmac_util_class :: get_bmac_reg_name(integer id) {
535 case(id) {
536
537 BTxMAC_SW_RST: get_bmac_reg_name = "BTxMAC_SW_RST";
538 BRxMAC_SW_RST: get_bmac_reg_name = "BRxMAC_SW_RST";
539 MAC_SEND_PAUSE: get_bmac_reg_name = "MAC_SEND_PAUSE";
540 BTxMAC_STATUS: get_bmac_reg_name = "BTxMAC_STATUS";
541 BRxMAC_STATUS: get_bmac_reg_name = "BRxMAC_STATUS";
542 BMAC_CTRL_STAT: get_bmac_reg_name = "BMAC_CTRL_STAT";
543 BTxMAC_STAT_MSK: get_bmac_reg_name = "BTxMAC_STAT_MSK";
544 BRxMAC_STAT_MSK: get_bmac_reg_name = "BRxMAC_STAT_MSK";
545 BMAC_C_S_MSK: get_bmac_reg_name = "BMAC_C_S_MSK";
546 TxMAC_CONFIG: get_bmac_reg_name = "TxMAC_CONFIG";
547 RxMAC_CONFIG: get_bmac_reg_name = "RxMAC_CONFIG";
548 MAC_CTRL_CONFIG: get_bmac_reg_name = "MAC_CTRL_CONFIG";
549 MAC_XIF_CONFIG: get_bmac_reg_name = "MAC_XIF_CONFIG";
550 MAC_IPG0: get_bmac_reg_name = "MAC_IPG0";
551 MAC_IPG1: get_bmac_reg_name = "MAC_IPG1";
552 MAC_IPG2: get_bmac_reg_name = "MAC_IPG2";
553 MAC_SLOT_TIME: get_bmac_reg_name = "MAC_SLOT_TIME";
554 BMAC_MIN: get_bmac_reg_name = "BMAC_MIN";
555 BMAC_MAX: get_bmac_reg_name = "BMAC_MAX";
556 MAC_PA_SIZE: get_bmac_reg_name = "MAC_PA_SIZE";
557 MAC_JAM_SIZE: get_bmac_reg_name = "MAC_JAM_SIZE";
558 MAC_ATTMPT_LMT: get_bmac_reg_name = "MAC_ATTMPT_LMT";
559 MAC_CTRL_TYPE: get_bmac_reg_name = "MAC_CTRL_TYPE";
560 BMAC_ADDR0: get_bmac_reg_name = "BMAC_ADDR0";
561 BMAC_ADDR1: get_bmac_reg_name = "BMAC_ADDR1";
562 BMAC_ADDR2: get_bmac_reg_name = "BMAC_ADDR2";
563 MAC_ADDR3: get_bmac_reg_name = "MAC_ADDR3";
564 MAC_ADDR4: get_bmac_reg_name = "MAC_ADDR4";
565 MAC_ADDR5: get_bmac_reg_name = "MAC_ADDR5";
566 MAC_ADDR6: get_bmac_reg_name = "MAC_ADDR6";
567 MAC_ADDR7: get_bmac_reg_name = "MAC_ADDR7";
568 MAC_ADDR8: get_bmac_reg_name = "MAC_ADDR8";
569 MAC_ADDR9: get_bmac_reg_name = "MAC_ADDR9";
570 MAC_ADDR10: get_bmac_reg_name = "MAC_ADDR10";
571 MAC_ADDR11: get_bmac_reg_name = "MAC_ADDR11";
572 MAC_ADDR12: get_bmac_reg_name = "MAC_ADDR12";
573 MAC_ADDR13: get_bmac_reg_name = "MAC_ADDR13";
574 MAC_ADDR14: get_bmac_reg_name = "MAC_ADDR14";
575 MAC_ADDR15: get_bmac_reg_name = "MAC_ADDR15";
576 MAC_ADDR16: get_bmac_reg_name = "MAC_ADDR16";
577 MAC_ADDR17: get_bmac_reg_name = "MAC_ADDR17";
578 MAC_ADDR18: get_bmac_reg_name = "MAC_ADDR18";
579 MAC_ADDR19: get_bmac_reg_name = "MAC_ADDR19";
580 MAC_ADDR20: get_bmac_reg_name = "MAC_ADDR20";
581 MAC_ADDR21: get_bmac_reg_name = "MAC_ADDR21";
582 MAC_ADDR22: get_bmac_reg_name = "MAC_ADDR22";
583 MAC_ADDR23: get_bmac_reg_name = "MAC_ADDR23";
584 MAC_ADDR24: get_bmac_reg_name = "MAC_ADDR24";
585 MAC_ADDR25: get_bmac_reg_name = "MAC_ADDR25";
586 MAC_ADDR26: get_bmac_reg_name = "MAC_ADDR26";
587 MAC_ADDR27: get_bmac_reg_name = "MAC_ADDR27";
588 MAC_ADDR28: get_bmac_reg_name = "MAC_ADDR28";
589 MAC_ADDR29: get_bmac_reg_name = "MAC_ADDR29";
590 MAC_ADDR30: get_bmac_reg_name = "MAC_ADDR30";
591 MAC_ADDR31: get_bmac_reg_name = "MAC_ADDR31";
592 MAC_ADDR32: get_bmac_reg_name = "MAC_ADDR32";
593 MAC_ADDR33: get_bmac_reg_name = "MAC_ADDR33";
594 MAC_ADDR34: get_bmac_reg_name = "MAC_ADDR34";
595 MAC_ADDR35: get_bmac_reg_name = "MAC_ADDR35";
596 MAC_ADDR36: get_bmac_reg_name = "MAC_ADDR36";
597 MAC_ADDR37: get_bmac_reg_name = "MAC_ADDR37";
598 MAC_ADDR38: get_bmac_reg_name = "MAC_ADDR38";
599 MAC_ADDR39: get_bmac_reg_name = "MAC_ADDR39";
600 MAC_ADDR40: get_bmac_reg_name = "MAC_ADDR40";
601 MAC_ADDR41: get_bmac_reg_name = "MAC_ADDR41";
602 MAC_ADDR42: get_bmac_reg_name = "MAC_ADDR42";
603 MAC_ADDR43: get_bmac_reg_name = "MAC_ADDR43";
604 MAC_ADDR44: get_bmac_reg_name = "MAC_ADDR44";
605 MAC_FC_ADDR0: get_bmac_reg_name = "MAC_FC_ADDR0";
606 MAC_FC_ADDR1: get_bmac_reg_name = "MAC_FC_ADDR1";
607 MAC_FC_ADDR2: get_bmac_reg_name = "MAC_FC_ADDR2";
608 MAC_ADD_FILT0: get_bmac_reg_name = "MAC_ADD_FILT0";
609 MAC_ADD_FILT1: get_bmac_reg_name = "MAC_ADD_FILT1";
610 MAC_ADD_FILT2: get_bmac_reg_name = "MAC_ADD_FILT2";
611 MAC_ADD_FILT12_MASK: get_bmac_reg_name = "MAC_ADD_FILT12_MASK";
612 MAC_ADD_FILT00_MASK: get_bmac_reg_name = "MAC_ADD_FILT00_MASK";
613 MAC_HASH_TBL0: get_bmac_reg_name = "MAC_HASH_TBL0";
614 MAC_HASH_TBL1: get_bmac_reg_name = "MAC_HASH_TBL1";
615 MAC_HASH_TBL2: get_bmac_reg_name = "MAC_HASH_TBL2";
616 MAC_HASH_TBL3: get_bmac_reg_name = "MAC_HASH_TBL3";
617 MAC_HASH_TBL4: get_bmac_reg_name = "MAC_HASH_TBL4";
618 MAC_HASH_TBL5: get_bmac_reg_name = "MAC_HASH_TBL5";
619 MAC_HASH_TBL6: get_bmac_reg_name = "MAC_HASH_TBL6";
620 MAC_HASH_TBL7: get_bmac_reg_name = "MAC_HASH_TBL7";
621 MAC_HASH_TBL8: get_bmac_reg_name = "MAC_HASH_TBL8";
622 MAC_HASH_TBL9: get_bmac_reg_name = "MAC_HASH_TBL9";
623 MAC_HASH_TBL10: get_bmac_reg_name = "MAC_HASH_TBL10";
624 MAC_HASH_TBL11: get_bmac_reg_name = "MAC_HASH_TBL11";
625 MAC_HASH_TBL12: get_bmac_reg_name = "MAC_HASH_TBL12";
626 MAC_HASH_TBL13: get_bmac_reg_name = "MAC_HASH_TBL13";
627 MAC_HASH_TBL14: get_bmac_reg_name = "MAC_HASH_TBL14";
628 MAC_HASH_TBL15: get_bmac_reg_name = "MAC_HASH_TBL15";
629 BMAC_COL_CNT: get_bmac_reg_name = "BMAC_COL_CNT";
630 BMAC_OA_COL_CNT: get_bmac_reg_name = "BMAC_OA_COL_CNT";
631 BMAC_EX_COL_CNT: get_bmac_reg_name = "BMAC_EX_COL_CNT";
632 BMAC_LT_COL_CNT: get_bmac_reg_name = "BMAC_LT_COL_CNT";
633 MAC_DEF_TIMER: get_bmac_reg_name = "MAC_DEF_TIMER";
634 BMAC_PK_ATT_CNT: get_bmac_reg_name = "BMAC_PK_ATT_CNT";
635 BRxMAC_FRM_CNT: get_bmac_reg_name = "BRxMAC_FRM_CNT";
636 MAC_LEN_ER_CNT: get_bmac_reg_name = "MAC_LEN_ER_CNT";
637 BMAC_AL_ER_CNT: get_bmac_reg_name = "BMAC_AL_ER_CNT";
638 BMAC_CRC_ER_CNT: get_bmac_reg_name = "BMAC_CRC_ER_CNT";
639 BMAC_CD_VIO_CNT: get_bmac_reg_name = "BMAC_CD_VIO_CNT";
640 MAC_RND_SEED: get_bmac_reg_name = "MAC_RND_SEED";
641 BMAC_SM_REG: get_bmac_reg_name = "BMAC_SM_REG";
642 BMAC_ALTAD_CMPEN: get_bmac_reg_name = "BMAC_ALTAD_CMPEN";
643 BMAC_HOST_INFO: get_bmac_reg_name = "BMAC_HOST_INFO";
644 BMAC_HOST_INF1: get_bmac_reg_name = "BMAC_HOST_INF1";
645 BMAC_HOST_INF2: get_bmac_reg_name = "BMAC_HOST_INF2";
646 BMAC_HOST_INF3: get_bmac_reg_name = "BMAC_HOST_INF3";
647 BMAC_HOST_INF4: get_bmac_reg_name = "BMAC_HOST_INF4";
648 BMAC_HOST_INF5: get_bmac_reg_name = "BMAC_HOST_INF5";
649 BMAC_HOST_INF6: get_bmac_reg_name = "BMAC_HOST_INF6";
650 BMAC_HOST_INF7: get_bmac_reg_name = "BMAC_HOST_INF7";
651 BTxMAC_BYTE_CNT: get_bmac_reg_name = "BTxMAC_BYTE_CNT";
652 BTxMAC_FRM_CNT: get_bmac_reg_name = "BTxMAC_FRM_CNT";
653 BRxMAC_BYTE_CNT: get_bmac_reg_name = "BRxMAC_BYTE_CNT";
654 }
655}
656
657function bit[32:0] bmac_util_class :: get_bmac_reg_adr(integer id) {
658 case(id) {
659 0: get_bmac_reg_adr = BTxMAC_SW_RST;
660 1: get_bmac_reg_adr = BRxMAC_SW_RST;
661 2: get_bmac_reg_adr = MAC_SEND_PAUSE;
662 //3: get_bmac_reg_adr = BTxMAC_STATUS;
663 //4: get_bmac_reg_adr = BRxMAC_STATUS;
664 //5: get_bmac_reg_adr = BMAC_CTRL_STAT;
665 3: get_bmac_reg_adr = BTxMAC_STAT_MSK;
666 4: get_bmac_reg_adr = BRxMAC_STAT_MSK;
667 5: get_bmac_reg_adr = BMAC_C_S_MSK;
668 6: get_bmac_reg_adr = TxMAC_CONFIG;
669 7: get_bmac_reg_adr = RxMAC_CONFIG;
670 8: get_bmac_reg_adr = MAC_CTRL_CONFIG;
671 9: get_bmac_reg_adr = MAC_XIF_CONFIG;
672 10: get_bmac_reg_adr = MAC_IPG0;
673 11: get_bmac_reg_adr = MAC_IPG1;
674 12: get_bmac_reg_adr = MAC_IPG2;
675 13: get_bmac_reg_adr = MAC_SLOT_TIME;
676 14: get_bmac_reg_adr = BMAC_MIN;
677 15: get_bmac_reg_adr = BMAC_MAX;
678 16: get_bmac_reg_adr = MAC_PA_SIZE;
679 17: get_bmac_reg_adr = MAC_JAM_SIZE;
680 18: get_bmac_reg_adr = MAC_ATTMPT_LMT;
681 19: get_bmac_reg_adr = MAC_CTRL_TYPE;
682 20: get_bmac_reg_adr = BMAC_ADDR0;
683 21: get_bmac_reg_adr = BMAC_ADDR1;
684 22: get_bmac_reg_adr = BMAC_ADDR2;
685 23: get_bmac_reg_adr = MAC_ADDR3;
686 24: get_bmac_reg_adr = MAC_ADDR4;
687 25: get_bmac_reg_adr = MAC_ADDR5;
688 26: get_bmac_reg_adr = MAC_ADDR6;
689 27: get_bmac_reg_adr = MAC_ADDR7;
690 28: get_bmac_reg_adr = MAC_ADDR8;
691 29: get_bmac_reg_adr = MAC_ADDR9;
692 30: get_bmac_reg_adr = MAC_ADDR10;
693 31: get_bmac_reg_adr = MAC_ADDR11;
694 32: get_bmac_reg_adr = MAC_ADDR12;
695 33: get_bmac_reg_adr = MAC_ADDR13;
696 34: get_bmac_reg_adr = MAC_ADDR14;
697 35: get_bmac_reg_adr = MAC_ADDR15;
698 36: get_bmac_reg_adr = MAC_ADDR16;
699 37: get_bmac_reg_adr = MAC_ADDR17;
700 38: get_bmac_reg_adr = MAC_ADDR18;
701 39: get_bmac_reg_adr = MAC_ADDR19;
702 40: get_bmac_reg_adr = MAC_ADDR20;
703 41: get_bmac_reg_adr = MAC_ADDR21;
704 42: get_bmac_reg_adr = MAC_ADDR22;
705 43: get_bmac_reg_adr = MAC_ADDR23;
706 44: get_bmac_reg_adr = MAC_ADDR24;
707 45: get_bmac_reg_adr = MAC_ADDR25;
708 46: get_bmac_reg_adr = MAC_ADDR26;
709 47: get_bmac_reg_adr = MAC_ADDR27;
710 48: get_bmac_reg_adr = MAC_ADDR28;
711 49: get_bmac_reg_adr = MAC_ADDR29;
712 50: get_bmac_reg_adr = MAC_ADDR30;
713 51: get_bmac_reg_adr = MAC_ADDR31;
714 52: get_bmac_reg_adr = MAC_ADDR32;
715 53: get_bmac_reg_adr = MAC_ADDR33;
716 54: get_bmac_reg_adr = MAC_ADDR34;
717 55: get_bmac_reg_adr = MAC_ADDR35;
718 56: get_bmac_reg_adr = MAC_ADDR36;
719 57: get_bmac_reg_adr = MAC_ADDR37;
720 58: get_bmac_reg_adr = MAC_ADDR38;
721 59: get_bmac_reg_adr = MAC_ADDR39;
722 60: get_bmac_reg_adr = MAC_ADDR40;
723 61: get_bmac_reg_adr = MAC_ADDR41;
724 62: get_bmac_reg_adr = MAC_ADDR42;
725 63: get_bmac_reg_adr = MAC_ADDR43;
726 64: get_bmac_reg_adr = MAC_ADDR44;
727 65: get_bmac_reg_adr = MAC_FC_ADDR0;
728 66: get_bmac_reg_adr = MAC_FC_ADDR1;
729 67: get_bmac_reg_adr = MAC_FC_ADDR2;
730 68: get_bmac_reg_adr = MAC_ADD_FILT0;
731 69: get_bmac_reg_adr = MAC_ADD_FILT1;
732 70: get_bmac_reg_adr = MAC_ADD_FILT2;
733 71: get_bmac_reg_adr = MAC_ADD_FILT12_MASK;
734 72: get_bmac_reg_adr = MAC_ADD_FILT00_MASK;
735 73: get_bmac_reg_adr = MAC_HASH_TBL0;
736 74: get_bmac_reg_adr = MAC_HASH_TBL1;
737 75: get_bmac_reg_adr = MAC_HASH_TBL2;
738 76: get_bmac_reg_adr = MAC_HASH_TBL3;
739 77: get_bmac_reg_adr = MAC_HASH_TBL4;
740 78: get_bmac_reg_adr = MAC_HASH_TBL5;
741 79: get_bmac_reg_adr = MAC_HASH_TBL6;
742 80: get_bmac_reg_adr = MAC_HASH_TBL7;
743 81: get_bmac_reg_adr = MAC_HASH_TBL8;
744 82: get_bmac_reg_adr = MAC_HASH_TBL9;
745 83: get_bmac_reg_adr = MAC_HASH_TBL10;
746 84: get_bmac_reg_adr = MAC_HASH_TBL11;
747 85: get_bmac_reg_adr = MAC_HASH_TBL12;
748 86: get_bmac_reg_adr = MAC_HASH_TBL13;
749 87: get_bmac_reg_adr = MAC_HASH_TBL14;
750 88: get_bmac_reg_adr = MAC_HASH_TBL15;
751 89: get_bmac_reg_adr = BMAC_COL_CNT;
752 90: get_bmac_reg_adr = BMAC_OA_COL_CNT;
753 91: get_bmac_reg_adr = BMAC_EX_COL_CNT;
754 92: get_bmac_reg_adr = BMAC_LT_COL_CNT;
755 93: get_bmac_reg_adr = MAC_DEF_TIMER;
756 //97: get_bmac_reg_adr = BMAC_PK_ATT_CNT;
757 94: get_bmac_reg_adr = BRxMAC_FRM_CNT;
758 95: get_bmac_reg_adr = MAC_LEN_ER_CNT;
759 96: get_bmac_reg_adr = BMAC_AL_ER_CNT;
760 97: get_bmac_reg_adr = BMAC_CRC_ER_CNT;
761 98: get_bmac_reg_adr = BMAC_CD_VIO_CNT;
762 99: get_bmac_reg_adr = MAC_RND_SEED;
763 //104: get_bmac_reg_adr = BMAC_SM_REG;
764 100: get_bmac_reg_adr = BMAC_ALTAD_CMPEN;
765 101: get_bmac_reg_adr = BMAC_HOST_INFO;
766 102: get_bmac_reg_adr = BMAC_HOST_INF1;
767 103: get_bmac_reg_adr = BMAC_HOST_INF2;
768 104: get_bmac_reg_adr = BMAC_HOST_INF3;
769 105: get_bmac_reg_adr = BMAC_HOST_INF4;
770 106: get_bmac_reg_adr = BMAC_HOST_INF5;
771 107: get_bmac_reg_adr = BMAC_HOST_INF6;
772 108: get_bmac_reg_adr = BMAC_HOST_INF7;
773 109: get_bmac_reg_adr = BTxMAC_BYTE_CNT;
774 110: get_bmac_reg_adr = BTxMAC_FRM_CNT;
775 111: get_bmac_reg_adr = BRxMAC_BYTE_CNT;
776 112: get_bmac_reg_adr = BMAC_SM_REG;
777
778 default: error("Error: Invalid register ID (%0d) for get_bmac_reg_adr.\n",id);
779 }
780}
781
782function bit[32:0] bmac_util_class :: bmac_reg_addr (integer sel) {
783 integer n,m;
784 bit [39:0] base_addr;
785
786 n = sel%BMAC_TOTAL_REGS;
787 m = (sel-n) / BMAC_TOTAL_REGS;
788
789 base_addr = get_mac_reg_base(m);
790 bmac_reg_addr = base_addr + get_bmac_reg_adr(n);
791}
792
793
794function bit[31:0] bmac_util_class :: bmac_reg_mask (integer sel) {
795 integer n;
796
797 n = sel%BMAC_TOTAL_REGS;
798
799 case(n) {
800
801 0: bmac_reg_mask = BTxMAC_SW_RST_MASK;
802 1: bmac_reg_mask = BRxMAC_SW_RST_MASK;
803 2: bmac_reg_mask = MAC_SEND_PAUSE_MASK;
804 // 3: bmac_reg_mask = BTxMAC_STATUS_MASK;
805 // 4: bmac_reg_mask = BRxMAC_STATUS_MASK;
806 //5: bmac_reg_mask = BMAC_CTRL_STAT_MASK;
807 3: bmac_reg_mask = BTxMAC_STAT_MSK_MASK;
808 4: bmac_reg_mask = BRxMAC_STAT_MSK_MASK;
809 5: bmac_reg_mask = BMAC_C_S_MSK_MASK;
810 6: bmac_reg_mask = TxMAC_CONFIG_MASK;
811 7: bmac_reg_mask = RxMAC_CONFIG_MASK;
812 8: bmac_reg_mask = MAC_CTRL_CONFIG_MASK;
813 9: bmac_reg_mask = MAC_XIF_CONFIG_MASK;
814 10: bmac_reg_mask = MAC_IPG0_MASK;
815 11: bmac_reg_mask = MAC_IPG1_MASK;
816 12: bmac_reg_mask = MAC_IPG2_MASK;
817 13: bmac_reg_mask = MAC_SLOT_TIME_MASK;
818 14: bmac_reg_mask = BMAC_MIN_MASK;
819 15: bmac_reg_mask = BMAC_MAX_MASK;
820 16: bmac_reg_mask = MAC_PA_SIZE_MASK;
821 17: bmac_reg_mask = MAC_JAM_SIZE_MASK;
822 18: bmac_reg_mask = MAC_ATTMPT_LMT_MASK;
823 19: bmac_reg_mask = MAC_CTRL_TYPE_MASK;
824 20: bmac_reg_mask = BMAC_ADDR0_MASK;
825 21: bmac_reg_mask = BMAC_ADDR1_MASK;
826 22: bmac_reg_mask = BMAC_ADDR2_MASK;
827 23: bmac_reg_mask = MAC_ADDR3_MASK;
828 24: bmac_reg_mask = MAC_ADDR4_MASK;
829 25: bmac_reg_mask = MAC_ADDR5_MASK;
830 26: bmac_reg_mask = MAC_ADDR6_MASK;
831 27: bmac_reg_mask = MAC_ADDR7_MASK;
832 28: bmac_reg_mask = MAC_ADDR8_MASK;
833 29: bmac_reg_mask = MAC_ADDR9_MASK;
834 30: bmac_reg_mask = MAC_ADDR10_MASK;
835 31: bmac_reg_mask = MAC_ADDR11_MASK;
836 32: bmac_reg_mask = MAC_ADDR12_MASK;
837 33: bmac_reg_mask = MAC_ADDR13_MASK;
838 34: bmac_reg_mask = MAC_ADDR14_MASK;
839 35: bmac_reg_mask = MAC_ADDR15_MASK;
840 36: bmac_reg_mask = MAC_ADDR16_MASK;
841 37: bmac_reg_mask = MAC_ADDR17_MASK;
842 38: bmac_reg_mask = MAC_ADDR18_MASK;
843 39: bmac_reg_mask = MAC_ADDR19_MASK;
844 40: bmac_reg_mask = MAC_ADDR20_MASK;
845 41: bmac_reg_mask = MAC_ADDR21_MASK;
846 42: bmac_reg_mask = MAC_ADDR22_MASK;
847 43: bmac_reg_mask = MAC_ADDR23_MASK;
848 44: bmac_reg_mask = MAC_ADDR24_MASK;
849 45: bmac_reg_mask = MAC_ADDR25_MASK;
850 46: bmac_reg_mask = MAC_ADDR26_MASK;
851 47: bmac_reg_mask = MAC_ADDR27_MASK;
852 48: bmac_reg_mask = MAC_ADDR28_MASK;
853 49: bmac_reg_mask = MAC_ADDR29_MASK;
854 50: bmac_reg_mask = MAC_ADDR30_MASK;
855 51: bmac_reg_mask = MAC_ADDR31_MASK;
856 52: bmac_reg_mask = MAC_ADDR32_MASK;
857 53: bmac_reg_mask = MAC_ADDR33_MASK;
858 54: bmac_reg_mask = MAC_ADDR34_MASK;
859 55: bmac_reg_mask = MAC_ADDR35_MASK;
860 56: bmac_reg_mask = MAC_ADDR36_MASK;
861 57: bmac_reg_mask = MAC_ADDR37_MASK;
862 58: bmac_reg_mask = MAC_ADDR38_MASK;
863 59: bmac_reg_mask = MAC_ADDR39_MASK;
864 60: bmac_reg_mask = MAC_ADDR40_MASK;
865 61: bmac_reg_mask = MAC_ADDR41_MASK;
866 62: bmac_reg_mask = MAC_ADDR42_MASK;
867 63: bmac_reg_mask = MAC_ADDR43_MASK;
868 64: bmac_reg_mask = MAC_ADDR44_MASK;
869 65: bmac_reg_mask = MAC_FC_ADDR0_MASK;
870 66: bmac_reg_mask = MAC_FC_ADDR1_MASK;
871 67: bmac_reg_mask = MAC_FC_ADDR2_MASK;
872 68: bmac_reg_mask = MAC_ADD_FILT0_MASK;
873 69: bmac_reg_mask = MAC_ADD_FILT1_MASK;
874 70: bmac_reg_mask = MAC_ADD_FILT2_MASK;
875 71: bmac_reg_mask = MAC_ADD_FILT12_MASK_MASK;
876 72: bmac_reg_mask = MAC_ADD_FILT00_MASK_MASK;
877 73: bmac_reg_mask = MAC_HASH_TBL0_MASK;
878 74: bmac_reg_mask = MAC_HASH_TBL1_MASK;
879 75: bmac_reg_mask = MAC_HASH_TBL2_MASK;
880 76: bmac_reg_mask = MAC_HASH_TBL3_MASK;
881 77: bmac_reg_mask = MAC_HASH_TBL4_MASK;
882 78: bmac_reg_mask = MAC_HASH_TBL5_MASK;
883 79: bmac_reg_mask = MAC_HASH_TBL6_MASK;
884 80: bmac_reg_mask = MAC_HASH_TBL7_MASK;
885 81: bmac_reg_mask = MAC_HASH_TBL8_MASK;
886 82: bmac_reg_mask = MAC_HASH_TBL9_MASK;
887 83: bmac_reg_mask = MAC_HASH_TBL10_MASK;
888 84: bmac_reg_mask = MAC_HASH_TBL11_MASK;
889 85: bmac_reg_mask = MAC_HASH_TBL12_MASK;
890 86: bmac_reg_mask = MAC_HASH_TBL13_MASK;
891 87: bmac_reg_mask = MAC_HASH_TBL14_MASK;
892 88: bmac_reg_mask = MAC_HASH_TBL15_MASK;
893 89: bmac_reg_mask = BMAC_COL_CNT_MASK;
894 90: bmac_reg_mask = BMAC_OA_COL_CNT_MASK;
895 91: bmac_reg_mask = BMAC_EX_COL_CNT_MASK;
896 92: bmac_reg_mask = BMAC_LT_COL_CNT_MASK;
897 93: bmac_reg_mask = MAC_DEF_TIMER_MASK;
898 //94: bmac_reg_mask = BMAC_PK_ATT_CNT_MASK;
899 94: bmac_reg_mask = BRxMAC_FRM_CNT_MASK;
900 95: bmac_reg_mask = MAC_LEN_ER_CNT_MASK;
901 96: bmac_reg_mask = BMAC_AL_ER_CNT_MASK;
902 97: bmac_reg_mask = BMAC_CRC_ER_CNT_MASK;
903 98: bmac_reg_mask = BMAC_CD_VIO_CNT_MASK;
904 99: bmac_reg_mask = MAC_RND_SEED_MASK;
905 //104: bmac_reg_mask = BMAC_SM_REG_MASK;
906 100: bmac_reg_mask = BMAC_ALTAD_CMPEN_MASK;
907 101: bmac_reg_mask = BMAC_HOST_INFO0_MASK;
908 102: bmac_reg_mask = BMAC_HOST_INFO1_MASK;
909 103: bmac_reg_mask = BMAC_HOST_INFO2_MASK;
910 104: bmac_reg_mask = BMAC_HOST_INFO3_MASK;
911 105: bmac_reg_mask = BMAC_HOST_INFO4_MASK;
912 106: bmac_reg_mask = BMAC_HOST_INFO5_MASK;
913 107: bmac_reg_mask = BMAC_HOST_INFO6_MASK;
914 108: bmac_reg_mask = BMAC_HOST_INFO7_MASK;
915 109: bmac_reg_mask = BTxMAC_BYTE_CNT_MASK;
916 110: bmac_reg_mask = BTxMAC_FRM_CNT_MASK;
917 111: bmac_reg_mask = BRxMAC_BYTE_CNT_MASK;
918 112: bmac_reg_mask = BMAC_SM_REG_MASK;
919
920
921
922 }
923}
924
925function bit[31:0] bmac_util_class :: bmac_reg_default (integer sel) {
926 integer n;
927
928 n = sel%BMAC_TOTAL_REGS;
929
930 case(n) {
931
932 0: bmac_reg_default = BTxMAC_SW_RST_DEFAULT;
933 1: bmac_reg_default = BRxMAC_SW_RST_DEFAULT;
934 2: bmac_reg_default = MAC_SEND_PAUSE_DEFAULT;
935 //3: bmac_reg_default = BTxMAC_STATUS_DEFAULT;
936 //4: bmac_reg_default = BRxMAC_STATUS_DEFAULT;
937 //5: bmac_reg_default = BMAC_CTRL_STAT_DEFAULT;
938 3: bmac_reg_default = BTxMAC_STAT_MSK_DEFAULT;
939 4: bmac_reg_default = BRxMAC_STAT_MSK_DEFAULT;
940 5: bmac_reg_default = BMAC_C_S_MSK_DEFAULT;
941 6: bmac_reg_default = TxMAC_CONFIG_DEFAULT;
942 7: bmac_reg_default = RxMAC_CONFIG_DEFAULT;
943 8: bmac_reg_default = MAC_CTRL_CONFIG_DEFAULT;
944 9: bmac_reg_default = MAC_XIF_CONFIG_DEFAULT;
945 10: bmac_reg_default = MAC_IPG0_DEFAULT;
946 11: bmac_reg_default = MAC_IPG1_DEFAULT;
947 12: bmac_reg_default = MAC_IPG2_DEFAULT;
948 13: bmac_reg_default = MAC_SLOT_TIME_DEFAULT;
949 14: bmac_reg_default = BMAC_MIN_DEFAULT;
950 15: bmac_reg_default = BMAC_MAX_DEFAULT;
951 16: bmac_reg_default = MAC_PA_SIZE_DEFAULT;
952 17: bmac_reg_default = MAC_JAM_SIZE_DEFAULT;
953 18: bmac_reg_default = MAC_ATTMPT_LMT_DEFAULT;
954 19: bmac_reg_default = MAC_CTRL_TYPE_DEFAULT;
955 20: bmac_reg_default = BMAC_ADDR0_DEFAULT;
956 21: bmac_reg_default = BMAC_ADDR1_DEFAULT;
957 22: bmac_reg_default = BMAC_ADDR2_DEFAULT;
958 23: bmac_reg_default = MAC_ADDR3_DEFAULT;
959 24: bmac_reg_default = MAC_ADDR4_DEFAULT;
960 25: bmac_reg_default = MAC_ADDR5_DEFAULT;
961 26: bmac_reg_default = MAC_ADDR6_DEFAULT;
962 27: bmac_reg_default = MAC_ADDR7_DEFAULT;
963 28: bmac_reg_default = MAC_ADDR8_DEFAULT;
964 29: bmac_reg_default = MAC_ADDR9_DEFAULT;
965 30: bmac_reg_default = MAC_ADDR10_DEFAULT;
966 31: bmac_reg_default = MAC_ADDR11_DEFAULT;
967 32: bmac_reg_default = MAC_ADDR12_DEFAULT;
968 33: bmac_reg_default = MAC_ADDR13_DEFAULT;
969 34: bmac_reg_default = MAC_ADDR14_DEFAULT;
970 35: bmac_reg_default = MAC_ADDR15_DEFAULT;
971 36: bmac_reg_default = MAC_ADDR16_DEFAULT;
972 37: bmac_reg_default = MAC_ADDR17_DEFAULT;
973 38: bmac_reg_default = MAC_ADDR18_DEFAULT;
974 39: bmac_reg_default = MAC_ADDR19_DEFAULT;
975 40: bmac_reg_default = MAC_ADDR20_DEFAULT;
976 41: bmac_reg_default = MAC_ADDR21_DEFAULT;
977 42: bmac_reg_default = MAC_ADDR22_DEFAULT;
978 43: bmac_reg_default = MAC_ADDR23_DEFAULT;
979 44: bmac_reg_default = MAC_ADDR24_DEFAULT;
980 45: bmac_reg_default = MAC_ADDR25_DEFAULT;
981 46: bmac_reg_default = MAC_ADDR26_DEFAULT;
982 47: bmac_reg_default = MAC_ADDR27_DEFAULT;
983 48: bmac_reg_default = MAC_ADDR28_DEFAULT;
984 49: bmac_reg_default = MAC_ADDR29_DEFAULT;
985 50: bmac_reg_default = MAC_ADDR30_DEFAULT;
986 51: bmac_reg_default = MAC_ADDR31_DEFAULT;
987 52: bmac_reg_default = MAC_ADDR32_DEFAULT;
988 53: bmac_reg_default = MAC_ADDR33_DEFAULT;
989 54: bmac_reg_default = MAC_ADDR34_DEFAULT;
990 55: bmac_reg_default = MAC_ADDR35_DEFAULT;
991 56: bmac_reg_default = MAC_ADDR36_DEFAULT;
992 57: bmac_reg_default = MAC_ADDR37_DEFAULT;
993 58: bmac_reg_default = MAC_ADDR38_DEFAULT;
994 59: bmac_reg_default = MAC_ADDR39_DEFAULT;
995 60: bmac_reg_default = MAC_ADDR40_DEFAULT;
996 61: bmac_reg_default = MAC_ADDR41_DEFAULT;
997 62: bmac_reg_default = MAC_ADDR42_DEFAULT;
998 63: bmac_reg_default = MAC_ADDR43_DEFAULT;
999 64: bmac_reg_default = MAC_ADDR44_DEFAULT;
1000 65: bmac_reg_default = MAC_FC_ADDR0_DEFAULT;
1001 66: bmac_reg_default = MAC_FC_ADDR1_DEFAULT;
1002 67: bmac_reg_default = MAC_FC_ADDR2_DEFAULT;
1003 68: bmac_reg_default = MAC_ADD_FILT0_DEFAULT;
1004 69: bmac_reg_default = MAC_ADD_FILT1_DEFAULT;
1005 70: bmac_reg_default = MAC_ADD_FILT2_DEFAULT;
1006 71: bmac_reg_default = MAC_ADD_FILT12_MASK_DEFAULT;
1007 72: bmac_reg_default = MAC_ADD_FILT00_MASK_DEFAULT;
1008 73: bmac_reg_default = MAC_HASH_TBL0_DEFAULT;
1009 74: bmac_reg_default = MAC_HASH_TBL1_DEFAULT;
1010 75: bmac_reg_default = MAC_HASH_TBL2_DEFAULT;
1011 76: bmac_reg_default = MAC_HASH_TBL3_DEFAULT;
1012 77: bmac_reg_default = MAC_HASH_TBL4_DEFAULT;
1013 78: bmac_reg_default = MAC_HASH_TBL5_DEFAULT;
1014 79: bmac_reg_default = MAC_HASH_TBL6_DEFAULT;
1015 80: bmac_reg_default = MAC_HASH_TBL7_DEFAULT;
1016 81: bmac_reg_default = MAC_HASH_TBL8_DEFAULT;
1017 82: bmac_reg_default = MAC_HASH_TBL9_DEFAULT;
1018 83: bmac_reg_default = MAC_HASH_TBL10_DEFAULT;
1019 84: bmac_reg_default = MAC_HASH_TBL11_DEFAULT;
1020 85: bmac_reg_default = MAC_HASH_TBL12_DEFAULT;
1021 86: bmac_reg_default = MAC_HASH_TBL13_DEFAULT;
1022 87: bmac_reg_default = MAC_HASH_TBL14_DEFAULT;
1023 88: bmac_reg_default = MAC_HASH_TBL15_DEFAULT;
1024 89: bmac_reg_default = BMAC_COL_CNT_DEFAULT;
1025 90: bmac_reg_default = BMAC_OA_COL_CNT_DEFAULT;
1026 91: bmac_reg_default = BMAC_EX_COL_CNT_DEFAULT;
1027 92: bmac_reg_default = BMAC_LT_COL_CNT_DEFAULT;
1028 93: bmac_reg_default = MAC_DEF_TIMER_DEFAULT;
1029 //97: bmac_reg_default = BMAC_PK_ATT_CNT_DEFAULT;
1030 94: bmac_reg_default = BRxMAC_FRM_CNT_DEFAULT;
1031 95: bmac_reg_default = MAC_LEN_ER_CNT_DEFAULT;
1032 96: bmac_reg_default = BMAC_AL_ER_CNT_DEFAULT;
1033 97: bmac_reg_default = BMAC_CRC_ER_CNT_DEFAULT;
1034 98: bmac_reg_default = BMAC_CD_VIO_CNT_DEFAULT;
1035 99: bmac_reg_default = MAC_RND_SEED_DEFAULT;
1036 //104: bmac_reg_default = BMAC_SM_REG_DEFAULT;
1037 100: bmac_reg_default = BMAC_ALTAD_CMPEN_DEFAULT;
1038 101: bmac_reg_default = MAC_HASH_TBL0_DEFAULT;
1039 102: bmac_reg_default = MAC_HASH_TBL1_DEFAULT;
1040 103: bmac_reg_default = MAC_HASH_TBL2_DEFAULT;
1041 104: bmac_reg_default = MAC_HASH_TBL3_DEFAULT;
1042 105: bmac_reg_default = MAC_HASH_TBL4_DEFAULT;
1043 106: bmac_reg_default = MAC_HASH_TBL5_DEFAULT;
1044 107: bmac_reg_default = MAC_HASH_TBL6_DEFAULT;
1045 108: bmac_reg_default = MAC_HASH_TBL7_DEFAULT;
1046 109: bmac_reg_default = BTxMAC_BYTE_CNT_DEFAULT;
1047 110: bmac_reg_default = BTxMAC_FRM_CNT_DEFAULT;
1048 111: bmac_reg_default = BRxMAC_BYTE_CNT_DEFAULT;
1049 112: bmac_reg_default = BMAC_SM_REG_DEFAULT;
1050
1051 }
1052}
1053
1054
1055function integer bmac_util_class :: flen(integer sel) {
1056 case(sel) {
1057
1058 00: flen = 22;
1059 01: flen = 23;
1060 02: flen = 27;
1061 03: flen = 28;
1062 04: flen = 29;
1063 05: flen = 30;
1064 06: flen = 31;
1065 07: flen = 34;
1066 08: flen = 35;
1067 09: flen = 38;
1068 10: flen = 39;
1069 11: flen = 40;
1070 12: flen = 41;
1071 13: flen = 45;
1072 14: flen = 46;
1073 15: flen = 49;
1074 16: flen = 50;
1075 17: flen = 51;
1076 18: flen = 52;
1077 19: flen = 53;
1078 20: flen = 54;
1079 21: flen = 55;
1080 22: flen = 56;
1081 23: flen = 57;
1082 24: flen = 58;
1083 25: flen = 59;
1084 26: flen = 60;
1085 27: flen = 61;
1086 28: flen = 62;
1087 29: flen = 63;
1088 30: flen = 64;
1089 31: flen = 65;
1090 32: flen = 66;
1091 33: flen = 67;
1092 34: flen = 68;
1093 35: flen = 69;
1094 36: flen = 70;
1095 37: flen = 71;
1096 38: flen = 72;
1097 39: flen = 87;
1098 40: flen = 88;
1099 41: flen = 89;
1100 42: flen = 90;
1101 43: flen = 91;
1102 44: flen = 93;
1103 45: flen = 95;
1104 46: flen = 98;
1105 47: flen = 99;
1106 48: flen = 100;
1107 49: flen = 101;
1108 50: flen = 102;
1109 51: flen = 103;
1110 52: flen = 500;
1111 53: flen = 501;
1112 54: flen = 502;
1113 55: flen = 503;
1114 56: flen = 504;
1115 57: flen = 505;
1116 58: flen = 506;
1117 59: flen = 507;
1118 60: flen = 508;
1119 61: flen = 509;
1120 62: flen = 510;
1121 63: flen = 511;
1122 64: flen = 512;
1123 65: flen = 513;
1124 66: flen = 514;
1125 67: flen = 515;
1126 68: flen = 516;
1127 69: flen = 517;
1128 70: flen = 1019;
1129 71: flen = 1020;
1130 72: flen = 1021;
1131 73: flen = 1022;
1132 74: flen = 1023;
1133 75: flen = 1024;
1134 76: flen = 1025;
1135 77: flen = 1026;
1136 78: flen = 1027;
1137 79: flen = 1028;
1138 80: flen = 1490;
1139 81: flen = 1491;
1140 82: flen = 1492;
1141 83: flen = 1493;
1142 84: flen = 1494;
1143 85: flen = 1495;
1144 86: flen = 1496;
1145 87: flen = 1497;
1146 88: flen = 1498;
1147 89: flen = 1499;
1148 90: flen = 1510;
1149 91: flen = 1511;
1150 92: flen = 1512;
1151 93: flen = 1513;
1152 94: flen = 1514;
1153 95: flen = 1515;
1154 96: flen = 1516;
1155 97: flen = 1517;
1156 98: flen = 1518;
1157 99: flen = 1519;
1158 100: flen = 1520;
1159 101: flen = 1521;
1160 102: flen = 1522;
1161 103: flen = 1523;
1162 104: flen = 1524;
1163 105: flen = 1525;
1164 106: flen = 1526;
1165 107: flen = 1527;
1166 108: flen = 1528;
1167 109: flen = 1529;
1168 110: flen = 1530;
1169 111: flen = 1531;
1170 112: flen = 1532;
1171 113: flen = 1533;
1172 114: flen = 1534;
1173 115: flen = 1535;
1174 }
1175}
1176
1177function integer bmac_util_class :: flen_j(integer sel) {
1178 case(sel) {
1179
1180 00: flen_j = 1800;
1181 01: flen_j = 4000;
1182 02: flen_j = 512;
1183 03: flen_j = 8000;
1184 04: flen_j = 128;
1185 05: flen_j = 7936;
1186 06: flen_j = 16000;
1187 07: flen_j = 341;
1188 08: flen_j = 13056;
1189 09: flen_j = 9237;
1190 }
1191}
1192
1193task bmac_util_class :: rx_pkt_count_check(integer pkt_count) {
1194
1195 bit [15:0] csr_rx_pkt_count;
1196 bit [31:0] cfg_rd_data;
1197 bit [31:0] rd_data;
1198 integer base_addr;
1199
1200
1201 if ( get_plus_arg(CHECK, "RX_TEST") ) {
1202 if ((get_plus_arg (CHECK, "GET_MAC_PORTS=0"))){
1203 base_addr = get_mac_reg_base(0);
1204 mac_pio_class.xmac_pio_rd( base_addr + XMAC_CONFIG, cfg_rd_data,1'b0 );
1205 if (cfg_rd_data[28:27] == 2'b01) {
1206 mac_pio_class.bmac_pio_rd(PCS0_BASE + PCS_PACKET_COUNTER,rd_data, 1'b0);
1207 csr_rx_pkt_count = rd_data[26:16];
1208 }
1209
1210 else if (cfg_rd_data[28:27] == 2'b00) {
1211 mac_pio_class.xmac_pio_rd(XPCS0_BASE + XPCS_PACKET_COUNTER,rd_data, 1'b0);
1212 csr_rx_pkt_count = rd_data[15:0];
1213 }
1214 }
1215
1216 else if ((get_plus_arg (CHECK, "GET_MAC_PORTS=1"))){
1217 base_addr = get_mac_reg_base(1);
1218 mac_pio_class.xmac_pio_rd( base_addr + XMAC_CONFIG, cfg_rd_data,1'b0 );
1219 if (cfg_rd_data[28:27] == 2'b01) {
1220 mac_pio_class.bmac_pio_rd(PCS1_BASE + PCS_PACKET_COUNTER,rd_data, 1'b0);
1221 csr_rx_pkt_count = rd_data[26:16];
1222 }
1223
1224 else if (cfg_rd_data[28:27] == 2'b00) {
1225 mac_pio_class.xmac_pio_rd(XPCS1_BASE + XPCS_PACKET_COUNTER,rd_data, 1'b0);
1226 csr_rx_pkt_count = rd_data[15:0];
1227 }
1228 }
1229
1230 if (csr_rx_pkt_count != pkt_count) {
1231 printf("ERROR :Rx Pkt Counter Error: Expected %0d Obeserved %0d \n", \
1232 pkt_count,csr_rx_pkt_count);
1233 }
1234 else
1235 printf("XPCS/PCS packet counter matches the no_of_packets\n");
1236 }
1237}
1238
1239task bmac_util_class :: tx_pkt_count_check(integer pkt_count) {
1240
1241 bit [15:0] csr_tx_pkt_count;
1242 bit [31:0] cfg_rd_data;
1243 bit [31:0] rd_data;
1244 integer base_addr;
1245
1246
1247 if ( get_plus_arg(CHECK, "TX_TEST") ) {
1248 if ((get_plus_arg (CHECK, "GET_MAC_PORTS=0"))){
1249 base_addr = get_mac_reg_base(0);
1250 mac_pio_class.xmac_pio_rd( base_addr + XMAC_CONFIG, cfg_rd_data,1'b0 );
1251 if (cfg_rd_data[28:27] == 2'b01) {
1252 mac_pio_class.bmac_pio_rd(PCS0_BASE + PCS_PACKET_COUNTER,rd_data, 1'b0);
1253 csr_tx_pkt_count = rd_data[10:0];
1254 }
1255
1256 else if (cfg_rd_data[28:27] == 2'b00) {
1257 mac_pio_class.xmac_pio_rd(XPCS0_BASE + XPCS_PACKET_COUNTER,rd_data, 1'b0);
1258 csr_tx_pkt_count = rd_data[31:16];
1259 }
1260 }
1261
1262 else if ((get_plus_arg (CHECK, "GET_MAC_PORTS=1"))){
1263 base_addr = get_mac_reg_base(1);
1264 mac_pio_class.xmac_pio_rd( base_addr + XMAC_CONFIG, cfg_rd_data,1'b0 );
1265 if (cfg_rd_data[28:27] == 2'b01) {
1266 mac_pio_class.bmac_pio_rd(PCS1_BASE + PCS_PACKET_COUNTER,rd_data, 1'b0);
1267 csr_tx_pkt_count = rd_data[10:0];
1268 }
1269
1270 else if (cfg_rd_data[28:27] == 2'b00) {
1271 mac_pio_class.xmac_pio_rd(XPCS1_BASE + XPCS_PACKET_COUNTER,rd_data, 1'b0);
1272 csr_tx_pkt_count = rd_data[31:16];
1273 }
1274 }
1275
1276 if (csr_tx_pkt_count != pkt_count) {
1277 printf("ERROR :Rx Pkt Counter Error: Expected %0d Obeserved %0d \n", \
1278 pkt_count,csr_tx_pkt_count);
1279 }
1280 else
1281 printf("XPCS/PCS packet counter matches the no_of_packets\n");
1282 }
1283}
1284
1285
1286
1287
1288
1289
1290/*
1291
1292 class RandPacketLen {
1293 rand {
1294 integer pack_len;
1295
1296 }
1297 // make the value of len evenly distributed between 20 and 1518
1298 constraint size_cons {
1299 pack_len in {20:1518 };
1300 }
1301 }
1302*/
1303
1304
Full OpenSPARC design & verification tarball including full HDL.