projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / niu / vera / niu_pio / esr_ti_init.vr
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: esr_ti_init.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36#include "cMesg.vrh"
37#include "mif_memory_map.vri"
38#include "niu_gen_pio.vrh"
39
40extern Mesg be_msg;
41extern niu_gen_pio gen_pio_drv;
42
43class esr_tiinit_util {
44
45 bit [31:0] get_port;
46 string str_port, temp_port;
47 integer port_num;
48 integer port_no[4];
49 integer port0_enb = 0;
50 integer port1_enb = 0;
51 integer mac_speed0,mac_speed1;
52
53
54 task new();
55 task serdes_init();
56 task wait_for_instr_comp();
57
58}
59
60task esr_tiinit_util :: new()
61{
62
63 integer i = 0;
64 if ( get_plus_arg(CHECK, "MAC_SPEED0=") )
65 {
66 mac_speed0 = get_plus_arg(NUM, "MAC_SPEED0") ;
67 printf("mac_init:INFO:MAC0 port is set %0d Speed\n" ,mac_speed0);
68 }
69 if ( get_plus_arg(CHECK, "MAC_SPEED1=") )
70 {
71 mac_speed1 = get_plus_arg(NUM, "MAC_SPEED1") ;
72 printf("mac_init:INFO:MAC1 port is set %0d Speed\n" ,mac_speed1);
73 }
74
75 if( get_plus_arg(CHECK,"GET_MAC_PORTS=")) {
76 get_port = get_plus_arg(STR,"GET_MAC_PORTS=");
77 printf("esr_ti_init_util : val of get_port is %h\n",get_port);
78
79 str_port.bittostr(get_port);
80 printf("esr_ti_init_util : val of LEN %0d\n",str_port.len());
81
82 for(i=0;i<str_port.len();i++) {
83 temp_port =str_port.substr(i,i);
84 port_no[i] = temp_port.atoi();
85 printf("esr_ti_init_util : val of Temp_port %d\n",temp_port.atoi());
86 }
87
88
89 for(i=0;i<str_port.len();i++) {
90 case(port_no[i]) {
91 0 : port0_enb = 1;
92 1 : port1_enb = 1;
93 }
94 }
95
96 }
97
98}
99
100
101task esr_tiinit_util :: serdes_init()
102{
103
104 bit v_bit = 1'b0;
105 bit[63:0] read_data;
106
107 if(port0_enb == 1) {
108 if (mac_speed0 == 10000)
109 {
110
111 @(posedge CLOCK);
112 gen_pio_drv.pio_wr(MIF_CONFIG,64'h0000_0000_0000_8008);
113 printf("write to mif_config Done\n");
114
115 // sel address 8000h Port0
116 repeat (10) @(posedge CLOCK);
117 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8000); //cfgpll0
118 repeat (10) @(posedge CLOCK);
119 wait_for_instr_comp();
120 printf("sel addr 8000h Done for port 0\n");
121
122 // write to address 8000h Port0 enable PLL for port0
123 repeat (10) @(posedge CLOCK);
124 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0003);
125 repeat (10) @(posedge CLOCK);
126 wait_for_instr_comp();
127 printf("write to 8000h Done\n");
128
129 // sel address 8000h Port0
130 repeat (10) @(posedge CLOCK);
131 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8000);
132 repeat (10) @(posedge CLOCK);
133 wait_for_instr_comp();
134 printf("sel addr 8000h Done\n");
135
136 // read to address 8000h PLL reg for port0
137 repeat (10) @(posedge CLOCK);
138 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_207a_0003);
139 repeat (10) @(posedge CLOCK);
140 wait_for_instr_comp();
141 printf("read to 8000h Done\n");
142
143 // sel address 8001h Port0
144 repeat (10) @(posedge CLOCK);
145 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8001); //cfgpll1
146 repeat (10) @(posedge CLOCK);
147 wait_for_instr_comp();
148 printf("sel addr 8001h Done\n");
149
150 // write to address 8001h Port0
151 repeat (10) @(posedge CLOCK);
152 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
153 repeat (10) @(posedge CLOCK);
154 wait_for_instr_comp();
155 printf("write to 8001h Done\n");
156
157 // sel address 8004h Port0
158 repeat (10) @(posedge CLOCK);
159 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8004); //testcfg0
160 repeat (10) @(posedge CLOCK);
161 wait_for_instr_comp();
162 printf("sel addr 8004h Done\n");
163
164 // write to address 8004h Port0
165 repeat (10) @(posedge CLOCK);
166 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
167 repeat (10) @(posedge CLOCK);
168 wait_for_instr_comp();
169 printf("write to 8004h Done\n");
170
171 // sel address 8005h Port0
172 repeat (10) @(posedge CLOCK);
173 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8005); //testcfg1
174 repeat (10) @(posedge CLOCK);
175 wait_for_instr_comp();
176 printf("sel addr 8005h Done\n");
177
178 // write to address 8005h Port0
179 repeat (10) @(posedge CLOCK);
180 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
181 repeat (10) @(posedge CLOCK);
182 wait_for_instr_comp();
183 printf("write to 8005h Done\n");
184
185
186 // sel address 8100h Port0
187 repeat (10) @(posedge CLOCK);
188 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8100); //cfgtx0_0
189 repeat (10) @(posedge CLOCK);
190 wait_for_instr_comp();
191 printf("sel addr 8100h Done\n");
192
193 // write to address 8100h Port0
194 repeat (10) @(posedge CLOCK);
195 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0001);
196 repeat (10) @(posedge CLOCK);
197 wait_for_instr_comp();
198 printf("write to 8100h Done\n");
199
200 // sel address 8101h Port0
201 repeat (10) @(posedge CLOCK);
202 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8101); //cfgtx0_1
203 repeat (10) @(posedge CLOCK);
204 wait_for_instr_comp();
205 printf("sel addr 8101h Done\n");
206
207 // write to address 8101h Port0
208 repeat (10) @(posedge CLOCK);
209 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
210 repeat (10) @(posedge CLOCK);
211 wait_for_instr_comp();
212 printf("write to 8101h Done\n");
213
214
215 // sel address 8104h Port0
216 repeat (10) @(posedge CLOCK);
217 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8104); //cfgtx1_0
218 repeat (10) @(posedge CLOCK);
219 wait_for_instr_comp();
220 printf("sel addr 8104h Done\n");
221
222 // write to address 8104h Port0
223 repeat (10) @(posedge CLOCK);
224 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0001);
225 repeat (10) @(posedge CLOCK);
226 wait_for_instr_comp();
227 printf("write to 8104h Done\n");
228
229 // sel address 8105h Port0
230 repeat (10) @(posedge CLOCK);
231 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8105); //cfgtx1_1
232 repeat (10) @(posedge CLOCK);
233 wait_for_instr_comp();
234 printf("sel addr 8105h Done\n");
235
236 // write to address 8105h Port0
237 repeat (10) @(posedge CLOCK);
238 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
239 repeat (10) @(posedge CLOCK);
240 wait_for_instr_comp();
241 printf("write to 8105h Done\n");
242
243
244 // sel address 8108h Port0
245 repeat (10) @(posedge CLOCK);
246 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8108); //cfgtx2_0
247 repeat (10) @(posedge CLOCK);
248 wait_for_instr_comp();
249 printf("sel addr 8108h Done\n");
250
251 // write to address 8108h Port0
252 repeat (10) @(posedge CLOCK);
253 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0001);
254 repeat (10) @(posedge CLOCK);
255 wait_for_instr_comp();
256 printf("write to 8108h Done\n");
257
258
259 // sel address 8109h Port0
260 repeat (10) @(posedge CLOCK);
261 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8109); //cfgtx2_1
262 repeat (10) @(posedge CLOCK);
263 wait_for_instr_comp();
264 printf("sel addr 8109h Done\n");
265
266 // write to address 8109h Port0
267 repeat (10) @(posedge CLOCK);
268 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
269 repeat (10) @(posedge CLOCK);
270 wait_for_instr_comp();
271 printf("write to 8109h Done\n");
272
273 // sel address 810ch Port0
274 repeat (10) @(posedge CLOCK);
275 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_810c); //cfgtx3_0
276 repeat (10) @(posedge CLOCK);
277 wait_for_instr_comp();
278 printf("sel addr 810ch Done\n");
279
280 // write to address 810ch Port0
281 repeat (10) @(posedge CLOCK);
282 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0001);
283 repeat (10) @(posedge CLOCK);
284 wait_for_instr_comp();
285 printf("write to 810ch Done\n");
286
287 // sel address 810dh Port0
288 repeat (10) @(posedge CLOCK);
289 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_810d); //cfgtx3_1
290 repeat (10) @(posedge CLOCK);
291 wait_for_instr_comp();
292 printf("sel addr 810dh Done\n");
293
294 // write to address 810dh Port0
295 repeat (10) @(posedge CLOCK);
296 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
297 repeat (10) @(posedge CLOCK);
298 wait_for_instr_comp();
299 printf("write to 810dh Done\n");
300
301
302 // sel address 8120h Port0
303 repeat (10) @(posedge CLOCK);
304 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8120); //cfgrx0_0
305 repeat (10) @(posedge CLOCK);
306 wait_for_instr_comp();
307 printf("sel addr 8120h Done\n");
308
309 // write to address 8120h Port0
310 repeat (10) @(posedge CLOCK);
311 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_5001);
312 repeat (10) @(posedge CLOCK);
313 wait_for_instr_comp();
314 printf("write to 8120h Done\n");
315
316 // sel address 8121h Port0
317 repeat (10) @(posedge CLOCK);
318 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8121);//cfgrx0_1
319 repeat (10) @(posedge CLOCK);
320 wait_for_instr_comp();
321 printf("sel addr 8121h Done\n");
322
323 // write to address 8121h Port0
324 repeat (10) @(posedge CLOCK);
325 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0008);
326 repeat (10) @(posedge CLOCK);
327 wait_for_instr_comp();
328 printf("write to 8121h Done\n");
329
330 // sel address 8124h Port0
331 repeat (10) @(posedge CLOCK);
332 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8124);//cfgrx1_0
333 repeat (10) @(posedge CLOCK);
334 wait_for_instr_comp();
335 printf("sel addr 8124h Done\n");
336
337 // write to address 8124h Port0
338 repeat (10) @(posedge CLOCK);
339 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_5001);
340 repeat (10) @(posedge CLOCK);
341 wait_for_instr_comp();
342 printf("write to 8124h Done\n");
343
344 // sel address 8125h Port0
345 repeat (10) @(posedge CLOCK);
346 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8125);//cfgrx1_1
347 repeat (10) @(posedge CLOCK);
348 wait_for_instr_comp();
349 printf("sel addr 8125h Done\n");
350
351 // write to address 8125h Port0
352 repeat (10) @(posedge CLOCK);
353 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0008);
354 repeat (10) @(posedge CLOCK);
355 wait_for_instr_comp();
356 printf("write to 8125h Done\n");
357
358
359 // sel address 8128h Port0
360 repeat (10) @(posedge CLOCK);
361 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8128);//cfgrx2_0
362 repeat (10) @(posedge CLOCK);
363 wait_for_instr_comp();
364 printf("sel addr 8128h Done\n");
365
366 // write to address 8128h Port0
367 repeat (10) @(posedge CLOCK);
368 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_5001);
369 repeat (10) @(posedge CLOCK);
370 wait_for_instr_comp();
371 printf("write to 8128h Done\n");
372
373
374 // sel address 8129h Port0
375 repeat (10) @(posedge CLOCK);
376 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8129);//cfgrx2_1
377 repeat (10) @(posedge CLOCK);
378 wait_for_instr_comp();
379 printf("sel addr 8129h Done\n");
380
381 // write to address 8129h Port0
382 repeat (10) @(posedge CLOCK);
383 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0008);
384 repeat (10) @(posedge CLOCK);
385 wait_for_instr_comp();
386 printf("write to 8129h Done\n");
387
388 // sel address 812ch Port0
389 repeat (10) @(posedge CLOCK);
390 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_812c);//cfgrx3_0
391 repeat (10) @(posedge CLOCK);
392 wait_for_instr_comp();
393 printf("sel addr 812ch Done\n");
394
395 // write to address 812ch Port0
396 repeat (10) @(posedge CLOCK);
397 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_5001);
398 repeat (10) @(posedge CLOCK);
399 wait_for_instr_comp();
400 printf("write to 812ch Done\n");
401
402 // sel address 812dh Port0
403 repeat (10) @(posedge CLOCK);
404 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_812d);//cfgrx3_1
405 repeat (10) @(posedge CLOCK);
406 wait_for_instr_comp();
407 printf("sel addr 812dh Done\n");
408
409 // write to address 812dh Port0
410 repeat (10) @(posedge CLOCK);
411 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0008);
412 repeat (10) @(posedge CLOCK);
413 wait_for_instr_comp();
414 printf("write to 812dh Done\n");
415
416 }
417 if (mac_speed0 == 1000)
418 {
419
420 gen_pio_drv.pio_wr(MIF_CONFIG,64'h0000_0000_0000_8008);
421 printf("write to mif_config Done\n");
422
423 // sel address 8000h Port0
424 repeat (10) @(posedge CLOCK);
425 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8000); //cfgpll0
426 repeat (10) @(posedge CLOCK);
427 wait_for_instr_comp();
428 printf("sel addr 8000h Done for port 0\n");
429
430 // write to address 8000h Port0 enable PLL for port0
431 repeat (10) @(posedge CLOCK);
432 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_000b);
433 repeat (10) @(posedge CLOCK);
434 wait_for_instr_comp();
435 printf("write to 8000h Done\n");
436
437 // sel address 8000h Port0
438 repeat (10) @(posedge CLOCK);
439 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8000);
440 repeat (10) @(posedge CLOCK);
441 wait_for_instr_comp();
442 printf("sel addr 8000h Done\n");
443
444 // read to address 8000h PLL reg for port0
445 repeat (10) @(posedge CLOCK);
446 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_207a_0003);
447 repeat (10) @(posedge CLOCK);
448 wait_for_instr_comp();
449 printf("read to 8000h Done\n");
450
451 // sel address 8001h Port0
452 repeat (10) @(posedge CLOCK);
453 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8001); //cfgpll1
454 repeat (10) @(posedge CLOCK);
455 wait_for_instr_comp();
456 printf("sel addr 8001h Done\n");
457
458 // write to address 8001h Port0
459 repeat (10) @(posedge CLOCK);
460 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_000b);
461 repeat (10) @(posedge CLOCK);
462 wait_for_instr_comp();
463 printf("write to 8001h Done\n");
464
465 // sel address 8004h Port0
466 repeat (10) @(posedge CLOCK);
467 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8004); //testcfg0
468 repeat (10) @(posedge CLOCK);
469 wait_for_instr_comp();
470 printf("sel addr 8004h Done\n");
471
472 // write to address 8004h Port0
473 repeat (10) @(posedge CLOCK);
474 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
475 repeat (10) @(posedge CLOCK);
476 wait_for_instr_comp();
477 printf("write to 8004h Done\n");
478
479 // sel address 8005h Port0
480 repeat (10) @(posedge CLOCK);
481 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8005); //testcfg1
482 repeat (10) @(posedge CLOCK);
483 wait_for_instr_comp();
484 printf("sel addr 8005h Done\n");
485
486 // write to address 8005h Port0
487 repeat (10) @(posedge CLOCK);
488 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
489 repeat (10) @(posedge CLOCK);
490 wait_for_instr_comp();
491 printf("write to 8005h Done\n");
492
493
494 // sel address 8100h Port0
495 repeat (10) @(posedge CLOCK);
496 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8100); //cfgtx0_0
497 repeat (10) @(posedge CLOCK);
498 wait_for_instr_comp();
499 printf("sel addr 8100h Done\n");
500
501 // write to address 8100h Port0
502 repeat (10) @(posedge CLOCK);
503 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0021);
504 repeat (10) @(posedge CLOCK);
505 wait_for_instr_comp();
506 printf("write to 8100h Done\n");
507
508 // sel address 8101h Port0
509 repeat (10) @(posedge CLOCK);
510 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8101); //cfgtx0_1
511 repeat (10) @(posedge CLOCK);
512 wait_for_instr_comp();
513 printf("sel addr 8101h Done\n");
514
515 // write to address 8101h Port0
516 repeat (10) @(posedge CLOCK);
517 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0021);
518 repeat (10) @(posedge CLOCK);
519 wait_for_instr_comp();
520 printf("write to 8101h Done\n");
521
522
523 // sel address 8104h Port0
524 repeat (10) @(posedge CLOCK);
525 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8104); //cfgtx1_0
526 repeat (10) @(posedge CLOCK);
527 wait_for_instr_comp();
528 printf("sel addr 8104h Done\n");
529
530 // write to address 8104h Port0
531 repeat (10) @(posedge CLOCK);
532 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
533 repeat (10) @(posedge CLOCK);
534 wait_for_instr_comp();
535 printf("write to 8104h Done\n");
536
537 // sel address 8105h Port0
538 repeat (10) @(posedge CLOCK);
539 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8105); //cfgtx1_1
540 repeat (10) @(posedge CLOCK);
541 wait_for_instr_comp();
542 printf("sel addr 8105h Done\n");
543
544 // write to address 8105h Port0
545 repeat (10) @(posedge CLOCK);
546 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
547 repeat (10) @(posedge CLOCK);
548 wait_for_instr_comp();
549 printf("write to 8105h Done\n");
550
551
552 // sel address 8108h Port0
553 repeat (10) @(posedge CLOCK);
554 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8108); //cfgtx2_0
555 repeat (10) @(posedge CLOCK);
556 wait_for_instr_comp();
557 printf("sel addr 8108h Done\n");
558
559 // write to address 8108h Port0
560 repeat (10) @(posedge CLOCK);
561 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
562 repeat (10) @(posedge CLOCK);
563 wait_for_instr_comp();
564 printf("write to 8108h Done\n");
565
566
567 // sel address 8109h Port0
568 repeat (10) @(posedge CLOCK);
569 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8109); //cfgtx2_1
570 repeat (10) @(posedge CLOCK);
571 wait_for_instr_comp();
572 printf("sel addr 8109h Done\n");
573
574 // write to address 8109h Port0
575 repeat (10) @(posedge CLOCK);
576 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
577 repeat (10) @(posedge CLOCK);
578 wait_for_instr_comp();
579 printf("write to 8109h Done\n");
580
581 // sel address 810ch Port0
582 repeat (10) @(posedge CLOCK);
583 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_810c); //cfgtx3_0
584 repeat (10) @(posedge CLOCK);
585 wait_for_instr_comp();
586 printf("sel addr 810ch Done\n");
587
588 // write to address 810ch Port0
589 repeat (10) @(posedge CLOCK);
590 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
591 repeat (10) @(posedge CLOCK);
592 wait_for_instr_comp();
593 printf("write to 810ch Done\n");
594
595 // sel address 810dh Port0
596 repeat (10) @(posedge CLOCK);
597 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_810d); //cfgtx3_1
598 repeat (10) @(posedge CLOCK);
599 wait_for_instr_comp();
600 printf("sel addr 810dh Done\n");
601
602 // write to address 810dh Port0
603 repeat (10) @(posedge CLOCK);
604 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
605 repeat (10) @(posedge CLOCK);
606 wait_for_instr_comp();
607 printf("write to 810dh Done\n");
608
609
610 // sel address 8120h Port0
611 repeat (10) @(posedge CLOCK);
612 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8120); //cfgrx0_0
613 repeat (10) @(posedge CLOCK);
614 wait_for_instr_comp();
615 printf("sel addr 8120h Done\n");
616
617 // write to address 8120h Port0
618 repeat (10) @(posedge CLOCK);
619 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_5021);
620 repeat (10) @(posedge CLOCK);
621 wait_for_instr_comp();
622 printf("write to 8120h Done\n");
623
624 // sel address 8121h Port0
625 repeat (10) @(posedge CLOCK);
626 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8121);//cfgrx0_1
627 repeat (10) @(posedge CLOCK);
628 wait_for_instr_comp();
629 printf("sel addr 8121h Done\n");
630
631 // write to address 8121h Port0
632 repeat (10) @(posedge CLOCK);
633 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_5021);
634 repeat (10) @(posedge CLOCK);
635 wait_for_instr_comp();
636 printf("write to 8121h Done\n");
637
638 // sel address 8124h Port0
639 repeat (10) @(posedge CLOCK);
640 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8124);//cfgrx1_0
641 repeat (10) @(posedge CLOCK);
642 wait_for_instr_comp();
643 printf("sel addr 8124h Done\n");
644
645 // write to address 8124h Port0
646 repeat (10) @(posedge CLOCK);
647 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
648 repeat (10) @(posedge CLOCK);
649 wait_for_instr_comp();
650 printf("write to 8124h Done\n");
651
652 // sel address 8125h Port0
653 repeat (10) @(posedge CLOCK);
654 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8125);//cfgrx1_1
655 repeat (10) @(posedge CLOCK);
656 wait_for_instr_comp();
657 printf("sel addr 8125h Done\n");
658
659 // write to address 8125h Port0
660 repeat (10) @(posedge CLOCK);
661 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
662 repeat (10) @(posedge CLOCK);
663 wait_for_instr_comp();
664 printf("write to 8125h Done\n");
665
666
667 // sel address 8128h Port0
668 repeat (10) @(posedge CLOCK);
669 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8128);//cfgrx2_0
670 repeat (10) @(posedge CLOCK);
671 wait_for_instr_comp();
672 printf("sel addr 8128h Done\n");
673
674 // write to address 8128h Port0
675 repeat (10) @(posedge CLOCK);
676 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
677 repeat (10) @(posedge CLOCK);
678 wait_for_instr_comp();
679 printf("write to 8128h Done\n");
680
681
682 // sel address 8129h Port0
683 repeat (10) @(posedge CLOCK);
684 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_8129);//cfgrx2_1
685 repeat (10) @(posedge CLOCK);
686 wait_for_instr_comp();
687 printf("sel addr 8129h Done\n");
688
689 // write to address 8129h Port0
690 repeat (10) @(posedge CLOCK);
691 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
692 repeat (10) @(posedge CLOCK);
693 wait_for_instr_comp();
694 printf("write to 8129h Done\n");
695
696 // sel address 812ch Port0
697 repeat (10) @(posedge CLOCK);
698 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_812c);//cfgrx3_0
699 repeat (10) @(posedge CLOCK);
700 wait_for_instr_comp();
701 printf("sel addr 812ch Done\n");
702
703 // write to address 812ch Port0
704 repeat (10) @(posedge CLOCK);
705 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
706 repeat (10) @(posedge CLOCK);
707 wait_for_instr_comp();
708 printf("write to 812ch Done\n");
709
710 // sel address 812dh Port0
711 repeat (10) @(posedge CLOCK);
712 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_007a_812d);//cfgrx3_1
713 repeat (10) @(posedge CLOCK);
714 wait_for_instr_comp();
715 printf("sel addr 812dh Done\n");
716
717 // write to address 812dh Port0
718 repeat (10) @(posedge CLOCK);
719 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_107a_0000);
720 repeat (10) @(posedge CLOCK);
721 wait_for_instr_comp();
722 printf("write to 812dh Done\n");
723 }
724 }
725
726
727
728 if(port1_enb == 1) {
729 if (mac_speed1 == 10000)
730 {
731 @(posedge CLOCK);
732 gen_pio_drv.pio_wr(MIF_CONFIG,64'h0000_0000_0000_8008);
733 printf("write to mif_config Done\n");
734
735
736 // enable the pll for port1
737 // sel address 8000h Port1
738 repeat (10) @(posedge CLOCK);
739 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8000);
740 repeat (10) @(posedge CLOCK);
741 wait_for_instr_comp();
742 printf("sel addr 8000h Done for port 1\n");
743
744 // write to address 8000h Port1
745 repeat (10) @(posedge CLOCK);
746 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0003);
747 repeat (10) @(posedge CLOCK);
748 wait_for_instr_comp();
749 printf("write to 8000h Done\n");
750
751 // sel address 8001h Port0
752 repeat (10) @(posedge CLOCK);
753 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8001);
754 repeat (10) @(posedge CLOCK);
755 wait_for_instr_comp();
756 printf("sel addr 8001h Done\n");
757
758 // write to address 8001h Port1
759 repeat (10) @(posedge CLOCK);
760 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
761 repeat (10) @(posedge CLOCK);
762 wait_for_instr_comp();
763 printf("write to 8001h Done\n");
764
765 // sel address 8004h Port1
766 repeat (10) @(posedge CLOCK);
767 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8004);
768 repeat (10) @(posedge CLOCK);
769 wait_for_instr_comp();
770 printf("sel addr 8004h Done\n");
771
772 // write to address 8004h Port1
773 repeat (10) @(posedge CLOCK);
774 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
775 repeat (10) @(posedge CLOCK);
776 wait_for_instr_comp();
777 printf("write to 8004h Done\n");
778
779 // sel address 8005h Port1
780 repeat (10) @(posedge CLOCK);
781 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8005);
782 repeat (10) @(posedge CLOCK);
783 wait_for_instr_comp();
784 printf("sel addr 8005h Done\n");
785
786 // write to address 8005h Port1
787 repeat (10) @(posedge CLOCK);
788 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
789 repeat (10) @(posedge CLOCK);
790 wait_for_instr_comp();
791 printf("write to 8005h Done\n");
792
793
794 // sel address 8100h Port1
795 repeat (10) @(posedge CLOCK);
796 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8100);
797 repeat (10) @(posedge CLOCK);
798 wait_for_instr_comp();
799 printf("sel addr 8100h Done\n");
800
801 // write to address 8100h Port1
802 repeat (10) @(posedge CLOCK);
803 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0001);
804 repeat (10) @(posedge CLOCK);
805 wait_for_instr_comp();
806 printf("write to 8100h Done\n");
807
808 // sel address 8101h Port1
809 repeat (10) @(posedge CLOCK);
810 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8101);
811 repeat (10) @(posedge CLOCK);
812 wait_for_instr_comp();
813 printf("sel addr 8101h Done\n");
814
815 // write to address 8101h Port1
816 repeat (10) @(posedge CLOCK);
817 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
818 repeat (10) @(posedge CLOCK);
819 wait_for_instr_comp();
820 printf("write to 8101h Done\n");
821
822
823 // sel address 8104h Port1
824 repeat (10) @(posedge CLOCK);
825 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8104);
826 repeat (10) @(posedge CLOCK);
827 wait_for_instr_comp();
828 printf("sel addr 8104h Done\n");
829
830 // write to address 8104h Port1
831 repeat (10) @(posedge CLOCK);
832 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0001);
833 repeat (10) @(posedge CLOCK);
834 wait_for_instr_comp();
835 printf("write to 8104h Done\n");
836
837 // sel address 8105h Port1
838 repeat (10) @(posedge CLOCK);
839 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8105);
840 repeat (10) @(posedge CLOCK);
841 wait_for_instr_comp();
842 printf("sel addr 8105h Done\n");
843
844 // write to address 8105h Port1
845 repeat (10) @(posedge CLOCK);
846 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
847 repeat (10) @(posedge CLOCK);
848 wait_for_instr_comp();
849 printf("write to 8105h Done\n");
850
851
852 // sel address 8108h Port1
853 repeat (10) @(posedge CLOCK);
854 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8108);
855 repeat (10) @(posedge CLOCK);
856 wait_for_instr_comp();
857 printf("sel addr 8108h Done\n");
858
859 // write to address 8108h Port1
860 repeat (10) @(posedge CLOCK);
861 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0001);
862 repeat (10) @(posedge CLOCK);
863 wait_for_instr_comp();
864 printf("write to 8108h Done\n");
865
866
867 // sel address 8109h Port1
868 repeat (10) @(posedge CLOCK);
869 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8109);
870 repeat (10) @(posedge CLOCK);
871 wait_for_instr_comp();
872 printf("sel addr 8109h Done\n");
873
874 // write to address 8109h Port1
875 repeat (10) @(posedge CLOCK);
876 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
877 repeat (10) @(posedge CLOCK);
878 wait_for_instr_comp();
879 printf("write to 8109h Done\n");
880
881 // sel address 810ch Port1
882 repeat (10) @(posedge CLOCK);
883 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_810c);
884 repeat (10) @(posedge CLOCK);
885 wait_for_instr_comp();
886 printf("sel addr 810ch Done\n");
887
888 // write to address 810ch Port1
889 repeat (10) @(posedge CLOCK);
890 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0001);
891 repeat (10) @(posedge CLOCK);
892 wait_for_instr_comp();
893 printf("write to 810ch Done\n");
894
895 // sel address 810dh Port1
896 repeat (10) @(posedge CLOCK);
897 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_810d);
898 repeat (10) @(posedge CLOCK);
899 wait_for_instr_comp();
900 printf("sel addr 810dh Done\n");
901
902 // write to address 811dh Port1
903 repeat (10) @(posedge CLOCK);
904 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
905 repeat (10) @(posedge CLOCK);
906 wait_for_instr_comp();
907 printf("write to 810dh Done\n");
908
909
910 // sel address 8120h Port1
911 repeat (10) @(posedge CLOCK);
912 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8120);
913 repeat (10) @(posedge CLOCK);
914 wait_for_instr_comp();
915 printf("sel addr 8120h Done\n");
916
917 // write to address 8120h Port1
918 repeat (10) @(posedge CLOCK);
919 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_5001);
920 repeat (10) @(posedge CLOCK);
921 wait_for_instr_comp();
922 printf("write to 8120h Done\n");
923
924 // sel address 8121h Port1
925 repeat (10) @(posedge CLOCK);
926 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8121);
927 repeat (10) @(posedge CLOCK);
928 wait_for_instr_comp();
929 printf("sel addr 8121h Done\n");
930
931 // write to address 8121h Port1
932 repeat (10) @(posedge CLOCK);
933 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0008);
934 repeat (10) @(posedge CLOCK);
935 wait_for_instr_comp();
936 printf("write to 8121h Done\n");
937
938 // sel address 8124h Port1
939 repeat (10) @(posedge CLOCK);
940 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8124);
941 repeat (10) @(posedge CLOCK);
942 wait_for_instr_comp();
943 printf("sel addr 8124h Done\n");
944
945 // write to address 8124h Port1
946 repeat (10) @(posedge CLOCK);
947 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_5001);
948 repeat (10) @(posedge CLOCK);
949 wait_for_instr_comp();
950 printf("write to 8124h Done\n");
951
952 // sel address 8125h Port1
953 repeat (10) @(posedge CLOCK);
954 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8125);
955 repeat (10) @(posedge CLOCK);
956 wait_for_instr_comp();
957 printf("sel addr 8125h Done\n");
958
959 // write to address 8125h Port1
960 repeat (10) @(posedge CLOCK);
961 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0008);
962 repeat (10) @(posedge CLOCK);
963 wait_for_instr_comp();
964 printf("write to 8125h Done\n");
965
966
967 // sel address 8128h Port1
968 repeat (10) @(posedge CLOCK);
969 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8128);
970 repeat (10) @(posedge CLOCK);
971 wait_for_instr_comp();
972 printf("sel addr 8128h Done\n");
973
974 // write to address 8128h Port1
975 repeat (10) @(posedge CLOCK);
976 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_5001);
977 repeat (10) @(posedge CLOCK);
978 wait_for_instr_comp();
979 printf("write to 8128h Done\n");
980
981
982 // sel address 8129h Port1
983 repeat (10) @(posedge CLOCK);
984 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8129);
985 repeat (10) @(posedge CLOCK);
986 wait_for_instr_comp();
987 printf("sel addr 8129h Done\n");
988
989 // write to address 8129h Port1
990 repeat (10) @(posedge CLOCK);
991 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0008);
992 repeat (10) @(posedge CLOCK);
993 wait_for_instr_comp();
994 printf("write to 8129h Done\n");
995
996 // sel address 812ch Port1
997 repeat (10) @(posedge CLOCK);
998 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_812c);
999 repeat (10) @(posedge CLOCK);
1000 wait_for_instr_comp();
1001 printf("sel addr 812ch Done\n");
1002
1003 // write to address 812ch Port1
1004 repeat (10) @(posedge CLOCK);
1005 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_5001);
1006 repeat (10) @(posedge CLOCK);
1007 wait_for_instr_comp();
1008 printf("write to 812ch Done\n");
1009
1010 // sel address 812dh Port1
1011 repeat (10) @(posedge CLOCK);
1012 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_812d);
1013 repeat (10) @(posedge CLOCK);
1014 wait_for_instr_comp();
1015 printf("sel addr 812dh Done\n");
1016
1017 // write to address 812dh Port1
1018 repeat (10) @(posedge CLOCK);
1019 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0008);
1020 repeat (10) @(posedge CLOCK);
1021 wait_for_instr_comp();
1022 printf("write to 812dh Done\n");
1023
1024 }
1025
1026 if (mac_speed1 == 1000)
1027 {
1028 gen_pio_drv.pio_wr(MIF_CONFIG,64'h0000_0000_0000_8008);
1029 printf("write to mif_config Done\n");
1030
1031 // sel address 8000h Port0
1032 repeat (10) @(posedge CLOCK);
1033 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8000); //cfgpll0
1034 repeat (10) @(posedge CLOCK);
1035 wait_for_instr_comp();
1036 printf("sel addr 8000h Done for port 0\n");
1037
1038 // write to address 8000h Port0 enable PLL for port0
1039 repeat (10) @(posedge CLOCK);
1040 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_000b);
1041 repeat (10) @(posedge CLOCK);
1042 wait_for_instr_comp();
1043 printf("write to 8000h Done\n");
1044
1045 // sel address 8000h Port0
1046 repeat (10) @(posedge CLOCK);
1047 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8000);
1048 repeat (10) @(posedge CLOCK);
1049 wait_for_instr_comp();
1050 printf("sel addr 8000h Done\n");
1051
1052 // read to address 8000h PLL reg for port0
1053 repeat (10) @(posedge CLOCK);
1054 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_20fa_0003);
1055 repeat (10) @(posedge CLOCK);
1056 wait_for_instr_comp();
1057 printf("read to 8000h Done\n");
1058
1059 // sel address 8001h Port0
1060 repeat (10) @(posedge CLOCK);
1061 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8001); //cfgpll1
1062 repeat (10) @(posedge CLOCK);
1063 wait_for_instr_comp();
1064 printf("sel addr 8001h Done\n");
1065
1066 // write to address 8001h Port0
1067 repeat (10) @(posedge CLOCK);
1068 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_000b);
1069 repeat (10) @(posedge CLOCK);
1070 wait_for_instr_comp();
1071 printf("write to 8001h Done\n");
1072
1073 // sel address 8004h Port0
1074 repeat (10) @(posedge CLOCK);
1075 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8004); //testcfg0
1076 repeat (10) @(posedge CLOCK);
1077 wait_for_instr_comp();
1078 printf("sel addr 8004h Done\n");
1079
1080 // write to address 8004h Port0
1081 repeat (10) @(posedge CLOCK);
1082 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
1083 repeat (10) @(posedge CLOCK);
1084 wait_for_instr_comp();
1085 printf("write to 8004h Done\n");
1086
1087 // sel address 8005h Port0
1088 repeat (10) @(posedge CLOCK);
1089 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8005); //testcfg1
1090 repeat (10) @(posedge CLOCK);
1091 wait_for_instr_comp();
1092 printf("sel addr 8005h Done\n");
1093
1094 // write to address 8005h Port0
1095 repeat (10) @(posedge CLOCK);
1096 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
1097 repeat (10) @(posedge CLOCK);
1098 wait_for_instr_comp();
1099 printf("write to 8005h Done\n");
1100
1101
1102 // sel address 8100h Port0
1103 repeat (10) @(posedge CLOCK);
1104 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8100); //cfgtx0_0
1105 repeat (10) @(posedge CLOCK);
1106 wait_for_instr_comp();
1107 printf("sel addr 8100h Done\n");
1108
1109 // write to address 8100h Port0
1110 repeat (10) @(posedge CLOCK);
1111 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0021);
1112 repeat (10) @(posedge CLOCK);
1113 wait_for_instr_comp();
1114 printf("write to 8100h Done\n");
1115
1116 // sel address 8101h Port0
1117 repeat (10) @(posedge CLOCK);
1118 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8101); //cfgtx0_1
1119 repeat (10) @(posedge CLOCK);
1120 wait_for_instr_comp();
1121 printf("sel addr 8101h Done\n");
1122
1123 // write to address 8101h Port0
1124 repeat (10) @(posedge CLOCK);
1125 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0021);
1126 repeat (10) @(posedge CLOCK);
1127 wait_for_instr_comp();
1128 printf("write to 8101h Done\n");
1129
1130
1131 // sel address 8104h Port0
1132 repeat (10) @(posedge CLOCK);
1133 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8104); //cfgtx1_0
1134 repeat (10) @(posedge CLOCK);
1135 wait_for_instr_comp();
1136 printf("sel addr 8104h Done\n");
1137
1138 // write to address 8104h Port0
1139 repeat (10) @(posedge CLOCK);
1140 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
1141 repeat (10) @(posedge CLOCK);
1142 wait_for_instr_comp();
1143 printf("write to 8104h Done\n");
1144
1145 // sel address 8105h Port0
1146 repeat (10) @(posedge CLOCK);
1147 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8105); //cfgtx1_1
1148 repeat (10) @(posedge CLOCK);
1149 wait_for_instr_comp();
1150 printf("sel addr 8105h Done\n");
1151
1152 // write to address 8105h Port0
1153 repeat (10) @(posedge CLOCK);
1154 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
1155 repeat (10) @(posedge CLOCK);
1156 wait_for_instr_comp();
1157 printf("write to 8105h Done\n");
1158
1159
1160 // sel address 8108h Port0
1161 repeat (10) @(posedge CLOCK);
1162 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8108); //cfgtx2_0
1163 repeat (10) @(posedge CLOCK);
1164 wait_for_instr_comp();
1165 printf("sel addr 8108h Done\n");
1166
1167 // write to address 8108h Port0
1168 repeat (10) @(posedge CLOCK);
1169 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
1170 repeat (10) @(posedge CLOCK);
1171 wait_for_instr_comp();
1172 printf("write to 8108h Done\n");
1173
1174
1175 // sel address 8109h Port0
1176 repeat (10) @(posedge CLOCK);
1177 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8109); //cfgtx2_1
1178 repeat (10) @(posedge CLOCK);
1179 wait_for_instr_comp();
1180 printf("sel addr 8109h Done\n");
1181
1182 // write to address 8109h Port0
1183 repeat (10) @(posedge CLOCK);
1184 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
1185 repeat (10) @(posedge CLOCK);
1186 wait_for_instr_comp();
1187 printf("write to 8109h Done\n");
1188
1189 // sel address 810ch Port0
1190 repeat (10) @(posedge CLOCK);
1191 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_810c); //cfgtx3_0
1192 repeat (10) @(posedge CLOCK);
1193 wait_for_instr_comp();
1194 printf("sel addr 810ch Done\n");
1195
1196 // write to address 810ch Port0
1197 repeat (10) @(posedge CLOCK);
1198 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
1199 repeat (10) @(posedge CLOCK);
1200 wait_for_instr_comp();
1201 printf("write to 810ch Done\n");
1202
1203 // sel address 810dh Port0
1204 repeat (10) @(posedge CLOCK);
1205 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_810d); //cfgtx3_1
1206 repeat (10) @(posedge CLOCK);
1207 wait_for_instr_comp();
1208 printf("sel addr 810dh Done\n");
1209
1210 // write to address 810dh Port0
1211 repeat (10) @(posedge CLOCK);
1212 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
1213 repeat (10) @(posedge CLOCK);
1214 wait_for_instr_comp();
1215 printf("write to 810dh Done\n");
1216
1217
1218 // sel address 8120h Port0
1219 repeat (10) @(posedge CLOCK);
1220 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8120); //cfgrx0_0
1221 repeat (10) @(posedge CLOCK);
1222 wait_for_instr_comp();
1223 printf("sel addr 8120h Done\n");
1224
1225 // write to address 8120h Port0
1226 repeat (10) @(posedge CLOCK);
1227 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_5021);
1228 repeat (10) @(posedge CLOCK);
1229 wait_for_instr_comp();
1230 printf("write to 8120h Done\n");
1231
1232 // sel address 8121h Port0
1233 repeat (10) @(posedge CLOCK);
1234 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8121);//cfgrx0_1
1235 repeat (10) @(posedge CLOCK);
1236 wait_for_instr_comp();
1237 printf("sel addr 8121h Done\n");
1238
1239 // write to address 8121h Port0
1240 repeat (10) @(posedge CLOCK);
1241 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_5021);
1242 repeat (10) @(posedge CLOCK);
1243 wait_for_instr_comp();
1244 printf("write to 8121h Done\n");
1245
1246 // sel address 8124h Port0
1247 repeat (10) @(posedge CLOCK);
1248 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8124);//cfgrx1_0
1249 repeat (10) @(posedge CLOCK);
1250 wait_for_instr_comp();
1251 printf("sel addr 8124h Done\n");
1252
1253 // write to address 8124h Port0
1254 repeat (10) @(posedge CLOCK);
1255 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
1256 repeat (10) @(posedge CLOCK);
1257 wait_for_instr_comp();
1258 printf("write to 8124h Done\n");
1259
1260 // sel address 8125h Port0
1261 repeat (10) @(posedge CLOCK);
1262 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8125);//cfgrx1_1
1263 repeat (10) @(posedge CLOCK);
1264 wait_for_instr_comp();
1265 printf("sel addr 8125h Done\n");
1266
1267 // write to address 8125h Port0
1268 repeat (10) @(posedge CLOCK);
1269 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
1270 repeat (10) @(posedge CLOCK);
1271 wait_for_instr_comp();
1272 printf("write to 8125h Done\n");
1273
1274
1275 // sel address 8128h Port0
1276 repeat (10) @(posedge CLOCK);
1277 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8128);//cfgrx2_0
1278 repeat (10) @(posedge CLOCK);
1279 wait_for_instr_comp();
1280 printf("sel addr 8128h Done\n");
1281
1282 // write to address 8128h Port0
1283 repeat (10) @(posedge CLOCK);
1284 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
1285 repeat (10) @(posedge CLOCK);
1286 wait_for_instr_comp();
1287 printf("write to 8128h Done\n");
1288
1289
1290 // sel address 8129h Port0
1291 repeat (10) @(posedge CLOCK);
1292 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_8129);//cfgrx2_1
1293 repeat (10) @(posedge CLOCK);
1294 wait_for_instr_comp();
1295 printf("sel addr 8129h Done\n");
1296
1297 // write to address 8129h Port0
1298 repeat (10) @(posedge CLOCK);
1299 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
1300 repeat (10) @(posedge CLOCK);
1301 wait_for_instr_comp();
1302 printf("write to 8129h Done\n");
1303
1304 // sel address 812ch Port0
1305 repeat (10) @(posedge CLOCK);
1306 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_812c);//cfgrx3_0
1307 repeat (10) @(posedge CLOCK);
1308 wait_for_instr_comp();
1309 printf("sel addr 812ch Done\n");
1310
1311 // write to address 812ch Port0
1312 repeat (10) @(posedge CLOCK);
1313 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
1314 repeat (10) @(posedge CLOCK);
1315 wait_for_instr_comp();
1316 printf("write to 812ch Done\n");
1317
1318 // sel address 812dh Port0
1319 repeat (10) @(posedge CLOCK);
1320 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_00fa_812d);//cfgrx3_1
1321 repeat (10) @(posedge CLOCK);
1322 wait_for_instr_comp();
1323 printf("sel addr 812dh Done\n");
1324
1325 // write to address 812dh Port0
1326 repeat (10) @(posedge CLOCK);
1327 gen_pio_drv.pio_wr(MIF_FRAMEOUT_REG,64'h0000_0000_10fa_0000);
1328 repeat (10) @(posedge CLOCK);
1329 wait_for_instr_comp();
1330 printf("write to 812dh Done\n");
1331
1332 }
1333 }
1334}
1335
1336
1337 task esr_tiinit_util :: wait_for_instr_comp()
1338 {
1339
1340 bit v_bit = 1'b0;
1341 bit[63:0] read_data;
1342
1343 while(~v_bit) {
1344 repeat (5000) @(posedge CLOCK);
1345 printf("Reading FRAME_REG to see if instr_wr completed\n");
1346 gen_pio_drv.pio_rd(MIF_FRAMEOUT_REG,read_data);
1347 if(read_data[16])
1348 v_bit = 1'b1;
1349 else
1350 v_bit = 1'b0;
1351 }
1352
1353 }
Full OpenSPARC design & verification tarball including full HDL.