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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / niu / vera / niu_pio / include / fflp_defines.vri
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fflp_defines.vri
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#ifdef VEGA_CHIP_LEVEL
36 #ifdef BH_BOARD_LEVEL
37 #define TESTBENCH_TOP "BH_board
38 #define FFLP_DUV_PATH "BH_board.vega.vega.ffl_blk
39 #define BMC_FULL_CTRL "BH_board
40 #define CAM_DUV_PATH "BH_board.cam_conn.cam_ram.IPC
41 #define ZBTRAM_DUV_PATH "BH_board.cam_conn.zbtram.ZBT_SRAM
42 #else
43 #ifdef DFTGATE_SIM
44 #define TESTBENCH_TOP "vega_tb_top
45 #define FFLP_DUV_PATH "vega_tb_top.vega_asic_top.ffl_blk.coreInstance
46 #define BMC_FULL_CTRL "vega_tb_top
47 #define CAM_DUV_PATH "vega_tb_top.cam_ram.IPC
48 #define ZBTRAM_DUV_PATH "vega_tb_top.cam_ram.ZBT_SRAM
49 #else
50 #define TESTBENCH_TOP "vega_tb_top
51 #define FFLP_DUV_PATH "vega_tb_top.vega_asic_top.ffl_blk
52 #define BMC_FULL_CTRL "vega_tb_top
53 #define CAM_DUV_PATH "vega_tb_top.cam_ram.IPC
54 #define ZBTRAM_DUV_PATH "vega_tb_top.cam_ram.ZBT_SRAM
55 #endif
56 #endif
57#else
58 #ifdef DFTGATE_SIM
59 #define TESTBENCH_TOP "fflp_testbench
60 #define FFLP_DUV_PATH "fflp_testbench.ffl_top
61 #define FFLP_DUV_PATH_DFT "fflp_testbench.ffl_top.coreInstance
62 #define BMC_FULL_CTRL "fflp_testbench
63 #define CAM_DUV_PATH "fflp_testbench.cam_ram.IPC
64 #define ZBTRAM_DUV_PATH "fflp_testbench.cam_ram.ZBT_SRAM
65 #else
66 #define TESTBENCH_TOP "fflp_testbench
67 #define FFLP_DUV_PATH "fflp_testbench.ffl_top
68 #define FFLP_DUV_PATH_DFT "fflp_testbench.ffl_top
69 #define BMC_FULL_CTRL "fflp_testbench
70 #define CAM_DUV_PATH "fflp_testbench.cam_ram.IPC
71 #define ZBTRAM_DUV_PATH "fflp_testbench.cam_ram.ZBT_SRAM
72 #endif
73#endif
74
75//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
76//@@ These are the FFLP defines which will be edited @@
77//@@ in vera_defines.vrh file @@
78//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
79
80#define OC192_MODE 1'b1
81
82#define ARP_FRAME_TYPE 16'h0806
83#define RARP_FRAME_TYPE 16'h8035
84#define IPV4_FRAME 16'h0800
85#define IPV6_FRAME 16'h86dd
86/*
87#define NO_IP_FRAME_TYPE 5'bxxx0x
88#define IPV4_FRAME_TYPE 5'b00010
89#define IPV4_TAGGED 5'b00110
90#define IPV4_LLC 5'b00011
91#define IPV4_TAGGED_LLC 5'b00111
92#define IPV6_FRAME_TYPE 5'b01010
93#define IPV6_TAGGED 5'b01110
94#define IPV6_LLC 5'b01011
95#define IPV6_TAGGED_LLC 5'b01111
96#define TUNNEL_FRAME 5'b1xxxx
97*/
98#define NO_IP_FRAME_TYPE 5'b0xx0x
99#define IPV4_FRAME_TYPE 5'b00010
100#define IPV4_TAGGED 5'b00110
101#define IPV4_LLC 5'b00011
102#define IPV4_TAGGED_LLC 5'b00111
103#define IPV6_FRAME_TYPE 5'b01010
104#define IPV6_TAGGED 5'b01110
105#define IPV6_LLC 5'b01011
106#define IPV6_TAGGED_LLC 5'b01111
107//#define TUNNEL_FRAME 6'bx1xxxx
108#define USER_FRAME_TYPE 5'b10000
109#define USER_TAGGED 5'b10100
110#define USER_LLC 5'b10001
111#define USER_TAGGED_LLC 5'b10101
112
113//#define NO_IP_TYPE 4'h0
114//#define IPV4_TYPE 4'h4
115//#define IPV6_TYPE 4'h6
116#define VER_IPV4 4'h4
117#define VER_IPV6 4'h6
118#define PROTOCOL_TCP 8'h06
119#define PROTOCOL_SCTP 8'h84
120#define NEXT_HDR_TCP 8'h06
121#define NEXT_HDR_SCTP 8'h84
122#define PROTOCOL_UDP 8'h11
123#define NEXT_HDR_UDP 8'h11
124#define PROTOCOL_IPSEC_ESP 8'h32
125#define PROTOCOL_IPSEC_AH 8'h33
126#define NEXT_HDR_IPSEC_ESP 8'h32
127#define NEXT_HDR_IPSEC_AH 8'h33
128#define CAM_ENTRIES 256
129
130//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
131//@@ Hardwire Class and Mask values. @@
132//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
133
134#define CLASS8_HDR 122'h0000_0600_0000_0000_0000_0045_0800 //TCP/IPv4
135#define CLASS9_HDR 122'h0000_1100_0000_0000_0000_0045_0800 //UDP/IPv4
136#define CLASS10_HDR 122'h0000_3200_0000_0000_0000_0045_0800 //SEC/IPv4
137#define CLASS11_HDR 122'h0000_0000_0006_0000_0000_0060_08dd //TCP/IPv6
138#define CLASS12_HDR 122'h0000_0000_0011_0000_0000_0060_08dd //UDP/IPv6
139#define CLASS13_HDR 122'h0000_0000_0032_0000_0000_0060_08dd //SEC/IPv6
140#define CLASS14_HDR 122'h0000_0000_0000_0000_0000_0000_0806 //ARP
141#define CLASS15_HDR 122'h0000_0000_0000_0000_0000_0000_0835 //RARP
142
143#define CLASS8_BIT_MASK_HDR 112'h0000_ff00_0000_0000_0000_00ff_ffff
144#define CLASS9_BIT_MASK_HDR 112'h0000_ff00_0000_0000_0000_00ff_ffff
145#define CLASS10_BIT_MASK_HDR 112'h0000_fe00_0000_0000_0000_00ff_ffff
146#define CLASS11_BIT_MASK_HDR 112'h0000_0000_00ff_0000_0000_00f0_ffff
147#define CLASS12_BIT_MASK_HDR 112'h0000_0000_00ff_0000_0000_00f0_ffff
148#define CLASS13_BIT_MASK_HDR 112'h0000_0000_00fe_0000_0000_00f0_ffff
149#define CLASS14_BIT_MASK_HDR 112'h0000_0000_0000_0000_0000_0000_ffff
150#define CLASS15_BIT_MASK_HDR 112'h0000_0000_0000_0000_0000_0000_ffff
151
152#define CLASS8_BYTE_MASK_HDR 28'b0000_0100_0000_0000_0000_0001_0101
153#define CLASS9_BYTE_MASK_HDR 28'b0000_0100_0000_0000_0000_0001_0101
154#define CLASS10_BYTE_MASK_HDR 28'b0000_1100_0000_0000_0000_0001_0101
155#define CLASS11_BYTE_MASK_HDR 28'b0000_0000_0001_0000_0000_0011_0101
156#define CLASS12_BYTE_MASK_HDR 28'b0000_0000_0001_0000_0000_0011_0101
157#define CLASS13_BYTE_MASK_HDR 28'b0000_0000_0011_0000_0000_0011_0101
158#define CLASS14_BYTE_MASK_HDR 28'b0000_0000_0000_0000_0000_0000_0101
159#define CLASS15_BYTE_MASK_HDR 28'b0000_0000_0000_0000_0000_0000_0101
160
161#define CLASS_0 0
162#define CLASS_1 1
163#define CLASS_2 2
164#define CLASS_3 3
165#define CLASS_4 4
166#define CLASS_5 5
167#define CLASS_6 6
168#define CLASS_7 7
169#define CLASS_8 8
170#define CLASS_9 9
171#define CLASS_10 10
172#define CLASS_11 11
173#define CLASS_12 12
174#define CLASS_13 13
175#define CLASS_14 14
176#define CLASS_15 15
177#define CLASS_16 16
178#define CLASS_17 17
179#define CLASS_18 18
180#define CLASS_19 19
181#define CLASS_20 20
182#define CLASS_21 21
183#define CLASS_22 22
184#define CLASS_23 23
185
186// CAM CMD Bus Defines
187//cam instructions, insn[16:0] with crb[2:0] tied to 0s.
188// gmask[16:11], segsel[10:7], ltin[6:4], inst=[3:0]
189
190#define SRCH_CMD 17'b1_0000_0000_0001_0010 //10012
191#define SRCH_WIDE_CMD 17'b1_0010_0000_1010_0010 //120a2
192#define SRCH_SEC_CMD 17'b1_0001_0000_0001_0010 //11012
193#define SRCH_WIDE_SEC_CMD 17'b1_0100_0000_1010_0010 //140a2
194#define NFA_LOOKUP_CMD 17'b0_0000_0001_0001_1010 //0011a
195#define NFA_WIDE_LOOKUP_CMD 17'b0_0000_0001_1010_1010 //001aa
196#define RD_CMD 17'b0_0000_0000_0000_0000 //00000
197#define WR_CMD 17'b0_0000_0000_0000_0001 //00001
198#define RD_SRAM_CMD 17'b0_0000_0000_0000_0100 //00004
199#define MOVE_CMD 17'b0_0000_0000_0000_0111 //00007
200
201
202// CAM Instruction
203#define INST_READ 4'b0000
204#define CAM_READ 4'b0000
205#define LMASK_READ 4'b0000
206#define REG_READ 4'b0000
207#define ZBTSRAM_READ 4'b0100
208#define PARITY 4'b0000
209#define MOVE_ENT 4'b0111
210#define NFA_LOOKUP 4'b0000
211
212#define INST_WRITE 4'b0001
213#define CAM_WRITE 4'b0000
214#define LMASK_WRITE 4'b0000
215#define REG_WRITE 4'b0000
216#define ZBTSRAM_WRITE 4'b0000
217
218#define INST_LOOKUP 4'b0010
219#define INST_SRAM_NOW_READ 4'b0000
220#define INST_PARITY 4'b0000
221#define INST_NFA_LOOKUP 4'b1010
222
223// CAM Instruction Access Type
224#define WRITE_CAM_KEY 4'b0001
225#define WRITE_CAM_LMASK 4'b0001
226#define WRITE_ZBTSRAM 4'b0001
227#define WRITE_CAM_REG 4'b0001
228
229// CAM CMDs Defines In CAM_CAM_REG
230#define NOP_CMD 5'b01000
231#define RD_CAM_REG 5'b01001
232#define WR_CAM_REG 5'b01010
233#define RD_CAM_KEY 5'b01011
234#define WR_CAM_KEY 5'b01100
235#define RD_CAM_LMASK 5'b01101
236#define WR_CAM_LMASK 5'b01110
237#define RD_ASSOC_D 5'b01111
238#define RD_ASSOC_D_W_KEY 5'b10000
239#define WR_ASSOC_D 5'b10001
240#define WR_ASSOC_D_W_KEY 5'b10010
241#define SET_AGE_BIT 5'b10011
242#define UPDATE_BACKLOG 5'b10100
243#define INC_BACKLOG 5'b10101
244#define DEC_BACKLOG 5'b10110
245#define INV_ENTRY 5'b10111
246#define INV_ENTRY_WR_DEF_LMASK 5'b11000
247#define INV_ALL 5'b11001
248#define MOVE_ENTRY 5'b11010
249
250// CAM Lookup Type
251#define LOOKUP_144 3'b001
252#define LOOKUP_288 3'b010
253
254// CAM Region Setup
255//#define REGION1_144_MAX_INDEX 16'h67ff // the last entry pointer
256//#define REGION2_144_MAX_INDEX 16'h7fff // the last entry pointer
257//#define REGION1_288_MAX_INDEX 16'he7f8 // the last entry pointer
258//#define REGION2_288_MAX_INDEX 16'hfffc // the last entry pointer
259
260// CAM Region Setup
261#define REGION1_144_1ST_CAM_INDEX 16'h0 // region1(fflp) 1st 144 entry pointer
262#define REGION1_144_LAST_CAM_INDEX 16'h67ff // region1(fflp) 1st 144 entry pointer
263#define REGION2_144_1ST_CAM_INDEX 16'h6800 // region2(cpu) 1st 144 entry pointer
264#define REGION2_144_LAST_CAM_INDEX 16'h7fff // region2(cpu) last 144 entry pointer
265
266#define REGION1_288_1ST_CAM_INDEX 16'h8000 // region1(fflp) 1st 288 entry pointer
267#define REGION1_288_LAST_CAM_INDEX 16'he7f8 // region1(fflp) 1st 288 entry pointer
268#define REGION2_288_1ST_CAM_INDEX 16'he7fc // region2(cpu) 1st 288 entry pointer
269#define REGION2_288_LAST_CAM_INDEX 16'hffff // region2(cpu) last 288 entry pointer
270
271//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
272//@ TCP/UDP Related Defines
273//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
274#define SYNC 1'b1
275
276#define TCP_SYN 2'b00
277#define TCP_FLAG 2'b01
278#define TCP_FIN 2'b10
279
280#define MAX_LOOKUP_INST_WAIT 1000 // number of clk2x to expect a cam cmd before timeout
281#define ZZ 1000 // number of clk2x to expect a cam cmd before timeout
282#define YY 500 // In normal mode: number of core_clk to expect a fwd_dec before timeout
283#define FWD_DEC_TIMEOUT 500 // In normal mode: number of core_clk to expect a fwd_dec before timeout
284#define BYBY 500 // In bypass mode: number of core_clk to expect a fwd_dec before timeout
285#define LB_TIMER 1000 // number of cam_clk to expect lb transaction by fflp
286#define BAD 1'b1
287#define MAX_WAIT 1000
288#define FFLP_BMC_W 1000 // number of cclk to expect fflp_bmc rd1_addr1 transaction
289#define FFLP_BMC_RD1_ADDR2_W 1000 // number of cclk to expect fflp_bmc rd1_addr2 transaction
290#define FFLP_BMC_RD_LATENCY 1000 // number of cclk to expect data0/1 passed by bmc to fflp
291#define FFLP_BMC_WR1_DATA_W 1000 // number of cclk to expect fflp_bmc wrt transaction
292
293#define BMC_CAM 1000 // number of cclk to expect fflp_cam transaction
294 // for lb table as_data update
295
296//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
297//@ VLAN TABLE Defines
298//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
299#define VLAN_BLOCK0 2'b00 // VLAN Table Block0
300#define VLAN_BLOCK1 2'b01 // VLAN Table Block1
301#define VLAN_BLOCK2 2'b10 // VLAN Table Block2
302#define VLAN_BLOCK3 2'b11 // VLAN Table Block3
303
304
305 #define IP_DB_ENTRIES 128
306
307#define CAM_COMP_ONLY_CLS_CODE 200'hf8_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000
308#define CAM_NO_LMASK 200'hff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff
309#define CAM_LMASK_CLS_CODE 200'h07_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff
310#define CAM_LMASK_L2RDC 200'hff_07ff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff
311#define CAM_LMASK_NOPORT 200'hff_fbff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff
312#define CAM_LMASK_L4PT_TOS 200'hff_ffff_ffff_ffff_ffff_ffff_00ff_ffff_ffff_ffff_ffff_ffff_ffff
313#define CAM_LMASK_L4PT_PID 200'hff_ffff_ffff_ffff_ffff_ffff_ff00_ffff_ffff_ffff_ffff_ffff_ffff
314#define CAM_LMASK_L4PT_SPI 200'hff_ffff_ffff_ffff_ffff_ffff_ffff_0000_0000_ffff_ffff_ffff_ffff
315#define CAM_LMASK_IPV4_SRC_ADDR 200'hff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_0000_0000_ffff_ffff
316#define CAM_LMASK_IPV4_DST_ADDR 200'hff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_0000_0000
317#define CAM_LMASK_IPV6_ADDR 200'hff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_0000_0000_0000_0000
318#define CAM_LMASK_FRAGMENT_PKTS 200'hf8_0400_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000
319
320#define FLOW_KEY_WIDTH_SIZE 384
321#define H1_CRC_32C_POLY 32'h1edc_6f41
322#define H2_CRC_CCITT_POLY 16'h1021
323#define DEFAULT_HASH1_INITIAL_VALUE 32'hc000_0000
Full OpenSPARC design & verification tarball including full HDL.