[OpenSPARC-T2-DV] / verif / env / niu / vera / niu_pio / include / fflp_memory_map.vri

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fflp_memory_map.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#include "neptune_memory_map.vri"

#define fullFFLP_CONFIG		 FFLP_ADDRESS_RANGE+FFLP_CONFIG
#define fullFFLP_CAM_KEY_REG0	 FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_REG0
#define fullFFLP_CAM_KEY_REG1	 FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_REG1
#define fullFFLP_CAM_KEY_REG2	 FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_REG2
#define fullFFLP_CAM_KEY_REG3	 FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_REG3
#define fullFFLP_CAM_MASK_REG0	 FFLP_ADDRESS_RANGE+20'h0_00b0
#define fullFFLP_CAM_MASK_REG1	 FFLP_ADDRESS_RANGE+20'h0_00b8
#define fullFFLP_CAM_MASK_REG2	 FFLP_ADDRESS_RANGE+20'h0_00c0
#define fullFFLP_CAM_MASK_REG3	 FFLP_ADDRESS_RANGE+20'h0_00c8
#define fullFFLP_CAM_CONTROL	 FFLP_ADDRESS_RANGE+FFLP_CAM_CONTROL
#define fullFFLP_TCAM_ERR	 FFLP_ADDRESS_RANGE+FFLP_TCAM_ERR

#define FFLP_CONFIG                      20'h0_0100
#define FFLP_DBG_TRAIN_VCT               20'h0_0148
#define FFLP_TCP_CFLAG_MASK		 20'h0_0108
#define FFLP_FCRAM_REF_TMR		 20'h0_0110
#define FFLP_FCRAM_FIO_ADDR              20'h0_0118
#define FFLP_FCRAM_FIO_DAT               20'h0_0120
#define FFLP_FCRAM_PHY_RD_LAT            20'h0_0150

//L2 class2 class3
#define FFLP_L2_CLS_2                    20'h0_0000
#define FFLP_L2_CLS_3                    20'h0_0008

//L3 class4-7 
#define FFLP_L3_CLS_4                    20'h0_0010
#define FFLP_L3_CLS_5                    20'h0_0018
#define FFLP_L3_CLS_6                    20'h0_0020
#define FFLP_L3_CLS_7                    20'h0_0028


//CAM KEY & MASK
#define FFLP_CAM_KEY_REG0                20'h0_0090
#define FFLP_CAM_KEY_REG1                20'h0_0098
#define FFLP_CAM_KEY_REG2                20'h0_00a0
#define FFLP_CAM_KEY_REG3                20'h0_00a8
#define FFLP_CAM_KEY_MASK_REG0           20'h0_00b0
#define FFLP_CAM_KEY_MASK_REG1           20'h0_00b8
#define FFLP_CAM_KEY_MASK_REG2           20'h0_00c0
#define FFLP_CAM_KEY_MASK_REG3           20'h0_00c8
#define FFLP_CAM_CONTROL		 20'h0_00d0

//HOW TO BUILD TCAM KEY REGISTERS
#define FFLP_HOW_TCAM_KEY_CLS_4          20'h0_0030
#define FFLP_HOW_TCAM_KEY_CLS_5          20'h0_0038
#define FFLP_HOW_TCAM_KEY_CLS_6          20'h0_0040
#define FFLP_HOW_TCAM_KEY_CLS_7          20'h0_0048
#define FFLP_HOW_TCAM_KEY_CLS_8          20'h0_0050
#define FFLP_HOW_TCAM_KEY_CLS_9          20'h0_0058
#define FFLP_HOW_TCAM_KEY_CLS_A          20'h0_0060
#define FFLP_HOW_TCAM_KEY_CLS_B          20'h0_0068
#define FFLP_HOW_TCAM_KEY_CLS_C          20'h0_0070
#define FFLP_HOW_TCAM_KEY_CLS_D          20'h0_0078
#define FFLP_HOW_TCAM_KEY_CLS_E          20'h0_0080
#define FFLP_HOW_TCAM_KEY_CLS_F          20'h0_0088

//HOW TO BUILD FLOW KEY REGISTERS
#define FFLP_HOW_FLOW_KEY_CLS_4          20'h0_0000
#define FFLP_HOW_FLOW_KEY_CLS_5          20'h0_0008
#define FFLP_HOW_FLOW_KEY_CLS_6          20'h0_0010
#define FFLP_HOW_FLOW_KEY_CLS_7          20'h0_0018
#define FFLP_HOW_FLOW_KEY_CLS_8          20'h0_0020
#define FFLP_HOW_FLOW_KEY_CLS_9          20'h0_0028
#define FFLP_HOW_FLOW_KEY_CLS_A          20'h0_0030
#define FFLP_HOW_FLOW_KEY_CLS_B          20'h0_0038
#define FFLP_HOW_FLOW_KEY_CLS_C          20'h0_0040
#define FFLP_HOW_FLOW_KEY_CLS_D          20'h0_0048
#define FFLP_HOW_FLOW_KEY_CLS_E          20'h0_0050
#define FFLP_HOW_FLOW_KEY_CLS_F          20'h0_0058

#define FFLP_FLOW_H1POLY                 20'h0_0060 
#define FFLP_FLOW_H2POLY                 20'h0_0068 
#define FFLP_FLOW_PARTITION_SEL          20'h0_0070 
#define FFLP_HASH_TABLE_ADDR             20'h0_0000  // count 8 step 8192
#define FFLP_HASH_TABLE_DATA             20'h0_0008  // count 8 step 8192
#define FFLP_HASH_TABLE_DATA_LOG         20'h0_0010  // count 8 step 8192

//ERROR reg
#define	FFLP_VLAN_PAR_ERR		 20'h0_8000 
#define FFLP_TCAM_ERR			 20'h0_00d8
#define FFLP_HASH_TABLE_DATA_ERR	 20'h0_0010
#define FFLP_HASH_TABLE_LOOKUP_ERR1	 20'h0_00e0
#define FFLP_HASH_TABLE_LOOKUP_ERR2	 20'h0_00e8
#define FFLP_FCRAM_ERR0			 20'h0_0128
#define FFLP_FCRAM_ERR1			 20'h0_0130
#define FFLP_FCRAM_ERR2			 20'h0_0138
#define FFLP_ERR_MASK			 20'h0_0140
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: fflp_memory_map.vri
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	#include "neptune_memory_map.vri"
	36
	37	#define fullFFLP_CONFIG FFLP_ADDRESS_RANGE+FFLP_CONFIG
	38	#define fullFFLP_CAM_KEY_REG0 FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_REG0
	39	#define fullFFLP_CAM_KEY_REG1 FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_REG1
	40	#define fullFFLP_CAM_KEY_REG2 FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_REG2
	41	#define fullFFLP_CAM_KEY_REG3 FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_REG3
	42	#define fullFFLP_CAM_MASK_REG0 FFLP_ADDRESS_RANGE+20'h0_00b0
	43	#define fullFFLP_CAM_MASK_REG1 FFLP_ADDRESS_RANGE+20'h0_00b8
	44	#define fullFFLP_CAM_MASK_REG2 FFLP_ADDRESS_RANGE+20'h0_00c0
	45	#define fullFFLP_CAM_MASK_REG3 FFLP_ADDRESS_RANGE+20'h0_00c8
	46	#define fullFFLP_CAM_CONTROL FFLP_ADDRESS_RANGE+FFLP_CAM_CONTROL
	47	#define fullFFLP_TCAM_ERR FFLP_ADDRESS_RANGE+FFLP_TCAM_ERR
	48
	49	#define FFLP_CONFIG 20'h0_0100
	50	#define FFLP_DBG_TRAIN_VCT 20'h0_0148
	51	#define FFLP_TCP_CFLAG_MASK 20'h0_0108
	52	#define FFLP_FCRAM_REF_TMR 20'h0_0110
	53	#define FFLP_FCRAM_FIO_ADDR 20'h0_0118
	54	#define FFLP_FCRAM_FIO_DAT 20'h0_0120
	55	#define FFLP_FCRAM_PHY_RD_LAT 20'h0_0150
	56
	57	//L2 class2 class3
	58	#define FFLP_L2_CLS_2 20'h0_0000
	59	#define FFLP_L2_CLS_3 20'h0_0008
	60
	61	//L3 class4-7
	62	#define FFLP_L3_CLS_4 20'h0_0010
	63	#define FFLP_L3_CLS_5 20'h0_0018
	64	#define FFLP_L3_CLS_6 20'h0_0020
65	#define FFLP_L3_CLS_7 20'h0_0028
66
67
68	//CAM KEY & MASK
69	#define FFLP_CAM_KEY_REG0 20'h0_0090
70	#define FFLP_CAM_KEY_REG1 20'h0_0098
71	#define FFLP_CAM_KEY_REG2 20'h0_00a0
72	#define FFLP_CAM_KEY_REG3 20'h0_00a8
73	#define FFLP_CAM_KEY_MASK_REG0 20'h0_00b0
74	#define FFLP_CAM_KEY_MASK_REG1 20'h0_00b8
75	#define FFLP_CAM_KEY_MASK_REG2 20'h0_00c0
76	#define FFLP_CAM_KEY_MASK_REG3 20'h0_00c8
77	#define FFLP_CAM_CONTROL 20'h0_00d0
78
79	//HOW TO BUILD TCAM KEY REGISTERS
80	#define FFLP_HOW_TCAM_KEY_CLS_4 20'h0_0030
81	#define FFLP_HOW_TCAM_KEY_CLS_5 20'h0_0038
82	#define FFLP_HOW_TCAM_KEY_CLS_6 20'h0_0040
83	#define FFLP_HOW_TCAM_KEY_CLS_7 20'h0_0048
84	#define FFLP_HOW_TCAM_KEY_CLS_8 20'h0_0050
85	#define FFLP_HOW_TCAM_KEY_CLS_9 20'h0_0058
86	#define FFLP_HOW_TCAM_KEY_CLS_A 20'h0_0060
87	#define FFLP_HOW_TCAM_KEY_CLS_B 20'h0_0068
88	#define FFLP_HOW_TCAM_KEY_CLS_C 20'h0_0070
89	#define FFLP_HOW_TCAM_KEY_CLS_D 20'h0_0078
90	#define FFLP_HOW_TCAM_KEY_CLS_E 20'h0_0080
91	#define FFLP_HOW_TCAM_KEY_CLS_F 20'h0_0088
92
93	//HOW TO BUILD FLOW KEY REGISTERS
94	#define FFLP_HOW_FLOW_KEY_CLS_4 20'h0_0000
95	#define FFLP_HOW_FLOW_KEY_CLS_5 20'h0_0008
96	#define FFLP_HOW_FLOW_KEY_CLS_6 20'h0_0010
97	#define FFLP_HOW_FLOW_KEY_CLS_7 20'h0_0018
98	#define FFLP_HOW_FLOW_KEY_CLS_8 20'h0_0020
99	#define FFLP_HOW_FLOW_KEY_CLS_9 20'h0_0028
100	#define FFLP_HOW_FLOW_KEY_CLS_A 20'h0_0030
101	#define FFLP_HOW_FLOW_KEY_CLS_B 20'h0_0038
102	#define FFLP_HOW_FLOW_KEY_CLS_C 20'h0_0040
103	#define FFLP_HOW_FLOW_KEY_CLS_D 20'h0_0048
104	#define FFLP_HOW_FLOW_KEY_CLS_E 20'h0_0050
105	#define FFLP_HOW_FLOW_KEY_CLS_F 20'h0_0058
106
107	#define FFLP_FLOW_H1POLY 20'h0_0060
108	#define FFLP_FLOW_H2POLY 20'h0_0068
109	#define FFLP_FLOW_PARTITION_SEL 20'h0_0070
110	#define FFLP_HASH_TABLE_ADDR 20'h0_0000 // count 8 step 8192
111	#define FFLP_HASH_TABLE_DATA 20'h0_0008 // count 8 step 8192
112	#define FFLP_HASH_TABLE_DATA_LOG 20'h0_0010 // count 8 step 8192
113
114	//ERROR reg
115	#define FFLP_VLAN_PAR_ERR 20'h0_8000
116	#define FFLP_TCAM_ERR 20'h0_00d8
117	#define FFLP_HASH_TABLE_DATA_ERR 20'h0_0010
118	#define FFLP_HASH_TABLE_LOOKUP_ERR1 20'h0_00e0
119	#define FFLP_HASH_TABLE_LOOKUP_ERR2 20'h0_00e8
120	#define FFLP_FCRAM_ERR0 20'h0_0128
121	#define FFLP_FCRAM_ERR1 20'h0_0130
122	#define FFLP_FCRAM_ERR2 20'h0_0138
123	#define FFLP_ERR_MASK 20'h0_0140
124