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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: txc_memory_map.vri | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #include "neptune_memory_map.vri" | |
36 | ||
37 | ||
38 | #define TXC_DMA0_BASE FZC_TXC_ADDRESS_RANGE + (8'h00 << 12) | |
39 | #define TXC_DMA1_BASE FZC_TXC_ADDRESS_RANGE + (8'h01 << 12) | |
40 | #define TXC_DMA2_BASE FZC_TXC_ADDRESS_RANGE + (8'h02 << 12) | |
41 | #define TXC_DMA3_BASE FZC_TXC_ADDRESS_RANGE + (8'h03 << 12) | |
42 | #define TXC_DMA4_BASE FZC_TXC_ADDRESS_RANGE + (8'h04 << 12) | |
43 | #define TXC_DMA5_BASE FZC_TXC_ADDRESS_RANGE + (8'h05 << 12) | |
44 | #define TXC_DMA6_BASE FZC_TXC_ADDRESS_RANGE + (8'h06 << 12) | |
45 | #define TXC_DMA7_BASE FZC_TXC_ADDRESS_RANGE + (8'h07 << 12) | |
46 | #define TXC_DMA8_BASE FZC_TXC_ADDRESS_RANGE + (8'h08 << 12) | |
47 | #define TXC_DMA9_BASE FZC_TXC_ADDRESS_RANGE + (8'h09 << 12) | |
48 | #define TXC_DMA10_BASE FZC_TXC_ADDRESS_RANGE + (8'h0a << 12) | |
49 | #define TXC_DMA11_BASE FZC_TXC_ADDRESS_RANGE + (8'h0b << 12) | |
50 | #define TXC_DMA12_BASE FZC_TXC_ADDRESS_RANGE + (8'h0c << 12) | |
51 | #define TXC_DMA13_BASE FZC_TXC_ADDRESS_RANGE + (8'h0d << 12) | |
52 | #define TXC_DMA14_BASE FZC_TXC_ADDRESS_RANGE + (8'h0e << 12) | |
53 | #define TXC_DMA15_BASE FZC_TXC_ADDRESS_RANGE + (8'h0f << 12) | |
54 | #define TXC_DMA16_BASE FZC_TXC_ADDRESS_RANGE + (8'h10 << 12) | |
55 | #define TXC_DMA17_BASE FZC_TXC_ADDRESS_RANGE + (8'h11 << 12) | |
56 | #define TXC_DMA18_BASE FZC_TXC_ADDRESS_RANGE + (8'h12 << 12) | |
57 | #define TXC_DMA19_BASE FZC_TXC_ADDRESS_RANGE + (8'h13 << 12) | |
58 | #define TXC_DMA20_BASE FZC_TXC_ADDRESS_RANGE + (8'h14 << 12) | |
59 | #define TXC_DMA21_BASE FZC_TXC_ADDRESS_RANGE + (8'h15 << 12) | |
60 | #define TXC_DMA22_BASE FZC_TXC_ADDRESS_RANGE + (8'h16 << 12) | |
61 | #define TXC_DMA23_BASE FZC_TXC_ADDRESS_RANGE + (8'h17 << 12) | |
62 | #define TXC_DMA24_BASE FZC_TXC_ADDRESS_RANGE + (8'h18 << 12) | |
63 | #define TXC_DMA25_BASE FZC_TXC_ADDRESS_RANGE + (8'h19 << 12) | |
64 | #define TXC_DMA26_BASE FZC_TXC_ADDRESS_RANGE + (8'h1a << 12) | |
65 | #define TXC_DMA27_BASE FZC_TXC_ADDRESS_RANGE + (8'h1b << 12) | |
66 | #define TXC_DMA28_BASE FZC_TXC_ADDRESS_RANGE + (8'h1c << 12) | |
67 | #define TXC_DMA29_BASE FZC_TXC_ADDRESS_RANGE + (8'h1d << 12) | |
68 | #define TXC_DMA30_BASE FZC_TXC_ADDRESS_RANGE + (8'h1e << 12) | |
69 | #define TXC_DMA31_BASE FZC_TXC_ADDRESS_RANGE + (8'h1f << 12) | |
70 | #define TXC_PIO_BASE TXC_ADDRESS_RANGE + (8'h20 << 12) | |
71 | ||
72 | // This should be FZC_TXC_ADDRESS_RANGE | |
73 | #define TXC_FZC_BASE FZC_TXC_ADDRESS_RANGE + (8'h20 << 12) | |
74 | ||
75 | ||
76 | ||
77 | ||
78 | #define TXC_DMA_MAXBURST 12'h000 | |
79 | #define TXC_DMA_MAX_LEN 12'h008 | |
80 | #define TXC_DMA_MAXBURST_MASK 64'h00000000000fffff | |
81 | ||
82 | #define TXC_CONTROL 12'h000 // enable txc and all four macs | |
83 | #define TXC_CONTROL_MASK 64'h000000000000001f | |
84 | #define TXC_TRAINING 12'h008 // for training | |
85 | #define TXC_DEBUG_SELECT 12'h010 // for debug select | |
86 | ||
87 | #define TXC_MAX_REORDER 12'h018 // max -reorder | |
88 | #define TXC_PORT0_CONTROL 12'h020 // not used for now | |
89 | #define TXC_PORT0_DMA_ENBALE 12'h028 // PORT0_DMA_list | |
90 | #define TXC_PKT_STUFFED 12'h030 // pkts processed by re-order and pkt_assembly | |
91 | #define TXC_PKT_XMIT 12'h038 // pkts_transmitted | |
92 | #define TXC_ROECC_CTL 12'h040 // reorder fifo ecc control | |
93 | #define TXC_ROECC_ST 12'h048 // reorder fifo ecc control status | |
94 | #define TXC_RO_DATA0 12'h050 // re-order ecc_data[31:0] | |
95 | #define TXC_RO_DATA1 12'h058 // re-order ecc_data[63:32] | |
96 | #define TXC_RO_DATA2 12'h060 // re-order ecc_data[95:64] | |
97 | #define TXC_RO_DATA3 12'h068 // re-order ecc_data[127:96] | |
98 | #define TXC_RO_DATA4 12'h070 // re-order ecc_data[151:128] | |
99 | #define TXC_SFECC_CTL 12'h078 // store-forward ecc control | |
100 | #define TXC_SFECC_ST 12'h080 // store-forward ecc control status | |
101 | #define TXC_SF_DATA0 12'h088 // store-forward ecc_data[31:0] | |
102 | #define TXC_SF_DATA1 12'h090 // store-forward ecc_data[63:32] | |
103 | #define TXC_SF_DATA2 12'h098 // store-forward ecc_data[95:64] | |
104 | #define TXC_SF_DATA3 12'h0A0 // store-forward ecc_data[127:96] | |
105 | #define TXC_SF_DATA4 12'h0A8 // store-forward ecc_data[151:128] | |
106 | #define TXC_RO_TIDS 12'h0B0 // meta TIDS in use | |
107 | #define TXC_RO_STATE0 12'h0B8 // detected duplicate TID in use | |
108 | #define TXC_RO_STATE1 12'h0C0 // Uninitialized TID dectected | |
109 | #define TXC_RO_STATE2 12'h0C8 // Timed out TIDS | |
110 | #define TXC_RO_STATE3 12'h0D0 // | |
111 | #define TXC_RO_CTL 12'h0D8 | |
112 | #define TXC_RO_ST_DATA0 12'h0E0 | |
113 | #define TXC_RO_ST_DATA1 12'h0E8 | |
114 | #define TXC_RO_ST_DATA2 12'h0F0 | |
115 | #define TXC_RO_ST_DATA3 12'h0F8 | |
116 | ||
117 | #define PORT0_PACKETS_REQUEST 12'h100 | |
118 | #define PORT1_PACKETS_REQUEST 12'h200 | |
119 | #define PORT2_PACKETS_REQUEST 12'h300 | |
120 | #define PORT3_PACKETS_REQUEST 12'h400 | |
121 | ||
122 | #define TXC_INT_STAT_DBG 12'h420 // reg to force interrupt event | |
123 | #define TXC_INT_STAT 12'h428 // reg to log the interrupt event | |
124 | #define TXC_INT_MASK 12'h430 // reg for setting the masks | |
125 | ||
126 | ||
127 | #define TXC_PORT1_CONTROL 12'h120 // not used for now | |
128 | #define TXC_PORT1_DMA_ENBALE 12'h128 // PORT1_DMA_list | |
129 | ||
130 | #define TXC_PORT2_CONTROL 12'h220 // not used for now | |
131 | #define TXC_PORT2_DMA_ENBALE 12'h228 // PORT2_DMA_list | |
132 | ||
133 | #define TXC_PORT3_CONTROL 12'h320 // not used for now | |
134 | #define TXC_PORT3_DMA_ENBALE 12'h328 // PORT3_DMA_list | |
135 | ||
136 | #define TXC_PORT_CONTROL_MASK 64'h0000000000ffffff | |
137 | ||
138 | #define TXC_PORT0_DMA_ENBALE_MASK 64'h0000_0000_0000_ffff // PORT0_DMA_list_mask | |
139 | ||
140 | #define TXC_DMA_0_DUMMY1 12'h008 // 20'h00008 - RW | |
141 | #define TXC_DMA_0_DUMMY2 12'h010 // 20'h00010 - RW | |
142 | #define TXC_DMA_0_DUMMY3 12'h018 // 20'h00018 - RW | |
143 | #define TXC_DMA_0_DUMMY4 12'h020 // 20'h00020 - RW | |
144 | #define TXC_DMA_0_DUMMY5 12'h028 // 20'h00028 - RW | |
145 | #define TXC_DMA_0_DUMMY6 12'h030 // 20'h00030 - RW | |
146 | #define TXC_DMA_0_DUMMY7 12'h038 // 20'h00038 - RW | |
147 | #define TXC_DMA_0_DUMMY8 12'h040 // 20'h00040 - RW | |
148 | #define TXC_DMA_0_DUMMY9 12'h048 // 20'h00048 - RW | |
149 | ||
150 |