Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / niu / vera / niu_pio / txc_util.vr
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: txc_util.vr
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35#include <vera_defines.vrh>
36#include "txc_memory_map.vri"
37#include "dmc_memory_map.vri"
38#include "mac_defines.vri"
39#include "pio_driver.vrh"
40//#include "ncu_stub.vrh"
41// extern Cncu_stub ncu_driver;
42extern niu_gen_pio gen_pio_drv;
43
44class txc_util_class {
45
46 task new( ) {
47 }
48
49 task txc_init ((bit [63:0] data = 64'h1f));
50 task write_train_vec(bit [31:0] data);
51 task write_tdmc_train_vec(bit [31:0] data);
52 task write_txc_dbgsel(bit [5:0] data);
53 task write_tdmc_dbgsel(bit [5:0] data);
54}
55
56
57task txc_util_class::txc_init((bit [63:0] data = 64'h1f)) {
58
59 bit [39:0] address;
60 bit [63:0] w_data;
61 bit [63:0] r_data;
62
63
64// For DMA0
65
66
67// Initialize DRR MAX BurstValue
68
69 address = TXC_FZC_BASE + TXC_CONTROL;
70 // w_data = 64'h1f; // Enable MAC All Ports and TXC
71 w_data = data; // Enable MAC All Ports and TXC
72 // ncu_driver.write_data(address,w_data);
73 gen_pio_drv.pio_wr(address,w_data);
74 printf(" Done with TXC_INIT \n");
75
76
77}
78
79task txc_util_class::write_train_vec(bit [31:0] data) {
80
81 bit [39:0] address;
82 bit [63:0] w_data;
83 bit [63:0] r_data;
84
85 w_data = {32'h0,data};
86
87 address = TXC_FZC_BASE + TXC_TRAINING;
88 gen_pio_drv.pio_wr(address,w_data);
89
90 repeat (10) @(posedge CLOCK);
91
92 address = TXC_FZC_BASE + TXC_TRAINING;
93 gen_pio_drv.pio_rd(address,r_data);
94
95}
96
97task txc_util_class::write_tdmc_train_vec(bit [31:0] data) {
98
99 bit [39:0] address;
100 bit [63:0] w_data;
101 bit [63:0] r_data;
102
103 w_data = {32'h0,data};
104
105 address = TDMC_TRAIN_VEC;
106 gen_pio_drv.pio_wr(address,w_data);
107
108 repeat (10) @(posedge CLOCK);
109
110 address = TDMC_TRAIN_VEC;
111 gen_pio_drv.pio_rd(address,r_data);
112
113}
114
115
116task txc_util_class::write_txc_dbgsel(bit [5:0] data) {
117
118 bit [39:0] address;
119 bit [63:0] w_data;
120 bit [63:0] r_data;
121
122 w_data = {58'h0,data};
123 address = TXC_FZC_BASE + TXC_DEBUG_SELECT;
124 gen_pio_drv.pio_wr(address,w_data);
125
126 repeat (10) @(posedge CLOCK);
127
128 address = TXC_FZC_BASE + TXC_DEBUG_SELECT;
129 gen_pio_drv.pio_rd(address,r_data);
130}
131
132task txc_util_class::write_tdmc_dbgsel(bit [5:0] data) {
133
134 bit [39:0] address;
135 bit [63:0] w_data;
136 bit [63:0] r_data;
137
138 w_data = {58'h0,data};
139 address = TDMC_DBG_SEL;
140 gen_pio_drv.pio_wr(address,w_data);
141
142 repeat (10) @(posedge CLOCK);
143
144 address = TDMC_DBG_SEL;
145 gen_pio_drv.pio_rd(address,r_data);
146}
147
148