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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_reset_port.vri | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #define OUTPUT_EDGE PHOLD | |
36 | #define INPUT_EDGE PSAMPLE #-1 | |
37 | #define OUTPUT_SKEW #1 | |
38 | #include "neptune_defines.vri" | |
39 | ||
40 | ||
41 | interface niu_reset_if { | |
42 | #ifdef NIU_GATE | |
43 | input clock CLOCK verilog_node NIU_DUV_PATH.rdp.iol2clk"; | |
44 | #else | |
45 | input clock CLOCK verilog_node NIU_DUV_PATH.rdp.niu_pio.niu_clk"; | |
46 | #endif | |
47 | output niu_reset_l OUTPUT_EDGE OUTPUT_SKEW verilog_node NIU_DUV_PATH.rdp.rst_por_"; | |
48 | ||
49 | } | |
50 | ||
51 | ||
52 | port reset_port { | |
53 | clock; | |
54 | niu_reset_l; | |
55 | } | |
56 | ||
57 | ||
58 | bind reset_port reset_bind { | |
59 | ||
60 | clock niu_reset_if.clock; | |
61 | niu_reset_l niu_reset_if.niu_reset_l; | |
62 | ||
63 | } |