Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / niu / vera / smx_drv / include / meta_driver.if.vri

#define OUTPUT_EDGE PHOLD
#define INPUT_EDGE PSAMPLE #-1
#define OUTPUT_SKEW #1


#define META_DUV_PATH NIU_DUV_PATH.tds
// #define META_DUV_PATH "meta_tb

#ifdef NIU_GATE

interface meta_write_if {

   input clk 	CLOCK verilog_node META_DUV_PATH.iol2clk";

//  These inputs are no longer used but since we don't want to rip them off 
//     they will be tied to "0" to get them to compile.    VJH

   input 	dmc_meta0_req INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_req";
   input [7:0] dmc_meta0_req_cmd INPUT_EDGE verilog_node "{ 2'b0, tb_top.cpu.tds.dmc_meta0_req_cmd_5_, tb_top.cpu.tds.dmc_meta0_req_cmd_4_, 1'b0, tb_top.cpu.tds.dmc_meta0_req_cmd_2_, tb_top.cpu.tds.dmc_meta0_req_cmd_1_, tb_top.cpu.tds.dmc_meta0_req_cmd_0_}";

   //input [5:0] dmc_meta0_transid INPUT_EDGE verilog_node "{ 1'b0, tb_top.cpu.tds.dmc_meta0_req_transID[4], tb_top.cpu.tds.dmc_meta0_req_transID[3], tb_top.cpu.tds.dmc_meta0_req_transID[2], tb_top.cpu.tds.dmc_meta0_req_transID[1], tb_top.cpu.tds.dmc_meta0_req_transID[0] }";
   input [5:0] dmc_meta0_transid INPUT_EDGE verilog_node "{ 6'b0}";

   input [1:0] dmc_meta0_port_num INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_req_port_num";
   input [4:0] dmc_meta0_dma_num INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_req_dma_num";
   input [13:0] dmc_meta0_req_length  INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_req_length";

   input [63:0] dmc_meta0_req_address INPUT_EDGE verilog_node "{ tb_top.cpu.tds.dmc_meta0_req_address_63_, tb_top.cpu.tds.dmc_meta0_req_address_62_, tb_top.cpu.tds.dmc_meta0_req_address_61_, tb_top.cpu.tds.dmc_meta0_req_address_60_, tb_top.cpu.tds.dmc_meta0_req_address_59_, tb_top.cpu.tds.dmc_meta0_req_address_58_, tb_top.cpu.tds.dmc_meta0_req_address_57_, tb_top.cpu.tds.dmc_meta0_req_address_56_, tb_top.cpu.tds.dmc_meta0_req_address_55_, tb_top.cpu.tds.dmc_meta0_req_address_54_, tb_top.cpu.tds.dmc_meta0_req_address_53_, tb_top.cpu.tds.dmc_meta0_req_address_52_, tb_top.cpu.tds.dmc_meta0_req_address_51_, tb_top.cpu.tds.dmc_meta0_req_address_50_, tb_top.cpu.tds.dmc_meta0_req_address_49_, tb_top.cpu.tds.dmc_meta0_req_address_48_, tb_top.cpu.tds.dmc_meta0_req_address_47_, tb_top.cpu.tds.dmc_meta0_req_address_46_, tb_top.cpu.tds.dmc_meta0_req_address_45_, tb_top.cpu.tds.dmc_meta0_req_address_44_, tb_top.cpu.tds.dmc_meta0_req_address_43_, tb_top.cpu.tds.dmc_meta0_req_address_42_, tb_top.cpu.tds.dmc_meta0_req_address_41_, tb_top.cpu.tds.dmc_meta0_req_address_40_, tb_top.cpu.tds.dmc_meta0_req_address_39_, tb_top.cpu.tds.dmc_meta0_req_address_38_, tb_top.cpu.tds.dmc_meta0_req_address_37_, tb_top.cpu.tds.dmc_meta0_req_address_36_, tb_top.cpu.tds.dmc_meta0_req_address_35_, tb_top.cpu.tds.dmc_meta0_req_address_34_, tb_top.cpu.tds.dmc_meta0_req_address_33_, tb_top.cpu.tds.dmc_meta0_req_address_32_, tb_top.cpu.tds.dmc_meta0_req_address_31_, tb_top.cpu.tds.dmc_meta0_req_address_30_, tb_top.cpu.tds.dmc_meta0_req_address_29_, tb_top.cpu.tds.dmc_meta0_req_address_28_, tb_top.cpu.tds.dmc_meta0_req_address_27_, tb_top.cpu.tds.dmc_meta0_req_address_26_, tb_top.cpu.tds.dmc_meta0_req_address_25_, tb_top.cpu.tds.dmc_meta0_req_address_24_, tb_top.cpu.tds.dmc_meta0_req_address_23_, tb_top.cpu.tds.dmc_meta0_req_address_22_, tb_top.cpu.tds.dmc_meta0_req_address_21_, tb_top.cpu.tds.dmc_meta0_req_address_20_, tb_top.cpu.tds.dmc_meta0_req_address_19_, tb_top.cpu.tds.dmc_meta0_req_address_18_, tb_top.cpu.tds.dmc_meta0_req_address_17_, tb_top.cpu.tds.dmc_meta0_req_address_16_, tb_top.cpu.tds.dmc_meta0_req_address_15_, tb_top.cpu.tds.dmc_meta0_req_address_14_, tb_top.cpu.tds.dmc_meta0_req_address_13_, tb_top.cpu.tds.dmc_meta0_req_address_12_, tb_top.cpu.tds.dmc_meta0_req_address_11_, tb_top.cpu.tds.dmc_meta0_req_address_10_,tb_top.cpu.tds.dmc_meta0_req_address_9_, tb_top.cpu.tds.dmc_meta0_req_address_8_, tb_top.cpu.tds.dmc_meta0_req_address_7_, tb_top.cpu.tds.dmc_meta0_req_address_6_, 6'b0}";

   // For I6.0 input [7:0]  dmc_meta0_clientid INPUT_EDGE verilog_node "{ 3'b0, tb_top.cpu.tds.dmc_meta0_req_client[4:2], 2'b0}"; 
   #ifdef POST_LAYOUT	// netlist changed via AStro
   input [7:0]  dmc_meta0_clientid INPUT_EDGE verilog_node "{ 3'b0, tb_top.cpu.tds.dmc_meta0_req_client_4_, tb_top.cpu.tds.niu_meta_arb_niu_wr_meta_arb_n267, tb_top.cpu.tds.dmc_meta0_req_client_2_, 2'b0}";
   #else
   //For 6.1 pre-layout back to _'s
   input [7:0]  dmc_meta0_clientid INPUT_EDGE verilog_node "{ 3'b0, tb_top.cpu.tds.dmc_meta0_req_client_4_, tb_top.cpu.tds.dmc_meta0_req_client_3_, tb_top.cpu.tds.dmc_meta0_req_client_2_, 2'b0}";
   #endif
   
   //input [127:0] dmc_meta0_data INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_data";
   input [127:0] dmc_meta0_data INPUT_EDGE verilog_node "{128'b0}";

   input         dmc_meta0_data_valid INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_data_valid";

   //input         dmc_meta0_transfer_complete INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_transfer_complete";
   input         dmc_meta0_transfer_complete INPUT_EDGE verilog_node "{1'b0}";

   //input [3:0]   dmc_meta0_status INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_status";
   input [3:0]   dmc_meta0_status INPUT_EDGE verilog_node "{4'b0}";

   //input [15:0]  dmc_meta0_req_byteenable INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_req_byteenable";
   input [15:0]  dmc_meta0_req_byteenable INPUT_EDGE verilog_node "{16'b0}";

   output          meta0_dmc_req_accept OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc0_req_accept";
   output          meta0_dmc_data_req OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc0_data_req";
   //output          meta0_dmc_req_errors OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc0_req_errors";

}

#else

interface meta_write_if {

   input clk 	CLOCK verilog_node META_DUV_PATH.niu_smx.niu_clk";

   input 	dmc_meta0_req INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_req";
   input [7:0] dmc_meta0_req_cmd INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_req_cmd";
   input [5:0] dmc_meta0_transid INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_req_transID";
   input [1:0] dmc_meta0_port_num INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_req_port_num";
   input [4:0] dmc_meta0_dma_num INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_req_dma_num";
   input [13:0] dmc_meta0_req_length  INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_req_length";
   input [63:0] dmc_meta0_req_address INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_req_address";
   input [7:0]  dmc_meta0_clientid INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_req_client";
   input [127:0] dmc_meta0_data INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_data";
   input         dmc_meta0_data_valid INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_data_valid";
   input         dmc_meta0_transfer_complete INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_transfer_complete";
   input [3:0]   dmc_meta0_status INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_status";
   input [15:0]  dmc_meta0_req_byteenable INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta0_req_byteenable";

   output          meta0_dmc_req_accept OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc0_req_accept";
   output          meta0_dmc_data_req OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc0_data_req";
   //output          meta0_dmc_req_errors OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc0_req_errors";

}
#endif



port dmc_write_port {

	clk ;
	command;
	address;
	command_request;
	length;
	dma_num;
	port_num;
	transid;
	client_id;
	data;
	data_valid;
	byte_enable;

	command_accept;
	data_req;


}

bind dmc_write_port meta_write_pbind {

	clk meta_write_if.clk;
	command_request meta_write_if.dmc_meta0_req;
	command meta_write_if.dmc_meta0_req_cmd;
	address meta_write_if.dmc_meta0_req_address;
	length meta_write_if.dmc_meta0_req_length;
	dma_num meta_write_if.dmc_meta0_dma_num;
	port_num meta_write_if.dmc_meta0_port_num;
	transid meta_write_if.dmc_meta0_transid;
	client_id meta_write_if.dmc_meta0_clientid;
	data meta_write_if.dmc_meta0_data;
	data_valid meta_write_if.dmc_meta0_data_valid;
	byte_enable meta_write_if.dmc_meta0_req_byteenable;

	command_accept meta_write_if.meta0_dmc_req_accept;
	data_req meta_write_if.meta0_dmc_data_req;

}



#ifdef NIU_GATE

interface meta_read_if {

   input clk 	CLOCK verilog_node META_DUV_PATH.iol2clk";

   input 	dmc_meta1_req INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta1_req";
   input [7:0] dmc_meta1_req_cmd INPUT_EDGE verilog_node "{ 2'b0, tb_top.cpu.tds.dmc_meta1_req_cmd_5_, tb_top.cpu.tds.dmc_meta1_req_cmd_4_, 1'b0, tb_top.cpu.tds.dmc_meta1_req_cmd_2_, tb_top.cpu.tds.dmc_meta1_req_cmd_1_, tb_top.cpu.tds.dmc_meta1_req_cmd_0_}";
   input [5:0] dmc_meta1_transid INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta1_req_trans_id";
   //input [5:0] dmc_meta1_transid INPUT_EDGE verilog_node "{tb_top.cpu.tds.dmc_meta1_req_transID[5], tb_top.cpu.tds.dmc_meta1_req_transID[4], tb_top.cpu.tds.dmc_meta1_req_transID[3], tb_top.cpu.tds.dmc_meta1_req_transID[2], tb_top.cpu.tds.dmc_meta1_req_transID[1], tb_top.cpu.tds.dmc_meta1_req_transID[0]}";
   input [1:0] dmc_meta1_port_num INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta1_req_port_num";
   input [4:0] dmc_meta1_dma_num INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta1_req_dma_num";
   input [13:0] dmc_meta1_req_length  INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta1_req_length";
   input [63:0] dmc_meta1_req_address INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta1_req_address";

   // For I6.0 use ['s input [7:0]  dmc_meta1_clientid INPUT_EDGE verilog_node "{ 2'b0, tb_top.cpu.tds.dmc_meta1_req_client[5], 2'b0, tb_top.cpu.tds.dmc_meta1_req_client[2], tb_top.cpu.tds.dmc_meta1_req_client[1], 1'b0}";
   //For I6.1 back to _'s.  ALso tied bit 1 to zero since not in netlist input [7:0]  dmc_meta1_clientid INPUT_EDGE verilog_node "{ 2'b0, tb_top.cpu.tds.dmc_meta1_req_client_5_, 2'b0, tb_top.cpu.tds.dmc_meta1_req_client_2_, 2'b0}";
// For PRE_TO_1.0 only bits dmc_meta1_req_client_[5,1 & 0] are available 
   
   #ifdef POST_LAYOUT
   input [7:0]  dmc_meta1_clientid INPUT_EDGE verilog_node "{ 2'b0, tb_top.cpu.tds.dmc_meta1_req_client_5_, 2'b0, tb_top.cpu.tds.niu_meta_arb_niu_rd_meta_arb_n485ASThfnNet2721, 2'b0}";
   #else
   input [7:0]  dmc_meta1_clientid INPUT_EDGE verilog_node "{ 2'b0, tb_top.cpu.tds.dmc_meta1_req_client_5_, 3'b0, tb_top.cpu.tds.dmc_meta1_req_client_1_, tb_top.cpu.tds.dmc_meta1_req_client_0_}";
   #endif

   output          meta1_dmc_req_accept OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc1_req_accept";

}

#else

interface meta_read_if {

   input clk 	CLOCK verilog_node META_DUV_PATH.niu_smx.niu_clk";

   input 	dmc_meta1_req INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta1_req";
   input [7:0] dmc_meta1_req_cmd INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta1_req_cmd";
   input [5:0] dmc_meta1_transid INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta1_req_trans_id";
   input [1:0] dmc_meta1_port_num INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta1_req_port_num";
   input [4:0] dmc_meta1_dma_num INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta1_req_dma_num";
   input [13:0] dmc_meta1_req_length  INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta1_req_length";
   input [63:0] dmc_meta1_req_address INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta1_req_address";
   input [7:0]  dmc_meta1_clientid INPUT_EDGE verilog_node META_DUV_PATH.dmc_meta1_req_client";

   output          meta1_dmc_req_accept OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc1_req_accept";

}
#endif

port dmc_read_port {

	clk ;
	command;
	address;
	command_request;
	length;
	dma_num;
	port_num;
	transid;
	client_id;

	command_accept;
}

bind dmc_read_port meta_read_pbind {

	clk meta_read_if.clk;
	command_request meta_read_if.dmc_meta1_req;
	command meta_read_if.dmc_meta1_req_cmd;
	address meta_read_if.dmc_meta1_req_address;
	length meta_read_if.dmc_meta1_req_length;
	dma_num meta_read_if.dmc_meta1_dma_num;
	port_num meta_read_if.dmc_meta1_port_num;
	transid meta_read_if.dmc_meta1_transid;
	client_id meta_read_if.dmc_meta1_clientid;
	command_accept meta_read_if.meta1_dmc_req_accept;

}



#ifdef NIU_GATE

interface meta_read_resp_if {

   input clk 	CLOCK verilog_node META_DUV_PATH.iol2clk";

   output 	meta_dmc_resp_ready OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_resp_ready";
   output [7:0] meta_dmc_resp_cmd OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_resp_cmd";
   output [5:0] meta_dmc_resp_transid OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_resp_trans_id";
   output [1:0] meta_dmc_resp_port_num OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_resp_port_num";
   output [4:0] meta_dmc_resp_dma_num OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_resp_dma_num";
   output [13:0] meta_dmc_resp_length  OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_resp_length";
   output [63:0] meta_dmc_resp_address OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_resp_address";

// Missing bits not used and eatten up by synopsys.  Tie to so pin of origating FF since no q pins
// in netlist   VJH
   output [7:0]  meta_dmc_resp_clientid OUTPUT_EDGE verilog_node "{ tb_top.cpu.tds.niu_smx_resp_dmc_resp_cmdlaunch_smx_dmc_client_reg_7_.so, tb_top.cpu.tds.niu_smx_resp_dmc_resp_cmdlaunch_smx_dmc_client_reg_6_.so, tb_top.cpu.tds.niu_smx_resp_dmc_resp_cmdlaunch_smx_dmc_client_reg_5_.so, tb_top.cpu.tds.meta_dmc_resp_client_tdmc, tb_top.cpu.tds.niu_smx_resp_dmc_resp_cmdlaunch_smx_dmc_client_reg_3_.so, tb_top.cpu.tds.meta_dmc_resp_client_txc, tb_top.cpu.tds.niu_smx_resp_dmc_resp_cmdlaunch_smx_dmc_client_reg_1_.so, tb_top.cpu.tds.meta_dmc_resp_client_rdmc }";

   output [15:0] meta_dmc_resp_byteenable OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_resp_byteenable";
   output [127:0] meta_dmc_resp_data OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_data";
  
// Missing bits not used and eatten up by synopsys   Tie to so pin of origating FF since no q pins
// in netlist	VJH
   output [7:0]  meta_dmc_resp_data_valid OUTPUT_EDGE verilog_node "{ tb_top.cpu.tds.niu_smx_resp_dmc_resp_dv_smx_dmc_dv_reg_7_.so, tb_top.cpu.tds.niu_smx_resp_dmc_resp_dv_smx_dmc_dv_reg_6_.so, tb_top.cpu.tds.niu_smx_resp_dmc_resp_dv_smx_dmc_dv_reg_5_.so, tb_top.cpu.tds.meta_dmc_data_valid_tdmc, tb_top.cpu.tds.niu_smx_resp_dmc_resp_dv_smx_dmc_dv_reg_3_.so, tb_top.cpu.tds.meta_dmc_data_valid_txc, tb_top.cpu.tds.niu_smx_resp_dmc_resp_dv_smx_dmc_dv_reg_1_.so, tb_top.cpu.tds.meta_dmc_data_valid_rdmc }";

   output [3:0] meta_dmc_status  OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_data_status";

   output [7:0]	meta_dmc_resp_complete OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_resp_complete_tdmc";
   output [7:0]	meta_dmc_trans_complete OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_resp_transfer_cmpl_tdmc";
   
   input        rdmc_meta_resp_accept INPUT_EDGE verilog_node META_DUV_PATH.rdmc_meta_resp_accept";
   input        txc_meta_resp_accept INPUT_EDGE verilog_node META_DUV_PATH.txc_meta_resp_accept";

}

#else

interface meta_read_resp_if {

   input clk 	CLOCK verilog_node META_DUV_PATH.niu_smx.niu_clk";

   output 	meta_dmc_resp_ready OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_resp_ready";
   output [7:0] meta_dmc_resp_cmd OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_resp_cmd";
   output [5:0] meta_dmc_resp_transid OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_resp_trans_id";
   output [1:0] meta_dmc_resp_port_num OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_resp_port_num";
   output [4:0] meta_dmc_resp_dma_num OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_resp_dma_num";
   output [13:0] meta_dmc_resp_length  OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_resp_length";
   output [63:0] meta_dmc_resp_address OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_resp_address";
   output [7:0]  meta_dmc_resp_clientid OUTPUT_EDGE verilog_node META_DUV_PATH.niu_smx.meta_dmc_resp_client";
   output [15:0] meta_dmc_resp_byteenable OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_resp_byteenable";
   output [127:0] meta_dmc_resp_data OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_data";
   output [7:0]  meta_dmc_resp_data_valid OUTPUT_EDGE verilog_node META_DUV_PATH.niu_smx.meta_dmc_data_valid";
   output [3:0] meta_dmc_status  OUTPUT_EDGE verilog_node META_DUV_PATH.meta_dmc_data_status";

   output [7:0]	meta_dmc_resp_complete OUTPUT_EDGE verilog_node META_DUV_PATH.niu_smx.meta_dmc_resp_complete";
   output [7:0]	meta_dmc_trans_complete OUTPUT_EDGE verilog_node META_DUV_PATH.niu_smx.meta_dmc_resp_transfer_cmpl";
   
   input        rdmc_meta_resp_accept INPUT_EDGE verilog_node META_DUV_PATH.rdmc_meta_resp_accept";
   input        txc_meta_resp_accept INPUT_EDGE verilog_node META_DUV_PATH.txc_meta_resp_accept";

}
#endif
port dmc_read_resp_port {

	clk ;
	resp_command;
	address;
	resp_ready;
	length;
	dma_num;
	port_num;
	transid;
	client_id;
	resp_accept;
	data;
	byte_enables;
	status;
	data_valid;
	resp_complete;
	trans_complete;

}

bind dmc_read_resp_port meta_resp_pbind {
	clk		meta_read_resp_if.clk;
	resp_command    meta_read_resp_if.meta_dmc_resp_cmd;
	address    meta_read_resp_if.meta_dmc_resp_address;
	resp_ready    meta_read_resp_if.meta_dmc_resp_ready;
	length    meta_read_resp_if.meta_dmc_resp_length;
	dma_num    meta_read_resp_if.meta_dmc_resp_dma_num;
	port_num    meta_read_resp_if.meta_dmc_resp_port_num;
	transid    meta_read_resp_if.meta_dmc_resp_transid;
	client_id    meta_read_resp_if.meta_dmc_resp_clientid;
	resp_accept    meta_read_resp_if.txc_meta_resp_accept;
	data    meta_read_resp_if.meta_dmc_resp_data;
	byte_enables    meta_read_resp_if.meta_dmc_resp_byteenable;
	status    meta_read_resp_if.meta_dmc_status;
	data_valid    meta_read_resp_if.meta_dmc_resp_data_valid;
	resp_complete meta_read_resp_if.meta_dmc_resp_complete;
	trans_complete meta_read_resp_if.meta_dmc_trans_complete;
}

#ifdef NIU_GATE

interface rdmc_pio_intr_intf {
  input         clk CLOCK verilog_node NIU_DUV_PATH.rdp.iol2clk ";

//  input [31:0]  rdmc_pio_intr_ldf_a INPUT_EDGE verilog_node "{tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_a_31_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_a_30_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_a_29_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_a_28_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_a_27_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_a_26_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_a_25_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_a_24_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_a_23_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_a_22_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_a_21_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_a_20_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_a_19_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_a_18_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_a_17_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_a_16_, 16'b0 }";

 // input [31:0]  rdmc_pio_intr_ldf_b INPUT_EDGE verilog_node "{tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_b_31_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_b_30_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_b_29_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_b_28_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_b_27_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_b_26_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_b_25_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_b_24_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_b_23_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_b_22_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_b_21_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_b_20_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_b_19_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_b_18_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_b_17_, tb_top.cpu.rdp.niu_rdmc_rdmc_pio_intr_ldf_b_16_, 16'b0 }";

}

#else

interface rdmc_pio_intr_intf {
  input         clk CLOCK verilog_node NIU_DUV_PATH.rdp.niu_rdmc.niu_clk ";
  input [31:0]  rdmc_pio_intr_ldf_a INPUT_EDGE verilog_node NIU_DUV_PATH.rdp.niu_rdmc.rdmc_pio_intr_ldf_a";
  input [31:0]  rdmc_pio_intr_ldf_b INPUT_EDGE verilog_node NIU_DUV_PATH.rdp.niu_rdmc.rdmc_pio_intr_ldf_b";
}

#endif

port rdmc_intr {
       
        clk;
#ifdef NIU_GATE
#else
        rdmc_pio_intr_ldf_a;
        rdmc_pio_intr_ldf_b;
#endif
}

bind rdmc_intr rdmc_intr_pbind {
      clk rdmc_pio_intr_intf.clk;
#ifdef NIU_GATE
#else
      rdmc_pio_intr_ldf_a rdmc_pio_intr_intf.rdmc_pio_intr_ldf_a;
      rdmc_pio_intr_ldf_b rdmc_pio_intr_intf.rdmc_pio_intr_ldf_b;
#endif

}