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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: smx_drv_ports.if.vri | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #define SMX_CK_IN_TIMING PSAMPLE #-1 | |
36 | #define SMX_CK_OUT_TIMING PHOLD #1 | |
37 | #define SMX_CK_CLK_TIMING CLOCK | |
38 | #include "neptune_defines.vri" | |
39 | ||
40 | #define META_PATH NIU_DUV_PATH.tds | |
41 | ||
42 | /* | |
43 | interface dmc_send_q_if { | |
44 | ||
45 | // Send Queue releated Signals | |
46 | input [7:0] dmc_smx_cmd_req SMX_CK_IN_TIMING ; | |
47 | input [63:0] dmc_smx_address SMX_CK_IN_TIMING ; | |
48 | input [5:0] dmc_smx_transid SMX_CK_IN_TIMING; | |
49 | input [15:0] dmc_smx_length SMX_CK_IN_TIMING; | |
50 | input dmc_smx_valid SMX_CK_IN_TIMING; | |
51 | ||
52 | output smx_dmc_grant SMX_CK_OUT_TIMING; | |
53 | output smx_dmc_xfer_data_req SMX_CK_OUT_TIMING; | |
54 | ||
55 | input dmc_smx_xfer_data_ack SMX_CK_IN_TIMING; | |
56 | input [4:0] dmc_smx_xfer_status SMX_CK_IN_TIMING; | |
57 | input [127:0] dmc_smx_data SMX_CK_IN_TIMING; | |
58 | ||
59 | input clk SMX_CK_CLK_TIMING; | |
60 | ||
61 | ||
62 | } | |
63 | ||
64 | interface dmc_receive_q_if { | |
65 | ||
66 | // Receive Queue related Signals | |
67 | ||
68 | output [7:0] smx_dmc_cmd_req SMX_CK_OUT_TIMING ; | |
69 | output [63:0] smx_dmc_address SMX_CK_OUT_TIMING ; | |
70 | output [5:0] smx_dmc_transid SMX_CK_OUT_TIMING; | |
71 | output [15:0] smx_dmc_length SMX_CK_OUT_TIMING; | |
72 | output smx_dmc_valid SMX_CK_OUT_TIMING; | |
73 | ||
74 | input dmc_smx_grant SMX_CK_IN_TIMING; | |
75 | input dmc_smx_xfer_data_req SMX_CK_IN_TIMING; | |
76 | ||
77 | output smx_dmc_xfer_data_ack SMX_CK_OUT_TIMING; | |
78 | output [4:0] smx_dmc_xfer_status SMX_CK_OUT_TIMING; | |
79 | output [127:0] smx_dmc_data SMX_CK_OUT_TIMING; | |
80 | ||
81 | input clk SMX_CK_CLK_TIMING; | |
82 | ||
83 | ||
84 | } | |
85 | ||
86 | */ | |
87 | ||
88 | #ifdef NIU_GATE | |
89 | ||
90 | interface dmc_txc_sb_if { | |
91 | // TX-SMX - Sideband Signals | |
92 | ||
93 | input clk SMX_CK_CLK_TIMING verilog_node META_PATH.iol2clk"; | |
94 | ||
95 | input [1:0] dmc_smx_tx_port_num SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_port_num"; | |
96 | input [4:0] dmc_smx_tx_dma_num SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_dma_num"; | |
97 | output [1:0] smx_dmc_tx_port_num SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_port_num"; | |
98 | output [4:0] smx_dmc_tx_dma_num SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_dma_num"; | |
99 | ||
100 | } | |
101 | ||
102 | #else | |
103 | ||
104 | interface dmc_txc_sb_if { | |
105 | // TX-SMX - Sideband Signals | |
106 | ||
107 | input clk SMX_CK_CLK_TIMING verilog_node META_PATH.niu_smx.niu_clk"; | |
108 | ||
109 | input [1:0] dmc_smx_tx_port_num SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_port_num"; | |
110 | input [4:0] dmc_smx_tx_dma_num SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_dma_num"; | |
111 | output [1:0] smx_dmc_tx_port_num SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_port_num"; | |
112 | output [4:0] smx_dmc_tx_dma_num SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_dma_num"; | |
113 | ||
114 | } | |
115 | ||
116 | #endif | |
117 | ||
118 | interface dmc_send_q_if { | |
119 | ||
120 | // Send Queue releated Signals | |
121 | input [7:0] dmc_smx_cmd_req SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_cmd_req" ; | |
122 | input [63:0] dmc_smx_address SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_address"; | |
123 | // input [5:0] dmc_smx_transid SMX_CK_IN_TIMING verilog_node "neptune_tb_top.dmc_smx_transid"; | |
124 | input [5:0] dmc_smx_transid SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_transID"; | |
125 | input [15:0] dmc_smx_length SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_length"; | |
126 | input dmc_smx_valid SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_valid"; | |
127 | ||
128 | output smx_dmc_grant SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_grant"; | |
129 | output smx_dmc_xfer_data_req SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_xfer_data_req" ; | |
130 | ||
131 | input dmc_smx_xfer_data_ack SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_xfer_data_ack" ; | |
132 | input [4:0] dmc_smx_xfer_status SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_xfer_status" ; | |
133 | input [127:0] dmc_smx_data SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_data" ; | |
134 | ||
135 | input clk SMX_CK_CLK_TIMING verilog_node META_PATH.clk"; | |
136 | ||
137 | ||
138 | } | |
139 | ||
140 | interface dmc_receive_q_if { | |
141 | ||
142 | // Receive Queue related Signals | |
143 | ||
144 | output [7:0] smx_dmc_cmd_req SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_cmd_req" ; | |
145 | output [63:0] smx_dmc_address SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_address" ; | |
146 | // output [5:0] smx_dmc_transid SMX_CK_OUT_TIMING verilog_node "neptune_tb_top.smx_dmc_transid" ; | |
147 | output [5:0] smx_dmc_transid SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_transID" ; | |
148 | output [15:0] smx_dmc_length SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_length" ; | |
149 | output smx_dmc_valid SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_valid" ; | |
150 | ||
151 | input dmc_smx_grant SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_grant" ; | |
152 | input dmc_smx_xfer_data_req SMX_CK_IN_TIMING verilog_node META_PATH.dmc_smx_xfer_data_req"; | |
153 | ||
154 | output smx_dmc_xfer_data_ack SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_xfer_data_ack" ; | |
155 | output [4:0] smx_dmc_xfer_status SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_xfer_status" ; | |
156 | output [127:0] smx_dmc_data SMX_CK_OUT_TIMING verilog_node META_PATH.smx_dmc_data" ; | |
157 | ||
158 | #ifdef NIU_GATE | |
159 | input clk SMX_CK_CLK_TIMING verilog_node META_PATH.iol2clk" ; | |
160 | #else | |
161 | input clk SMX_CK_CLK_TIMING verilog_node META_PATH.smx.niu_clk" ; | |
162 | #endif | |
163 | ||
164 | ||
165 | } | |
166 | ||
167 | ||
168 | ||
169 | ||
170 | ||
171 | ||
172 | port dmc_send_port { | |
173 | ||
174 | clk; | |
175 | s_cmd_req; | |
176 | s_address; | |
177 | s_transid; | |
178 | s_length; | |
179 | s_valid; | |
180 | s_grant; | |
181 | s_data_req; | |
182 | s_data_ack; | |
183 | s_status; | |
184 | s_data; | |
185 | ||
186 | ||
187 | } | |
188 | port dmc_receive_port { | |
189 | ||
190 | clk; | |
191 | r_cmd_req; | |
192 | r_address; | |
193 | r_transid; | |
194 | r_length; | |
195 | r_valid; | |
196 | r_grant; | |
197 | r_data_req; | |
198 | r_data_ack; | |
199 | r_status; | |
200 | r_data; | |
201 | ||
202 | } | |
203 | ||
204 | port smx_tx_sb_ports { | |
205 | ||
206 | clk; | |
207 | dmctx_port_num; | |
208 | dmctx_dma_num; | |
209 | txdmc_port_num; | |
210 | txdmc_dma_num; | |
211 | ||
212 | } | |
213 | ||
214 | bind smx_tx_sb_ports tx_sb_pbind { | |
215 | clk dmc_txc_sb_if.clk; | |
216 | txdmc_port_num dmc_txc_sb_if.dmc_smx_tx_port_num; | |
217 | txdmc_dma_num dmc_txc_sb_if.dmc_smx_tx_dma_num; | |
218 | dmctx_port_num dmc_txc_sb_if.smx_dmc_tx_port_num; | |
219 | dmctx_dma_num dmc_txc_sb_if.smx_dmc_tx_dma_num; | |
220 | } | |
221 | ||
222 | bind dmc_send_port dmc_send_pbind { | |
223 | ||
224 | ||
225 | clk dmc_send_q_if.clk; | |
226 | s_cmd_req dmc_send_q_if.dmc_smx_cmd_req; | |
227 | s_address dmc_send_q_if.dmc_smx_address; | |
228 | s_transid dmc_send_q_if.dmc_smx_transid; | |
229 | s_length dmc_send_q_if.dmc_smx_length; | |
230 | s_valid dmc_send_q_if.dmc_smx_valid; | |
231 | s_grant dmc_send_q_if.smx_dmc_grant; | |
232 | s_data_req dmc_send_q_if.smx_dmc_xfer_data_req; | |
233 | s_data_ack dmc_send_q_if.dmc_smx_xfer_data_ack; | |
234 | s_status dmc_send_q_if.dmc_smx_xfer_status; | |
235 | s_data dmc_send_q_if.dmc_smx_data; | |
236 | } | |
237 | ||
238 | ||
239 | ||
240 | bind dmc_receive_port dmc_receive_pbind { | |
241 | ||
242 | ||
243 | clk dmc_receive_q_if.clk; | |
244 | r_cmd_req dmc_receive_q_if.smx_dmc_cmd_req; | |
245 | r_address dmc_receive_q_if.smx_dmc_address; | |
246 | r_transid dmc_receive_q_if.smx_dmc_transid; | |
247 | r_length dmc_receive_q_if.smx_dmc_length; | |
248 | r_valid dmc_receive_q_if.smx_dmc_valid; | |
249 | r_grant dmc_receive_q_if.dmc_smx_grant; | |
250 | r_data_req dmc_receive_q_if.dmc_smx_xfer_data_req; | |
251 | r_data_ack dmc_receive_q_if.smx_dmc_xfer_data_ack; | |
252 | r_status dmc_receive_q_if.smx_dmc_xfer_status; | |
253 | r_data dmc_receive_q_if.smx_dmc_data; | |
254 | } | |
255 |