Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / siu / vera / include / siumon.if.vrhpal

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: siumon.if.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
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// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
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// ========== Copyright Header End ============================================
#inc "siu_inc.pal"

#ifndef INC_SIUMON_IF_VRH
#define INC_SIUMON_IF_VRH

#include "top_defines.vrh"

interface ncu_mon {
input		iol2clk	CLOCK		verilog_node "`SII.iol2clk";
input		syn_vld		INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.sii_ncu_syn_vld";
input [3:0]	syn_data	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.sii_ncu_syn_data";
input		niu_a_pei	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.ncu_sii_niua_pei";
input		niu_a_pe	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.sii_ncu_niua_pe";
input		niu_d_pei	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.ncu_sii_niud_pei";
input		niu_d_pe	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.sii_ncu_niud_pe";
input		niu_ctag_uei	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.ncu_sii_niuctag_uei";
input		niu_ctag_ue	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.sii_ncu_niuctag_ue";
input		niu_ctag_cei	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.ncu_sii_niuctag_cei";
input		niu_ctag_ce	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.sii_ncu_niuctag_ce";
input		dmu_a_pei	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.ncu_sii_dmua_pei";
input		dmu_a_pe	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.sii_ncu_dmua_pe";
input		dmu_d_pei	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.ncu_sii_dmud_pei";
input		dmu_d_pe	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.sii_ncu_dmud_pe";
input		dmu_ctag_uei	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.ncu_sii_dmuctag_uei";
input		dmu_ctag_ue	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.sii_ncu_dmuctag_ue";
input		dmu_ctag_cei	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.ncu_sii_dmuctag_cei";
input		dmu_ctag_ce	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.sii_ncu_dmuctag_ce";
input		sio_ctag_uei	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SIO.ncu_sio_ctag_uei";
input		sio_ctag_ue	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SIO.sio_ncu_ctag_ue";
input		sio_ctag_cei	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SIO.ncu_sio_ctag_cei";
input		sio_ctag_ce	INPUT_EDGE 	INPUT_SKEW	verilog_node "`SIO.sio_ncu_ctag_ce";
}

interface cmd_mon {
input		l2clk	CLOCK		verilog_node "`SII.l2clk";
#ifdef GATESIM
input           cmd_parity_err  INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ipcc__n2852";
input           cur_source      INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ipcc__n2857";
#else
input           cmd_parity_err  INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ipcc.cmd_parity_err";
input           cur_source      INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.ipcc.cur_source";
#endif
}

interface niu_mon {
input		clk	CLOCK		verilog_node "`SII.iol2clk";
input		sreq		INPUT_EDGE 	INPUT_SKEW	verilog_node "`SII.niu_sii_hdr_vld";
input 		bypass		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.niu_sii_reqbypass";
input		sdatareq 	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.niu_sii_datareq";
input	[127:0] sdata		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.niu_sii_data";
input	[1:0]	sparity		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.niu_sii_parity";
input		oqdq		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.sii_niu_oqdq";
input           bqdq    	INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.sii_niu_bqdq";
input		rreq		INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.sio_niu_hdr_vld";
input		rdatareq	INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.sio_niu_datareq";
input	[127:0]	rdata		INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.sio_niu_data";
input	[1:0]	rparity		INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.sio_niu_parity";
input		niu_dq		INPUT_EDGE      INPUT_SKEW      verilog_node "`SIO.niu_sio_dq";
}

interface dmu_mon {
input		clk	CLOCK		verilog_node "`SII.iol2clk";
input		sreq		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.dmu_sii_hdr_vld";
input		bypass		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.dmu_sii_reqbypass";
input		sdatareq	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.dmu_sii_datareq";
input		datareq16	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.dmu_sii_datareq16";
input [127:0]	sdata		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.dmu_sii_data";
input [1:0]	sparity		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.dmu_sii_parity";
input [15:0]	be		INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.dmu_sii_be";
input 	        beparity	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.dmu_sii_be_parity";
input		wrack_vld 	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.sii_dmu_wrack_vld";
input [3:0]	wrack_tag 	INPUT_EDGE	INPUT_SKEW	verilog_node "`SII.sii_dmu_wrack_tag";
input		rreq		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.sio_dmu_hdr_vld";
//input		rdatareq	INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.sio_dmu_datareq";
input [127:0]	rdata		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.sio_dmu_data";
input [1:0]	rparity		INPUT_EDGE	INPUT_SKEW	verilog_node "`SIO.sio_dmu_parity";
}

.for($b=0; $b<$BANKS; $b++) {
interface l2_${b}_mon {
input           clk     CLOCK           verilog_node "`SII.l2clk";
input		req_vld		INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.sii_l2t${b}_req_vld";
input [31:0]	req		INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.sii_l2t${b}_req";
input [6:0]	ecc		INPUT_EDGE      INPUT_SKEW      verilog_node "`SII.sii_l2b${b}_ecc";
input		ctag_vld	INPUT_EDGE 	INPUT_SKEW 	verilog_node "`SIO.l2b${b}_sio_ctag_vld";
input [31:0]	data		INPUT_EDGE 	INPUT_SKEW 	verilog_node "`SIO.l2b${b}_sio_data";
input [1:0]	parity		INPUT_EDGE 	INPUT_SKEW 	verilog_node "`SIO.l2b${b}_sio_parity";
input 		ue_err		INPUT_EDGE 	INPUT_SKEW 	verilog_node "`SIO.l2b${b}_sio_ue_err";
input 		iq_dequeue	INPUT_EDGE 	INPUT_SKEW 	verilog_node "`SII.l2t${b}_sii_iq_dequeue";
input 		wib_dequeue	INPUT_EDGE 	INPUT_SKEW 	verilog_node "`SII.l2t${b}_sii_wib_dequeue";
input [1:0] 	dbg_req	        INPUT_EDGE 	INPUT_SKEW 	verilog_node "`SII.sii_dbg1_l2t${b}_req";
}

.}

#endif