Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / siu / vera / packets / siu_common.vr
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: siu_common.vr
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35#include <vera_defines.vrh>
36
37function reg[2:0] pbank_sel(reg[3:0] pbank, reg[2:0] bank_sel)
38{
39 reg [2:0] result = bank_sel;
40
41 case (pbank) {
42 4'b0001: result[2:1] = 2'b0;
43 4'b0010: result[2:1] = 2'b01;
44 4'b0011: result[2] = 1'b0;
45 4'b0100: result[2:1] = 2'b10;
46 4'b0101: result[2:1] = {bank_sel[1], 1'b0};
47 4'b0110: result[2:1] = {bank_sel[1], ~bank_sel[1]};
48 4'b1000: result[2:1] = 2'b11;
49 4'b1001: result[2:1] = {bank_sel[1], bank_sel[1]};
50 4'b1010: result[1] = 1'b1;
51 4'b1100: result[2:1] = {1'b1, bank_sel[1]};
52 4'b1111: result = bank_sel;
53 default:
54 printf ("ERROR! illegal partial bank selections!\n");
55 }
56
57 pbank_sel = result;
58}
59
60function reg[1:0] interleave_parity(reg[39:0] data, integer size)
61{
62 integer i;
63 reg oparity = 0;
64 reg eparity = 0;
65
66 size = (size > 40) ? 40 : size;
67
68 for (i=0; i<size; i=i+2) eparity ^= data[i];
69 for (i=1; i<size; i=i+2) oparity ^= data[i];
70
71 interleave_parity = {~oparity, ~eparity};
72}
73
74function reg[5:0] gen_ctag_ecc(reg[15:0] data)
75{
76 bit [5:0] temp_ecc;
77
78 temp_ecc[0] = data[0] ^ data[1] ^ data[3] ^ data[4] ^ data[6] ^ data[8] ^
79 data[10] ^ data[11] ^ data[13] ^ data[15];
80
81 temp_ecc[1] = data[0] ^ data[2] ^ data[3] ^ data[5] ^ data[6] ^ data[9] ^
82 data[10] ^ data[12] ^ data[13];
83
84 temp_ecc[2] = data[1] ^ data[2] ^ data[3] ^ data[7] ^ data[8] ^ data[9] ^
85 data[10] ^ data[14] ^ data[15];
86
87 temp_ecc[3] = data[4] ^ data[5] ^ data[6] ^ data[7] ^ data[8] ^ data[9] ^
88 data[10];
89
90 temp_ecc[4] = data[11] ^ data[12] ^ data[13] ^ data[14] ^ data[15];
91
92 //temp_ecc[5] = ~(temp_ecc[0] ^ temp_ecc[1] ^ temp_ecc[2] ^ temp_ecc[3] ^ temp_ecc[4]);
93 temp_ecc[5] = data[0] ^ data[1] ^ data[2] ^ data[3] ^ temp_ecc[0] ^ temp_ecc[1] ^ temp_ecc[2];
94 gen_ctag_ecc = temp_ecc;
95}
96
97function reg gen_beparity(reg[15:0] data)
98{
99 bit temp_beparity;
100
101 temp_beparity = data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[5] ^ data[6] ^ data[7] ^ data[8] ^ data[9] ^ data[10] ^ data[11] ^ data[12] ^ data[13] ^ data[14] ^ data[15];
102 gen_beparity = !(temp_beparity);
103}