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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ccu_mon.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `include "tcu_top.h" | |
36 | ||
37 | module ccu_mon(); | |
38 | ||
39 | //############################################################# | |
40 | //### WHAT: monitor ccu and print out clock info | |
41 | //############################################################# | |
42 | ||
43 | `ifndef GATESIM | |
44 | `ifndef ASIC_GATES | |
45 | ||
46 | integer sys_clk_per_int, dtm_mode; | |
47 | reg [5:0] div1, div2, div3; | |
48 | reg [6:0] div4; | |
49 | real div1_eff, div2_eff, div3_eff, div4_eff; // effective values (warning: in real number) | |
50 | real sys_clk_per, cmp_clk_per, dr_clk_per, io_clk_per, io2x_clk_per; // expected values | |
51 | real cmp2sys_ratio, dr2sys_ratio, cmp2dr_ratio, cmp2io_ratio, cmp2io2x_ratio; // clk ratio | |
52 | ||
53 | always @(negedge `CCU.rst_ccu_pll_) | |
54 | $display("%t: ccu_mon[ccu_mon]: clk info: rst asserts rst_ccu_pll_ to reset/relock PLL", $time); | |
55 | ||
56 | always @(posedge `CCU.rst_ccu_pll_) begin // at CCU input: get sys clk period | |
57 | @(posedge `CCU.pll_sys_clk_p); | |
58 | sys_clk_per_int = $time; | |
59 | @(posedge `CCU.pll_sys_clk_p); | |
60 | sys_clk_per_int = $time - sys_clk_per_int; | |
61 | sys_clk_per = sys_clk_per_int; // warning: convert to real number | |
62 | end | |
63 | ||
64 | always @(posedge `CCU.rst_ccu_pll_) begin // at CCU's csr_blk: record div values when CCU should latch them in | |
65 | $display("%t: ccu_mon[ccu_mon]: clk info: rst deasserts rst_ccu_pll_", $time); | |
66 | div1 = `CCU.csr_blk.pll_div1; | |
67 | div2 = `CCU.csr_blk.pll_div2; | |
68 | div3 = `CCU.csr_blk.pll_div3; | |
69 | div4 = `CCU.csr_blk.pll_div4; | |
70 | div1_eff = div1 + 1.0; // effective value. Warning: convert to real number | |
71 | div2_eff = div2 + 1.0; // effective value. Warning: convert to real number | |
72 | div3_eff = div3 + 1.0; // effective value. Warning: convert to real number | |
73 | div4_eff = div4[6:1]; // integral/whole part. Warning: convert to real number | |
74 | if (div4[0] == 1'b1) | |
75 | div4_eff = div4_eff + 0.5; // fractional part. Warning: convert to real number | |
76 | end | |
77 | ||
78 | always @(posedge `CCU.ccu_rst_sync_stable) begin // clock info: compute and print out expected values when clocks and sync are stable | |
79 | $display("%t: ccu_mon[ccu_mon]: clk info: ccu asserts ccu_rst_sync_stable", $time); | |
80 | dtm_mode = ((`CCU.csr_blk.serdes_dtm1 === 1'b1) | |
81 | || (`CCU.csr_blk.serdes_dtm2 === 1'b1))? 1 : 0; // serdes dtm signals should be stable here | |
82 | cmp_clk_per = (sys_clk_per * div1_eff) / div2_eff; | |
83 | if (dtm_mode) begin // DTM mode | |
84 | dr_clk_per = sys_clk_per * div1_eff; | |
85 | io_clk_per = sys_clk_per * div1_eff; | |
86 | io2x_clk_per = sys_clk_per * div1_eff; | |
87 | cmp2sys_ratio = div2_eff / div1_eff; | |
88 | dr2sys_ratio = div1_eff; | |
89 | cmp2dr_ratio = div2_eff; | |
90 | cmp2io_ratio = div2_eff; | |
91 | cmp2io2x_ratio = div2_eff; | |
92 | end | |
93 | else begin // functional mode | |
94 | io_clk_per = cmp_clk_per * 4.0; | |
95 | io2x_clk_per = cmp_clk_per * 2.0; | |
96 | dr_clk_per = (sys_clk_per * div1_eff * div4_eff) / (div2_eff * div3_eff); | |
97 | cmp2sys_ratio = div2_eff / div1_eff; | |
98 | dr2sys_ratio = (div2_eff * div3_eff) / (div1_eff * div4_eff); | |
99 | cmp2dr_ratio = div4_eff / div3_eff; | |
100 | cmp2io_ratio = 4.0; | |
101 | cmp2io2x_ratio = 2.0; | |
102 | end | |
103 | $display("%t: ccu_mon[ccu_mon]: clk info: div1_eff=%.0f, div2_eff=%.0f, div3_eff=%.0f, div4_eff=%.1f, serdes_dtm=%0d", $time, div1_eff, div2_eff, div3_eff, div4_eff, dtm_mode); | |
104 | $display("%t: ccu_mon[ccu_mon]: clk info: sys_clk_per=%.2f", $time, sys_clk_per); | |
105 | $display("%t: ccu_mon[ccu_mon]: clk info: expected: cmp_clk_per=%.2f, dr_clk_per=%.2f, io_clk_per=%.2f, io2x_clk_per=%.2f", $time, cmp_clk_per, dr_clk_per, io_clk_per, io2x_clk_per); | |
106 | ||
107 | $display("%t: ccu_mon[ccu_mon]: clk info: expected: cmp2sys_ratio=%.2f, dr2sys_ratio=%.2f, cmp2dr_ratio=%.2f, cmp2io_ratio=%.2f, cmp2io2x_ratio=%.2f", $time, cmp2sys_ratio, dr2sys_ratio, cmp2dr_ratio, cmp2io_ratio, cmp2io2x_ratio); | |
108 | end | |
109 | ||
110 | `endif // end of `ifndef ASIC_GATES | |
111 | `endif // end of `ifndef GATESIM | |
112 | ||
113 | //############################################################# | |
114 | //### WHAT: monitor JTAG tck clock (this is legacy code) | |
115 | //############################################################# | |
116 | ||
117 | `ifdef TCU_SAT | |
118 | ||
119 | reg [63:0] period; | |
120 | reg [63:0] posTime; | |
121 | reg [63:0] negTime; | |
122 | reg [63:0] posCycle; | |
123 | reg [63:0] negCycle; | |
124 | wire tckCLK; | |
125 | ||
126 | assign tckCLK = `TOP.tck; | |
127 | ||
128 | always @(posCycle or negCycle) | |
129 | period=posCycle+negCycle; | |
130 | ||
131 | always @(tckCLK) begin | |
132 | if (tckCLK) begin | |
133 | posTime = $time; | |
134 | posCycle = posTime - negTime; | |
135 | if (negCycle != posCycle) | |
136 | $dispmon("tb_top", `DEBUG, "Period change for tck: %0dps (neg:%0dps -> pos:%0dps)", posCycle*2, negCycle, posCycle); | |
137 | end else begin | |
138 | negTime = $time; | |
139 | negCycle = negTime - posTime; | |
140 | if (negCycle != posCycle) | |
141 | $dispmon("tb_top", `DEBUG, "Period change for tck: %0dps (pos:%0dps -> neg:%0dps)", negCycle*2, posCycle, negCycle); | |
142 | end | |
143 | end | |
144 | ||
145 | //// This Verilog task is called from the Vera testbench side at end of simulation | |
146 | task showClocks; | |
147 | begin | |
148 | $dispmon("tb_top", `INFO, "TCK : %0d ps (%0d MHz)", period, 1.0E6/period); | |
149 | end | |
150 | endtask | |
151 | ||
152 | `endif // `ifdef TCU_SAT | |
153 | ||
154 | //################################################### | |
155 | //### WHAT: instantiate MCU's DR clkgen module for TCU SAT | |
156 | //### to produce an ALWAYS running DR clock | |
157 | //################################################### | |
158 | ||
159 | `ifndef GATESIM | |
160 | `ifndef ASIC_GATES | |
161 | ||
162 | clkgen_mcu_dr clkgen_dr( | |
163 | //-----inputs----- | |
164 | .gclk(`CPU.mcu0.dr_gclk), // connect to MCU's DR gclk | |
165 | .cluster_div_en(1'b0), // must tie low | |
166 | .cluster_arst_l(1'b1), // tie high | |
167 | ||
168 | //---the rest of the inputs: tie low/high--- | |
169 | .ccu_cmp_slow_sync_en(1'b0), | |
170 | .ccu_slow_cmp_sync_en(1'b0), | |
171 | .ccu_div_ph(1'b0), // not matter if cluster_div_en is 0 | |
172 | .ccu_serdes_dtm(1'b0), // not used inside clkgen module | |
173 | .clk_ext(1'b0), // not used inside clkgen module | |
174 | .rst_por_(1'b0), | |
175 | .rst_wmr_(1'b0), | |
176 | .rst_wmr_protect(1'b0), | |
177 | .scan_en(1'b0), | |
178 | .scan_in(1'b0), | |
179 | .tcu_aclk(1'b0), | |
180 | .tcu_bclk(1'b0), | |
181 | .tcu_atpg_mode(1'b0), | |
182 | .tcu_clk_stop(1'b0), | |
183 | .tcu_div_bypass(1'b0), | |
184 | .tcu_pce_ov(1'b0), | |
185 | .tcu_wr_inhibit(1'b0), | |
186 | ||
187 | //---outputs: not connect--- | |
188 | .aclk(), | |
189 | .aclk_wmr(), | |
190 | .array_wr_inhibit(), | |
191 | .bclk(), | |
192 | .cmp_slow_sync_en(), | |
193 | .l2clk(), | |
194 | .pce_ov(), | |
195 | .por_(), | |
196 | .scan_out(), | |
197 | .slow_cmp_sync_en(), | |
198 | .wmr_(), | |
199 | .wmr_protect() | |
200 | ); | |
201 | ||
202 | //################################################### | |
203 | //### WHAT: instantiate RDP's IO2X clkgen module for TCU SAT | |
204 | //### to produce ALWAYS running IO2X clock | |
205 | //################################################### | |
206 | ||
207 | ||
208 | `ifdef FC_NO_NIU_T2 | |
209 | ||
210 | // added this for removing NIU in T2 | |
211 | // 2 signals were getting called from rdp (which is in NIU). | |
212 | // so, i replaced them with their equivalent behavior (since i removed rdp when i removed NIU) | |
213 | // list of signals that are stubbed for NIU | |
214 | ||
215 | integer status; time niu_stub_time; | |
216 | initial begin | |
217 | status = $value$plusargs("NIU_STUB_TIME=%d", niu_stub_time); | |
218 | end | |
219 | initial begin | |
220 | #niu_stub_time | |
221 | $display("At time %0t, stubbing initiated for NCU/SIU - NIU signals from %m (OpenSparc T2)\n",$time); | |
222 | // | |
223 | //#687002 | |
224 | //$dispmon("ccu_mon",1,"At time %0d, stubbing initiated for NCU/SIU - NIU signals (OpenSparc T2)\n",$time); | |
225 | // | |
226 | force `CPU.ncu_niu_ctag_cei =0; | |
227 | force `CPU.ncu_niu_ctag_uei =0; | |
228 | force `CPU.ncu_niu_d_pei =0; | |
229 | force `CPU.ncu_niu_data[31:0] =32'b0; | |
230 | force `CPU.ncu_niu_stall =0; | |
231 | force `CPU.ncu_niu_vld =0; | |
232 | force `CPU.ncu_sii_niua_pei =0; | |
233 | force `CPU.ncu_sii_niuctag_cei =0; | |
234 | force `CPU.ncu_sii_niuctag_uei =0; | |
235 | force `CPU.ncu_sii_niud_pei =0; | |
236 | force `CPU.niu_dbg1_stall_ack =0; | |
237 | force `CPU.niu_efu_4k_data =0; | |
238 | force `CPU.niu_efu_4k_xfer_en =0; | |
239 | force `CPU.niu_efu_cfifo0_data =0; | |
240 | force `CPU.niu_efu_cfifo0_xfer_en =0; | |
241 | force `CPU.niu_efu_cfifo1_data =0; | |
242 | force `CPU.niu_efu_cfifo1_xfer_en =0; | |
243 | force `CPU.niu_efu_fdo =0; | |
244 | force `CPU.niu_efu_ipp0_data =0; | |
245 | force `CPU.niu_efu_ipp0_xfer_en =0; | |
246 | force `CPU.niu_efu_ipp1_data =0; | |
247 | force `CPU.niu_efu_ipp1_xfer_en =0; | |
248 | force `CPU.niu_efu_mac0_ro_data =0; | |
249 | force `CPU.niu_efu_mac0_ro_xfer_en =0; | |
250 | force `CPU.niu_efu_mac0_sf_data =0; | |
251 | force `CPU.niu_efu_mac0_sf_xfer_en =0; | |
252 | force `CPU.niu_efu_mac1_ro_data =0; | |
253 | force `CPU.niu_efu_mac1_ro_xfer_en =0; | |
254 | force `CPU.niu_efu_mac1_sf_data =0; | |
255 | force `CPU.niu_efu_mac1_sf_xfer_en =0; | |
256 | force `CPU.niu_efu_ram0_data =0; | |
257 | force `CPU.niu_efu_ram0_xfer_en =0; | |
258 | force `CPU.niu_efu_ram1_data =0; | |
259 | force `CPU.niu_efu_ram1_xfer_en =0; | |
260 | force `CPU.niu_efu_ram_data =0; | |
261 | force `CPU.niu_efu_ram_xfer_en =0; | |
262 | force `CPU.niu_mio_debug_clock[1:0] =2'b0; | |
263 | force `CPU.niu_mio_debug_data[31:0] =32'b0; | |
264 | force `CPU.niu_ncu_ctag_ce =0; | |
265 | force `CPU.niu_ncu_ctag_ue =0; | |
266 | force `CPU.niu_ncu_d_pe =0; | |
267 | force `CPU.niu_ncu_data[31:0] =32'b0; | |
268 | force `CPU.niu_ncu_stall =0; | |
269 | force `CPU.niu_ncu_vld =0; | |
270 | force `CPU.niu_sii_data[127:0] =128'b0; | |
271 | force `CPU.niu_sii_datareq =0; | |
272 | force `CPU.niu_sii_hdr_vld =0; | |
273 | force `CPU.niu_sii_parity[7:0] =8'b0; | |
274 | force `CPU.niu_sii_reqbypass =0; | |
275 | force `CPU.niu_sio_dq =0; | |
276 | force `CPU.niu_txc_interrupts =0; | |
277 | end | |
278 | ||
279 | // very important to have the following free running clock with the associated delays | |
280 | // exactly as is used below......... also, note we are in ps now instead of fs | |
281 | ||
282 | reg x; | |
283 | initial begin | |
284 | #194251 x=1'b1; | |
285 | #107250 forever #750 x=~x; // clock half-period is 750 ps, not 750 fs | |
286 | end | |
287 | ||
288 | // added this module and the 2 associated 'rdp' derivative signals | |
289 | clkgen_rdp_io2x clkgen_io2x( | |
290 | //---inputs--- | |
291 | .gclk(`CPU.cmp_gclk_c0_rdp), | |
292 | .ccu_div_ph(x), | |
293 | ||
294 | `else | |
295 | clkgen_rdp_io2x clkgen_io2x( | |
296 | //---inputs--- | |
297 | `ifdef NIU_SYSTEMC_T2 | |
298 | .gclk(`CPU.niu.cmp_gclk_c0_rdp), // connect to RDP's gclk | |
299 | .ccu_div_ph(`CPU.niu.gl_io2x_out_c1b), // connect to RDP's io2x_out | |
300 | `else | |
301 | .gclk(`CPU.rdp.cmp_gclk_c0_rdp), // connect to RDP's gclk | |
302 | .ccu_div_ph(`CPU.rdp.gl_rdp_io2x_out), // connect to RDP's io2x_out | |
303 | `endif | |
304 | `endif | |
305 | ||
306 | .cluster_div_en(1'b1), // must tie high | |
307 | .cluster_arst_l(1'b1), // tie high | |
308 | ||
309 | //---the rest of the inputs: tie low/high--- | |
310 | .ccu_cmp_slow_sync_en(1'b0), | |
311 | .ccu_slow_cmp_sync_en(1'b0), | |
312 | .ccu_serdes_dtm(1'b0), // not used inside clkgen module | |
313 | .clk_ext(1'b0), // not used inside clkgen module | |
314 | .rst_por_(1'b0), | |
315 | .rst_wmr_(1'b0), | |
316 | .rst_wmr_protect(1'b0), | |
317 | .scan_en(1'b0), | |
318 | .scan_in(1'b0), | |
319 | .tcu_aclk(1'b0), | |
320 | .tcu_bclk(1'b0), | |
321 | .tcu_atpg_mode(1'b0), | |
322 | .tcu_clk_stop(1'b0), | |
323 | .tcu_div_bypass(1'b0), | |
324 | .tcu_pce_ov(1'b0), | |
325 | .tcu_wr_inhibit(1'b0), | |
326 | ||
327 | //-----outputs----- | |
328 | .aclk(), | |
329 | .aclk_wmr(), | |
330 | .array_wr_inhibit(), | |
331 | .bclk(), | |
332 | .cmp_slow_sync_en(), | |
333 | .l2clk(), | |
334 | .pce_ov(), | |
335 | .por_(), | |
336 | .scan_out(), | |
337 | .slow_cmp_sync_en(), | |
338 | .wmr_(), | |
339 | .wmr_protect() | |
340 | ); | |
341 | ||
342 | `endif // end of `ifndef ASIC_GATES | |
343 | `endif // end of `ifndef GATESIM | |
344 | ||
345 | endmodule // ccu_mon | |
346 | ||
347 | // added these modules, they are necessary for compilation | |
348 | ||
349 | `ifdef FC_NO_NIU_T2 | |
350 | module clkgen_rdp_io2x ( | |
351 | array_wr_inhibit, | |
352 | tcu_atpg_mode, | |
353 | tcu_wr_inhibit, | |
354 | l2clk, | |
355 | aclk, | |
356 | bclk, | |
357 | scan_out, | |
358 | pce_ov, | |
359 | aclk_wmr, | |
360 | wmr_protect, | |
361 | wmr_, | |
362 | por_, | |
363 | cmp_slow_sync_en, | |
364 | slow_cmp_sync_en, | |
365 | tcu_clk_stop, | |
366 | tcu_pce_ov, | |
367 | rst_wmr_protect, | |
368 | rst_wmr_, | |
369 | rst_por_, | |
370 | ccu_cmp_slow_sync_en, | |
371 | ccu_slow_cmp_sync_en, | |
372 | tcu_div_bypass, | |
373 | ccu_div_ph, | |
374 | cluster_div_en, | |
375 | gclk, | |
376 | cluster_arst_l, | |
377 | clk_ext, | |
378 | ccu_serdes_dtm, | |
379 | tcu_aclk, | |
380 | tcu_bclk, | |
381 | scan_en, | |
382 | scan_in | |
383 | ); | |
384 | ||
385 | ||
386 | // ************************** | |
387 | // port declaration | |
388 | // ************************** | |
389 | ||
390 | // clock & test out | |
391 | output l2clk; // assume we do not need aclk, bclk outputs | |
392 | output aclk; // buffered version of aclk | |
393 | output bclk; // buffered version of bclk | |
394 | output scan_out; // unused as of today - feb 10, 05 | |
395 | output aclk_wmr; | |
396 | ||
397 | // pipelined out | |
398 | output pce_ov; // pce override to l1 header | |
399 | output wmr_protect; // warm reset protect | |
400 | output wmr_; // warm reset (active low) | |
401 | output por_; // power-on-reset | |
402 | output cmp_slow_sync_en; // cmp->slow clk sync pulse | |
403 | output slow_cmp_sync_en; // slow->cmp clk sync pulse | |
404 | // output io2x_sync_en; // cmp<->io2x clk sync pulse | |
405 | // output dr_sync_en; // cmp<->dr clk sync pulse | |
406 | ||
407 | // ctrl in (for pipelining) | |
408 | output array_wr_inhibit; | |
409 | input tcu_atpg_mode; | |
410 | input tcu_wr_inhibit; | |
411 | input tcu_clk_stop; | |
412 | input tcu_pce_ov; | |
413 | input rst_wmr_protect; | |
414 | input rst_wmr_; | |
415 | input rst_por_; | |
416 | input ccu_cmp_slow_sync_en; | |
417 | input ccu_slow_cmp_sync_en; | |
418 | // input ccu_io2x_sync_en; | |
419 | // input ccu_dr_sync_en; | |
420 | ||
421 | // ctrl in (for clock gen) | |
422 | input tcu_div_bypass; // bypasses clk divider to mux in ext clk | |
423 | input ccu_div_ph; // phase signal from ccu (div/4 or div/2) | |
424 | input cluster_div_en; // if enabled, l2clk is divided down | |
425 | ||
426 | // clock & test in | |
427 | input gclk; // global clk - this is either cmp or dr | |
428 | input cluster_arst_l; | |
429 | input ccu_serdes_dtm; | |
430 | input clk_ext; // external clk muxed in for ioclk bypass | |
431 | input scan_en; // unused as of today - feb 10, 05 | |
432 | input scan_in; // unused as of today - feb 10, 05 | |
433 | input tcu_aclk; | |
434 | input tcu_bclk; | |
435 | ||
436 | ||
437 | ||
438 | // ************************** | |
439 | // wire declaration | |
440 | // ************************** | |
441 | wire array_wr_inhibit; | |
442 | wire tcu_atpg_mode; | |
443 | wire tcu_wr_inhibit; | |
444 | wire l2clk; | |
445 | wire aclk; | |
446 | wire bclk; | |
447 | wire scan_out; | |
448 | wire aclk_wmr; | |
449 | wire pce_ov; | |
450 | wire wmr_protect; | |
451 | wire wmr_; | |
452 | wire por_; | |
453 | wire cmp_slow_sync_en; | |
454 | wire slow_cmp_sync_en; | |
455 | // wire io2x_sync_en; | |
456 | // wire dr_sync_en; | |
457 | wire tcu_clk_stop; | |
458 | wire tcu_pce_ov; | |
459 | wire rst_wmr_protect; | |
460 | wire rst_wmr_; | |
461 | wire rst_por_; | |
462 | wire ccu_cmp_slow_sync_en; | |
463 | wire ccu_slow_cmp_sync_en; | |
464 | // wire ccu_io2x_sync_en; | |
465 | // wire ccu_dr_sync_en; | |
466 | wire tcu_div_bypass; | |
467 | wire ccu_div_ph; | |
468 | wire cluster_div_en; | |
469 | wire gclk; | |
470 | wire cluster_arst_l; | |
471 | wire clk_ext; | |
472 | wire ccu_serdes_dtm; | |
473 | wire scan_en; | |
474 | wire scan_in; | |
475 | wire tcu_aclk; | |
476 | wire tcu_bclk; | |
477 | ||
478 | wire cclk; | |
479 | ||
480 | ||
481 | // ************************** | |
482 | // instantiations | |
483 | // ************************** | |
484 | ||
485 | // needs a few edits to cluster header def - mahmud.hassan | |
486 | // modified custom cell name for avoiding | |
487 | // collision with sparc core and other clusters - mhassan | |
488 | n2_clk_clstr_hdr_cust xcluster_header ( | |
489 | .gclk (gclk), | |
490 | .l2clk (l2clk), | |
491 | .cluster_arst_l (cluster_arst_l), | |
492 | .ccu_div_ph (ccu_div_ph), | |
493 | .cluster_div_en (cluster_div_en), | |
494 | .tcu_div_bypass (tcu_div_bypass), | |
495 | // .clk_ext (clk_ext), | |
496 | // .ccu_serdes_dtm (ccu_serdes_dtm), | |
497 | .scan_in (scan_in), | |
498 | .scan_en (scan_en), | |
499 | .tcu_aclk (tcu_aclk), | |
500 | .tcu_bclk (tcu_bclk), | |
501 | .ccu_cmp_slow_sync_en (ccu_cmp_slow_sync_en), | |
502 | .ccu_slow_cmp_sync_en (ccu_slow_cmp_sync_en), | |
503 | // .ccu_io2x_sync_en (ccu_io2x_sync_en ), | |
504 | // .ccu_dr_sync_en (ccu_dr_sync_en ), | |
505 | .tcu_pce_ov (tcu_pce_ov), | |
506 | .tcu_clk_stop (tcu_clk_stop), | |
507 | .rst_por_ (rst_por_), | |
508 | .rst_wmr_ (rst_wmr_), | |
509 | .rst_wmr_protect (rst_wmr_protect), | |
510 | .aclk_wmr (aclk_wmr), | |
511 | .aclk (aclk), | |
512 | .bclk (bclk), | |
513 | .cmp_slow_sync_en (cmp_slow_sync_en), | |
514 | .slow_cmp_sync_en (slow_cmp_sync_en), | |
515 | // .io2x_sync_en (io2x_sync_en ), | |
516 | // .dr_sync_en (dr_sync_en ), | |
517 | .pce_ov (pce_ov), | |
518 | .por_ (por_), | |
519 | .wmr_ (wmr_), | |
520 | .wmr_protect (wmr_protect), | |
521 | .scan_out (scan_out), | |
522 | .array_wr_inhibit (array_wr_inhibit), | |
523 | .tcu_atpg_mode (tcu_atpg_mode), | |
524 | .tcu_wr_inhibit (tcu_wr_inhibit), | |
525 | .cclk (cclk) | |
526 | ); | |
527 | ||
528 | ||
529 | ||
530 | // cclk -> l2clk from right | |
531 | FC_NO_NIU_T2_n2_clk_rdp_io2x_cust xright ( | |
532 | .l2clk (l2clk), | |
533 | .cclk (cclk) | |
534 | ); | |
535 | ||
536 | ||
537 | ||
538 | // cclk -> l2clk from left | |
539 | FC_NO_NIU_T2_n2_clk_rdp_io2x_cust xleft ( | |
540 | .l2clk (l2clk), | |
541 | .cclk (cclk) | |
542 | ); | |
543 | ||
544 | endmodule | |
545 | ||
546 | module FC_NO_NIU_T2_n2_clk_rdp_io2x_cust(cclk, l2clk); | |
547 | ||
548 | input cclk; | |
549 | output l2clk; | |
550 | ||
551 | assign #(1) l2clk = cclk; | |
552 | endmodule | |
553 | `endif |