projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: tcu_mon.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | `include "tcu_top.h" | |
| 36 | ||
| 37 | module tcu_mon(); | |
| 38 | ||
| 39 | wire tb_spc0_clk_stop = `TCU.tcu_spc0_clk_stop; | |
| 40 | wire tb_spc1_clk_stop = `TCU.tcu_spc1_clk_stop; | |
| 41 | wire tb_spc2_clk_stop = `TCU.tcu_spc2_clk_stop; | |
| 42 | wire tb_spc3_clk_stop = `TCU.tcu_spc3_clk_stop; | |
| 43 | wire tb_spc4_clk_stop = `TCU.tcu_spc4_clk_stop; | |
| 44 | wire tb_spc5_clk_stop = `TCU.tcu_spc5_clk_stop; | |
| 45 | wire tb_spc6_clk_stop = `TCU.tcu_spc6_clk_stop; | |
| 46 | wire tb_spc7_clk_stop = `TCU.tcu_spc7_clk_stop; | |
| 47 | wire tb_l2d0_clk_stop = `TCU.tcu_l2d0_clk_stop; | |
| 48 | wire tb_l2d1_clk_stop = `TCU.tcu_l2d1_clk_stop; | |
| 49 | wire tb_l2d2_clk_stop = `TCU.tcu_l2d2_clk_stop; | |
| 50 | wire tb_l2d3_clk_stop = `TCU.tcu_l2d3_clk_stop; | |
| 51 | wire tb_l2d4_clk_stop = `TCU.tcu_l2d4_clk_stop; | |
| 52 | wire tb_l2d5_clk_stop = `TCU.tcu_l2d5_clk_stop; | |
| 53 | wire tb_l2d6_clk_stop = `TCU.tcu_l2d6_clk_stop; | |
| 54 | wire tb_l2d7_clk_stop = `TCU.tcu_l2d7_clk_stop; | |
| 55 | wire tb_mcu0_clk_stop = `TCU.tcu_mcu0_clk_stop; | |
| 56 | wire tb_mcu1_clk_stop = `TCU.tcu_mcu1_clk_stop; | |
| 57 | wire tb_mcu2_clk_stop = `TCU.tcu_mcu2_clk_stop; | |
| 58 | wire tb_mcu3_clk_stop = `TCU.tcu_mcu3_clk_stop; | |
| 59 | wire tb_sii_clk_stop = `TCU.tcu_sii_clk_stop; | |
| 60 | wire tb_tds_io_clk_stop = `TCU.tcu_tds_io_clk_stop; | |
| 61 | wire tb_dmu_io_clk_stop = `TCU.tcu_dmu_io_clk_stop; | |
| 62 | wire tb_peu_io_clk_stop = `TCU.tcu_peu_io_clk_stop; | |
| 63 | //wire tb_soc0cmp_clk_stop = `TCU.tcu_soc0cmp_clk_stop; | |
| 64 | //wire tb_soc1cmp_clk_stop = `TCU.tcu_soc1cmp_clk_stop; | |
| 65 | //wire tb_soc2cmp_clk_stop = `TCU.tcu_soc2cmp_clk_stop; | |
| 66 | //wire tb_soc3cmp_clk_stop = `TCU.tcu_soc3cmp_clk_stop; | |
| 67 | //wire tb_soc4cmp_clk_stop = `TCU.tcu_soc4cmp_clk_stop; | |
| 68 | //wire tb_soc5ddr_clk_stop = `TCU.tcu_soc5ddr_clk_stop; | |
| 69 | //wire tb_soc6io_clk_stop = `TCU.tcu_soc6io_clk_stop; | |
| 70 | //wire tb_soc7pc_clk_stop = `TCU.tcu_soc7pc_clk_stop; | |
| 71 | //wire tb_soc8en_clk_stop = `TCU.tcu_soc8en_clk_stop; | |
| 72 | wire tb_l2clk = `CCU.cmp_pll_clk; | |
| 73 | wire tb_sc_POR = `RST.mio_rst_pwron_rst_l; | |
| 74 | wire tb_sc_XIR = `RST.mio_rst_button_xir_l; | |
| 75 | wire tb_sc_PB = `RST.mio_rst_pb_rst_l; | |
| 76 | wire tb_spc0_core_avail = `TCU.ncu_spc0_core_available; // Clock stop control, used below and by 0in | |
| 77 | wire tb_spc1_core_avail = `TCU.ncu_spc1_core_available; // Clock stop control, used below and by 0in | |
| 78 | wire tb_spc2_core_avail = `TCU.ncu_spc2_core_available; // Clock stop control, used below and by 0in | |
| 79 | wire tb_spc3_core_avail = `TCU.ncu_spc3_core_available; // Clock stop control, used below and by 0in | |
| 80 | wire tb_spc4_core_avail = `TCU.ncu_spc4_core_available; // Clock stop control, used below and by 0in | |
| 81 | wire tb_spc5_core_avail = `TCU.ncu_spc5_core_available; // Clock stop control, used below and by 0in | |
| 82 | wire tb_spc6_core_avail = `TCU.ncu_spc6_core_available; // Clock stop control, used below and by 0in | |
| 83 | wire tb_spc7_core_avail = `TCU.ncu_spc7_core_available; // Clock stop control, used below and by 0in | |
| 84 | wire [21:0] tb_fusedata_init; // Used by ncu_init.v/vera interface for setting up efuse | |
| 85 | wire [7:0] tb_spc_clk_stop_bus = {tb_spc7_clk_stop, tb_spc6_clk_stop, tb_spc5_clk_stop, tb_spc4_clk_stop, tb_spc3_clk_stop, tb_spc2_clk_stop, tb_spc1_clk_stop, tb_spc0_clk_stop}; // Used by 0in for clk stop assert/deassert | |
| 86 | ||
| 87 | ||
| 88 | //------- 0in, Guard against unknowns going into cluster header ---------- | |
| 89 | wire tb_core_avail_xguard = tb_spc0_core_avail ^ tb_spc1_core_avail ^ tb_spc2_core_avail ^ tb_spc3_core_avail ^ tb_spc4_core_avail ^ tb_spc5_core_avail ^ tb_spc6_core_avail ^ tb_spc7_core_avail; | |
| 90 | wire tb_clk_stop_xguard = tb_spc0_clk_stop ^ tb_spc1_clk_stop ^ tb_spc2_clk_stop ^ tb_spc3_clk_stop ^ tb_spc4_clk_stop ^ tb_spc5_clk_stop ^ tb_spc6_clk_stop ^ tb_spc7_clk_stop ^ tb_l2d0_clk_stop ^ tb_l2d1_clk_stop ^ tb_l2d2_clk_stop ^ tb_l2d3_clk_stop ^ tb_l2d4_clk_stop ^ tb_l2d5_clk_stop ^ tb_l2d6_clk_stop ^ tb_l2d7_clk_stop ^ tb_mcu0_clk_stop ^ tb_mcu1_clk_stop ^ tb_mcu2_clk_stop ^ tb_mcu3_clk_stop ^ tb_sii_clk_stop ^ tb_tds_io_clk_stop ^ tb_dmu_io_clk_stop ^ tb_peu_io_clk_stop; | |
| 91 | ||
| 92 | ||
| 93 | //------- Vera interface, Reset testbench class uses this for all or nothing checks ---------- | |
| 94 | wire tb_clk_stop_all = tb_spc0_clk_stop & tb_spc1_clk_stop & tb_spc2_clk_stop & tb_spc3_clk_stop & tb_spc4_clk_stop & tb_spc5_clk_stop & tb_spc6_clk_stop & tb_spc7_clk_stop & tb_l2d0_clk_stop & tb_l2d1_clk_stop & tb_l2d2_clk_stop & tb_l2d3_clk_stop & tb_l2d4_clk_stop & tb_l2d5_clk_stop & tb_l2d6_clk_stop & tb_l2d7_clk_stop & tb_mcu0_clk_stop & tb_mcu1_clk_stop & tb_mcu2_clk_stop & tb_mcu3_clk_stop & tb_sii_clk_stop & tb_tds_io_clk_stop & tb_dmu_io_clk_stop & tb_peu_io_clk_stop; | |
| 95 | ||
| 96 | wire tb_clk_stop_one = tb_spc0_clk_stop | tb_spc1_clk_stop | tb_spc2_clk_stop | tb_spc3_clk_stop | tb_spc4_clk_stop | tb_spc5_clk_stop | tb_spc6_clk_stop | tb_spc7_clk_stop | tb_l2d0_clk_stop | tb_l2d1_clk_stop | tb_l2d2_clk_stop | tb_l2d3_clk_stop | tb_l2d4_clk_stop | tb_l2d5_clk_stop | tb_l2d6_clk_stop | tb_l2d7_clk_stop | tb_mcu0_clk_stop | tb_mcu1_clk_stop | tb_mcu2_clk_stop | tb_mcu3_clk_stop | tb_sii_clk_stop | tb_tds_io_clk_stop | tb_dmu_io_clk_stop | tb_peu_io_clk_stop; | |
| 97 | ||
| 98 | endmodule // tcu_mon | |
| 99 |