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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / tcu / vera / classes / ccu_clk_chkr_4fc.vr
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: ccu_clk_chkr_4fc.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36#include "std_display_class.vrh"
37#include "ucb_top.vri"
38#include "ccu_top.vri"
39#include "cluster_hdr_top.vri"
40#include "ucb___packet.vrh"
41#include "ccu_clk_packet.vrh"
42#include "ccu_clks_states.vrh"
43#include "ucb_monitor.vrh"
44#include "ccu_checker.vrh"
45#include "cluster_hdr_chkr.vrh"
46
47#ifndef FC_BENCH // ie. TCU SAT
48
49 class CCU_clk_chkr_4fc { // for TCU SAT, it is empty class
50 integer dummy; // dummy variable to avoid compilation error
51 }
52
53#else // this section is for FC bench
54
55class CCU_clk_chkr_4fc {
56 StandardDisplay dbg;
57 //----- vars for ports in CCU -----
58 CCU_clk_port ccu_clk_port = ccu_clk_bind;
59 CCU_mon_port ccu_mon_port = ccu_mon_bind;
60 UCB_port ccu_ucb_port = ccu_ucb_mon_bind;
61
62 //--- vars for ports for cluster headers in ccu_mon.v -----
63//added by to remove NIU
64#ifndef FC_NO_NIU_T2
65#ifndef NIU_SYSTEMC_T2
66 CLKGEN_port clkgen_ccumon_dr_port = clkgen_ccumon_dr_bind;
67 CLKGEN_port clkgen_ccumon_io2x_port = clkgen_ccumon_io2x_bind;
68#endif
69#endif
70 //--- vars for ports for cluster headers of blocks in TCU_SAT (listed in alphabetical order)---
71 CLKGEN_port clkgen_ccu_cmp_port = clkgen_ccu_cmp_bind;
72 CLKGEN_port clkgen_ccu_io_port = clkgen_ccu_io_bind;
73 CLKGEN_port clkgen_db0_cmp_port = clkgen_db0_cmp_bind;
74 CLKGEN_port clkgen_db0_io_port = clkgen_db0_io_bind;
75 CLKGEN_port clkgen_db1_cmp_port = clkgen_db1_cmp_bind;
76 CLKGEN_port clkgen_db1_io_port = clkgen_db1_io_bind;
77 CLKGEN_port clkgen_efu_cmp_port = clkgen_efu_cmp_bind;
78 CLKGEN_port clkgen_efu_io_port = clkgen_efu_io_bind;
79 CLKGEN_port clkgen_mio_0_cmp_port = clkgen_mio_0_cmp_bind;
80 CLKGEN_port clkgen_mio_1_cmp_port = clkgen_mio_1_cmp_bind;
81 CLKGEN_port clkgen_mio_2_cmp_port = clkgen_mio_2_cmp_bind;
82 CLKGEN_port clkgen_mio_3_cmp_port = clkgen_mio_3_cmp_bind;
83 CLKGEN_port clkgen_mio_io_port = clkgen_mio_io_bind;
84 CLKGEN_port clkgen_ncu_cmp_port = clkgen_ncu_cmp_bind;
85 CLKGEN_port clkgen_ncu_io_port = clkgen_ncu_io_bind;
86 CLKGEN_port clkgen_rst_cmp_port = clkgen_rst_cmp_bind;
87 CLKGEN_port clkgen_rst_io_port = clkgen_rst_io_bind;
88 CLKGEN_port clkgen_tcu_cmp_port = clkgen_tcu_cmp_bind;
89 CLKGEN_port clkgen_tcu_io_port = clkgen_tcu_io_bind;
90
91 //--- vars ports for cluster headers of blocks not in TCU_SAT (listed in alphabetical order)---
92 CLKGEN_port clkgen_ccx_cmp_port = clkgen_ccx_cmp_bind;
93 CLKGEN_port clkgen_dmu_io_port = clkgen_dmu_io_bind;
94 CLKGEN_port clkgen_l2b0_cmp_port = clkgen_l2b0_cmp_bind;
95 CLKGEN_port clkgen_l2b1_cmp_port = clkgen_l2b1_cmp_bind;
96 CLKGEN_port clkgen_l2b2_cmp_port = clkgen_l2b2_cmp_bind;
97 CLKGEN_port clkgen_l2b3_cmp_port = clkgen_l2b3_cmp_bind;
98 CLKGEN_port clkgen_l2b4_cmp_port = clkgen_l2b4_cmp_bind;
99 CLKGEN_port clkgen_l2b5_cmp_port = clkgen_l2b5_cmp_bind;
100 CLKGEN_port clkgen_l2b6_cmp_port = clkgen_l2b6_cmp_bind;
101 CLKGEN_port clkgen_l2b7_cmp_port = clkgen_l2b7_cmp_bind;
102
103//CLKGEN_port clkgen_l2d0_cmp_port = clkgen_l2d0_cmp_bind; // cluster hdr of l2d is changing
104//CLKGEN_port clkgen_l2d1_cmp_port = clkgen_l2d1_cmp_bind;
105//CLKGEN_port clkgen_l2d2_cmp_port = clkgen_l2d2_cmp_bind;
106//CLKGEN_port clkgen_l2d3_cmp_port = clkgen_l2d3_cmp_bind;
107//CLKGEN_port clkgen_l2d4_cmp_port = clkgen_l2d4_cmp_bind;
108//CLKGEN_port clkgen_l2d5_cmp_port = clkgen_l2d5_cmp_bind;
109//CLKGEN_port clkgen_l2d6_cmp_port = clkgen_l2d6_cmp_bind;
110//CLKGEN_port clkgen_l2d7_cmp_port = clkgen_l2d7_cmp_bind;
111
112 CLKGEN_port clkgen_l2t0_cmp_port = clkgen_l2t0_cmp_bind;
113 CLKGEN_port clkgen_l2t1_cmp_port = clkgen_l2t1_cmp_bind;
114 CLKGEN_port clkgen_l2t2_cmp_port = clkgen_l2t2_cmp_bind;
115 CLKGEN_port clkgen_l2t3_cmp_port = clkgen_l2t3_cmp_bind;
116 CLKGEN_port clkgen_l2t4_cmp_port = clkgen_l2t4_cmp_bind;
117 CLKGEN_port clkgen_l2t5_cmp_port = clkgen_l2t5_cmp_bind;
118 CLKGEN_port clkgen_l2t6_cmp_port = clkgen_l2t6_cmp_bind;
119 CLKGEN_port clkgen_l2t7_cmp_port = clkgen_l2t7_cmp_bind;
120#ifndef FC_NO_NIU_T2
121#ifndef NIU_SYSTEMC_T2
122 CLKGEN_port clkgen_mac_io_port = clkgen_mac_io_bind;
123#endif
124#endif
125 CLKGEN_port clkgen_mcu0_cmp_port = clkgen_mcu0_cmp_bind;
126 CLKGEN_port clkgen_mcu0_dr_port = clkgen_mcu0_dr_bind;
127 CLKGEN_port clkgen_mcu0_io_port = clkgen_mcu0_io_bind;
128 CLKGEN_port clkgen_mcu1_cmp_port = clkgen_mcu1_cmp_bind;
129 CLKGEN_port clkgen_mcu1_dr_port = clkgen_mcu1_dr_bind;
130 CLKGEN_port clkgen_mcu1_io_port = clkgen_mcu1_io_bind;
131 CLKGEN_port clkgen_mcu2_cmp_port = clkgen_mcu2_cmp_bind;
132 CLKGEN_port clkgen_mcu2_dr_port = clkgen_mcu2_dr_bind;
133 CLKGEN_port clkgen_mcu2_io_port = clkgen_mcu2_io_bind;
134 CLKGEN_port clkgen_mcu3_cmp_port = clkgen_mcu3_cmp_bind;
135 CLKGEN_port clkgen_mcu3_dr_port = clkgen_mcu3_dr_bind;
136 CLKGEN_port clkgen_mcu3_io_port = clkgen_mcu3_io_bind;
137#ifndef FC_NO_PEU_VERA
138#ifndef PEU_SYSTEMC_T2
139 CLKGEN_port clkgen_peu_io_port = clkgen_peu_io_bind;
140 CLKGEN_port clkgen_peu_pc_port = clkgen_peu_pc_bind;
141#endif
142#endif
143#ifndef FC_NO_NIU_T2
144#ifndef NIU_SYSTEMC_T2
145 CLKGEN_port clkgen_rdp_io_port = clkgen_rdp_io_bind;
146 CLKGEN_port clkgen_rdp_io2x_port = clkgen_rdp_io2x_bind;
147 CLKGEN_port clkgen_rtx_io_port = clkgen_rtx_io_bind;
148 CLKGEN_port clkgen_rtx_io2x_port = clkgen_rtx_io2x_bind;
149#endif
150#endif
151 CLKGEN_port clkgen_sii_cmp_port = clkgen_sii_cmp_bind;
152 CLKGEN_port clkgen_sii_io_port = clkgen_sii_io_bind;
153 CLKGEN_port clkgen_sio_cmp_port = clkgen_sio_cmp_bind;
154 CLKGEN_port clkgen_sio_io_port = clkgen_sio_io_bind;
155#ifndef RTL_NO_SPC0
156 CLKGEN_port clkgen_spc0_cmp_port = clkgen_spc0_cmp_bind;
157#endif
158#ifndef RTL_NO_SPC1
159 CLKGEN_port clkgen_spc1_cmp_port = clkgen_spc1_cmp_bind;
160#endif
161#ifndef RTL_NO_SPC2
162 CLKGEN_port clkgen_spc2_cmp_port = clkgen_spc2_cmp_bind;
163#endif
164#ifndef RTL_NO_SPC3
165 CLKGEN_port clkgen_spc3_cmp_port = clkgen_spc3_cmp_bind;
166#endif
167#ifndef RTL_NO_SPC4
168 CLKGEN_port clkgen_spc4_cmp_port = clkgen_spc4_cmp_bind;
169#endif
170#ifndef RTL_NO_SPC5
171 CLKGEN_port clkgen_spc5_cmp_port = clkgen_spc5_cmp_bind;
172#endif
173#ifndef RTL_NO_SPC6
174 CLKGEN_port clkgen_spc6_cmp_port = clkgen_spc6_cmp_bind;
175#endif
176#ifndef RTL_NO_SPC7
177 CLKGEN_port clkgen_spc7_cmp_port = clkgen_spc7_cmp_bind;
178#endif
179#ifndef FC_NO_NIU_T2
180#ifndef NIU_SYSTEMC_T2
181 CLKGEN_port clkgen_tds_io_port = clkgen_tds_io_bind;
182 CLKGEN_port clkgen_tds_io2x_port = clkgen_tds_io2x_bind;
183#endif
184#endif
185
186 //---- vars for CCU objects ------
187 CCU_clk_packet ccu_clk_pkt;
188 CCU_clks_states ccu_states;
189
190 //--- var for CCU checker ---
191 CCU_checker ccu_checker;
192
193 //--- vars for cluster header checkers of blks in TCU SAT (listed in alphabetical order)---
194 CLUSTER_hdr_chkr clkgen_ccu_cmp_chkr;
195 CLUSTER_hdr_chkr clkgen_ccu_io_chkr;
196 CLUSTER_hdr_chkr clkgen_db0_cmp_chkr;
197 CLUSTER_hdr_chkr clkgen_db0_io_chkr;
198 CLUSTER_hdr_chkr clkgen_db1_cmp_chkr;
199 CLUSTER_hdr_chkr clkgen_db1_io_chkr;
200 CLUSTER_hdr_chkr clkgen_efu_cmp_chkr;
201 CLUSTER_hdr_chkr clkgen_efu_io_chkr;
202 CLUSTER_hdr_chkr clkgen_mio_0_cmp_chkr;
203 CLUSTER_hdr_chkr clkgen_mio_1_cmp_chkr;
204 CLUSTER_hdr_chkr clkgen_mio_2_cmp_chkr;
205 CLUSTER_hdr_chkr clkgen_mio_3_cmp_chkr;
206 CLUSTER_hdr_chkr clkgen_mio_io_chkr;
207 CLUSTER_hdr_chkr clkgen_ncu_cmp_chkr;
208 CLUSTER_hdr_chkr clkgen_ncu_io_chkr;
209 CLUSTER_hdr_chkr clkgen_rst_cmp_chkr;
210 CLUSTER_hdr_chkr clkgen_rst_io_chkr;
211 CLUSTER_hdr_chkr clkgen_tcu_cmp_chkr;
212 CLUSTER_hdr_chkr clkgen_tcu_io_chkr;
213
214 //--- vars for cluster header checkers of blks not in TCU SAT (listed in alphabetical order)---
215 CLUSTER_hdr_chkr clkgen_ccx_cmp_chkr;
216 CLUSTER_hdr_chkr clkgen_dmu_io_chkr;
217 CLUSTER_hdr_chkr clkgen_l2b0_cmp_chkr;
218 CLUSTER_hdr_chkr clkgen_l2b1_cmp_chkr;
219 CLUSTER_hdr_chkr clkgen_l2b2_cmp_chkr;
220 CLUSTER_hdr_chkr clkgen_l2b3_cmp_chkr;
221 CLUSTER_hdr_chkr clkgen_l2b4_cmp_chkr;
222 CLUSTER_hdr_chkr clkgen_l2b5_cmp_chkr;
223 CLUSTER_hdr_chkr clkgen_l2b6_cmp_chkr;
224 CLUSTER_hdr_chkr clkgen_l2b7_cmp_chkr;
225 CLUSTER_hdr_chkr clkgen_l2d0_cmp_chkr;
226 CLUSTER_hdr_chkr clkgen_l2d1_cmp_chkr;
227 CLUSTER_hdr_chkr clkgen_l2d2_cmp_chkr;
228 CLUSTER_hdr_chkr clkgen_l2d3_cmp_chkr;
229 CLUSTER_hdr_chkr clkgen_l2d4_cmp_chkr;
230 CLUSTER_hdr_chkr clkgen_l2d5_cmp_chkr;
231 CLUSTER_hdr_chkr clkgen_l2d6_cmp_chkr;
232 CLUSTER_hdr_chkr clkgen_l2d7_cmp_chkr;
233 CLUSTER_hdr_chkr clkgen_l2t0_cmp_chkr;
234 CLUSTER_hdr_chkr clkgen_l2t1_cmp_chkr;
235 CLUSTER_hdr_chkr clkgen_l2t2_cmp_chkr;
236 CLUSTER_hdr_chkr clkgen_l2t3_cmp_chkr;
237 CLUSTER_hdr_chkr clkgen_l2t4_cmp_chkr;
238 CLUSTER_hdr_chkr clkgen_l2t5_cmp_chkr;
239 CLUSTER_hdr_chkr clkgen_l2t6_cmp_chkr;
240 CLUSTER_hdr_chkr clkgen_l2t7_cmp_chkr;
241#ifndef FC_NO_NIU_T2
242#ifndef NIU_SYSTEMC_T2
243 CLUSTER_hdr_chkr clkgen_mac_io_chkr;
244#endif
245#endif
246 CLUSTER_hdr_chkr clkgen_mcu0_cmp_chkr;
247 CLUSTER_hdr_chkr clkgen_mcu0_dr_chkr;
248 CLUSTER_hdr_chkr clkgen_mcu0_io_chkr;
249 CLUSTER_hdr_chkr clkgen_mcu1_cmp_chkr;
250 CLUSTER_hdr_chkr clkgen_mcu1_dr_chkr;
251 CLUSTER_hdr_chkr clkgen_mcu1_io_chkr;
252 CLUSTER_hdr_chkr clkgen_mcu2_cmp_chkr;
253 CLUSTER_hdr_chkr clkgen_mcu2_dr_chkr;
254 CLUSTER_hdr_chkr clkgen_mcu2_io_chkr;
255 CLUSTER_hdr_chkr clkgen_mcu3_cmp_chkr;
256 CLUSTER_hdr_chkr clkgen_mcu3_dr_chkr;
257 CLUSTER_hdr_chkr clkgen_mcu3_io_chkr;
258#ifndef FC_NO_PEU_VERA
259#ifndef PEU_SYSTEMC_T2
260 CLUSTER_hdr_chkr clkgen_peu_io_chkr;
261 CLUSTER_hdr_chkr clkgen_peu_pc_chkr;
262#endif
263#endif
264#ifndef FC_NO_NIU_T2
265#ifndef NIU_SYSTEMC_T2
266 CLUSTER_hdr_chkr clkgen_rdp_io_chkr;
267 CLUSTER_hdr_chkr clkgen_rdp_io2x_chkr;
268 CLUSTER_hdr_chkr clkgen_rtx_io_chkr;
269 CLUSTER_hdr_chkr clkgen_rtx_io2x_chkr;
270#endif
271#endif
272 CLUSTER_hdr_chkr clkgen_sii_cmp_chkr;
273 CLUSTER_hdr_chkr clkgen_sii_io_chkr;
274 CLUSTER_hdr_chkr clkgen_sio_cmp_chkr;
275 CLUSTER_hdr_chkr clkgen_sio_io_chkr;
276 CLUSTER_hdr_chkr clkgen_spc0_cmp_chkr;
277 CLUSTER_hdr_chkr clkgen_spc1_cmp_chkr;
278 CLUSTER_hdr_chkr clkgen_spc2_cmp_chkr;
279 CLUSTER_hdr_chkr clkgen_spc3_cmp_chkr;
280 CLUSTER_hdr_chkr clkgen_spc4_cmp_chkr;
281 CLUSTER_hdr_chkr clkgen_spc5_cmp_chkr;
282 CLUSTER_hdr_chkr clkgen_spc6_cmp_chkr;
283 CLUSTER_hdr_chkr clkgen_spc7_cmp_chkr;
284#ifndef FC_NO_NIU_T2
285#ifndef NIU_SYSTEMC_T2
286 CLUSTER_hdr_chkr clkgen_tds_io_chkr;
287 CLUSTER_hdr_chkr clkgen_tds_io2x_chkr;
288#endif
289#endif
290 //---public subroutines---
291 task new(StandardDisplay dbg);
292}
293
294//################################################################
295//######### implementation of subroutines ###########
296//################################################################
297
298task CCU_clk_chkr_4fc::new(StandardDisplay dbg) {
299 integer start_it = 1, not_start_it = 0; // 0: not start; otherwise, start the checkers
300
301 if (!get_plus_arg(CHECK, "ccu_checker"))
302 return; // by default, checkers are disabble
303
304 ccu_states = new("CCU_states", dbg, start_it);
305 ccu_checker = new("CCU_checker", dbg, ccu_states, start_it); // ccu checker
306
307 // template: clstrHdrChkr = new("name", dbg, ccu_states, hdrType, clkgen_port, dr_port, io_port, io2x_port, chkCmpSlowSync, chkSlowCmpSync, chkDrSycn, chkIo2xSync, cmpSlowSyncIsIO2X, start_it);
308
309 //---obj instantiations: all cluster hdr checkers for blks in TCU SAT (listed in alphabetical order) ---
310 clkgen_ccu_cmp_chkr = new("ccu_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_ccu_cmp_port, null, null, null, 0, 0, 0, 0, 0, start_it);
311 clkgen_ccu_io_chkr = new("ccu_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_ccu_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
312 clkgen_db0_cmp_chkr = new("db0_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP1, clkgen_db0_cmp_port, null, clkgen_db0_io_port, null, 0, 1, 0, 1, 0, start_it);
313 clkgen_db0_io_chkr = new("db0_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_db0_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
314 clkgen_db1_cmp_chkr = new("db1_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP1, clkgen_db1_cmp_port, null, clkgen_db1_io_port, null, 1, 1, 0, 1, 0, start_it);
315 clkgen_db1_io_chkr = new("db1_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_db1_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
316 clkgen_efu_cmp_chkr = new("efu_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_efu_cmp_port, null, clkgen_efu_io_port, null, 1, 1, 0, 0, 0, start_it);
317 clkgen_efu_io_chkr = new("efu_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_efu_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
318 clkgen_mio_0_cmp_chkr = new("mio_0_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_mio_0_cmp_port, null, null, null, 1, 0, 0, 0, 1, start_it);
319 clkgen_mio_1_cmp_chkr = new("mio_1_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_mio_1_cmp_port, null, null, null, 1, 0, 0, 0, 1, start_it);
320 clkgen_mio_2_cmp_chkr = new("mio_2_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_mio_2_cmp_port, null, null, null, 1, 0, 0, 0, 1, start_it);
321 clkgen_mio_3_cmp_chkr = new("mio_3_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_mio_3_cmp_port, null, null, null, 1, 0, 0, 0, 1, start_it);
322 clkgen_mio_io_chkr = new("mio_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_mio_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
323 clkgen_ncu_cmp_chkr = new("ncu_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_ncu_cmp_port, null, clkgen_ncu_io_port, null, 1, 1, 0, 0, 0, start_it);
324 clkgen_ncu_io_chkr = new("ncu_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_ncu_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
325 clkgen_rst_cmp_chkr = new("rst_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_rst_cmp_port, null, clkgen_rst_io_port, null, 1, 1, 0, 0, 0, start_it);
326 clkgen_rst_io_chkr = new("rst_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_rst_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
327 clkgen_tcu_cmp_chkr = new("tcu_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP1, clkgen_tcu_cmp_port, null, clkgen_tcu_io_port, null, 1, 1, 1, 1, 0, start_it);
328 clkgen_tcu_io_chkr = new("tcu_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_tcu_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
329
330 //---obj instantiations: cluster hdr checkers for blocks not in TCU SAT (listed in alphabetical order) ---
331 clkgen_ccx_cmp_chkr = new("ccx_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_ccx_cmp_port, null, null, null, 0, 0, 0, 0, 0, start_it);
332 clkgen_dmu_io_chkr = new("dmu_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_dmu_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
333
334 clkgen_l2b0_cmp_chkr = new("l2b0_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2b0_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
335 clkgen_l2b1_cmp_chkr = new("l2b1_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2b1_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
336 clkgen_l2b2_cmp_chkr = new("l2b2_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2b2_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
337 clkgen_l2b3_cmp_chkr = new("l2b3_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2b3_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
338 clkgen_l2b4_cmp_chkr = new("l2b4_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2b4_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
339 clkgen_l2b5_cmp_chkr = new("l2b5_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2b5_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
340 clkgen_l2b6_cmp_chkr = new("l2b6_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2b6_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
341 clkgen_l2b7_cmp_chkr = new("l2b7_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2b7_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
342
343//clkgen_l2d0_cmp_chkr = new("l2d0_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2d0_cmp_port, null, null, null, 0, 0, 0, 0, 0, start_it);
344//clkgen_l2d1_cmp_chkr = new("l2d1_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2d1_cmp_port, null, null, null, 0, 0, 0, 0, 0, start_it);
345//clkgen_l2d2_cmp_chkr = new("l2d2_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2d2_cmp_port, null, null, null, 0, 0, 0, 0, 0, start_it);
346//clkgen_l2d3_cmp_chkr = new("l2d3_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2d3_cmp_port, null, null, null, 0, 0, 0, 0, 0, start_it);
347//clkgen_l2d4_cmp_chkr = new("l2d4_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2d4_cmp_port, null, null, null, 0, 0, 0, 0, 0, start_it);
348//clkgen_l2d5_cmp_chkr = new("l2d5_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2d5_cmp_port, null, null, null, 0, 0, 0, 0, 0, start_it);
349//clkgen_l2d6_cmp_chkr = new("l2d6_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2d6_cmp_port, null, null, null, 0, 0, 0, 0, 0, start_it);
350//clkgen_l2d7_cmp_chkr = new("l2d7_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2d7_cmp_port, null, null, null, 0, 0, 0, 0, 0, start_it);
351
352 clkgen_l2t0_cmp_chkr = new("l2t0_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2t0_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
353 clkgen_l2t1_cmp_chkr = new("l2t1_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2t1_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
354 clkgen_l2t2_cmp_chkr = new("l2t2_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2t2_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
355 clkgen_l2t3_cmp_chkr = new("l2t3_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2t3_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
356 clkgen_l2t4_cmp_chkr = new("l2t4_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2t4_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
357 clkgen_l2t5_cmp_chkr = new("l2t5_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2t5_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
358 clkgen_l2t6_cmp_chkr = new("l2t6_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2t6_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
359 clkgen_l2t7_cmp_chkr = new("l2t7_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_l2t7_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
360#ifndef FC_NO_NIU_T2
361#ifndef NIU_SYSTEMC_T2
362 clkgen_mac_io_chkr = new("mac_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_mac_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
363#endif
364#endif
365 clkgen_mcu0_cmp_chkr = new("mcu0_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_mcu0_cmp_port, clkgen_mcu0_dr_port, clkgen_mcu0_io_port, null, 1, 1, 1, 0, 0, start_it);
366 clkgen_mcu0_dr_chkr = new("mcu0_dr_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_DR, clkgen_mcu0_dr_port, null, null, null, 0, 0, 0, 0, 0, start_it);
367 clkgen_mcu0_io_chkr = new("mcu0_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_mcu0_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
368 clkgen_mcu1_cmp_chkr = new("mcu1_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_mcu1_cmp_port, clkgen_mcu1_dr_port, clkgen_mcu1_io_port, null, 1, 1, 1, 0, 0, start_it);
369 clkgen_mcu1_dr_chkr = new("mcu1_dr_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_DR, clkgen_mcu1_dr_port, null, null, null, 0, 0, 0, 0, 0, start_it);
370 clkgen_mcu1_io_chkr = new("mcu1_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_mcu1_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
371 clkgen_mcu2_cmp_chkr = new("mcu2_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_mcu2_cmp_port, clkgen_mcu2_dr_port, clkgen_mcu2_io_port, null, 1, 1, 1, 0, 0, start_it);
372 clkgen_mcu2_dr_chkr = new("mcu2_dr_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_DR, clkgen_mcu2_dr_port, null, null, null, 0, 0, 0, 0, 0, start_it);
373 clkgen_mcu2_io_chkr = new("mcu2_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_mcu2_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
374 clkgen_mcu3_cmp_chkr = new("mcu3_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_mcu3_cmp_port, clkgen_mcu3_dr_port, clkgen_mcu3_io_port, null, 1, 1, 1, 0, 0, start_it);
375 clkgen_mcu3_dr_chkr = new("mcu3_dr_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_DR, clkgen_mcu3_dr_port, null, null, null, 0, 0, 0, 0, 0, start_it);
376 clkgen_mcu3_io_chkr = new("mcu3_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_mcu3_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
377#ifndef FC_NO_PEU_VERA
378#ifndef PEU_SYSTEMC_T2
379 clkgen_peu_io_chkr = new("peu_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_peu_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
380 clkgen_peu_pc_chkr = new("peu_pc_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_peu_pc_port, null, null, null, 0, 0, 0, 0, 0, not_start_it); // review: handle later
381#endif
382#endif
383#ifndef FC_NO_NIU_T2
384#ifndef NIU_SYSTEMC_T2
385 clkgen_rdp_io_chkr = new("rdp_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_rdp_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
386 clkgen_rdp_io2x_chkr = new("rdp_io2x_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO2X, clkgen_rdp_io2x_port, null, null, null, 0, 0, 0, 0, 0, start_it);
387
388 clkgen_rtx_io_chkr = new("rtx_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_rtx_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
389 clkgen_rtx_io2x_chkr = new("rtx_io2x_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO2X, clkgen_rtx_io2x_port, null, null, null, 0, 0, 0, 0, 0, start_it);
390#endif
391#endif
392 clkgen_sii_cmp_chkr = new("sii_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_sii_cmp_port, null, clkgen_sii_io_port, null, 1, 1, 0, 0, 0, start_it);
393 clkgen_sii_io_chkr = new("sii_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_sii_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
394
395 clkgen_sio_cmp_chkr = new("sio_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_sio_cmp_port, null, clkgen_sio_io_port, null, 1, 1, 0, 0, 0, start_it);
396 clkgen_sio_io_chkr = new("sio_io_hdr_chkr ", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_sio_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
397
398#ifndef RTL_NO_SPC0
399 clkgen_spc0_cmp_chkr = new("spc0_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_spc0_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
400#endif
401#ifndef RTL_NO_SPC1
402 clkgen_spc1_cmp_chkr = new("spc1_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_spc1_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
403#endif
404#ifndef RTL_NO_SPC2
405 clkgen_spc2_cmp_chkr = new("spc2_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_spc2_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
406#endif
407#ifndef RTL_NO_SPC3
408 clkgen_spc3_cmp_chkr = new("spc3_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_spc3_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
409#endif
410#ifndef RTL_NO_SPC4
411 clkgen_spc4_cmp_chkr = new("spc4_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_spc4_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
412#endif
413#ifndef RTL_NO_SPC5
414 clkgen_spc5_cmp_chkr = new("spc5_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_spc5_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
415#endif
416#ifndef RTL_NO_SPC6
417 clkgen_spc6_cmp_chkr = new("spc6_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_spc6_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
418#endif
419#ifndef RTL_NO_SPC7
420 clkgen_spc7_cmp_chkr = new("spc7_cmp_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_CMP, clkgen_spc7_cmp_port, null, clkgen_ccu_io_port, null, 1, 1, 0, 0, 0, start_it);
421#endif
422
423#ifndef FC_NO_NIU_T2
424#ifndef NIU_SYSTEMC_T2
425 clkgen_tds_io_chkr = new("tds_io_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO, clkgen_tds_io_port, null, null, null, 0, 0, 0, 0, 0, start_it);
426 clkgen_tds_io2x_chkr = new("tds_io2x_hdr_chkr", dbg, ccu_states, CLUSTER_HDR_IO2X, clkgen_tds_io2x_port, null, null, null, 0, 0, 0, 0, 0, start_it);
427#endif
428#endif
429}
430
431#endif // end of "#ifndef FC_BENCH else"
432
Full OpenSPARC design & verification tarball including full HDL.