projects / OpenSPARC-T2-DV / blame
| Commit | Line | Data |
|---|---|---|
| 86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: cluster_hdrs_mon.vr | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | #include <vera_defines.vrh> | |
| 36 | #include "std_display_class.vrh" | |
| 37 | #include "cluster_hdr_top.vri" | |
| 38 | #include "ccu_top.vri" | |
| 39 | ||
| 40 | #ifndef FC_BENCH // ie. TCU SAT | |
| 41 | ||
| 42 | class CLUSTER_hdrs_mon { // for TCU SAT, it is empty class | |
| 43 | integer dummy; // dummy variable to avoid compilation error | |
| 44 | } | |
| 45 | ||
| 46 | #else // this section is for fullchip bench | |
| 47 | ||
| 48 | class CLUSTER_hdrs_mon { | |
| 49 | StandardDisplay dbg; | |
| 50 | local string dispScope = "cluster_hdrs_mon"; // standard display: display scope | |
| 51 | CCU_clk_port ccu_clk_port = ccu_clk_bind; | |
| 52 | integer sysclk_per; // period of sys clk | |
| 53 | integer verbose; // 0: disable verbose mode; otherwise, enable | |
| 54 | ||
| 55 | //--- vars indicate if spc<n> is present ------ | |
| 56 | integer is_no_spc0, is_no_spc1, is_no_spc2, is_no_spc3, is_no_spc4, is_no_spc5, is_no_spc6, is_no_spc7; // 0: present, else: not present | |
| 57 | //--- vars for ports of all cluster headers (listed in alphabetical order)--- | |
| 58 | CLKGEN_port clkgen_ccu_cmp_port = clkgen_ccu_cmp_bind; | |
| 59 | CLKGEN_port clkgen_ccu_io_port = clkgen_ccu_io_bind; | |
| 60 | CLKGEN_port clkgen_ccx_cmp_port = clkgen_ccx_cmp_bind; | |
| 61 | CLKGEN_port clkgen_db0_cmp_port = clkgen_db0_cmp_bind; | |
| 62 | CLKGEN_port clkgen_db0_io_port = clkgen_db0_io_bind; | |
| 63 | CLKGEN_port clkgen_db1_cmp_port = clkgen_db1_cmp_bind; | |
| 64 | CLKGEN_port clkgen_db1_io_port = clkgen_db1_io_bind; | |
| 65 | CLKGEN_port clkgen_dmu_io_port = clkgen_dmu_io_bind; | |
| 66 | CLKGEN_port clkgen_efu_cmp_port = clkgen_efu_cmp_bind; | |
| 67 | CLKGEN_port clkgen_efu_io_port = clkgen_efu_io_bind; | |
| 68 | CLKGEN_port clkgen_l2b0_cmp_port = clkgen_l2b0_cmp_bind; | |
| 69 | CLKGEN_port clkgen_l2b1_cmp_port = clkgen_l2b1_cmp_bind; | |
| 70 | CLKGEN_port clkgen_l2b2_cmp_port = clkgen_l2b2_cmp_bind; | |
| 71 | CLKGEN_port clkgen_l2b3_cmp_port = clkgen_l2b3_cmp_bind; | |
| 72 | CLKGEN_port clkgen_l2b4_cmp_port = clkgen_l2b4_cmp_bind; | |
| 73 | CLKGEN_port clkgen_l2b5_cmp_port = clkgen_l2b5_cmp_bind; | |
| 74 | CLKGEN_port clkgen_l2b6_cmp_port = clkgen_l2b6_cmp_bind; | |
| 75 | CLKGEN_port clkgen_l2b7_cmp_port = clkgen_l2b7_cmp_bind; | |
| 76 | CLKGEN_port clkgen_l2d0_cmp_port = clkgen_l2d0_cmp_bind; | |
| 77 | CLKGEN_port clkgen_l2d1_cmp_port = clkgen_l2d1_cmp_bind; | |
| 78 | CLKGEN_port clkgen_l2d2_cmp_port = clkgen_l2d2_cmp_bind; | |
| 79 | CLKGEN_port clkgen_l2d3_cmp_port = clkgen_l2d3_cmp_bind; | |
| 80 | CLKGEN_port clkgen_l2d4_cmp_port = clkgen_l2d4_cmp_bind; | |
| 81 | CLKGEN_port clkgen_l2d5_cmp_port = clkgen_l2d5_cmp_bind; | |
| 82 | CLKGEN_port clkgen_l2d6_cmp_port = clkgen_l2d6_cmp_bind; | |
| 83 | CLKGEN_port clkgen_l2d7_cmp_port = clkgen_l2d7_cmp_bind; | |
| 84 | CLKGEN_port clkgen_l2t0_cmp_port = clkgen_l2t0_cmp_bind; | |
| 85 | CLKGEN_port clkgen_l2t1_cmp_port = clkgen_l2t1_cmp_bind; | |
| 86 | CLKGEN_port clkgen_l2t2_cmp_port = clkgen_l2t2_cmp_bind; | |
| 87 | CLKGEN_port clkgen_l2t3_cmp_port = clkgen_l2t3_cmp_bind; | |
| 88 | CLKGEN_port clkgen_l2t4_cmp_port = clkgen_l2t4_cmp_bind; | |
| 89 | CLKGEN_port clkgen_l2t5_cmp_port = clkgen_l2t5_cmp_bind; | |
| 90 | CLKGEN_port clkgen_l2t6_cmp_port = clkgen_l2t6_cmp_bind; | |
| 91 | CLKGEN_port clkgen_l2t7_cmp_port = clkgen_l2t7_cmp_bind; | |
| 92 | //added to remove NIU | |
| 93 | #ifndef FC_NO_NIU_T2 | |
| 94 | #ifndef NIU_SYSTEMC_T2 | |
| 95 | CLKGEN_port clkgen_mac_io_port = clkgen_mac_io_bind; | |
| 96 | #endif | |
| 97 | #endif | |
| 98 | CLKGEN_port clkgen_mcu0_cmp_port = clkgen_mcu0_cmp_bind; | |
| 99 | CLKGEN_port clkgen_mcu0_dr_port = clkgen_mcu0_dr_bind; | |
| 100 | CLKGEN_port clkgen_mcu0_io_port = clkgen_mcu0_io_bind; | |
| 101 | CLKGEN_port clkgen_mcu1_cmp_port = clkgen_mcu1_cmp_bind; | |
| 102 | CLKGEN_port clkgen_mcu1_dr_port = clkgen_mcu1_dr_bind; | |
| 103 | CLKGEN_port clkgen_mcu1_io_port = clkgen_mcu1_io_bind; | |
| 104 | CLKGEN_port clkgen_mcu2_cmp_port = clkgen_mcu2_cmp_bind; | |
| 105 | CLKGEN_port clkgen_mcu2_dr_port = clkgen_mcu2_dr_bind; | |
| 106 | CLKGEN_port clkgen_mcu2_io_port = clkgen_mcu2_io_bind; | |
| 107 | CLKGEN_port clkgen_mcu3_cmp_port = clkgen_mcu3_cmp_bind; | |
| 108 | CLKGEN_port clkgen_mcu3_dr_port = clkgen_mcu3_dr_bind; | |
| 109 | CLKGEN_port clkgen_mcu3_io_port = clkgen_mcu3_io_bind; | |
| 110 | CLKGEN_port clkgen_mio_0_cmp_port = clkgen_mio_0_cmp_bind; | |
| 111 | CLKGEN_port clkgen_mio_1_cmp_port = clkgen_mio_1_cmp_bind; | |
| 112 | CLKGEN_port clkgen_mio_2_cmp_port = clkgen_mio_2_cmp_bind; | |
| 113 | CLKGEN_port clkgen_mio_3_cmp_port = clkgen_mio_3_cmp_bind; | |
| 114 | CLKGEN_port clkgen_mio_io_port = clkgen_mio_io_bind; | |
| 115 | CLKGEN_port clkgen_ncu_cmp_port = clkgen_ncu_cmp_bind; | |
| 116 | CLKGEN_port clkgen_ncu_io_port = clkgen_ncu_io_bind; | |
| 117 | #ifndef FC_NO_PEU_VERA | |
| 118 | #ifndef PEU_SYSTEMC_T2 | |
| 119 | CLKGEN_port clkgen_peu_io_port = clkgen_peu_io_bind; | |
| 120 | CLKGEN_port clkgen_peu_pc_port = clkgen_peu_pc_bind; | |
| 121 | #endif | |
| 122 | #endif | |
| 123 | #ifndef FC_NO_NIU_T2 | |
| 124 | #ifndef NIU_SYSTEMC_T2 | |
| 125 | CLKGEN_port clkgen_rdp_io2x_port = clkgen_rdp_io2x_bind; | |
| 126 | CLKGEN_port clkgen_rdp_io_port = clkgen_rdp_io_bind; | |
| 127 | CLKGEN_port clkgen_rtx_io2x_port = clkgen_rtx_io2x_bind; | |
| 128 | CLKGEN_port clkgen_rtx_io_port = clkgen_rtx_io_bind; | |
| 129 | #endif | |
| 130 | #endif | |
| 131 | CLKGEN_port clkgen_rst_cmp_port = clkgen_rst_cmp_bind; | |
| 132 | CLKGEN_port clkgen_rst_io_port = clkgen_rst_io_bind; | |
| 133 | CLKGEN_port clkgen_sii_cmp_port = clkgen_sii_cmp_bind; | |
| 134 | CLKGEN_port clkgen_sii_io_port = clkgen_sii_io_bind; | |
| 135 | CLKGEN_port clkgen_sio_cmp_port = clkgen_sio_cmp_bind; | |
| 136 | CLKGEN_port clkgen_sio_io_port = clkgen_sio_io_bind; | |
| 137 | #ifndef RTL_NO_SPC0 | |
| 138 | CLKGEN_port clkgen_spc0_cmp_port = clkgen_spc0_cmp_bind; | |
| 139 | #endif | |
| 140 | #ifndef RTL_NO_SPC1 | |
| 141 | CLKGEN_port clkgen_spc1_cmp_port = clkgen_spc1_cmp_bind; | |
| 142 | #endif | |
| 143 | #ifndef RTL_NO_SPC2 | |
| 144 | CLKGEN_port clkgen_spc2_cmp_port = clkgen_spc2_cmp_bind; | |
| 145 | #endif | |
| 146 | #ifndef RTL_NO_SPC3 | |
| 147 | CLKGEN_port clkgen_spc3_cmp_port = clkgen_spc3_cmp_bind; | |
| 148 | #endif | |
| 149 | #ifndef RTL_NO_SPC4 | |
| 150 | CLKGEN_port clkgen_spc4_cmp_port = clkgen_spc4_cmp_bind; | |
| 151 | #endif | |
| 152 | #ifndef RTL_NO_SPC5 | |
| 153 | CLKGEN_port clkgen_spc5_cmp_port = clkgen_spc5_cmp_bind; | |
| 154 | #endif | |
| 155 | #ifndef RTL_NO_SPC6 | |
| 156 | CLKGEN_port clkgen_spc6_cmp_port = clkgen_spc6_cmp_bind; | |
| 157 | #endif | |
| 158 | #ifndef RTL_NO_SPC7 | |
| 159 | CLKGEN_port clkgen_spc7_cmp_port = clkgen_spc7_cmp_bind; | |
| 160 | #endif | |
| 161 | CLKGEN_port clkgen_tcu_cmp_port = clkgen_tcu_cmp_bind; | |
| 162 | CLKGEN_port clkgen_tcu_io_port = clkgen_tcu_io_bind; | |
| 163 | #ifndef FC_NO_NIU_T2 | |
| 164 | #ifndef NIU_SYSTEMC_T2 | |
| 165 | CLKGEN_port clkgen_tds_io2x_port = clkgen_tds_io2x_bind; | |
| 166 | CLKGEN_port clkgen_tds_io_port = clkgen_tds_io_bind; | |
| 167 | #endif | |
| 168 | #endif | |
| 169 | //---- vars keep track of edges of l2clk and tcu_clk_stop. t: time, c: cycle ---- | |
| 170 | integer ccu_cmp_clkstp_pedge_t, ccu_cmp_clkstp_pedge_c, ccu_cmp_clkstp_pedge_cnt, ccu_cmp_clkstp_nedge_t, ccu_cmp_clkstp_nedge_c, ccu_cmp_clkstp_nedge_cnt, ccu_cmp_l2clk_pedge, ccu_cmp_l2clk_nedge; | |
| 171 | integer ccu_io_clkstp_pedge_t, ccu_io_clkstp_pedge_c, ccu_io_clkstp_pedge_cnt, ccu_io_clkstp_nedge_t, ccu_io_clkstp_nedge_c, ccu_io_clkstp_nedge_cnt, ccu_io_l2clk_pedge, ccu_io_l2clk_nedge; | |
| 172 | integer ccx_cmp_clkstp_pedge_t, ccx_cmp_clkstp_pedge_c, ccx_cmp_clkstp_pedge_cnt, ccx_cmp_clkstp_nedge_t, ccx_cmp_clkstp_nedge_c, ccx_cmp_clkstp_nedge_cnt, ccx_cmp_l2clk_pedge, ccx_cmp_l2clk_nedge; | |
| 173 | integer db0_cmp_clkstp_pedge_t, db0_cmp_clkstp_pedge_c, db0_cmp_clkstp_pedge_cnt, db0_cmp_clkstp_nedge_t, db0_cmp_clkstp_nedge_c, db0_cmp_clkstp_nedge_cnt, db0_cmp_l2clk_pedge, db0_cmp_l2clk_nedge; | |
| 174 | integer db0_io_clkstp_pedge_t, db0_io_clkstp_pedge_c, db0_io_clkstp_pedge_cnt, db0_io_clkstp_nedge_t, db0_io_clkstp_nedge_c, db0_io_clkstp_nedge_cnt, db0_io_l2clk_pedge, db0_io_l2clk_nedge; | |
| 175 | integer db1_cmp_clkstp_pedge_t, db1_cmp_clkstp_pedge_c, db1_cmp_clkstp_pedge_cnt, db1_cmp_clkstp_nedge_t, db1_cmp_clkstp_nedge_c, db1_cmp_clkstp_nedge_cnt, db1_cmp_l2clk_pedge, db1_cmp_l2clk_nedge; | |
| 176 | integer db1_io_clkstp_pedge_t, db1_io_clkstp_pedge_c, db1_io_clkstp_pedge_cnt, db1_io_clkstp_nedge_t, db1_io_clkstp_nedge_c, db1_io_clkstp_nedge_cnt, db1_io_l2clk_pedge, db1_io_l2clk_nedge; | |
| 177 | integer dmu_io_clkstp_pedge_t, dmu_io_clkstp_pedge_c, dmu_io_clkstp_pedge_cnt, dmu_io_clkstp_nedge_t, dmu_io_clkstp_nedge_c, dmu_io_clkstp_nedge_cnt, dmu_io_l2clk_pedge, dmu_io_l2clk_nedge; | |
| 178 | integer efu_cmp_clkstp_pedge_t, efu_cmp_clkstp_pedge_c, efu_cmp_clkstp_pedge_cnt, efu_cmp_clkstp_nedge_t, efu_cmp_clkstp_nedge_c, efu_cmp_clkstp_nedge_cnt, efu_cmp_l2clk_pedge, efu_cmp_l2clk_nedge; | |
| 179 | integer efu_io_clkstp_pedge_t, efu_io_clkstp_pedge_c, efu_io_clkstp_pedge_cnt, efu_io_clkstp_nedge_t, efu_io_clkstp_nedge_c, efu_io_clkstp_nedge_cnt, efu_io_l2clk_pedge, efu_io_l2clk_nedge; | |
| 180 | integer l2b0_cmp_clkstp_pedge_t, l2b0_cmp_clkstp_pedge_c, l2b0_cmp_clkstp_pedge_cnt, l2b0_cmp_clkstp_nedge_t, l2b0_cmp_clkstp_nedge_c, l2b0_cmp_clkstp_nedge_cnt, l2b0_cmp_l2clk_pedge, l2b0_cmp_l2clk_nedge; | |
| 181 | integer l2b1_cmp_clkstp_pedge_t, l2b1_cmp_clkstp_pedge_c, l2b1_cmp_clkstp_pedge_cnt, l2b1_cmp_clkstp_nedge_t, l2b1_cmp_clkstp_nedge_c, l2b1_cmp_clkstp_nedge_cnt, l2b1_cmp_l2clk_pedge, l2b1_cmp_l2clk_nedge; | |
| 182 | integer l2b2_cmp_clkstp_pedge_t, l2b2_cmp_clkstp_pedge_c, l2b2_cmp_clkstp_pedge_cnt, l2b2_cmp_clkstp_nedge_t, l2b2_cmp_clkstp_nedge_c, l2b2_cmp_clkstp_nedge_cnt, l2b2_cmp_l2clk_pedge, l2b2_cmp_l2clk_nedge; | |
| 183 | integer l2b3_cmp_clkstp_pedge_t, l2b3_cmp_clkstp_pedge_c, l2b3_cmp_clkstp_pedge_cnt, l2b3_cmp_clkstp_nedge_t, l2b3_cmp_clkstp_nedge_c, l2b3_cmp_clkstp_nedge_cnt, l2b3_cmp_l2clk_pedge, l2b3_cmp_l2clk_nedge; | |
| 184 | integer l2b4_cmp_clkstp_pedge_t, l2b4_cmp_clkstp_pedge_c, l2b4_cmp_clkstp_pedge_cnt, l2b4_cmp_clkstp_nedge_t, l2b4_cmp_clkstp_nedge_c, l2b4_cmp_clkstp_nedge_cnt, l2b4_cmp_l2clk_pedge, l2b4_cmp_l2clk_nedge; | |
| 185 | integer l2b5_cmp_clkstp_pedge_t, l2b5_cmp_clkstp_pedge_c, l2b5_cmp_clkstp_pedge_cnt, l2b5_cmp_clkstp_nedge_t, l2b5_cmp_clkstp_nedge_c, l2b5_cmp_clkstp_nedge_cnt, l2b5_cmp_l2clk_pedge, l2b5_cmp_l2clk_nedge; | |
| 186 | integer l2b6_cmp_clkstp_pedge_t, l2b6_cmp_clkstp_pedge_c, l2b6_cmp_clkstp_pedge_cnt, l2b6_cmp_clkstp_nedge_t, l2b6_cmp_clkstp_nedge_c, l2b6_cmp_clkstp_nedge_cnt, l2b6_cmp_l2clk_pedge, l2b6_cmp_l2clk_nedge; | |
| 187 | integer l2b7_cmp_clkstp_pedge_t, l2b7_cmp_clkstp_pedge_c, l2b7_cmp_clkstp_pedge_cnt, l2b7_cmp_clkstp_nedge_t, l2b7_cmp_clkstp_nedge_c, l2b7_cmp_clkstp_nedge_cnt, l2b7_cmp_l2clk_pedge, l2b7_cmp_l2clk_nedge; | |
| 188 | integer l2d0_cmp_clkstp_pedge_t, l2d0_cmp_clkstp_pedge_c, l2d0_cmp_clkstp_pedge_cnt, l2d0_cmp_clkstp_nedge_t, l2d0_cmp_clkstp_nedge_c, l2d0_cmp_clkstp_nedge_cnt, l2d0_cmp_l2clk_pedge, l2d0_cmp_l2clk_nedge; | |
| 189 | integer l2d1_cmp_clkstp_pedge_t, l2d1_cmp_clkstp_pedge_c, l2d1_cmp_clkstp_pedge_cnt, l2d1_cmp_clkstp_nedge_t, l2d1_cmp_clkstp_nedge_c, l2d1_cmp_clkstp_nedge_cnt, l2d1_cmp_l2clk_pedge, l2d1_cmp_l2clk_nedge; | |
| 190 | integer l2d2_cmp_clkstp_pedge_t, l2d2_cmp_clkstp_pedge_c, l2d2_cmp_clkstp_pedge_cnt, l2d2_cmp_clkstp_nedge_t, l2d2_cmp_clkstp_nedge_c, l2d2_cmp_clkstp_nedge_cnt, l2d2_cmp_l2clk_pedge, l2d2_cmp_l2clk_nedge; | |
| 191 | integer l2d3_cmp_clkstp_pedge_t, l2d3_cmp_clkstp_pedge_c, l2d3_cmp_clkstp_pedge_cnt, l2d3_cmp_clkstp_nedge_t, l2d3_cmp_clkstp_nedge_c, l2d3_cmp_clkstp_nedge_cnt, l2d3_cmp_l2clk_pedge, l2d3_cmp_l2clk_nedge; | |
| 192 | integer l2d4_cmp_clkstp_pedge_t, l2d4_cmp_clkstp_pedge_c, l2d4_cmp_clkstp_pedge_cnt, l2d4_cmp_clkstp_nedge_t, l2d4_cmp_clkstp_nedge_c, l2d4_cmp_clkstp_nedge_cnt, l2d4_cmp_l2clk_pedge, l2d4_cmp_l2clk_nedge; | |
| 193 | integer l2d5_cmp_clkstp_pedge_t, l2d5_cmp_clkstp_pedge_c, l2d5_cmp_clkstp_pedge_cnt, l2d5_cmp_clkstp_nedge_t, l2d5_cmp_clkstp_nedge_c, l2d5_cmp_clkstp_nedge_cnt, l2d5_cmp_l2clk_pedge, l2d5_cmp_l2clk_nedge; | |
| 194 | integer l2d6_cmp_clkstp_pedge_t, l2d6_cmp_clkstp_pedge_c, l2d6_cmp_clkstp_pedge_cnt, l2d6_cmp_clkstp_nedge_t, l2d6_cmp_clkstp_nedge_c, l2d6_cmp_clkstp_nedge_cnt, l2d6_cmp_l2clk_pedge, l2d6_cmp_l2clk_nedge; | |
| 195 | integer l2d7_cmp_clkstp_pedge_t, l2d7_cmp_clkstp_pedge_c, l2d7_cmp_clkstp_pedge_cnt, l2d7_cmp_clkstp_nedge_t, l2d7_cmp_clkstp_nedge_c, l2d7_cmp_clkstp_nedge_cnt, l2d7_cmp_l2clk_pedge, l2d7_cmp_l2clk_nedge; | |
| 196 | integer l2t0_cmp_clkstp_pedge_t, l2t0_cmp_clkstp_pedge_c, l2t0_cmp_clkstp_pedge_cnt, l2t0_cmp_clkstp_nedge_t, l2t0_cmp_clkstp_nedge_c, l2t0_cmp_clkstp_nedge_cnt, l2t0_cmp_l2clk_pedge, l2t0_cmp_l2clk_nedge; | |
| 197 | integer l2t1_cmp_clkstp_pedge_t, l2t1_cmp_clkstp_pedge_c, l2t1_cmp_clkstp_pedge_cnt, l2t1_cmp_clkstp_nedge_t, l2t1_cmp_clkstp_nedge_c, l2t1_cmp_clkstp_nedge_cnt, l2t1_cmp_l2clk_pedge, l2t1_cmp_l2clk_nedge; | |
| 198 | integer l2t2_cmp_clkstp_pedge_t, l2t2_cmp_clkstp_pedge_c, l2t2_cmp_clkstp_pedge_cnt, l2t2_cmp_clkstp_nedge_t, l2t2_cmp_clkstp_nedge_c, l2t2_cmp_clkstp_nedge_cnt, l2t2_cmp_l2clk_pedge, l2t2_cmp_l2clk_nedge; | |
| 199 | integer l2t3_cmp_clkstp_pedge_t, l2t3_cmp_clkstp_pedge_c, l2t3_cmp_clkstp_pedge_cnt, l2t3_cmp_clkstp_nedge_t, l2t3_cmp_clkstp_nedge_c, l2t3_cmp_clkstp_nedge_cnt, l2t3_cmp_l2clk_pedge, l2t3_cmp_l2clk_nedge; | |
| 200 | integer l2t4_cmp_clkstp_pedge_t, l2t4_cmp_clkstp_pedge_c, l2t4_cmp_clkstp_pedge_cnt, l2t4_cmp_clkstp_nedge_t, l2t4_cmp_clkstp_nedge_c, l2t4_cmp_clkstp_nedge_cnt, l2t4_cmp_l2clk_pedge, l2t4_cmp_l2clk_nedge; | |
| 201 | integer l2t5_cmp_clkstp_pedge_t, l2t5_cmp_clkstp_pedge_c, l2t5_cmp_clkstp_pedge_cnt, l2t5_cmp_clkstp_nedge_t, l2t5_cmp_clkstp_nedge_c, l2t5_cmp_clkstp_nedge_cnt, l2t5_cmp_l2clk_pedge, l2t5_cmp_l2clk_nedge; | |
| 202 | integer l2t6_cmp_clkstp_pedge_t, l2t6_cmp_clkstp_pedge_c, l2t6_cmp_clkstp_pedge_cnt, l2t6_cmp_clkstp_nedge_t, l2t6_cmp_clkstp_nedge_c, l2t6_cmp_clkstp_nedge_cnt, l2t6_cmp_l2clk_pedge, l2t6_cmp_l2clk_nedge; | |
| 203 | integer l2t7_cmp_clkstp_pedge_t, l2t7_cmp_clkstp_pedge_c, l2t7_cmp_clkstp_pedge_cnt, l2t7_cmp_clkstp_nedge_t, l2t7_cmp_clkstp_nedge_c, l2t7_cmp_clkstp_nedge_cnt, l2t7_cmp_l2clk_pedge, l2t7_cmp_l2clk_nedge; | |
| 204 | #ifndef FC_NO_NIU_T2 | |
| 205 | #ifndef NIU_SYSTEMC_T2 | |
| 206 | integer mac_io_clkstp_pedge_t, mac_io_clkstp_pedge_c, mac_io_clkstp_pedge_cnt, mac_io_clkstp_nedge_t, mac_io_clkstp_nedge_c, mac_io_clkstp_nedge_cnt, mac_io_l2clk_pedge, mac_io_l2clk_nedge; | |
| 207 | #endif | |
| 208 | #endif | |
| 209 | integer mcu0_cmp_clkstp_pedge_t, mcu0_cmp_clkstp_pedge_c, mcu0_cmp_clkstp_pedge_cnt, mcu0_cmp_clkstp_nedge_t, mcu0_cmp_clkstp_nedge_c, mcu0_cmp_clkstp_nedge_cnt, mcu0_cmp_l2clk_pedge, mcu0_cmp_l2clk_nedge; | |
| 210 | integer mcu0_dr_clkstp_pedge_t, mcu0_dr_clkstp_pedge_c, mcu0_dr_clkstp_pedge_cnt, mcu0_dr_clkstp_nedge_t, mcu0_dr_clkstp_nedge_c, mcu0_dr_clkstp_nedge_cnt, mcu0_dr_l2clk_pedge, mcu0_dr_l2clk_nedge; | |
| 211 | integer mcu0_io_clkstp_pedge_t, mcu0_io_clkstp_pedge_c, mcu0_io_clkstp_pedge_cnt, mcu0_io_clkstp_nedge_t, mcu0_io_clkstp_nedge_c, mcu0_io_clkstp_nedge_cnt, mcu0_io_l2clk_pedge, mcu0_io_l2clk_nedge; | |
| 212 | integer mcu1_cmp_clkstp_pedge_t, mcu1_cmp_clkstp_pedge_c, mcu1_cmp_clkstp_pedge_cnt, mcu1_cmp_clkstp_nedge_t, mcu1_cmp_clkstp_nedge_c, mcu1_cmp_clkstp_nedge_cnt, mcu1_cmp_l2clk_pedge, mcu1_cmp_l2clk_nedge; | |
| 213 | integer mcu1_dr_clkstp_pedge_t, mcu1_dr_clkstp_pedge_c, mcu1_dr_clkstp_pedge_cnt, mcu1_dr_clkstp_nedge_t, mcu1_dr_clkstp_nedge_c, mcu1_dr_clkstp_nedge_cnt, mcu1_dr_l2clk_pedge, mcu1_dr_l2clk_nedge; | |
| 214 | integer mcu1_io_clkstp_pedge_t, mcu1_io_clkstp_pedge_c, mcu1_io_clkstp_pedge_cnt, mcu1_io_clkstp_nedge_t, mcu1_io_clkstp_nedge_c, mcu1_io_clkstp_nedge_cnt, mcu1_io_l2clk_pedge, mcu1_io_l2clk_nedge; | |
| 215 | integer mcu2_cmp_clkstp_pedge_t, mcu2_cmp_clkstp_pedge_c, mcu2_cmp_clkstp_pedge_cnt, mcu2_cmp_clkstp_nedge_t, mcu2_cmp_clkstp_nedge_c, mcu2_cmp_clkstp_nedge_cnt, mcu2_cmp_l2clk_pedge, mcu2_cmp_l2clk_nedge; | |
| 216 | integer mcu2_dr_clkstp_pedge_t, mcu2_dr_clkstp_pedge_c, mcu2_dr_clkstp_pedge_cnt, mcu2_dr_clkstp_nedge_t, mcu2_dr_clkstp_nedge_c, mcu2_dr_clkstp_nedge_cnt, mcu2_dr_l2clk_pedge, mcu2_dr_l2clk_nedge; | |
| 217 | integer mcu2_io_clkstp_pedge_t, mcu2_io_clkstp_pedge_c, mcu2_io_clkstp_pedge_cnt, mcu2_io_clkstp_nedge_t, mcu2_io_clkstp_nedge_c, mcu2_io_clkstp_nedge_cnt, mcu2_io_l2clk_pedge, mcu2_io_l2clk_nedge; | |
| 218 | integer mcu3_cmp_clkstp_pedge_t, mcu3_cmp_clkstp_pedge_c, mcu3_cmp_clkstp_pedge_cnt, mcu3_cmp_clkstp_nedge_t, mcu3_cmp_clkstp_nedge_c, mcu3_cmp_clkstp_nedge_cnt, mcu3_cmp_l2clk_pedge, mcu3_cmp_l2clk_nedge; | |
| 219 | integer mcu3_dr_clkstp_pedge_t, mcu3_dr_clkstp_pedge_c, mcu3_dr_clkstp_pedge_cnt, mcu3_dr_clkstp_nedge_t, mcu3_dr_clkstp_nedge_c, mcu3_dr_clkstp_nedge_cnt, mcu3_dr_l2clk_pedge, mcu3_dr_l2clk_nedge; | |
| 220 | integer mcu3_io_clkstp_pedge_t, mcu3_io_clkstp_pedge_c, mcu3_io_clkstp_pedge_cnt, mcu3_io_clkstp_nedge_t, mcu3_io_clkstp_nedge_c, mcu3_io_clkstp_nedge_cnt, mcu3_io_l2clk_pedge, mcu3_io_l2clk_nedge; | |
| 221 | integer mio_0_cmp_clkstp_pedge_t, mio_0_cmp_clkstp_pedge_c, mio_0_cmp_clkstp_pedge_cnt, mio_0_cmp_clkstp_nedge_t, mio_0_cmp_clkstp_nedge_c, mio_0_cmp_clkstp_nedge_cnt, mio_0_cmp_l2clk_pedge, mio_0_cmp_l2clk_nedge; | |
| 222 | integer mio_1_cmp_clkstp_pedge_t, mio_1_cmp_clkstp_pedge_c, mio_1_cmp_clkstp_pedge_cnt, mio_1_cmp_clkstp_nedge_t, mio_1_cmp_clkstp_nedge_c, mio_1_cmp_clkstp_nedge_cnt, mio_1_cmp_l2clk_pedge, mio_1_cmp_l2clk_nedge; | |
| 223 | integer mio_2_cmp_clkstp_pedge_t, mio_2_cmp_clkstp_pedge_c, mio_2_cmp_clkstp_pedge_cnt, mio_2_cmp_clkstp_nedge_t, mio_2_cmp_clkstp_nedge_c, mio_2_cmp_clkstp_nedge_cnt, mio_2_cmp_l2clk_pedge, mio_2_cmp_l2clk_nedge; | |
| 224 | integer mio_3_cmp_clkstp_pedge_t, mio_3_cmp_clkstp_pedge_c, mio_3_cmp_clkstp_pedge_cnt, mio_3_cmp_clkstp_nedge_t, mio_3_cmp_clkstp_nedge_c, mio_3_cmp_clkstp_nedge_cnt, mio_3_cmp_l2clk_pedge, mio_3_cmp_l2clk_nedge; | |
| 225 | integer mio_io_clkstp_pedge_t, mio_io_clkstp_pedge_c, mio_io_clkstp_pedge_cnt, mio_io_clkstp_nedge_t, mio_io_clkstp_nedge_c, mio_io_clkstp_nedge_cnt, mio_io_l2clk_pedge, mio_io_l2clk_nedge; | |
| 226 | integer ncu_cmp_clkstp_pedge_t, ncu_cmp_clkstp_pedge_c, ncu_cmp_clkstp_pedge_cnt, ncu_cmp_clkstp_nedge_t, ncu_cmp_clkstp_nedge_c, ncu_cmp_clkstp_nedge_cnt, ncu_cmp_l2clk_pedge, ncu_cmp_l2clk_nedge; | |
| 227 | integer ncu_io_clkstp_pedge_t, ncu_io_clkstp_pedge_c, ncu_io_clkstp_pedge_cnt, ncu_io_clkstp_nedge_t, ncu_io_clkstp_nedge_c, ncu_io_clkstp_nedge_cnt, ncu_io_l2clk_pedge, ncu_io_l2clk_nedge; | |
| 228 | #ifndef FC_NO_PEU_VERA | |
| 229 | #ifndef PEU_SYSTEMC_T2 | |
| 230 | integer peu_io_clkstp_pedge_t, peu_io_clkstp_pedge_c, peu_io_clkstp_pedge_cnt, peu_io_clkstp_nedge_t, peu_io_clkstp_nedge_c, peu_io_clkstp_nedge_cnt, peu_io_l2clk_pedge, peu_io_l2clk_nedge; | |
| 231 | integer peu_pc_clkstp_pedge_t, peu_pc_clkstp_pedge_c, peu_pc_clkstp_pedge_cnt, peu_pc_clkstp_nedge_t, peu_pc_clkstp_nedge_c, peu_pc_clkstp_nedge_cnt, peu_pc_l2clk_pedge, peu_pc_l2clk_nedge; | |
| 232 | #endif | |
| 233 | #endif | |
| 234 | #ifndef FC_NO_NIU_T2 | |
| 235 | #ifndef NIU_SYSTEMC_T2 | |
| 236 | integer rdp_io2x_clkstp_pedge_t, rdp_io2x_clkstp_pedge_c, rdp_io2x_clkstp_pedge_cnt, rdp_io2x_clkstp_nedge_t, rdp_io2x_clkstp_nedge_c, rdp_io2x_clkstp_nedge_cnt, rdp_io2x_l2clk_pedge, rdp_io2x_l2clk_nedge; | |
| 237 | integer rdp_io_clkstp_pedge_t, rdp_io_clkstp_pedge_c, rdp_io_clkstp_pedge_cnt, rdp_io_clkstp_nedge_t, rdp_io_clkstp_nedge_c, rdp_io_clkstp_nedge_cnt, rdp_io_l2clk_pedge, rdp_io_l2clk_nedge; | |
| 238 | integer rtx_io2x_clkstp_pedge_t, rtx_io2x_clkstp_pedge_c, rtx_io2x_clkstp_pedge_cnt, rtx_io2x_clkstp_nedge_t, rtx_io2x_clkstp_nedge_c, rtx_io2x_clkstp_nedge_cnt, rtx_io2x_l2clk_pedge, rtx_io2x_l2clk_nedge; | |
| 239 | integer rtx_io_clkstp_pedge_t, rtx_io_clkstp_pedge_c, rtx_io_clkstp_pedge_cnt, rtx_io_clkstp_nedge_t, rtx_io_clkstp_nedge_c, rtx_io_clkstp_nedge_cnt, rtx_io_l2clk_pedge, rtx_io_l2clk_nedge; | |
| 240 | #endif | |
| 241 | #endif | |
| 242 | integer rst_cmp_clkstp_pedge_t, rst_cmp_clkstp_pedge_c, rst_cmp_clkstp_pedge_cnt, rst_cmp_clkstp_nedge_t, rst_cmp_clkstp_nedge_c, rst_cmp_clkstp_nedge_cnt, rst_cmp_l2clk_pedge, rst_cmp_l2clk_nedge; | |
| 243 | integer rst_io_clkstp_pedge_t, rst_io_clkstp_pedge_c, rst_io_clkstp_pedge_cnt, rst_io_clkstp_nedge_t, rst_io_clkstp_nedge_c, rst_io_clkstp_nedge_cnt, rst_io_l2clk_pedge, rst_io_l2clk_nedge; | |
| 244 | integer sii_cmp_clkstp_pedge_t, sii_cmp_clkstp_pedge_c, sii_cmp_clkstp_pedge_cnt, sii_cmp_clkstp_nedge_t, sii_cmp_clkstp_nedge_c, sii_cmp_clkstp_nedge_cnt, sii_cmp_l2clk_pedge, sii_cmp_l2clk_nedge; | |
| 245 | integer sii_io_clkstp_pedge_t, sii_io_clkstp_pedge_c, sii_io_clkstp_pedge_cnt, sii_io_clkstp_nedge_t, sii_io_clkstp_nedge_c, sii_io_clkstp_nedge_cnt, sii_io_l2clk_pedge, sii_io_l2clk_nedge; | |
| 246 | integer sio_cmp_clkstp_pedge_t, sio_cmp_clkstp_pedge_c, sio_cmp_clkstp_pedge_cnt, sio_cmp_clkstp_nedge_t, sio_cmp_clkstp_nedge_c, sio_cmp_clkstp_nedge_cnt, sio_cmp_l2clk_pedge, sio_cmp_l2clk_nedge; | |
| 247 | integer sio_io_clkstp_pedge_t, sio_io_clkstp_pedge_c, sio_io_clkstp_pedge_cnt, sio_io_clkstp_nedge_t, sio_io_clkstp_nedge_c, sio_io_clkstp_nedge_cnt, sio_io_l2clk_pedge, sio_io_l2clk_nedge; | |
| 248 | integer spc0_cmp_clkstp_pedge_t, spc0_cmp_clkstp_pedge_c, spc0_cmp_clkstp_pedge_cnt, spc0_cmp_clkstp_nedge_t, spc0_cmp_clkstp_nedge_c, spc0_cmp_clkstp_nedge_cnt, spc0_cmp_l2clk_pedge, spc0_cmp_l2clk_nedge; | |
| 249 | integer spc1_cmp_clkstp_pedge_t, spc1_cmp_clkstp_pedge_c, spc1_cmp_clkstp_pedge_cnt, spc1_cmp_clkstp_nedge_t, spc1_cmp_clkstp_nedge_c, spc1_cmp_clkstp_nedge_cnt, spc1_cmp_l2clk_pedge, spc1_cmp_l2clk_nedge; | |
| 250 | integer spc2_cmp_clkstp_pedge_t, spc2_cmp_clkstp_pedge_c, spc2_cmp_clkstp_pedge_cnt, spc2_cmp_clkstp_nedge_t, spc2_cmp_clkstp_nedge_c, spc2_cmp_clkstp_nedge_cnt, spc2_cmp_l2clk_pedge, spc2_cmp_l2clk_nedge; | |
| 251 | integer spc3_cmp_clkstp_pedge_t, spc3_cmp_clkstp_pedge_c, spc3_cmp_clkstp_pedge_cnt, spc3_cmp_clkstp_nedge_t, spc3_cmp_clkstp_nedge_c, spc3_cmp_clkstp_nedge_cnt, spc3_cmp_l2clk_pedge, spc3_cmp_l2clk_nedge; | |
| 252 | integer spc4_cmp_clkstp_pedge_t, spc4_cmp_clkstp_pedge_c, spc4_cmp_clkstp_pedge_cnt, spc4_cmp_clkstp_nedge_t, spc4_cmp_clkstp_nedge_c, spc4_cmp_clkstp_nedge_cnt, spc4_cmp_l2clk_pedge, spc4_cmp_l2clk_nedge; | |
| 253 | integer spc5_cmp_clkstp_pedge_t, spc5_cmp_clkstp_pedge_c, spc5_cmp_clkstp_pedge_cnt, spc5_cmp_clkstp_nedge_t, spc5_cmp_clkstp_nedge_c, spc5_cmp_clkstp_nedge_cnt, spc5_cmp_l2clk_pedge, spc5_cmp_l2clk_nedge; | |
| 254 | integer spc6_cmp_clkstp_pedge_t, spc6_cmp_clkstp_pedge_c, spc6_cmp_clkstp_pedge_cnt, spc6_cmp_clkstp_nedge_t, spc6_cmp_clkstp_nedge_c, spc6_cmp_clkstp_nedge_cnt, spc6_cmp_l2clk_pedge, spc6_cmp_l2clk_nedge; | |
| 255 | integer spc7_cmp_clkstp_pedge_t, spc7_cmp_clkstp_pedge_c, spc7_cmp_clkstp_pedge_cnt, spc7_cmp_clkstp_nedge_t, spc7_cmp_clkstp_nedge_c, spc7_cmp_clkstp_nedge_cnt, spc7_cmp_l2clk_pedge, spc7_cmp_l2clk_nedge; | |
| 256 | integer tcu_cmp_clkstp_pedge_t, tcu_cmp_clkstp_pedge_c, tcu_cmp_clkstp_pedge_cnt, tcu_cmp_clkstp_nedge_t, tcu_cmp_clkstp_nedge_c, tcu_cmp_clkstp_nedge_cnt, tcu_cmp_l2clk_pedge, tcu_cmp_l2clk_nedge; | |
| 257 | integer tcu_io_clkstp_pedge_t, tcu_io_clkstp_pedge_c, tcu_io_clkstp_pedge_cnt, tcu_io_clkstp_nedge_t, tcu_io_clkstp_nedge_c, tcu_io_clkstp_nedge_cnt, tcu_io_l2clk_pedge, tcu_io_l2clk_nedge; | |
| 258 | #ifndef FC_NO_NIU_T2 | |
| 259 | #ifndef NIU_SYSTEMC_T2 | |
| 260 | integer tds_io2x_clkstp_pedge_t, tds_io2x_clkstp_pedge_c, tds_io2x_clkstp_pedge_cnt, tds_io2x_clkstp_nedge_t, tds_io2x_clkstp_nedge_c, tds_io2x_clkstp_nedge_cnt, tds_io2x_l2clk_pedge, tds_io2x_l2clk_nedge; | |
| 261 | integer tds_io_clkstp_pedge_t, tds_io_clkstp_pedge_c, tds_io_clkstp_pedge_cnt, tds_io_clkstp_nedge_t, tds_io_clkstp_nedge_c, tds_io_clkstp_nedge_cnt, tds_io_l2clk_pedge, tds_io_l2clk_nedge; | |
| 262 | #endif | |
| 263 | #endif | |
| 264 | //----tasks ----- | |
| 265 | task new(StandardDisplay dbg); | |
| 266 | task start_l2clk_n_clkstop_mon(); // run in background | |
| 267 | task reset_l2clk_n_clkstop_vars(); // set all vars to 0 | |
| 268 | function integer is_any_hdr_clkstp_pedge_occur(); // occured | |
| 269 | function integer is_any_hdr_clkstp_nedge_occur(); // occured | |
| 270 | function integer is_any_hdr_clkstp_pedge_more_once(); // occured more than once | |
| 271 | function integer is_any_hdr_clkstp_nedge_more_once(); // occured more than once | |
| 272 | function integer is_all_l2clk_running(); // including ccu, rst and tcu headers | |
| 273 | function integer is_all_l2clk_stopped(); // except ccu, rst and tcu headers | |
| 274 | ||
| 275 | function integer is_all_clkstp_sigs_asserted(); // except ccu, rst and tcu headers | |
| 276 | function integer is_all_clkstp_sigs_deasserted(); // include ccu, rst and tcu headers | |
| 277 | ||
| 278 | } | |
| 279 | ||
| 280 | //======================================================================== | |
| 281 | // | |
| 282 | //======================================================================== | |
| 283 | task CLUSTER_hdrs_mon::new(StandardDisplay dbg) { | |
| 284 | this.dbg = dbg; | |
| 285 | this.verbose = (get_plus_arg(CHECK, "clstrHdrMon_verbose"))? 1 : 0; | |
| 286 | //---- set var indicating if the spc<n> core is present--- | |
| 287 | is_no_spc0 = 0; | |
| 288 | is_no_spc1 = 0; | |
| 289 | is_no_spc2 = 0; | |
| 290 | is_no_spc3 = 0; | |
| 291 | is_no_spc4 = 0; | |
| 292 | is_no_spc5 = 0; | |
| 293 | is_no_spc6 = 0; | |
| 294 | is_no_spc7 = 0; | |
| 295 | #ifdef RTL_NO_SPC0 | |
| 296 | is_no_spc0 = 1; | |
| 297 | #endif | |
| 298 | #ifdef RTL_NO_SPC1 | |
| 299 | is_no_spc1 = 1; | |
| 300 | #endif | |
| 301 | #ifdef RTL_NO_SPC2 | |
| 302 | is_no_spc2 = 1; | |
| 303 | #endif | |
| 304 | #ifdef RTL_NO_SPC3 | |
| 305 | is_no_spc3 = 1; | |
| 306 | #endif | |
| 307 | #ifdef RTL_NO_SPC4 | |
| 308 | is_no_spc4 = 1; | |
| 309 | #endif | |
| 310 | #ifdef RTL_NO_SPC5 | |
| 311 | is_no_spc5 = 1; | |
| 312 | #endif | |
| 313 | #ifdef RTL_NO_SPC6 | |
| 314 | is_no_spc6 = 1; | |
| 315 | #endif | |
| 316 | #ifdef RTL_NO_SPC7 | |
| 317 | is_no_spc7 = 1; | |
| 318 | #endif | |
| 319 | //---task calls --- | |
| 320 | this.reset_l2clk_n_clkstop_vars(); // | |
| 321 | fork { // get period of sys clk | |
| 322 | repeat (5) @(posedge ccu_clk_port.$sys_clk); | |
| 323 | sysclk_per = get_time(LO); | |
| 324 | @(posedge ccu_clk_port.$sys_clk); | |
| 325 | sysclk_per = get_time(LO) - sysclk_per; | |
| 326 | } join none | |
| 327 | ||
| 328 | } | |
| 329 | ||
| 330 | //======================================================================== | |
| 331 | // WHAT: reset all variables to 0 | |
| 332 | //======================================================================== | |
| 333 | task CLUSTER_hdrs_mon::reset_l2clk_n_clkstop_vars() { | |
| 334 | if (this.verbose) dbg.dispmon(this.dispScope, MON_ALWAYS, "reset variables for l2clk and clk_stop"); | |
| 335 | ccu_cmp_clkstp_pedge_t=0; ccu_cmp_clkstp_pedge_c=0; ccu_cmp_clkstp_pedge_cnt=0; ccu_cmp_clkstp_nedge_t=0; ccu_cmp_clkstp_nedge_c=0; ccu_cmp_clkstp_nedge_cnt=0; ccu_cmp_l2clk_pedge=0; ccu_cmp_l2clk_nedge=0; | |
| 336 | ccu_io_clkstp_pedge_t=0; ccu_io_clkstp_pedge_c=0; ccu_io_clkstp_pedge_cnt=0; ccu_io_clkstp_nedge_t=0; ccu_io_clkstp_nedge_c=0; ccu_io_clkstp_nedge_cnt=0; ccu_io_l2clk_pedge=0; ccu_io_l2clk_nedge=0; | |
| 337 | ccx_cmp_clkstp_pedge_t=0; ccx_cmp_clkstp_pedge_c=0; ccx_cmp_clkstp_pedge_cnt=0; ccx_cmp_clkstp_nedge_t=0; ccx_cmp_clkstp_nedge_c=0; ccx_cmp_clkstp_nedge_cnt=0; ccx_cmp_l2clk_pedge=0; ccx_cmp_l2clk_nedge=0; | |
| 338 | db0_cmp_clkstp_pedge_t=0; db0_cmp_clkstp_pedge_c=0; db0_cmp_clkstp_pedge_cnt=0; db0_cmp_clkstp_nedge_t=0; db0_cmp_clkstp_nedge_c=0; db0_cmp_clkstp_nedge_cnt=0; db0_cmp_l2clk_pedge=0; db0_cmp_l2clk_nedge=0; | |
| 339 | db0_io_clkstp_pedge_t=0; db0_io_clkstp_pedge_c=0; db0_io_clkstp_pedge_cnt=0; db0_io_clkstp_nedge_t=0; db0_io_clkstp_nedge_c=0; db0_io_clkstp_nedge_cnt=0; db0_io_l2clk_pedge=0; db0_io_l2clk_nedge=0; | |
| 340 | db1_cmp_clkstp_pedge_t=0; db1_cmp_clkstp_pedge_c=0; db1_cmp_clkstp_pedge_cnt=0; db1_cmp_clkstp_nedge_t=0; db1_cmp_clkstp_nedge_c=0; db1_cmp_clkstp_nedge_cnt=0; db1_cmp_l2clk_pedge=0; db1_cmp_l2clk_nedge=0; | |
| 341 | db1_io_clkstp_pedge_t=0; db1_io_clkstp_pedge_c=0; db1_io_clkstp_pedge_cnt=0; db1_io_clkstp_nedge_t=0; db1_io_clkstp_nedge_c=0; db1_io_clkstp_nedge_cnt=0; db1_io_l2clk_pedge=0; db1_io_l2clk_nedge=0; | |
| 342 | dmu_io_clkstp_pedge_t=0; dmu_io_clkstp_pedge_c=0; dmu_io_clkstp_pedge_cnt=0; dmu_io_clkstp_nedge_t=0; dmu_io_clkstp_nedge_c=0; dmu_io_clkstp_nedge_cnt=0; dmu_io_l2clk_pedge=0; dmu_io_l2clk_nedge=0; | |
| 343 | efu_cmp_clkstp_pedge_t=0; efu_cmp_clkstp_pedge_c=0; efu_cmp_clkstp_pedge_cnt=0; efu_cmp_clkstp_nedge_t=0; efu_cmp_clkstp_nedge_c=0; efu_cmp_clkstp_nedge_cnt=0; efu_cmp_l2clk_pedge=0; efu_cmp_l2clk_nedge=0; | |
| 344 | efu_io_clkstp_pedge_t=0; efu_io_clkstp_pedge_c=0; efu_io_clkstp_pedge_cnt=0; efu_io_clkstp_nedge_t=0; efu_io_clkstp_nedge_c=0; efu_io_clkstp_nedge_cnt=0; efu_io_l2clk_pedge=0; efu_io_l2clk_nedge=0; | |
| 345 | l2b0_cmp_clkstp_pedge_t=0; l2b0_cmp_clkstp_pedge_c=0; l2b0_cmp_clkstp_pedge_cnt=0; l2b0_cmp_clkstp_nedge_t=0; l2b0_cmp_clkstp_nedge_c=0; l2b0_cmp_clkstp_nedge_cnt=0; l2b0_cmp_l2clk_pedge=0; l2b0_cmp_l2clk_nedge=0; | |
| 346 | l2b1_cmp_clkstp_pedge_t=0; l2b1_cmp_clkstp_pedge_c=0; l2b1_cmp_clkstp_pedge_cnt=0; l2b1_cmp_clkstp_nedge_t=0; l2b1_cmp_clkstp_nedge_c=0; l2b1_cmp_clkstp_nedge_cnt=0; l2b1_cmp_l2clk_pedge=0; l2b1_cmp_l2clk_nedge=0; | |
| 347 | l2b2_cmp_clkstp_pedge_t=0; l2b2_cmp_clkstp_pedge_c=0; l2b2_cmp_clkstp_pedge_cnt=0; l2b2_cmp_clkstp_nedge_t=0; l2b2_cmp_clkstp_nedge_c=0; l2b2_cmp_clkstp_nedge_cnt=0; l2b2_cmp_l2clk_pedge=0; l2b2_cmp_l2clk_nedge=0; | |
| 348 | l2b3_cmp_clkstp_pedge_t=0; l2b3_cmp_clkstp_pedge_c=0; l2b3_cmp_clkstp_pedge_cnt=0; l2b3_cmp_clkstp_nedge_t=0; l2b3_cmp_clkstp_nedge_c=0; l2b3_cmp_clkstp_nedge_cnt=0; l2b3_cmp_l2clk_pedge=0; l2b3_cmp_l2clk_nedge=0; | |
| 349 | l2b4_cmp_clkstp_pedge_t=0; l2b4_cmp_clkstp_pedge_c=0; l2b4_cmp_clkstp_pedge_cnt=0; l2b4_cmp_clkstp_nedge_t=0; l2b4_cmp_clkstp_nedge_c=0; l2b4_cmp_clkstp_nedge_cnt=0; l2b4_cmp_l2clk_pedge=0; l2b4_cmp_l2clk_nedge=0; | |
| 350 | l2b5_cmp_clkstp_pedge_t=0; l2b5_cmp_clkstp_pedge_c=0; l2b5_cmp_clkstp_pedge_cnt=0; l2b5_cmp_clkstp_nedge_t=0; l2b5_cmp_clkstp_nedge_c=0; l2b5_cmp_clkstp_nedge_cnt=0; l2b5_cmp_l2clk_pedge=0; l2b5_cmp_l2clk_nedge=0; | |
| 351 | l2b6_cmp_clkstp_pedge_t=0; l2b6_cmp_clkstp_pedge_c=0; l2b6_cmp_clkstp_pedge_cnt=0; l2b6_cmp_clkstp_nedge_t=0; l2b6_cmp_clkstp_nedge_c=0; l2b6_cmp_clkstp_nedge_cnt=0; l2b6_cmp_l2clk_pedge=0; l2b6_cmp_l2clk_nedge=0; | |
| 352 | l2b7_cmp_clkstp_pedge_t=0; l2b7_cmp_clkstp_pedge_c=0; l2b7_cmp_clkstp_pedge_cnt=0; l2b7_cmp_clkstp_nedge_t=0; l2b7_cmp_clkstp_nedge_c=0; l2b7_cmp_clkstp_nedge_cnt=0; l2b7_cmp_l2clk_pedge=0; l2b7_cmp_l2clk_nedge=0; | |
| 353 | l2d0_cmp_clkstp_pedge_t=0; l2d0_cmp_clkstp_pedge_c=0; l2d0_cmp_clkstp_pedge_cnt=0; l2d0_cmp_clkstp_nedge_t=0; l2d0_cmp_clkstp_nedge_c=0; l2d0_cmp_clkstp_nedge_cnt=0; l2d0_cmp_l2clk_pedge=0; l2d0_cmp_l2clk_nedge=0; | |
| 354 | l2d1_cmp_clkstp_pedge_t=0; l2d1_cmp_clkstp_pedge_c=0; l2d1_cmp_clkstp_pedge_cnt=0; l2d1_cmp_clkstp_nedge_t=0; l2d1_cmp_clkstp_nedge_c=0; l2d1_cmp_clkstp_nedge_cnt=0; l2d1_cmp_l2clk_pedge=0; l2d1_cmp_l2clk_nedge=0; | |
| 355 | l2d2_cmp_clkstp_pedge_t=0; l2d2_cmp_clkstp_pedge_c=0; l2d2_cmp_clkstp_pedge_cnt=0; l2d2_cmp_clkstp_nedge_t=0; l2d2_cmp_clkstp_nedge_c=0; l2d2_cmp_clkstp_nedge_cnt=0; l2d2_cmp_l2clk_pedge=0; l2d2_cmp_l2clk_nedge=0; | |
| 356 | l2d3_cmp_clkstp_pedge_t=0; l2d3_cmp_clkstp_pedge_c=0; l2d3_cmp_clkstp_pedge_cnt=0; l2d3_cmp_clkstp_nedge_t=0; l2d3_cmp_clkstp_nedge_c=0; l2d3_cmp_clkstp_nedge_cnt=0; l2d3_cmp_l2clk_pedge=0; l2d3_cmp_l2clk_nedge=0; | |
| 357 | l2d4_cmp_clkstp_pedge_t=0; l2d4_cmp_clkstp_pedge_c=0; l2d4_cmp_clkstp_pedge_cnt=0; l2d4_cmp_clkstp_nedge_t=0; l2d4_cmp_clkstp_nedge_c=0; l2d4_cmp_clkstp_nedge_cnt=0; l2d4_cmp_l2clk_pedge=0; l2d4_cmp_l2clk_nedge=0; | |
| 358 | l2d5_cmp_clkstp_pedge_t=0; l2d5_cmp_clkstp_pedge_c=0; l2d5_cmp_clkstp_pedge_cnt=0; l2d5_cmp_clkstp_nedge_t=0; l2d5_cmp_clkstp_nedge_c=0; l2d5_cmp_clkstp_nedge_cnt=0; l2d5_cmp_l2clk_pedge=0; l2d5_cmp_l2clk_nedge=0; | |
| 359 | l2d6_cmp_clkstp_pedge_t=0; l2d6_cmp_clkstp_pedge_c=0; l2d6_cmp_clkstp_pedge_cnt=0; l2d6_cmp_clkstp_nedge_t=0; l2d6_cmp_clkstp_nedge_c=0; l2d6_cmp_clkstp_nedge_cnt=0; l2d6_cmp_l2clk_pedge=0; l2d6_cmp_l2clk_nedge=0; | |
| 360 | l2d7_cmp_clkstp_pedge_t=0; l2d7_cmp_clkstp_pedge_c=0; l2d7_cmp_clkstp_pedge_cnt=0; l2d7_cmp_clkstp_nedge_t=0; l2d7_cmp_clkstp_nedge_c=0; l2d7_cmp_clkstp_nedge_cnt=0; l2d7_cmp_l2clk_pedge=0; l2d7_cmp_l2clk_nedge=0; | |
| 361 | l2t0_cmp_clkstp_pedge_t=0; l2t0_cmp_clkstp_pedge_c=0; l2t0_cmp_clkstp_pedge_cnt=0; l2t0_cmp_clkstp_nedge_t=0; l2t0_cmp_clkstp_nedge_c=0; l2t0_cmp_clkstp_nedge_cnt=0; l2t0_cmp_l2clk_pedge=0; l2t0_cmp_l2clk_nedge=0; | |
| 362 | l2t1_cmp_clkstp_pedge_t=0; l2t1_cmp_clkstp_pedge_c=0; l2t1_cmp_clkstp_pedge_cnt=0; l2t1_cmp_clkstp_nedge_t=0; l2t1_cmp_clkstp_nedge_c=0; l2t1_cmp_clkstp_nedge_cnt=0; l2t1_cmp_l2clk_pedge=0; l2t1_cmp_l2clk_nedge=0; | |
| 363 | l2t2_cmp_clkstp_pedge_t=0; l2t2_cmp_clkstp_pedge_c=0; l2t2_cmp_clkstp_pedge_cnt=0; l2t2_cmp_clkstp_nedge_t=0; l2t2_cmp_clkstp_nedge_c=0; l2t2_cmp_clkstp_nedge_cnt=0; l2t2_cmp_l2clk_pedge=0; l2t2_cmp_l2clk_nedge=0; | |
| 364 | l2t3_cmp_clkstp_pedge_t=0; l2t3_cmp_clkstp_pedge_c=0; l2t3_cmp_clkstp_pedge_cnt=0; l2t3_cmp_clkstp_nedge_t=0; l2t3_cmp_clkstp_nedge_c=0; l2t3_cmp_clkstp_nedge_cnt=0; l2t3_cmp_l2clk_pedge=0; l2t3_cmp_l2clk_nedge=0; | |
| 365 | l2t4_cmp_clkstp_pedge_t=0; l2t4_cmp_clkstp_pedge_c=0; l2t4_cmp_clkstp_pedge_cnt=0; l2t4_cmp_clkstp_nedge_t=0; l2t4_cmp_clkstp_nedge_c=0; l2t4_cmp_clkstp_nedge_cnt=0; l2t4_cmp_l2clk_pedge=0; l2t4_cmp_l2clk_nedge=0; | |
| 366 | l2t5_cmp_clkstp_pedge_t=0; l2t5_cmp_clkstp_pedge_c=0; l2t5_cmp_clkstp_pedge_cnt=0; l2t5_cmp_clkstp_nedge_t=0; l2t5_cmp_clkstp_nedge_c=0; l2t5_cmp_clkstp_nedge_cnt=0; l2t5_cmp_l2clk_pedge=0; l2t5_cmp_l2clk_nedge=0; | |
| 367 | l2t6_cmp_clkstp_pedge_t=0; l2t6_cmp_clkstp_pedge_c=0; l2t6_cmp_clkstp_pedge_cnt=0; l2t6_cmp_clkstp_nedge_t=0; l2t6_cmp_clkstp_nedge_c=0; l2t6_cmp_clkstp_nedge_cnt=0; l2t6_cmp_l2clk_pedge=0; l2t6_cmp_l2clk_nedge=0; | |
| 368 | l2t7_cmp_clkstp_pedge_t=0; l2t7_cmp_clkstp_pedge_c=0; l2t7_cmp_clkstp_pedge_cnt=0; l2t7_cmp_clkstp_nedge_t=0; l2t7_cmp_clkstp_nedge_c=0; l2t7_cmp_clkstp_nedge_cnt=0; l2t7_cmp_l2clk_pedge=0; l2t7_cmp_l2clk_nedge=0; | |
| 369 | #ifndef FC_NO_NIU_T2 | |
| 370 | #ifndef NIU_SYSTEMC_T2 | |
| 371 | mac_io_clkstp_pedge_t=0; mac_io_clkstp_pedge_c=0; mac_io_clkstp_pedge_cnt=0; mac_io_clkstp_nedge_t=0; mac_io_clkstp_nedge_c=0; mac_io_clkstp_nedge_cnt=0; mac_io_l2clk_pedge=0; mac_io_l2clk_nedge=0; | |
| 372 | #endif | |
| 373 | #endif | |
| 374 | mcu0_cmp_clkstp_pedge_t=0; mcu0_cmp_clkstp_pedge_c=0; mcu0_cmp_clkstp_pedge_cnt=0; mcu0_cmp_clkstp_nedge_t=0; mcu0_cmp_clkstp_nedge_c=0; mcu0_cmp_clkstp_nedge_cnt=0; mcu0_cmp_l2clk_pedge=0; mcu0_cmp_l2clk_nedge=0; | |
| 375 | mcu0_dr_clkstp_pedge_t=0; mcu0_dr_clkstp_pedge_c=0; mcu0_dr_clkstp_pedge_cnt=0; mcu0_dr_clkstp_nedge_t=0; mcu0_dr_clkstp_nedge_c=0; mcu0_dr_clkstp_nedge_cnt=0; mcu0_dr_l2clk_pedge=0; mcu0_dr_l2clk_nedge=0; | |
| 376 | mcu0_io_clkstp_pedge_t=0; mcu0_io_clkstp_pedge_c=0; mcu0_io_clkstp_pedge_cnt=0; mcu0_io_clkstp_nedge_t=0; mcu0_io_clkstp_nedge_c=0; mcu0_io_clkstp_nedge_cnt=0; mcu0_io_l2clk_pedge=0; mcu0_io_l2clk_nedge=0; | |
| 377 | mcu1_cmp_clkstp_pedge_t=0; mcu1_cmp_clkstp_pedge_c=0; mcu1_cmp_clkstp_pedge_cnt=0; mcu1_cmp_clkstp_nedge_t=0; mcu1_cmp_clkstp_nedge_c=0; mcu1_cmp_clkstp_nedge_cnt=0; mcu1_cmp_l2clk_pedge=0; mcu1_cmp_l2clk_nedge=0; | |
| 378 | mcu1_dr_clkstp_pedge_t=0; mcu1_dr_clkstp_pedge_c=0; mcu1_dr_clkstp_pedge_cnt=0; mcu1_dr_clkstp_nedge_t=0; mcu1_dr_clkstp_nedge_c=0; mcu1_dr_clkstp_nedge_cnt=0; mcu1_dr_l2clk_pedge=0; mcu1_dr_l2clk_nedge=0; | |
| 379 | mcu1_io_clkstp_pedge_t=0; mcu1_io_clkstp_pedge_c=0; mcu1_io_clkstp_pedge_cnt=0; mcu1_io_clkstp_nedge_t=0; mcu1_io_clkstp_nedge_c=0; mcu1_io_clkstp_nedge_cnt=0; mcu1_io_l2clk_pedge=0; mcu1_io_l2clk_nedge=0; | |
| 380 | mcu2_cmp_clkstp_pedge_t=0; mcu2_cmp_clkstp_pedge_c=0; mcu2_cmp_clkstp_pedge_cnt=0; mcu2_cmp_clkstp_nedge_t=0; mcu2_cmp_clkstp_nedge_c=0; mcu2_cmp_clkstp_nedge_cnt=0; mcu2_cmp_l2clk_pedge=0; mcu2_cmp_l2clk_nedge=0; | |
| 381 | mcu2_dr_clkstp_pedge_t=0; mcu2_dr_clkstp_pedge_c=0; mcu2_dr_clkstp_pedge_cnt=0; mcu2_dr_clkstp_nedge_t=0; mcu2_dr_clkstp_nedge_c=0; mcu2_dr_clkstp_nedge_cnt=0; mcu2_dr_l2clk_pedge=0; mcu2_dr_l2clk_nedge=0; | |
| 382 | mcu2_io_clkstp_pedge_t=0; mcu2_io_clkstp_pedge_c=0; mcu2_io_clkstp_pedge_cnt=0; mcu2_io_clkstp_nedge_t=0; mcu2_io_clkstp_nedge_c=0; mcu2_io_clkstp_nedge_cnt=0; mcu2_io_l2clk_pedge=0; mcu2_io_l2clk_nedge=0; | |
| 383 | mcu3_cmp_clkstp_pedge_t=0; mcu3_cmp_clkstp_pedge_c=0; mcu3_cmp_clkstp_pedge_cnt=0; mcu3_cmp_clkstp_nedge_t=0; mcu3_cmp_clkstp_nedge_c=0; mcu3_cmp_clkstp_nedge_cnt=0; mcu3_cmp_l2clk_pedge=0; mcu3_cmp_l2clk_nedge=0; | |
| 384 | mcu3_dr_clkstp_pedge_t=0; mcu3_dr_clkstp_pedge_c=0; mcu3_dr_clkstp_pedge_cnt=0; mcu3_dr_clkstp_nedge_t=0; mcu3_dr_clkstp_nedge_c=0; mcu3_dr_clkstp_nedge_cnt=0; mcu3_dr_l2clk_pedge=0; mcu3_dr_l2clk_nedge=0; | |
| 385 | mcu3_io_clkstp_pedge_t=0; mcu3_io_clkstp_pedge_c=0; mcu3_io_clkstp_pedge_cnt=0; mcu3_io_clkstp_nedge_t=0; mcu3_io_clkstp_nedge_c=0; mcu3_io_clkstp_nedge_cnt=0; mcu3_io_l2clk_pedge=0; mcu3_io_l2clk_nedge=0; | |
| 386 | mio_0_cmp_clkstp_pedge_t=0; mio_0_cmp_clkstp_pedge_c=0; mio_0_cmp_clkstp_pedge_cnt=0; mio_0_cmp_clkstp_nedge_t=0; mio_0_cmp_clkstp_nedge_c=0; mio_0_cmp_clkstp_nedge_cnt=0; mio_0_cmp_l2clk_pedge=0; mio_0_cmp_l2clk_nedge=0; | |
| 387 | mio_1_cmp_clkstp_pedge_t=0; mio_1_cmp_clkstp_pedge_c=0; mio_1_cmp_clkstp_pedge_cnt=0; mio_1_cmp_clkstp_nedge_t=0; mio_1_cmp_clkstp_nedge_c=0; mio_1_cmp_clkstp_nedge_cnt=0; mio_1_cmp_l2clk_pedge=0; mio_1_cmp_l2clk_nedge=0; | |
| 388 | mio_2_cmp_clkstp_pedge_t=0; mio_2_cmp_clkstp_pedge_c=0; mio_2_cmp_clkstp_pedge_cnt=0; mio_2_cmp_clkstp_nedge_t=0; mio_2_cmp_clkstp_nedge_c=0; mio_2_cmp_clkstp_nedge_cnt=0; mio_2_cmp_l2clk_pedge=0; mio_2_cmp_l2clk_nedge=0; | |
| 389 | mio_3_cmp_clkstp_pedge_t=0; mio_3_cmp_clkstp_pedge_c=0; mio_3_cmp_clkstp_pedge_cnt=0; mio_3_cmp_clkstp_nedge_t=0; mio_3_cmp_clkstp_nedge_c=0; mio_3_cmp_clkstp_nedge_cnt=0; mio_3_cmp_l2clk_pedge=0; mio_3_cmp_l2clk_nedge=0; | |
| 390 | mio_io_clkstp_pedge_t=0; mio_io_clkstp_pedge_c=0; mio_io_clkstp_pedge_cnt=0; mio_io_clkstp_nedge_t=0; mio_io_clkstp_nedge_c=0; mio_io_clkstp_nedge_cnt=0; mio_io_l2clk_pedge=0; mio_io_l2clk_nedge=0; | |
| 391 | ncu_cmp_clkstp_pedge_t=0; ncu_cmp_clkstp_pedge_c=0; ncu_cmp_clkstp_pedge_cnt=0; ncu_cmp_clkstp_nedge_t=0; ncu_cmp_clkstp_nedge_c=0; ncu_cmp_clkstp_nedge_cnt=0; ncu_cmp_l2clk_pedge=0; ncu_cmp_l2clk_nedge=0; | |
| 392 | ncu_io_clkstp_pedge_t=0; ncu_io_clkstp_pedge_c=0; ncu_io_clkstp_pedge_cnt=0; ncu_io_clkstp_nedge_t=0; ncu_io_clkstp_nedge_c=0; ncu_io_clkstp_nedge_cnt=0; ncu_io_l2clk_pedge=0; ncu_io_l2clk_nedge=0; | |
| 393 | #ifndef FC_NO_PEU_VERA | |
| 394 | #ifndef PEU_SYSTEMC_T2 | |
| 395 | peu_io_clkstp_pedge_t=0; peu_io_clkstp_pedge_c=0; peu_io_clkstp_pedge_cnt=0; peu_io_clkstp_nedge_t=0; peu_io_clkstp_nedge_c=0; peu_io_clkstp_nedge_cnt=0; peu_io_l2clk_pedge=0; peu_io_l2clk_nedge=0; | |
| 396 | peu_pc_clkstp_pedge_t=0; peu_pc_clkstp_pedge_c=0; peu_pc_clkstp_pedge_cnt=0; peu_pc_clkstp_nedge_t=0; peu_pc_clkstp_nedge_c=0; peu_pc_clkstp_nedge_cnt=0; peu_pc_l2clk_pedge=0; peu_pc_l2clk_nedge=0; | |
| 397 | #endif | |
| 398 | #endif | |
| 399 | #ifndef FC_NO_NIU_T2 | |
| 400 | #ifndef NIU_SYSTEMC_T2 | |
| 401 | rdp_io2x_clkstp_pedge_t=0; rdp_io2x_clkstp_pedge_c=0; rdp_io2x_clkstp_pedge_cnt=0; rdp_io2x_clkstp_nedge_t=0; rdp_io2x_clkstp_nedge_c=0; rdp_io2x_clkstp_nedge_cnt=0; rdp_io2x_l2clk_pedge=0; rdp_io2x_l2clk_nedge=0; | |
| 402 | rdp_io_clkstp_pedge_t=0; rdp_io_clkstp_pedge_c=0; rdp_io_clkstp_pedge_cnt=0; rdp_io_clkstp_nedge_t=0; rdp_io_clkstp_nedge_c=0; rdp_io_clkstp_nedge_cnt=0; rdp_io_l2clk_pedge=0; rdp_io_l2clk_nedge=0; | |
| 403 | rtx_io2x_clkstp_pedge_t=0; rtx_io2x_clkstp_pedge_c=0; rtx_io2x_clkstp_pedge_cnt=0; rtx_io2x_clkstp_nedge_t=0; rtx_io2x_clkstp_nedge_c=0; rtx_io2x_clkstp_nedge_cnt=0; rtx_io2x_l2clk_pedge=0; rtx_io2x_l2clk_nedge=0; | |
| 404 | rtx_io_clkstp_pedge_t=0; rtx_io_clkstp_pedge_c=0; rtx_io_clkstp_pedge_cnt=0; rtx_io_clkstp_nedge_t=0; rtx_io_clkstp_nedge_c=0; rtx_io_clkstp_nedge_cnt=0; rtx_io_l2clk_pedge=0; rtx_io_l2clk_nedge=0; | |
| 405 | #endif | |
| 406 | #endif | |
| 407 | rst_cmp_clkstp_pedge_t=0; rst_cmp_clkstp_pedge_c=0; rst_cmp_clkstp_pedge_cnt=0; rst_cmp_clkstp_nedge_t=0; rst_cmp_clkstp_nedge_c=0; rst_cmp_clkstp_nedge_cnt=0; rst_cmp_l2clk_pedge=0; rst_cmp_l2clk_nedge=0; | |
| 408 | rst_io_clkstp_pedge_t=0; rst_io_clkstp_pedge_c=0; rst_io_clkstp_pedge_cnt=0; rst_io_clkstp_nedge_t=0; rst_io_clkstp_nedge_c=0; rst_io_clkstp_nedge_cnt=0; rst_io_l2clk_pedge=0; rst_io_l2clk_nedge=0; | |
| 409 | sii_cmp_clkstp_pedge_t=0; sii_cmp_clkstp_pedge_c=0; sii_cmp_clkstp_pedge_cnt=0; sii_cmp_clkstp_nedge_t=0; sii_cmp_clkstp_nedge_c=0; sii_cmp_clkstp_nedge_cnt=0; sii_cmp_l2clk_pedge=0; sii_cmp_l2clk_nedge=0; | |
| 410 | sii_io_clkstp_pedge_t=0; sii_io_clkstp_pedge_c=0; sii_io_clkstp_pedge_cnt=0; sii_io_clkstp_nedge_t=0; sii_io_clkstp_nedge_c=0; sii_io_clkstp_nedge_cnt=0; sii_io_l2clk_pedge=0; sii_io_l2clk_nedge=0; | |
| 411 | sio_cmp_clkstp_pedge_t=0; sio_cmp_clkstp_pedge_c=0; sio_cmp_clkstp_pedge_cnt=0; sio_cmp_clkstp_nedge_t=0; sio_cmp_clkstp_nedge_c=0; sio_cmp_clkstp_nedge_cnt=0; sio_cmp_l2clk_pedge=0; sio_cmp_l2clk_nedge=0; | |
| 412 | sio_io_clkstp_pedge_t=0; sio_io_clkstp_pedge_c=0; sio_io_clkstp_pedge_cnt=0; sio_io_clkstp_nedge_t=0; sio_io_clkstp_nedge_c=0; sio_io_clkstp_nedge_cnt=0; sio_io_l2clk_pedge=0; sio_io_l2clk_nedge=0; | |
| 413 | spc0_cmp_clkstp_pedge_t=0; spc0_cmp_clkstp_pedge_c=0; spc0_cmp_clkstp_pedge_cnt=0; spc0_cmp_clkstp_nedge_t=0; spc0_cmp_clkstp_nedge_c=0; spc0_cmp_clkstp_nedge_cnt=0; spc0_cmp_l2clk_pedge=0; spc0_cmp_l2clk_nedge=0; | |
| 414 | spc1_cmp_clkstp_pedge_t=0; spc1_cmp_clkstp_pedge_c=0; spc1_cmp_clkstp_pedge_cnt=0; spc1_cmp_clkstp_nedge_t=0; spc1_cmp_clkstp_nedge_c=0; spc1_cmp_clkstp_nedge_cnt=0; spc1_cmp_l2clk_pedge=0; spc1_cmp_l2clk_nedge=0; | |
| 415 | spc2_cmp_clkstp_pedge_t=0; spc2_cmp_clkstp_pedge_c=0; spc2_cmp_clkstp_pedge_cnt=0; spc2_cmp_clkstp_nedge_t=0; spc2_cmp_clkstp_nedge_c=0; spc2_cmp_clkstp_nedge_cnt=0; spc2_cmp_l2clk_pedge=0; spc2_cmp_l2clk_nedge=0; | |
| 416 | spc3_cmp_clkstp_pedge_t=0; spc3_cmp_clkstp_pedge_c=0; spc3_cmp_clkstp_pedge_cnt=0; spc3_cmp_clkstp_nedge_t=0; spc3_cmp_clkstp_nedge_c=0; spc3_cmp_clkstp_nedge_cnt=0; spc3_cmp_l2clk_pedge=0; spc3_cmp_l2clk_nedge=0; | |
| 417 | spc4_cmp_clkstp_pedge_t=0; spc4_cmp_clkstp_pedge_c=0; spc4_cmp_clkstp_pedge_cnt=0; spc4_cmp_clkstp_nedge_t=0; spc4_cmp_clkstp_nedge_c=0; spc4_cmp_clkstp_nedge_cnt=0; spc4_cmp_l2clk_pedge=0; spc4_cmp_l2clk_nedge=0; | |
| 418 | spc5_cmp_clkstp_pedge_t=0; spc5_cmp_clkstp_pedge_c=0; spc5_cmp_clkstp_pedge_cnt=0; spc5_cmp_clkstp_nedge_t=0; spc5_cmp_clkstp_nedge_c=0; spc5_cmp_clkstp_nedge_cnt=0; spc5_cmp_l2clk_pedge=0; spc5_cmp_l2clk_nedge=0; | |
| 419 | spc6_cmp_clkstp_pedge_t=0; spc6_cmp_clkstp_pedge_c=0; spc6_cmp_clkstp_pedge_cnt=0; spc6_cmp_clkstp_nedge_t=0; spc6_cmp_clkstp_nedge_c=0; spc6_cmp_clkstp_nedge_cnt=0; spc6_cmp_l2clk_pedge=0; spc6_cmp_l2clk_nedge=0; | |
| 420 | spc7_cmp_clkstp_pedge_t=0; spc7_cmp_clkstp_pedge_c=0; spc7_cmp_clkstp_pedge_cnt=0; spc7_cmp_clkstp_nedge_t=0; spc7_cmp_clkstp_nedge_c=0; spc7_cmp_clkstp_nedge_cnt=0; spc7_cmp_l2clk_pedge=0; spc7_cmp_l2clk_nedge=0; | |
| 421 | tcu_cmp_clkstp_pedge_t=0; tcu_cmp_clkstp_pedge_c=0; tcu_cmp_clkstp_pedge_cnt=0; tcu_cmp_clkstp_nedge_t=0; tcu_cmp_clkstp_nedge_c=0; tcu_cmp_clkstp_nedge_cnt=0; tcu_cmp_l2clk_pedge=0; tcu_cmp_l2clk_nedge=0; | |
| 422 | tcu_io_clkstp_pedge_t=0; tcu_io_clkstp_pedge_c=0; tcu_io_clkstp_pedge_cnt=0; tcu_io_clkstp_nedge_t=0; tcu_io_clkstp_nedge_c=0; tcu_io_clkstp_nedge_cnt=0; tcu_io_l2clk_pedge=0; tcu_io_l2clk_nedge=0; | |
| 423 | #ifndef FC_NO_NIU_T2 | |
| 424 | #ifndef NIU_SYSTEMC_T2 | |
| 425 | tds_io2x_clkstp_pedge_t=0; tds_io2x_clkstp_pedge_c=0; tds_io2x_clkstp_pedge_cnt=0; tds_io2x_clkstp_nedge_t=0; tds_io2x_clkstp_nedge_c=0; tds_io2x_clkstp_nedge_cnt=0; tds_io2x_l2clk_pedge=0; tds_io2x_l2clk_nedge=0; | |
| 426 | tds_io_clkstp_pedge_t=0; tds_io_clkstp_pedge_c=0; tds_io_clkstp_pedge_cnt=0; tds_io_clkstp_nedge_t=0; tds_io_clkstp_nedge_c=0; tds_io_clkstp_nedge_cnt=0; tds_io_l2clk_pedge=0; tds_io_l2clk_nedge=0; | |
| 427 | #endif | |
| 428 | #endif | |
| 429 | } | |
| 430 | ||
| 431 | //======================================================================== | |
| 432 | // WHAT: start to monitor l2clk and tcu_clk_stop | |
| 433 | //======================================================================== | |
| 434 | task CLUSTER_hdrs_mon::start_l2clk_n_clkstop_mon() { | |
| 435 | dbg.dispmon(this.dispScope, MON_ALWAYS, "start monitoring l2clk and tcu_clk_stop ..."); | |
| 436 | fork | |
| 437 | { | |
| 438 | while (1) { | |
| 439 | @(posedge clkgen_ccu_cmp_port.$tcu_clk_stop__gclk); | |
| 440 | ccu_cmp_clkstp_pedge_t = get_time(LO); | |
| 441 | ccu_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 442 | ccu_cmp_clkstp_pedge_cnt++; | |
| 443 | } | |
| 444 | } | |
| 445 | { | |
| 446 | while (1) { | |
| 447 | @(negedge clkgen_ccu_cmp_port.$tcu_clk_stop__gclk); | |
| 448 | ccu_cmp_clkstp_nedge_t = get_time(LO); | |
| 449 | ccu_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 450 | ccu_cmp_clkstp_nedge_cnt++; | |
| 451 | } | |
| 452 | } | |
| 453 | { | |
| 454 | while (1) { | |
| 455 | @(clkgen_ccu_cmp_port.$l2clk); | |
| 456 | if (clkgen_ccu_cmp_port.$l2clk) | |
| 457 | ccu_cmp_l2clk_pedge = get_time(LO); | |
| 458 | else | |
| 459 | ccu_cmp_l2clk_nedge = get_time(LO); | |
| 460 | } | |
| 461 | } | |
| 462 | { | |
| 463 | while (1) { | |
| 464 | @(posedge clkgen_ccu_io_port.$tcu_clk_stop__gclk); | |
| 465 | ccu_io_clkstp_pedge_t = get_time(LO); | |
| 466 | ccu_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 467 | ccu_io_clkstp_pedge_cnt++; | |
| 468 | } | |
| 469 | } | |
| 470 | { | |
| 471 | while (1) { | |
| 472 | @(negedge clkgen_ccu_io_port.$tcu_clk_stop__gclk); | |
| 473 | ccu_io_clkstp_nedge_t = get_time(LO); | |
| 474 | ccu_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 475 | ccu_io_clkstp_nedge_cnt++; | |
| 476 | } | |
| 477 | } | |
| 478 | { | |
| 479 | while (1) { | |
| 480 | @(clkgen_ccu_io_port.$l2clk); | |
| 481 | if (clkgen_ccu_io_port.$l2clk) | |
| 482 | ccu_io_l2clk_pedge = get_time(LO); | |
| 483 | else | |
| 484 | ccu_io_l2clk_nedge = get_time(LO); | |
| 485 | } | |
| 486 | } | |
| 487 | { | |
| 488 | while (1) { | |
| 489 | @(posedge clkgen_ccx_cmp_port.$tcu_clk_stop__gclk); | |
| 490 | ccx_cmp_clkstp_pedge_t = get_time(LO); | |
| 491 | ccx_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 492 | ccx_cmp_clkstp_pedge_cnt++; | |
| 493 | } | |
| 494 | } | |
| 495 | { | |
| 496 | while (1) { | |
| 497 | @(negedge clkgen_ccx_cmp_port.$tcu_clk_stop__gclk); | |
| 498 | ccx_cmp_clkstp_nedge_t = get_time(LO); | |
| 499 | ccx_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 500 | ccx_cmp_clkstp_nedge_cnt++; | |
| 501 | } | |
| 502 | } | |
| 503 | { | |
| 504 | while (1) { | |
| 505 | @(clkgen_ccx_cmp_port.$l2clk); | |
| 506 | if (clkgen_ccx_cmp_port.$l2clk) | |
| 507 | ccx_cmp_l2clk_pedge = get_time(LO); | |
| 508 | else | |
| 509 | ccx_cmp_l2clk_nedge = get_time(LO); | |
| 510 | } | |
| 511 | } | |
| 512 | { | |
| 513 | while (1) { | |
| 514 | @(posedge clkgen_db0_cmp_port.$tcu_clk_stop__gclk); | |
| 515 | db0_cmp_clkstp_pedge_t = get_time(LO); | |
| 516 | db0_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 517 | db0_cmp_clkstp_pedge_cnt++; | |
| 518 | } | |
| 519 | } | |
| 520 | { | |
| 521 | while (1) { | |
| 522 | @(negedge clkgen_db0_cmp_port.$tcu_clk_stop__gclk); | |
| 523 | db0_cmp_clkstp_nedge_t = get_time(LO); | |
| 524 | db0_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 525 | db0_cmp_clkstp_nedge_cnt++; | |
| 526 | } | |
| 527 | } | |
| 528 | { | |
| 529 | while (1) { | |
| 530 | @(clkgen_db0_cmp_port.$l2clk); | |
| 531 | if (clkgen_db0_cmp_port.$l2clk) | |
| 532 | db0_cmp_l2clk_pedge = get_time(LO); | |
| 533 | else | |
| 534 | db0_cmp_l2clk_nedge = get_time(LO); | |
| 535 | } | |
| 536 | } | |
| 537 | { | |
| 538 | while (1) { | |
| 539 | @(posedge clkgen_db0_io_port.$tcu_clk_stop__gclk); | |
| 540 | db0_io_clkstp_pedge_t = get_time(LO); | |
| 541 | db0_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 542 | db0_io_clkstp_pedge_cnt++; | |
| 543 | } | |
| 544 | } | |
| 545 | { | |
| 546 | while (1) { | |
| 547 | @(negedge clkgen_db0_io_port.$tcu_clk_stop__gclk); | |
| 548 | db0_io_clkstp_nedge_t = get_time(LO); | |
| 549 | db0_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 550 | db0_io_clkstp_nedge_cnt++; | |
| 551 | } | |
| 552 | } | |
| 553 | { | |
| 554 | while (1) { | |
| 555 | @(clkgen_db0_io_port.$l2clk); | |
| 556 | if (clkgen_db0_io_port.$l2clk) | |
| 557 | db0_io_l2clk_pedge = get_time(LO); | |
| 558 | else | |
| 559 | db0_io_l2clk_nedge = get_time(LO); | |
| 560 | } | |
| 561 | } | |
| 562 | { | |
| 563 | while (1) { | |
| 564 | @(posedge clkgen_db1_cmp_port.$tcu_clk_stop__gclk); | |
| 565 | db1_cmp_clkstp_pedge_t = get_time(LO); | |
| 566 | db1_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 567 | db1_cmp_clkstp_pedge_cnt++; | |
| 568 | } | |
| 569 | } | |
| 570 | { | |
| 571 | while (1) { | |
| 572 | @(negedge clkgen_db1_cmp_port.$tcu_clk_stop__gclk); | |
| 573 | db1_cmp_clkstp_nedge_t = get_time(LO); | |
| 574 | db1_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 575 | db1_cmp_clkstp_nedge_cnt++; | |
| 576 | } | |
| 577 | } | |
| 578 | { | |
| 579 | while (1) { | |
| 580 | @(clkgen_db1_cmp_port.$l2clk); | |
| 581 | if (clkgen_db1_cmp_port.$l2clk) | |
| 582 | db1_cmp_l2clk_pedge = get_time(LO); | |
| 583 | else | |
| 584 | db1_cmp_l2clk_nedge = get_time(LO); | |
| 585 | } | |
| 586 | } | |
| 587 | { | |
| 588 | while (1) { | |
| 589 | @(posedge clkgen_db1_io_port.$tcu_clk_stop__gclk); | |
| 590 | db1_io_clkstp_pedge_t = get_time(LO); | |
| 591 | db1_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 592 | db1_io_clkstp_pedge_cnt++; | |
| 593 | } | |
| 594 | } | |
| 595 | { | |
| 596 | while (1) { | |
| 597 | @(negedge clkgen_db1_io_port.$tcu_clk_stop__gclk); | |
| 598 | db1_io_clkstp_nedge_t = get_time(LO); | |
| 599 | db1_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 600 | db1_io_clkstp_nedge_cnt++; | |
| 601 | } | |
| 602 | } | |
| 603 | { | |
| 604 | while (1) { | |
| 605 | @(clkgen_db1_io_port.$l2clk); | |
| 606 | if (clkgen_db1_io_port.$l2clk) | |
| 607 | db1_io_l2clk_pedge = get_time(LO); | |
| 608 | else | |
| 609 | db1_io_l2clk_nedge = get_time(LO); | |
| 610 | } | |
| 611 | } | |
| 612 | { | |
| 613 | while (1) { | |
| 614 | @(posedge clkgen_dmu_io_port.$tcu_clk_stop__gclk); | |
| 615 | dmu_io_clkstp_pedge_t = get_time(LO); | |
| 616 | dmu_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 617 | dmu_io_clkstp_pedge_cnt++; | |
| 618 | } | |
| 619 | } | |
| 620 | { | |
| 621 | while (1) { | |
| 622 | @(negedge clkgen_dmu_io_port.$tcu_clk_stop__gclk); | |
| 623 | dmu_io_clkstp_nedge_t = get_time(LO); | |
| 624 | dmu_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 625 | dmu_io_clkstp_nedge_cnt++; | |
| 626 | } | |
| 627 | } | |
| 628 | { | |
| 629 | while (1) { | |
| 630 | @(clkgen_dmu_io_port.$l2clk); | |
| 631 | if (clkgen_dmu_io_port.$l2clk) | |
| 632 | dmu_io_l2clk_pedge = get_time(LO); | |
| 633 | else | |
| 634 | dmu_io_l2clk_nedge = get_time(LO); | |
| 635 | } | |
| 636 | } | |
| 637 | { | |
| 638 | while (1) { | |
| 639 | @(posedge clkgen_efu_cmp_port.$tcu_clk_stop__gclk); | |
| 640 | efu_cmp_clkstp_pedge_t = get_time(LO); | |
| 641 | efu_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 642 | efu_cmp_clkstp_pedge_cnt++; | |
| 643 | } | |
| 644 | } | |
| 645 | { | |
| 646 | while (1) { | |
| 647 | @(negedge clkgen_efu_cmp_port.$tcu_clk_stop__gclk); | |
| 648 | efu_cmp_clkstp_nedge_t = get_time(LO); | |
| 649 | efu_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 650 | efu_cmp_clkstp_nedge_cnt++; | |
| 651 | } | |
| 652 | } | |
| 653 | { | |
| 654 | while (1) { | |
| 655 | @(clkgen_efu_cmp_port.$l2clk); | |
| 656 | if (clkgen_efu_cmp_port.$l2clk) | |
| 657 | efu_cmp_l2clk_pedge = get_time(LO); | |
| 658 | else | |
| 659 | efu_cmp_l2clk_nedge = get_time(LO); | |
| 660 | } | |
| 661 | } | |
| 662 | { | |
| 663 | while (1) { | |
| 664 | @(posedge clkgen_efu_io_port.$tcu_clk_stop__gclk); | |
| 665 | efu_io_clkstp_pedge_t = get_time(LO); | |
| 666 | efu_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 667 | efu_io_clkstp_pedge_cnt++; | |
| 668 | } | |
| 669 | } | |
| 670 | { | |
| 671 | while (1) { | |
| 672 | @(negedge clkgen_efu_io_port.$tcu_clk_stop__gclk); | |
| 673 | efu_io_clkstp_nedge_t = get_time(LO); | |
| 674 | efu_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 675 | efu_io_clkstp_nedge_cnt++; | |
| 676 | } | |
| 677 | } | |
| 678 | { | |
| 679 | while (1) { | |
| 680 | @(clkgen_efu_io_port.$l2clk); | |
| 681 | if (clkgen_efu_io_port.$l2clk) | |
| 682 | efu_io_l2clk_pedge = get_time(LO); | |
| 683 | else | |
| 684 | efu_io_l2clk_nedge = get_time(LO); | |
| 685 | } | |
| 686 | } | |
| 687 | { | |
| 688 | while (1) { | |
| 689 | @(posedge clkgen_l2b0_cmp_port.$tcu_clk_stop__gclk); | |
| 690 | l2b0_cmp_clkstp_pedge_t = get_time(LO); | |
| 691 | l2b0_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 692 | l2b0_cmp_clkstp_pedge_cnt++; | |
| 693 | } | |
| 694 | } | |
| 695 | { | |
| 696 | while (1) { | |
| 697 | @(negedge clkgen_l2b0_cmp_port.$tcu_clk_stop__gclk); | |
| 698 | l2b0_cmp_clkstp_nedge_t = get_time(LO); | |
| 699 | l2b0_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 700 | l2b0_cmp_clkstp_nedge_cnt++; | |
| 701 | } | |
| 702 | } | |
| 703 | { | |
| 704 | while (1) { | |
| 705 | @(clkgen_l2b0_cmp_port.$l2clk); | |
| 706 | if (clkgen_l2b0_cmp_port.$l2clk) | |
| 707 | l2b0_cmp_l2clk_pedge = get_time(LO); | |
| 708 | else | |
| 709 | l2b0_cmp_l2clk_nedge = get_time(LO); | |
| 710 | } | |
| 711 | } | |
| 712 | { | |
| 713 | while (1) { | |
| 714 | @(posedge clkgen_l2b1_cmp_port.$tcu_clk_stop__gclk); | |
| 715 | l2b1_cmp_clkstp_pedge_t = get_time(LO); | |
| 716 | l2b1_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 717 | l2b1_cmp_clkstp_pedge_cnt++; | |
| 718 | } | |
| 719 | } | |
| 720 | { | |
| 721 | while (1) { | |
| 722 | @(negedge clkgen_l2b1_cmp_port.$tcu_clk_stop__gclk); | |
| 723 | l2b1_cmp_clkstp_nedge_t = get_time(LO); | |
| 724 | l2b1_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 725 | l2b1_cmp_clkstp_nedge_cnt++; | |
| 726 | } | |
| 727 | } | |
| 728 | { | |
| 729 | while (1) { | |
| 730 | @(clkgen_l2b1_cmp_port.$l2clk); | |
| 731 | if (clkgen_l2b1_cmp_port.$l2clk) | |
| 732 | l2b1_cmp_l2clk_pedge = get_time(LO); | |
| 733 | else | |
| 734 | l2b1_cmp_l2clk_nedge = get_time(LO); | |
| 735 | } | |
| 736 | } | |
| 737 | { | |
| 738 | while (1) { | |
| 739 | @(posedge clkgen_l2b2_cmp_port.$tcu_clk_stop__gclk); | |
| 740 | l2b2_cmp_clkstp_pedge_t = get_time(LO); | |
| 741 | l2b2_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 742 | l2b2_cmp_clkstp_pedge_cnt++; | |
| 743 | } | |
| 744 | } | |
| 745 | { | |
| 746 | while (1) { | |
| 747 | @(negedge clkgen_l2b2_cmp_port.$tcu_clk_stop__gclk); | |
| 748 | l2b2_cmp_clkstp_nedge_t = get_time(LO); | |
| 749 | l2b2_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 750 | l2b2_cmp_clkstp_nedge_cnt++; | |
| 751 | } | |
| 752 | } | |
| 753 | { | |
| 754 | while (1) { | |
| 755 | @(clkgen_l2b2_cmp_port.$l2clk); | |
| 756 | if (clkgen_l2b2_cmp_port.$l2clk) | |
| 757 | l2b2_cmp_l2clk_pedge = get_time(LO); | |
| 758 | else | |
| 759 | l2b2_cmp_l2clk_nedge = get_time(LO); | |
| 760 | } | |
| 761 | } | |
| 762 | { | |
| 763 | while (1) { | |
| 764 | @(posedge clkgen_l2b3_cmp_port.$tcu_clk_stop__gclk); | |
| 765 | l2b3_cmp_clkstp_pedge_t = get_time(LO); | |
| 766 | l2b3_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 767 | l2b3_cmp_clkstp_pedge_cnt++; | |
| 768 | } | |
| 769 | } | |
| 770 | { | |
| 771 | while (1) { | |
| 772 | @(negedge clkgen_l2b3_cmp_port.$tcu_clk_stop__gclk); | |
| 773 | l2b3_cmp_clkstp_nedge_t = get_time(LO); | |
| 774 | l2b3_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 775 | l2b3_cmp_clkstp_nedge_cnt++; | |
| 776 | } | |
| 777 | } | |
| 778 | { | |
| 779 | while (1) { | |
| 780 | @(clkgen_l2b3_cmp_port.$l2clk); | |
| 781 | if (clkgen_l2b3_cmp_port.$l2clk) | |
| 782 | l2b3_cmp_l2clk_pedge = get_time(LO); | |
| 783 | else | |
| 784 | l2b3_cmp_l2clk_nedge = get_time(LO); | |
| 785 | } | |
| 786 | } | |
| 787 | { | |
| 788 | while (1) { | |
| 789 | @(posedge clkgen_l2b4_cmp_port.$tcu_clk_stop__gclk); | |
| 790 | l2b4_cmp_clkstp_pedge_t = get_time(LO); | |
| 791 | l2b4_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 792 | l2b4_cmp_clkstp_pedge_cnt++; | |
| 793 | } | |
| 794 | } | |
| 795 | { | |
| 796 | while (1) { | |
| 797 | @(negedge clkgen_l2b4_cmp_port.$tcu_clk_stop__gclk); | |
| 798 | l2b4_cmp_clkstp_nedge_t = get_time(LO); | |
| 799 | l2b4_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 800 | l2b4_cmp_clkstp_nedge_cnt++; | |
| 801 | } | |
| 802 | } | |
| 803 | { | |
| 804 | while (1) { | |
| 805 | @(clkgen_l2b4_cmp_port.$l2clk); | |
| 806 | if (clkgen_l2b4_cmp_port.$l2clk) | |
| 807 | l2b4_cmp_l2clk_pedge = get_time(LO); | |
| 808 | else | |
| 809 | l2b4_cmp_l2clk_nedge = get_time(LO); | |
| 810 | } | |
| 811 | } | |
| 812 | { | |
| 813 | while (1) { | |
| 814 | @(posedge clkgen_l2b5_cmp_port.$tcu_clk_stop__gclk); | |
| 815 | l2b5_cmp_clkstp_pedge_t = get_time(LO); | |
| 816 | l2b5_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 817 | l2b5_cmp_clkstp_pedge_cnt++; | |
| 818 | } | |
| 819 | } | |
| 820 | { | |
| 821 | while (1) { | |
| 822 | @(negedge clkgen_l2b5_cmp_port.$tcu_clk_stop__gclk); | |
| 823 | l2b5_cmp_clkstp_nedge_t = get_time(LO); | |
| 824 | l2b5_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 825 | l2b5_cmp_clkstp_nedge_cnt++; | |
| 826 | } | |
| 827 | } | |
| 828 | { | |
| 829 | while (1) { | |
| 830 | @(clkgen_l2b5_cmp_port.$l2clk); | |
| 831 | if (clkgen_l2b5_cmp_port.$l2clk) | |
| 832 | l2b5_cmp_l2clk_pedge = get_time(LO); | |
| 833 | else | |
| 834 | l2b5_cmp_l2clk_nedge = get_time(LO); | |
| 835 | } | |
| 836 | } | |
| 837 | { | |
| 838 | while (1) { | |
| 839 | @(posedge clkgen_l2b6_cmp_port.$tcu_clk_stop__gclk); | |
| 840 | l2b6_cmp_clkstp_pedge_t = get_time(LO); | |
| 841 | l2b6_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 842 | l2b6_cmp_clkstp_pedge_cnt++; | |
| 843 | } | |
| 844 | } | |
| 845 | { | |
| 846 | while (1) { | |
| 847 | @(negedge clkgen_l2b6_cmp_port.$tcu_clk_stop__gclk); | |
| 848 | l2b6_cmp_clkstp_nedge_t = get_time(LO); | |
| 849 | l2b6_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 850 | l2b6_cmp_clkstp_nedge_cnt++; | |
| 851 | } | |
| 852 | } | |
| 853 | { | |
| 854 | while (1) { | |
| 855 | @(clkgen_l2b6_cmp_port.$l2clk); | |
| 856 | if (clkgen_l2b6_cmp_port.$l2clk) | |
| 857 | l2b6_cmp_l2clk_pedge = get_time(LO); | |
| 858 | else | |
| 859 | l2b6_cmp_l2clk_nedge = get_time(LO); | |
| 860 | } | |
| 861 | } | |
| 862 | { | |
| 863 | while (1) { | |
| 864 | @(posedge clkgen_l2b7_cmp_port.$tcu_clk_stop__gclk); | |
| 865 | l2b7_cmp_clkstp_pedge_t = get_time(LO); | |
| 866 | l2b7_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 867 | l2b7_cmp_clkstp_pedge_cnt++; | |
| 868 | } | |
| 869 | } | |
| 870 | { | |
| 871 | while (1) { | |
| 872 | @(negedge clkgen_l2b7_cmp_port.$tcu_clk_stop__gclk); | |
| 873 | l2b7_cmp_clkstp_nedge_t = get_time(LO); | |
| 874 | l2b7_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 875 | l2b7_cmp_clkstp_nedge_cnt++; | |
| 876 | } | |
| 877 | } | |
| 878 | { | |
| 879 | while (1) { | |
| 880 | @(clkgen_l2b7_cmp_port.$l2clk); | |
| 881 | if (clkgen_l2b7_cmp_port.$l2clk) | |
| 882 | l2b7_cmp_l2clk_pedge = get_time(LO); | |
| 883 | else | |
| 884 | l2b7_cmp_l2clk_nedge = get_time(LO); | |
| 885 | } | |
| 886 | } | |
| 887 | { | |
| 888 | while (1) { | |
| 889 | @(posedge clkgen_l2d0_cmp_port.$tcu_clk_stop__gclk); | |
| 890 | l2d0_cmp_clkstp_pedge_t = get_time(LO); | |
| 891 | l2d0_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 892 | l2d0_cmp_clkstp_pedge_cnt++; | |
| 893 | } | |
| 894 | } | |
| 895 | { | |
| 896 | while (1) { | |
| 897 | @(negedge clkgen_l2d0_cmp_port.$tcu_clk_stop__gclk); | |
| 898 | l2d0_cmp_clkstp_nedge_t = get_time(LO); | |
| 899 | l2d0_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 900 | l2d0_cmp_clkstp_nedge_cnt++; | |
| 901 | } | |
| 902 | } | |
| 903 | { | |
| 904 | while (1) { | |
| 905 | @(clkgen_l2d0_cmp_port.$l2clk); | |
| 906 | if (clkgen_l2d0_cmp_port.$l2clk) | |
| 907 | l2d0_cmp_l2clk_pedge = get_time(LO); | |
| 908 | else | |
| 909 | l2d0_cmp_l2clk_nedge = get_time(LO); | |
| 910 | } | |
| 911 | } | |
| 912 | { | |
| 913 | while (1) { | |
| 914 | @(posedge clkgen_l2d1_cmp_port.$tcu_clk_stop__gclk); | |
| 915 | l2d1_cmp_clkstp_pedge_t = get_time(LO); | |
| 916 | l2d1_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 917 | l2d1_cmp_clkstp_pedge_cnt++; | |
| 918 | } | |
| 919 | } | |
| 920 | { | |
| 921 | while (1) { | |
| 922 | @(negedge clkgen_l2d1_cmp_port.$tcu_clk_stop__gclk); | |
| 923 | l2d1_cmp_clkstp_nedge_t = get_time(LO); | |
| 924 | l2d1_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 925 | l2d1_cmp_clkstp_nedge_cnt++; | |
| 926 | } | |
| 927 | } | |
| 928 | { | |
| 929 | while (1) { | |
| 930 | @(clkgen_l2d1_cmp_port.$l2clk); | |
| 931 | if (clkgen_l2d1_cmp_port.$l2clk) | |
| 932 | l2d1_cmp_l2clk_pedge = get_time(LO); | |
| 933 | else | |
| 934 | l2d1_cmp_l2clk_nedge = get_time(LO); | |
| 935 | } | |
| 936 | } | |
| 937 | { | |
| 938 | while (1) { | |
| 939 | @(posedge clkgen_l2d2_cmp_port.$tcu_clk_stop__gclk); | |
| 940 | l2d2_cmp_clkstp_pedge_t = get_time(LO); | |
| 941 | l2d2_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 942 | l2d2_cmp_clkstp_pedge_cnt++; | |
| 943 | } | |
| 944 | } | |
| 945 | { | |
| 946 | while (1) { | |
| 947 | @(negedge clkgen_l2d2_cmp_port.$tcu_clk_stop__gclk); | |
| 948 | l2d2_cmp_clkstp_nedge_t = get_time(LO); | |
| 949 | l2d2_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 950 | l2d2_cmp_clkstp_nedge_cnt++; | |
| 951 | } | |
| 952 | } | |
| 953 | { | |
| 954 | while (1) { | |
| 955 | @(clkgen_l2d2_cmp_port.$l2clk); | |
| 956 | if (clkgen_l2d2_cmp_port.$l2clk) | |
| 957 | l2d2_cmp_l2clk_pedge = get_time(LO); | |
| 958 | else | |
| 959 | l2d2_cmp_l2clk_nedge = get_time(LO); | |
| 960 | } | |
| 961 | } | |
| 962 | { | |
| 963 | while (1) { | |
| 964 | @(posedge clkgen_l2d3_cmp_port.$tcu_clk_stop__gclk); | |
| 965 | l2d3_cmp_clkstp_pedge_t = get_time(LO); | |
| 966 | l2d3_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 967 | l2d3_cmp_clkstp_pedge_cnt++; | |
| 968 | } | |
| 969 | } | |
| 970 | { | |
| 971 | while (1) { | |
| 972 | @(negedge clkgen_l2d3_cmp_port.$tcu_clk_stop__gclk); | |
| 973 | l2d3_cmp_clkstp_nedge_t = get_time(LO); | |
| 974 | l2d3_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 975 | l2d3_cmp_clkstp_nedge_cnt++; | |
| 976 | } | |
| 977 | } | |
| 978 | { | |
| 979 | while (1) { | |
| 980 | @(clkgen_l2d3_cmp_port.$l2clk); | |
| 981 | if (clkgen_l2d3_cmp_port.$l2clk) | |
| 982 | l2d3_cmp_l2clk_pedge = get_time(LO); | |
| 983 | else | |
| 984 | l2d3_cmp_l2clk_nedge = get_time(LO); | |
| 985 | } | |
| 986 | } | |
| 987 | { | |
| 988 | while (1) { | |
| 989 | @(posedge clkgen_l2d4_cmp_port.$tcu_clk_stop__gclk); | |
| 990 | l2d4_cmp_clkstp_pedge_t = get_time(LO); | |
| 991 | l2d4_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 992 | l2d4_cmp_clkstp_pedge_cnt++; | |
| 993 | } | |
| 994 | } | |
| 995 | { | |
| 996 | while (1) { | |
| 997 | @(negedge clkgen_l2d4_cmp_port.$tcu_clk_stop__gclk); | |
| 998 | l2d4_cmp_clkstp_nedge_t = get_time(LO); | |
| 999 | l2d4_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1000 | l2d4_cmp_clkstp_nedge_cnt++; | |
| 1001 | } | |
| 1002 | } | |
| 1003 | { | |
| 1004 | while (1) { | |
| 1005 | @(clkgen_l2d4_cmp_port.$l2clk); | |
| 1006 | if (clkgen_l2d4_cmp_port.$l2clk) | |
| 1007 | l2d4_cmp_l2clk_pedge = get_time(LO); | |
| 1008 | else | |
| 1009 | l2d4_cmp_l2clk_nedge = get_time(LO); | |
| 1010 | } | |
| 1011 | } | |
| 1012 | { | |
| 1013 | while (1) { | |
| 1014 | @(posedge clkgen_l2d5_cmp_port.$tcu_clk_stop__gclk); | |
| 1015 | l2d5_cmp_clkstp_pedge_t = get_time(LO); | |
| 1016 | l2d5_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1017 | l2d5_cmp_clkstp_pedge_cnt++; | |
| 1018 | } | |
| 1019 | } | |
| 1020 | { | |
| 1021 | while (1) { | |
| 1022 | @(negedge clkgen_l2d5_cmp_port.$tcu_clk_stop__gclk); | |
| 1023 | l2d5_cmp_clkstp_nedge_t = get_time(LO); | |
| 1024 | l2d5_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1025 | l2d5_cmp_clkstp_nedge_cnt++; | |
| 1026 | } | |
| 1027 | } | |
| 1028 | { | |
| 1029 | while (1) { | |
| 1030 | @(clkgen_l2d5_cmp_port.$l2clk); | |
| 1031 | if (clkgen_l2d5_cmp_port.$l2clk) | |
| 1032 | l2d5_cmp_l2clk_pedge = get_time(LO); | |
| 1033 | else | |
| 1034 | l2d5_cmp_l2clk_nedge = get_time(LO); | |
| 1035 | } | |
| 1036 | } | |
| 1037 | { | |
| 1038 | while (1) { | |
| 1039 | @(posedge clkgen_l2d6_cmp_port.$tcu_clk_stop__gclk); | |
| 1040 | l2d6_cmp_clkstp_pedge_t = get_time(LO); | |
| 1041 | l2d6_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1042 | l2d6_cmp_clkstp_pedge_cnt++; | |
| 1043 | } | |
| 1044 | } | |
| 1045 | { | |
| 1046 | while (1) { | |
| 1047 | @(negedge clkgen_l2d6_cmp_port.$tcu_clk_stop__gclk); | |
| 1048 | l2d6_cmp_clkstp_nedge_t = get_time(LO); | |
| 1049 | l2d6_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1050 | l2d6_cmp_clkstp_nedge_cnt++; | |
| 1051 | } | |
| 1052 | } | |
| 1053 | { | |
| 1054 | while (1) { | |
| 1055 | @(clkgen_l2d6_cmp_port.$l2clk); | |
| 1056 | if (clkgen_l2d6_cmp_port.$l2clk) | |
| 1057 | l2d6_cmp_l2clk_pedge = get_time(LO); | |
| 1058 | else | |
| 1059 | l2d6_cmp_l2clk_nedge = get_time(LO); | |
| 1060 | } | |
| 1061 | } | |
| 1062 | { | |
| 1063 | while (1) { | |
| 1064 | @(posedge clkgen_l2d7_cmp_port.$tcu_clk_stop__gclk); | |
| 1065 | l2d7_cmp_clkstp_pedge_t = get_time(LO); | |
| 1066 | l2d7_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1067 | l2d7_cmp_clkstp_pedge_cnt++; | |
| 1068 | } | |
| 1069 | } | |
| 1070 | { | |
| 1071 | while (1) { | |
| 1072 | @(negedge clkgen_l2d7_cmp_port.$tcu_clk_stop__gclk); | |
| 1073 | l2d7_cmp_clkstp_nedge_t = get_time(LO); | |
| 1074 | l2d7_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1075 | l2d7_cmp_clkstp_nedge_cnt++; | |
| 1076 | } | |
| 1077 | } | |
| 1078 | { | |
| 1079 | while (1) { | |
| 1080 | @(clkgen_l2d7_cmp_port.$l2clk); | |
| 1081 | if (clkgen_l2d7_cmp_port.$l2clk) | |
| 1082 | l2d7_cmp_l2clk_pedge = get_time(LO); | |
| 1083 | else | |
| 1084 | l2d7_cmp_l2clk_nedge = get_time(LO); | |
| 1085 | } | |
| 1086 | } | |
| 1087 | { | |
| 1088 | while (1) { | |
| 1089 | @(posedge clkgen_l2t0_cmp_port.$tcu_clk_stop__gclk); | |
| 1090 | l2t0_cmp_clkstp_pedge_t = get_time(LO); | |
| 1091 | l2t0_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1092 | l2t0_cmp_clkstp_pedge_cnt++; | |
| 1093 | } | |
| 1094 | } | |
| 1095 | { | |
| 1096 | while (1) { | |
| 1097 | @(negedge clkgen_l2t0_cmp_port.$tcu_clk_stop__gclk); | |
| 1098 | l2t0_cmp_clkstp_nedge_t = get_time(LO); | |
| 1099 | l2t0_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1100 | l2t0_cmp_clkstp_nedge_cnt++; | |
| 1101 | } | |
| 1102 | } | |
| 1103 | { | |
| 1104 | while (1) { | |
| 1105 | @(clkgen_l2t0_cmp_port.$l2clk); | |
| 1106 | if (clkgen_l2t0_cmp_port.$l2clk) | |
| 1107 | l2t0_cmp_l2clk_pedge = get_time(LO); | |
| 1108 | else | |
| 1109 | l2t0_cmp_l2clk_nedge = get_time(LO); | |
| 1110 | } | |
| 1111 | } | |
| 1112 | { | |
| 1113 | while (1) { | |
| 1114 | @(posedge clkgen_l2t1_cmp_port.$tcu_clk_stop__gclk); | |
| 1115 | l2t1_cmp_clkstp_pedge_t = get_time(LO); | |
| 1116 | l2t1_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1117 | l2t1_cmp_clkstp_pedge_cnt++; | |
| 1118 | } | |
| 1119 | } | |
| 1120 | { | |
| 1121 | while (1) { | |
| 1122 | @(negedge clkgen_l2t1_cmp_port.$tcu_clk_stop__gclk); | |
| 1123 | l2t1_cmp_clkstp_nedge_t = get_time(LO); | |
| 1124 | l2t1_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1125 | l2t1_cmp_clkstp_nedge_cnt++; | |
| 1126 | } | |
| 1127 | } | |
| 1128 | { | |
| 1129 | while (1) { | |
| 1130 | @(clkgen_l2t1_cmp_port.$l2clk); | |
| 1131 | if (clkgen_l2t1_cmp_port.$l2clk) | |
| 1132 | l2t1_cmp_l2clk_pedge = get_time(LO); | |
| 1133 | else | |
| 1134 | l2t1_cmp_l2clk_nedge = get_time(LO); | |
| 1135 | } | |
| 1136 | } | |
| 1137 | { | |
| 1138 | while (1) { | |
| 1139 | @(posedge clkgen_l2t2_cmp_port.$tcu_clk_stop__gclk); | |
| 1140 | l2t2_cmp_clkstp_pedge_t = get_time(LO); | |
| 1141 | l2t2_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1142 | l2t2_cmp_clkstp_pedge_cnt++; | |
| 1143 | } | |
| 1144 | } | |
| 1145 | { | |
| 1146 | while (1) { | |
| 1147 | @(negedge clkgen_l2t2_cmp_port.$tcu_clk_stop__gclk); | |
| 1148 | l2t2_cmp_clkstp_nedge_t = get_time(LO); | |
| 1149 | l2t2_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1150 | l2t2_cmp_clkstp_nedge_cnt++; | |
| 1151 | } | |
| 1152 | } | |
| 1153 | { | |
| 1154 | while (1) { | |
| 1155 | @(clkgen_l2t2_cmp_port.$l2clk); | |
| 1156 | if (clkgen_l2t2_cmp_port.$l2clk) | |
| 1157 | l2t2_cmp_l2clk_pedge = get_time(LO); | |
| 1158 | else | |
| 1159 | l2t2_cmp_l2clk_nedge = get_time(LO); | |
| 1160 | } | |
| 1161 | } | |
| 1162 | { | |
| 1163 | while (1) { | |
| 1164 | @(posedge clkgen_l2t3_cmp_port.$tcu_clk_stop__gclk); | |
| 1165 | l2t3_cmp_clkstp_pedge_t = get_time(LO); | |
| 1166 | l2t3_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1167 | l2t3_cmp_clkstp_pedge_cnt++; | |
| 1168 | } | |
| 1169 | } | |
| 1170 | { | |
| 1171 | while (1) { | |
| 1172 | @(negedge clkgen_l2t3_cmp_port.$tcu_clk_stop__gclk); | |
| 1173 | l2t3_cmp_clkstp_nedge_t = get_time(LO); | |
| 1174 | l2t3_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1175 | l2t3_cmp_clkstp_nedge_cnt++; | |
| 1176 | } | |
| 1177 | } | |
| 1178 | { | |
| 1179 | while (1) { | |
| 1180 | @(clkgen_l2t3_cmp_port.$l2clk); | |
| 1181 | if (clkgen_l2t3_cmp_port.$l2clk) | |
| 1182 | l2t3_cmp_l2clk_pedge = get_time(LO); | |
| 1183 | else | |
| 1184 | l2t3_cmp_l2clk_nedge = get_time(LO); | |
| 1185 | } | |
| 1186 | } | |
| 1187 | { | |
| 1188 | while (1) { | |
| 1189 | @(posedge clkgen_l2t4_cmp_port.$tcu_clk_stop__gclk); | |
| 1190 | l2t4_cmp_clkstp_pedge_t = get_time(LO); | |
| 1191 | l2t4_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1192 | l2t4_cmp_clkstp_pedge_cnt++; | |
| 1193 | } | |
| 1194 | } | |
| 1195 | { | |
| 1196 | while (1) { | |
| 1197 | @(negedge clkgen_l2t4_cmp_port.$tcu_clk_stop__gclk); | |
| 1198 | l2t4_cmp_clkstp_nedge_t = get_time(LO); | |
| 1199 | l2t4_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1200 | l2t4_cmp_clkstp_nedge_cnt++; | |
| 1201 | } | |
| 1202 | } | |
| 1203 | { | |
| 1204 | while (1) { | |
| 1205 | @(clkgen_l2t4_cmp_port.$l2clk); | |
| 1206 | if (clkgen_l2t4_cmp_port.$l2clk) | |
| 1207 | l2t4_cmp_l2clk_pedge = get_time(LO); | |
| 1208 | else | |
| 1209 | l2t4_cmp_l2clk_nedge = get_time(LO); | |
| 1210 | } | |
| 1211 | } | |
| 1212 | { | |
| 1213 | while (1) { | |
| 1214 | @(posedge clkgen_l2t5_cmp_port.$tcu_clk_stop__gclk); | |
| 1215 | l2t5_cmp_clkstp_pedge_t = get_time(LO); | |
| 1216 | l2t5_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1217 | l2t5_cmp_clkstp_pedge_cnt++; | |
| 1218 | } | |
| 1219 | } | |
| 1220 | { | |
| 1221 | while (1) { | |
| 1222 | @(negedge clkgen_l2t5_cmp_port.$tcu_clk_stop__gclk); | |
| 1223 | l2t5_cmp_clkstp_nedge_t = get_time(LO); | |
| 1224 | l2t5_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1225 | l2t5_cmp_clkstp_nedge_cnt++; | |
| 1226 | } | |
| 1227 | } | |
| 1228 | { | |
| 1229 | while (1) { | |
| 1230 | @(clkgen_l2t5_cmp_port.$l2clk); | |
| 1231 | if (clkgen_l2t5_cmp_port.$l2clk) | |
| 1232 | l2t5_cmp_l2clk_pedge = get_time(LO); | |
| 1233 | else | |
| 1234 | l2t5_cmp_l2clk_nedge = get_time(LO); | |
| 1235 | } | |
| 1236 | } | |
| 1237 | { | |
| 1238 | while (1) { | |
| 1239 | @(posedge clkgen_l2t6_cmp_port.$tcu_clk_stop__gclk); | |
| 1240 | l2t6_cmp_clkstp_pedge_t = get_time(LO); | |
| 1241 | l2t6_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1242 | l2t6_cmp_clkstp_pedge_cnt++; | |
| 1243 | } | |
| 1244 | } | |
| 1245 | { | |
| 1246 | while (1) { | |
| 1247 | @(negedge clkgen_l2t6_cmp_port.$tcu_clk_stop__gclk); | |
| 1248 | l2t6_cmp_clkstp_nedge_t = get_time(LO); | |
| 1249 | l2t6_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1250 | l2t6_cmp_clkstp_nedge_cnt++; | |
| 1251 | } | |
| 1252 | } | |
| 1253 | { | |
| 1254 | while (1) { | |
| 1255 | @(clkgen_l2t6_cmp_port.$l2clk); | |
| 1256 | if (clkgen_l2t6_cmp_port.$l2clk) | |
| 1257 | l2t6_cmp_l2clk_pedge = get_time(LO); | |
| 1258 | else | |
| 1259 | l2t6_cmp_l2clk_nedge = get_time(LO); | |
| 1260 | } | |
| 1261 | } | |
| 1262 | { | |
| 1263 | while (1) { | |
| 1264 | @(posedge clkgen_l2t7_cmp_port.$tcu_clk_stop__gclk); | |
| 1265 | l2t7_cmp_clkstp_pedge_t = get_time(LO); | |
| 1266 | l2t7_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1267 | l2t7_cmp_clkstp_pedge_cnt++; | |
| 1268 | } | |
| 1269 | } | |
| 1270 | { | |
| 1271 | while (1) { | |
| 1272 | @(negedge clkgen_l2t7_cmp_port.$tcu_clk_stop__gclk); | |
| 1273 | l2t7_cmp_clkstp_nedge_t = get_time(LO); | |
| 1274 | l2t7_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1275 | l2t7_cmp_clkstp_nedge_cnt++; | |
| 1276 | } | |
| 1277 | } | |
| 1278 | { | |
| 1279 | while (1) { | |
| 1280 | @(clkgen_l2t7_cmp_port.$l2clk); | |
| 1281 | if (clkgen_l2t7_cmp_port.$l2clk) | |
| 1282 | l2t7_cmp_l2clk_pedge = get_time(LO); | |
| 1283 | else | |
| 1284 | l2t7_cmp_l2clk_nedge = get_time(LO); | |
| 1285 | } | |
| 1286 | } | |
| 1287 | #ifndef FC_NO_NIU_T2 | |
| 1288 | #ifndef NIU_SYSTEMC_T2 | |
| 1289 | { | |
| 1290 | while (1) { | |
| 1291 | @(posedge clkgen_mac_io_port.$tcu_clk_stop__gclk); | |
| 1292 | mac_io_clkstp_pedge_t = get_time(LO); | |
| 1293 | mac_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1294 | mac_io_clkstp_pedge_cnt++; | |
| 1295 | } | |
| 1296 | } | |
| 1297 | { | |
| 1298 | while (1) { | |
| 1299 | @(negedge clkgen_mac_io_port.$tcu_clk_stop__gclk); | |
| 1300 | mac_io_clkstp_nedge_t = get_time(LO); | |
| 1301 | mac_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1302 | mac_io_clkstp_nedge_cnt++; | |
| 1303 | } | |
| 1304 | } | |
| 1305 | { | |
| 1306 | while (1) { | |
| 1307 | @(clkgen_mac_io_port.$l2clk); | |
| 1308 | if (clkgen_mac_io_port.$l2clk) | |
| 1309 | mac_io_l2clk_pedge = get_time(LO); | |
| 1310 | else | |
| 1311 | mac_io_l2clk_nedge = get_time(LO); | |
| 1312 | } | |
| 1313 | } | |
| 1314 | #endif | |
| 1315 | #endif | |
| 1316 | { | |
| 1317 | while (1) { | |
| 1318 | @(posedge clkgen_mcu0_cmp_port.$tcu_clk_stop__gclk); | |
| 1319 | mcu0_cmp_clkstp_pedge_t = get_time(LO); | |
| 1320 | mcu0_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1321 | mcu0_cmp_clkstp_pedge_cnt++; | |
| 1322 | } | |
| 1323 | } | |
| 1324 | { | |
| 1325 | while (1) { | |
| 1326 | @(negedge clkgen_mcu0_cmp_port.$tcu_clk_stop__gclk); | |
| 1327 | mcu0_cmp_clkstp_nedge_t = get_time(LO); | |
| 1328 | mcu0_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1329 | mcu0_cmp_clkstp_nedge_cnt++; | |
| 1330 | } | |
| 1331 | } | |
| 1332 | { | |
| 1333 | while (1) { | |
| 1334 | @(clkgen_mcu0_cmp_port.$l2clk); | |
| 1335 | if (clkgen_mcu0_cmp_port.$l2clk) | |
| 1336 | mcu0_cmp_l2clk_pedge = get_time(LO); | |
| 1337 | else | |
| 1338 | mcu0_cmp_l2clk_nedge = get_time(LO); | |
| 1339 | } | |
| 1340 | } | |
| 1341 | { | |
| 1342 | while (1) { | |
| 1343 | @(posedge clkgen_mcu0_dr_port.$tcu_clk_stop__gclk); | |
| 1344 | mcu0_dr_clkstp_pedge_t = get_time(LO); | |
| 1345 | mcu0_dr_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1346 | mcu0_dr_clkstp_pedge_cnt++; | |
| 1347 | } | |
| 1348 | } | |
| 1349 | { | |
| 1350 | while (1) { | |
| 1351 | @(negedge clkgen_mcu0_dr_port.$tcu_clk_stop__gclk); | |
| 1352 | mcu0_dr_clkstp_nedge_t = get_time(LO); | |
| 1353 | mcu0_dr_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1354 | mcu0_dr_clkstp_nedge_cnt++; | |
| 1355 | } | |
| 1356 | } | |
| 1357 | { | |
| 1358 | while (1) { | |
| 1359 | @(clkgen_mcu0_dr_port.$l2clk); | |
| 1360 | if (clkgen_mcu0_dr_port.$l2clk) | |
| 1361 | mcu0_dr_l2clk_pedge = get_time(LO); | |
| 1362 | else | |
| 1363 | mcu0_dr_l2clk_nedge = get_time(LO); | |
| 1364 | } | |
| 1365 | } | |
| 1366 | { | |
| 1367 | while (1) { | |
| 1368 | @(posedge clkgen_mcu0_io_port.$tcu_clk_stop__gclk); | |
| 1369 | mcu0_io_clkstp_pedge_t = get_time(LO); | |
| 1370 | mcu0_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1371 | mcu0_io_clkstp_pedge_cnt++; | |
| 1372 | } | |
| 1373 | } | |
| 1374 | { | |
| 1375 | while (1) { | |
| 1376 | @(negedge clkgen_mcu0_io_port.$tcu_clk_stop__gclk); | |
| 1377 | mcu0_io_clkstp_nedge_t = get_time(LO); | |
| 1378 | mcu0_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1379 | mcu0_io_clkstp_nedge_cnt++; | |
| 1380 | } | |
| 1381 | } | |
| 1382 | { | |
| 1383 | while (1) { | |
| 1384 | @(clkgen_mcu0_io_port.$l2clk); | |
| 1385 | if (clkgen_mcu0_io_port.$l2clk) | |
| 1386 | mcu0_io_l2clk_pedge = get_time(LO); | |
| 1387 | else | |
| 1388 | mcu0_io_l2clk_nedge = get_time(LO); | |
| 1389 | } | |
| 1390 | } | |
| 1391 | { | |
| 1392 | while (1) { | |
| 1393 | @(posedge clkgen_mcu1_cmp_port.$tcu_clk_stop__gclk); | |
| 1394 | mcu1_cmp_clkstp_pedge_t = get_time(LO); | |
| 1395 | mcu1_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1396 | mcu1_cmp_clkstp_pedge_cnt++; | |
| 1397 | } | |
| 1398 | } | |
| 1399 | { | |
| 1400 | while (1) { | |
| 1401 | @(negedge clkgen_mcu1_cmp_port.$tcu_clk_stop__gclk); | |
| 1402 | mcu1_cmp_clkstp_nedge_t = get_time(LO); | |
| 1403 | mcu1_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1404 | mcu1_cmp_clkstp_nedge_cnt++; | |
| 1405 | } | |
| 1406 | } | |
| 1407 | { | |
| 1408 | while (1) { | |
| 1409 | @(clkgen_mcu1_cmp_port.$l2clk); | |
| 1410 | if (clkgen_mcu1_cmp_port.$l2clk) | |
| 1411 | mcu1_cmp_l2clk_pedge = get_time(LO); | |
| 1412 | else | |
| 1413 | mcu1_cmp_l2clk_nedge = get_time(LO); | |
| 1414 | } | |
| 1415 | } | |
| 1416 | { | |
| 1417 | while (1) { | |
| 1418 | @(posedge clkgen_mcu1_dr_port.$tcu_clk_stop__gclk); | |
| 1419 | mcu1_dr_clkstp_pedge_t = get_time(LO); | |
| 1420 | mcu1_dr_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1421 | mcu1_dr_clkstp_pedge_cnt++; | |
| 1422 | } | |
| 1423 | } | |
| 1424 | { | |
| 1425 | while (1) { | |
| 1426 | @(negedge clkgen_mcu1_dr_port.$tcu_clk_stop__gclk); | |
| 1427 | mcu1_dr_clkstp_nedge_t = get_time(LO); | |
| 1428 | mcu1_dr_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1429 | mcu1_dr_clkstp_nedge_cnt++; | |
| 1430 | } | |
| 1431 | } | |
| 1432 | { | |
| 1433 | while (1) { | |
| 1434 | @(clkgen_mcu1_dr_port.$l2clk); | |
| 1435 | if (clkgen_mcu1_dr_port.$l2clk) | |
| 1436 | mcu1_dr_l2clk_pedge = get_time(LO); | |
| 1437 | else | |
| 1438 | mcu1_dr_l2clk_nedge = get_time(LO); | |
| 1439 | } | |
| 1440 | } | |
| 1441 | { | |
| 1442 | while (1) { | |
| 1443 | @(posedge clkgen_mcu1_io_port.$tcu_clk_stop__gclk); | |
| 1444 | mcu1_io_clkstp_pedge_t = get_time(LO); | |
| 1445 | mcu1_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1446 | mcu1_io_clkstp_pedge_cnt++; | |
| 1447 | } | |
| 1448 | } | |
| 1449 | { | |
| 1450 | while (1) { | |
| 1451 | @(negedge clkgen_mcu1_io_port.$tcu_clk_stop__gclk); | |
| 1452 | mcu1_io_clkstp_nedge_t = get_time(LO); | |
| 1453 | mcu1_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1454 | mcu1_io_clkstp_nedge_cnt++; | |
| 1455 | } | |
| 1456 | } | |
| 1457 | { | |
| 1458 | while (1) { | |
| 1459 | @(clkgen_mcu1_io_port.$l2clk); | |
| 1460 | if (clkgen_mcu1_io_port.$l2clk) | |
| 1461 | mcu1_io_l2clk_pedge = get_time(LO); | |
| 1462 | else | |
| 1463 | mcu1_io_l2clk_nedge = get_time(LO); | |
| 1464 | } | |
| 1465 | } | |
| 1466 | { | |
| 1467 | while (1) { | |
| 1468 | @(posedge clkgen_mcu2_cmp_port.$tcu_clk_stop__gclk); | |
| 1469 | mcu2_cmp_clkstp_pedge_t = get_time(LO); | |
| 1470 | mcu2_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1471 | mcu2_cmp_clkstp_pedge_cnt++; | |
| 1472 | } | |
| 1473 | } | |
| 1474 | { | |
| 1475 | while (1) { | |
| 1476 | @(negedge clkgen_mcu2_cmp_port.$tcu_clk_stop__gclk); | |
| 1477 | mcu2_cmp_clkstp_nedge_t = get_time(LO); | |
| 1478 | mcu2_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1479 | mcu2_cmp_clkstp_nedge_cnt++; | |
| 1480 | } | |
| 1481 | } | |
| 1482 | { | |
| 1483 | while (1) { | |
| 1484 | @(clkgen_mcu2_cmp_port.$l2clk); | |
| 1485 | if (clkgen_mcu2_cmp_port.$l2clk) | |
| 1486 | mcu2_cmp_l2clk_pedge = get_time(LO); | |
| 1487 | else | |
| 1488 | mcu2_cmp_l2clk_nedge = get_time(LO); | |
| 1489 | } | |
| 1490 | } | |
| 1491 | { | |
| 1492 | while (1) { | |
| 1493 | @(posedge clkgen_mcu2_dr_port.$tcu_clk_stop__gclk); | |
| 1494 | mcu2_dr_clkstp_pedge_t = get_time(LO); | |
| 1495 | mcu2_dr_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1496 | mcu2_dr_clkstp_pedge_cnt++; | |
| 1497 | } | |
| 1498 | } | |
| 1499 | { | |
| 1500 | while (1) { | |
| 1501 | @(negedge clkgen_mcu2_dr_port.$tcu_clk_stop__gclk); | |
| 1502 | mcu2_dr_clkstp_nedge_t = get_time(LO); | |
| 1503 | mcu2_dr_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1504 | mcu2_dr_clkstp_nedge_cnt++; | |
| 1505 | } | |
| 1506 | } | |
| 1507 | { | |
| 1508 | while (1) { | |
| 1509 | @(clkgen_mcu2_dr_port.$l2clk); | |
| 1510 | if (clkgen_mcu2_dr_port.$l2clk) | |
| 1511 | mcu2_dr_l2clk_pedge = get_time(LO); | |
| 1512 | else | |
| 1513 | mcu2_dr_l2clk_nedge = get_time(LO); | |
| 1514 | } | |
| 1515 | } | |
| 1516 | { | |
| 1517 | while (1) { | |
| 1518 | @(posedge clkgen_mcu2_io_port.$tcu_clk_stop__gclk); | |
| 1519 | mcu2_io_clkstp_pedge_t = get_time(LO); | |
| 1520 | mcu2_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1521 | mcu2_io_clkstp_pedge_cnt++; | |
| 1522 | } | |
| 1523 | } | |
| 1524 | { | |
| 1525 | while (1) { | |
| 1526 | @(negedge clkgen_mcu2_io_port.$tcu_clk_stop__gclk); | |
| 1527 | mcu2_io_clkstp_nedge_t = get_time(LO); | |
| 1528 | mcu2_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1529 | mcu2_io_clkstp_nedge_cnt++; | |
| 1530 | } | |
| 1531 | } | |
| 1532 | { | |
| 1533 | while (1) { | |
| 1534 | @(clkgen_mcu2_io_port.$l2clk); | |
| 1535 | if (clkgen_mcu2_io_port.$l2clk) | |
| 1536 | mcu2_io_l2clk_pedge = get_time(LO); | |
| 1537 | else | |
| 1538 | mcu2_io_l2clk_nedge = get_time(LO); | |
| 1539 | } | |
| 1540 | } | |
| 1541 | { | |
| 1542 | while (1) { | |
| 1543 | @(posedge clkgen_mcu3_cmp_port.$tcu_clk_stop__gclk); | |
| 1544 | mcu3_cmp_clkstp_pedge_t = get_time(LO); | |
| 1545 | mcu3_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1546 | mcu3_cmp_clkstp_pedge_cnt++; | |
| 1547 | } | |
| 1548 | } | |
| 1549 | { | |
| 1550 | while (1) { | |
| 1551 | @(negedge clkgen_mcu3_cmp_port.$tcu_clk_stop__gclk); | |
| 1552 | mcu3_cmp_clkstp_nedge_t = get_time(LO); | |
| 1553 | mcu3_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1554 | mcu3_cmp_clkstp_nedge_cnt++; | |
| 1555 | } | |
| 1556 | } | |
| 1557 | { | |
| 1558 | while (1) { | |
| 1559 | @(clkgen_mcu3_cmp_port.$l2clk); | |
| 1560 | if (clkgen_mcu3_cmp_port.$l2clk) | |
| 1561 | mcu3_cmp_l2clk_pedge = get_time(LO); | |
| 1562 | else | |
| 1563 | mcu3_cmp_l2clk_nedge = get_time(LO); | |
| 1564 | } | |
| 1565 | } | |
| 1566 | { | |
| 1567 | while (1) { | |
| 1568 | @(posedge clkgen_mcu3_dr_port.$tcu_clk_stop__gclk); | |
| 1569 | mcu3_dr_clkstp_pedge_t = get_time(LO); | |
| 1570 | mcu3_dr_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1571 | mcu3_dr_clkstp_pedge_cnt++; | |
| 1572 | } | |
| 1573 | } | |
| 1574 | { | |
| 1575 | while (1) { | |
| 1576 | @(negedge clkgen_mcu3_dr_port.$tcu_clk_stop__gclk); | |
| 1577 | mcu3_dr_clkstp_nedge_t = get_time(LO); | |
| 1578 | mcu3_dr_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1579 | mcu3_dr_clkstp_nedge_cnt++; | |
| 1580 | } | |
| 1581 | } | |
| 1582 | { | |
| 1583 | while (1) { | |
| 1584 | @(clkgen_mcu3_dr_port.$l2clk); | |
| 1585 | if (clkgen_mcu3_dr_port.$l2clk) | |
| 1586 | mcu3_dr_l2clk_pedge = get_time(LO); | |
| 1587 | else | |
| 1588 | mcu3_dr_l2clk_nedge = get_time(LO); | |
| 1589 | } | |
| 1590 | } | |
| 1591 | { | |
| 1592 | while (1) { | |
| 1593 | @(posedge clkgen_mcu3_io_port.$tcu_clk_stop__gclk); | |
| 1594 | mcu3_io_clkstp_pedge_t = get_time(LO); | |
| 1595 | mcu3_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1596 | mcu3_io_clkstp_pedge_cnt++; | |
| 1597 | } | |
| 1598 | } | |
| 1599 | { | |
| 1600 | while (1) { | |
| 1601 | @(negedge clkgen_mcu3_io_port.$tcu_clk_stop__gclk); | |
| 1602 | mcu3_io_clkstp_nedge_t = get_time(LO); | |
| 1603 | mcu3_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1604 | mcu3_io_clkstp_nedge_cnt++; | |
| 1605 | } | |
| 1606 | } | |
| 1607 | { | |
| 1608 | while (1) { | |
| 1609 | @(clkgen_mcu3_io_port.$l2clk); | |
| 1610 | if (clkgen_mcu3_io_port.$l2clk) | |
| 1611 | mcu3_io_l2clk_pedge = get_time(LO); | |
| 1612 | else | |
| 1613 | mcu3_io_l2clk_nedge = get_time(LO); | |
| 1614 | } | |
| 1615 | } | |
| 1616 | { | |
| 1617 | while (1) { | |
| 1618 | @(posedge clkgen_mio_0_cmp_port.$tcu_clk_stop__gclk); | |
| 1619 | mio_0_cmp_clkstp_pedge_t = get_time(LO); | |
| 1620 | mio_0_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1621 | mio_0_cmp_clkstp_pedge_cnt++; | |
| 1622 | } | |
| 1623 | } | |
| 1624 | { | |
| 1625 | while (1) { | |
| 1626 | @(negedge clkgen_mio_0_cmp_port.$tcu_clk_stop__gclk); | |
| 1627 | mio_0_cmp_clkstp_nedge_t = get_time(LO); | |
| 1628 | mio_0_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1629 | mio_0_cmp_clkstp_nedge_cnt++; | |
| 1630 | } | |
| 1631 | } | |
| 1632 | { | |
| 1633 | while (1) { | |
| 1634 | @(clkgen_mio_0_cmp_port.$l2clk); | |
| 1635 | if (clkgen_mio_0_cmp_port.$l2clk) | |
| 1636 | mio_0_cmp_l2clk_pedge = get_time(LO); | |
| 1637 | else | |
| 1638 | mio_0_cmp_l2clk_nedge = get_time(LO); | |
| 1639 | } | |
| 1640 | } | |
| 1641 | { | |
| 1642 | while (1) { | |
| 1643 | @(posedge clkgen_mio_1_cmp_port.$tcu_clk_stop__gclk); | |
| 1644 | mio_1_cmp_clkstp_pedge_t = get_time(LO); | |
| 1645 | mio_1_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1646 | mio_1_cmp_clkstp_pedge_cnt++; | |
| 1647 | } | |
| 1648 | } | |
| 1649 | { | |
| 1650 | while (1) { | |
| 1651 | @(negedge clkgen_mio_1_cmp_port.$tcu_clk_stop__gclk); | |
| 1652 | mio_1_cmp_clkstp_nedge_t = get_time(LO); | |
| 1653 | mio_1_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1654 | mio_1_cmp_clkstp_nedge_cnt++; | |
| 1655 | } | |
| 1656 | } | |
| 1657 | { | |
| 1658 | while (1) { | |
| 1659 | @(clkgen_mio_1_cmp_port.$l2clk); | |
| 1660 | if (clkgen_mio_1_cmp_port.$l2clk) | |
| 1661 | mio_1_cmp_l2clk_pedge = get_time(LO); | |
| 1662 | else | |
| 1663 | mio_1_cmp_l2clk_nedge = get_time(LO); | |
| 1664 | } | |
| 1665 | } | |
| 1666 | { | |
| 1667 | while (1) { | |
| 1668 | @(posedge clkgen_mio_2_cmp_port.$tcu_clk_stop__gclk); | |
| 1669 | mio_2_cmp_clkstp_pedge_t = get_time(LO); | |
| 1670 | mio_2_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1671 | mio_2_cmp_clkstp_pedge_cnt++; | |
| 1672 | } | |
| 1673 | } | |
| 1674 | { | |
| 1675 | while (1) { | |
| 1676 | @(negedge clkgen_mio_2_cmp_port.$tcu_clk_stop__gclk); | |
| 1677 | mio_2_cmp_clkstp_nedge_t = get_time(LO); | |
| 1678 | mio_2_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1679 | mio_2_cmp_clkstp_nedge_cnt++; | |
| 1680 | } | |
| 1681 | } | |
| 1682 | { | |
| 1683 | while (1) { | |
| 1684 | @(clkgen_mio_2_cmp_port.$l2clk); | |
| 1685 | if (clkgen_mio_2_cmp_port.$l2clk) | |
| 1686 | mio_2_cmp_l2clk_pedge = get_time(LO); | |
| 1687 | else | |
| 1688 | mio_2_cmp_l2clk_nedge = get_time(LO); | |
| 1689 | } | |
| 1690 | } | |
| 1691 | { | |
| 1692 | while (1) { | |
| 1693 | @(posedge clkgen_mio_3_cmp_port.$tcu_clk_stop__gclk); | |
| 1694 | mio_3_cmp_clkstp_pedge_t = get_time(LO); | |
| 1695 | mio_3_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1696 | mio_3_cmp_clkstp_pedge_cnt++; | |
| 1697 | } | |
| 1698 | } | |
| 1699 | { | |
| 1700 | while (1) { | |
| 1701 | @(negedge clkgen_mio_3_cmp_port.$tcu_clk_stop__gclk); | |
| 1702 | mio_3_cmp_clkstp_nedge_t = get_time(LO); | |
| 1703 | mio_3_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1704 | mio_3_cmp_clkstp_nedge_cnt++; | |
| 1705 | } | |
| 1706 | } | |
| 1707 | { | |
| 1708 | while (1) { | |
| 1709 | @(clkgen_mio_3_cmp_port.$l2clk); | |
| 1710 | if (clkgen_mio_3_cmp_port.$l2clk) | |
| 1711 | mio_3_cmp_l2clk_pedge = get_time(LO); | |
| 1712 | else | |
| 1713 | mio_3_cmp_l2clk_nedge = get_time(LO); | |
| 1714 | } | |
| 1715 | } | |
| 1716 | { | |
| 1717 | while (1) { | |
| 1718 | @(posedge clkgen_mio_io_port.$tcu_clk_stop__gclk); | |
| 1719 | mio_io_clkstp_pedge_t = get_time(LO); | |
| 1720 | mio_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1721 | mio_io_clkstp_pedge_cnt++; | |
| 1722 | } | |
| 1723 | } | |
| 1724 | { | |
| 1725 | while (1) { | |
| 1726 | @(negedge clkgen_mio_io_port.$tcu_clk_stop__gclk); | |
| 1727 | mio_io_clkstp_nedge_t = get_time(LO); | |
| 1728 | mio_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1729 | mio_io_clkstp_nedge_cnt++; | |
| 1730 | } | |
| 1731 | } | |
| 1732 | { | |
| 1733 | while (1) { | |
| 1734 | @(clkgen_mio_io_port.$l2clk); | |
| 1735 | if (clkgen_mio_io_port.$l2clk) | |
| 1736 | mio_io_l2clk_pedge = get_time(LO); | |
| 1737 | else | |
| 1738 | mio_io_l2clk_nedge = get_time(LO); | |
| 1739 | } | |
| 1740 | } | |
| 1741 | { | |
| 1742 | while (1) { | |
| 1743 | @(posedge clkgen_ncu_cmp_port.$tcu_clk_stop__gclk); | |
| 1744 | ncu_cmp_clkstp_pedge_t = get_time(LO); | |
| 1745 | ncu_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1746 | ncu_cmp_clkstp_pedge_cnt++; | |
| 1747 | } | |
| 1748 | } | |
| 1749 | { | |
| 1750 | while (1) { | |
| 1751 | @(negedge clkgen_ncu_cmp_port.$tcu_clk_stop__gclk); | |
| 1752 | ncu_cmp_clkstp_nedge_t = get_time(LO); | |
| 1753 | ncu_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1754 | ncu_cmp_clkstp_nedge_cnt++; | |
| 1755 | } | |
| 1756 | } | |
| 1757 | { | |
| 1758 | while (1) { | |
| 1759 | @(clkgen_ncu_cmp_port.$l2clk); | |
| 1760 | if (clkgen_ncu_cmp_port.$l2clk) | |
| 1761 | ncu_cmp_l2clk_pedge = get_time(LO); | |
| 1762 | else | |
| 1763 | ncu_cmp_l2clk_nedge = get_time(LO); | |
| 1764 | } | |
| 1765 | } | |
| 1766 | { | |
| 1767 | while (1) { | |
| 1768 | @(posedge clkgen_ncu_io_port.$tcu_clk_stop__gclk); | |
| 1769 | ncu_io_clkstp_pedge_t = get_time(LO); | |
| 1770 | ncu_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1771 | ncu_io_clkstp_pedge_cnt++; | |
| 1772 | } | |
| 1773 | } | |
| 1774 | { | |
| 1775 | while (1) { | |
| 1776 | @(negedge clkgen_ncu_io_port.$tcu_clk_stop__gclk); | |
| 1777 | ncu_io_clkstp_nedge_t = get_time(LO); | |
| 1778 | ncu_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1779 | ncu_io_clkstp_nedge_cnt++; | |
| 1780 | } | |
| 1781 | } | |
| 1782 | { | |
| 1783 | while (1) { | |
| 1784 | @(clkgen_ncu_io_port.$l2clk); | |
| 1785 | if (clkgen_ncu_io_port.$l2clk) | |
| 1786 | ncu_io_l2clk_pedge = get_time(LO); | |
| 1787 | else | |
| 1788 | ncu_io_l2clk_nedge = get_time(LO); | |
| 1789 | } | |
| 1790 | } | |
| 1791 | #ifndef FC_NO_PEU_VERA | |
| 1792 | #ifndef PEU_SYSTEMC_T2 | |
| 1793 | { | |
| 1794 | while (1) { | |
| 1795 | @(posedge clkgen_peu_io_port.$tcu_clk_stop__gclk); | |
| 1796 | peu_io_clkstp_pedge_t = get_time(LO); | |
| 1797 | peu_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1798 | peu_io_clkstp_pedge_cnt++; | |
| 1799 | } | |
| 1800 | } | |
| 1801 | { | |
| 1802 | while (1) { | |
| 1803 | @(negedge clkgen_peu_io_port.$tcu_clk_stop__gclk); | |
| 1804 | peu_io_clkstp_nedge_t = get_time(LO); | |
| 1805 | peu_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1806 | peu_io_clkstp_nedge_cnt++; | |
| 1807 | } | |
| 1808 | } | |
| 1809 | { | |
| 1810 | while (1) { | |
| 1811 | @(clkgen_peu_io_port.$l2clk); | |
| 1812 | if (clkgen_peu_io_port.$l2clk) | |
| 1813 | peu_io_l2clk_pedge = get_time(LO); | |
| 1814 | else | |
| 1815 | peu_io_l2clk_nedge = get_time(LO); | |
| 1816 | } | |
| 1817 | } | |
| 1818 | { | |
| 1819 | while (1) { | |
| 1820 | @(posedge clkgen_peu_pc_port.$tcu_clk_stop__gclk); | |
| 1821 | peu_pc_clkstp_pedge_t = get_time(LO); | |
| 1822 | peu_pc_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1823 | peu_pc_clkstp_pedge_cnt++; | |
| 1824 | } | |
| 1825 | } | |
| 1826 | { | |
| 1827 | while (1) { | |
| 1828 | @(negedge clkgen_peu_pc_port.$tcu_clk_stop__gclk); | |
| 1829 | peu_pc_clkstp_nedge_t = get_time(LO); | |
| 1830 | peu_pc_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1831 | peu_pc_clkstp_nedge_cnt++; | |
| 1832 | } | |
| 1833 | } | |
| 1834 | { | |
| 1835 | while (1) { | |
| 1836 | @(clkgen_peu_pc_port.$l2clk); | |
| 1837 | if (clkgen_peu_pc_port.$l2clk) | |
| 1838 | peu_pc_l2clk_pedge = get_time(LO); | |
| 1839 | else | |
| 1840 | peu_pc_l2clk_nedge = get_time(LO); | |
| 1841 | } | |
| 1842 | } | |
| 1843 | #endif | |
| 1844 | #endif | |
| 1845 | #ifndef FC_NO_NIU_T2 | |
| 1846 | #ifndef NIU_SYSTEMC_T2 | |
| 1847 | { | |
| 1848 | while (1) { | |
| 1849 | @(posedge clkgen_rdp_io2x_port.$tcu_clk_stop__gclk); | |
| 1850 | rdp_io2x_clkstp_pedge_t = get_time(LO); | |
| 1851 | rdp_io2x_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1852 | rdp_io2x_clkstp_pedge_cnt++; | |
| 1853 | } | |
| 1854 | } | |
| 1855 | { | |
| 1856 | while (1) { | |
| 1857 | @(negedge clkgen_rdp_io2x_port.$tcu_clk_stop__gclk); | |
| 1858 | rdp_io2x_clkstp_nedge_t = get_time(LO); | |
| 1859 | rdp_io2x_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1860 | rdp_io2x_clkstp_nedge_cnt++; | |
| 1861 | } | |
| 1862 | } | |
| 1863 | { | |
| 1864 | while (1) { | |
| 1865 | @(clkgen_rdp_io2x_port.$l2clk); | |
| 1866 | if (clkgen_rdp_io2x_port.$l2clk) | |
| 1867 | rdp_io2x_l2clk_pedge = get_time(LO); | |
| 1868 | else | |
| 1869 | rdp_io2x_l2clk_nedge = get_time(LO); | |
| 1870 | } | |
| 1871 | } | |
| 1872 | { | |
| 1873 | while (1) { | |
| 1874 | @(posedge clkgen_rdp_io_port.$tcu_clk_stop__gclk); | |
| 1875 | rdp_io_clkstp_pedge_t = get_time(LO); | |
| 1876 | rdp_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1877 | rdp_io_clkstp_pedge_cnt++; | |
| 1878 | } | |
| 1879 | } | |
| 1880 | { | |
| 1881 | while (1) { | |
| 1882 | @(negedge clkgen_rdp_io_port.$tcu_clk_stop__gclk); | |
| 1883 | rdp_io_clkstp_nedge_t = get_time(LO); | |
| 1884 | rdp_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1885 | rdp_io_clkstp_nedge_cnt++; | |
| 1886 | } | |
| 1887 | } | |
| 1888 | { | |
| 1889 | while (1) { | |
| 1890 | @(clkgen_rdp_io_port.$l2clk); | |
| 1891 | if (clkgen_rdp_io_port.$l2clk) | |
| 1892 | rdp_io_l2clk_pedge = get_time(LO); | |
| 1893 | else | |
| 1894 | rdp_io_l2clk_nedge = get_time(LO); | |
| 1895 | } | |
| 1896 | } | |
| 1897 | #endif | |
| 1898 | #endif | |
| 1899 | { | |
| 1900 | while (1) { | |
| 1901 | @(posedge clkgen_rst_cmp_port.$tcu_clk_stop__gclk); | |
| 1902 | rst_cmp_clkstp_pedge_t = get_time(LO); | |
| 1903 | rst_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1904 | rst_cmp_clkstp_pedge_cnt++; | |
| 1905 | } | |
| 1906 | } | |
| 1907 | { | |
| 1908 | while (1) { | |
| 1909 | @(negedge clkgen_rst_cmp_port.$tcu_clk_stop__gclk); | |
| 1910 | rst_cmp_clkstp_nedge_t = get_time(LO); | |
| 1911 | rst_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1912 | rst_cmp_clkstp_nedge_cnt++; | |
| 1913 | } | |
| 1914 | } | |
| 1915 | { | |
| 1916 | while (1) { | |
| 1917 | @(clkgen_rst_cmp_port.$l2clk); | |
| 1918 | if (clkgen_rst_cmp_port.$l2clk) | |
| 1919 | rst_cmp_l2clk_pedge = get_time(LO); | |
| 1920 | else | |
| 1921 | rst_cmp_l2clk_nedge = get_time(LO); | |
| 1922 | } | |
| 1923 | } | |
| 1924 | { | |
| 1925 | while (1) { | |
| 1926 | @(posedge clkgen_rst_io_port.$tcu_clk_stop__gclk); | |
| 1927 | rst_io_clkstp_pedge_t = get_time(LO); | |
| 1928 | rst_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1929 | rst_io_clkstp_pedge_cnt++; | |
| 1930 | } | |
| 1931 | } | |
| 1932 | { | |
| 1933 | while (1) { | |
| 1934 | @(negedge clkgen_rst_io_port.$tcu_clk_stop__gclk); | |
| 1935 | rst_io_clkstp_nedge_t = get_time(LO); | |
| 1936 | rst_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1937 | rst_io_clkstp_nedge_cnt++; | |
| 1938 | } | |
| 1939 | } | |
| 1940 | { | |
| 1941 | while (1) { | |
| 1942 | @(clkgen_rst_io_port.$l2clk); | |
| 1943 | if (clkgen_rst_io_port.$l2clk) | |
| 1944 | rst_io_l2clk_pedge = get_time(LO); | |
| 1945 | else | |
| 1946 | rst_io_l2clk_nedge = get_time(LO); | |
| 1947 | } | |
| 1948 | } | |
| 1949 | #ifndef FC_NO_NIU_T2 | |
| 1950 | #ifndef NIU_SYSTEMC_T2 | |
| 1951 | { | |
| 1952 | while (1) { | |
| 1953 | @(posedge clkgen_rtx_io2x_port.$tcu_clk_stop__gclk); | |
| 1954 | rtx_io2x_clkstp_pedge_t = get_time(LO); | |
| 1955 | rtx_io2x_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1956 | rtx_io2x_clkstp_pedge_cnt++; | |
| 1957 | } | |
| 1958 | } | |
| 1959 | { | |
| 1960 | while (1) { | |
| 1961 | @(negedge clkgen_rtx_io2x_port.$tcu_clk_stop__gclk); | |
| 1962 | rtx_io2x_clkstp_nedge_t = get_time(LO); | |
| 1963 | rtx_io2x_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1964 | rtx_io2x_clkstp_nedge_cnt++; | |
| 1965 | } | |
| 1966 | } | |
| 1967 | { | |
| 1968 | while (1) { | |
| 1969 | @(clkgen_rtx_io2x_port.$l2clk); | |
| 1970 | if (clkgen_rtx_io2x_port.$l2clk) | |
| 1971 | rtx_io2x_l2clk_pedge = get_time(LO); | |
| 1972 | else | |
| 1973 | rtx_io2x_l2clk_nedge = get_time(LO); | |
| 1974 | } | |
| 1975 | } | |
| 1976 | { | |
| 1977 | while (1) { | |
| 1978 | @(posedge clkgen_rtx_io_port.$tcu_clk_stop__gclk); | |
| 1979 | rtx_io_clkstp_pedge_t = get_time(LO); | |
| 1980 | rtx_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1981 | rtx_io_clkstp_pedge_cnt++; | |
| 1982 | } | |
| 1983 | } | |
| 1984 | { | |
| 1985 | while (1) { | |
| 1986 | @(negedge clkgen_rtx_io_port.$tcu_clk_stop__gclk); | |
| 1987 | rtx_io_clkstp_nedge_t = get_time(LO); | |
| 1988 | rtx_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 1989 | rtx_io_clkstp_nedge_cnt++; | |
| 1990 | } | |
| 1991 | } | |
| 1992 | { | |
| 1993 | while (1) { | |
| 1994 | @(clkgen_rtx_io_port.$l2clk); | |
| 1995 | if (clkgen_rtx_io_port.$l2clk) | |
| 1996 | rtx_io_l2clk_pedge = get_time(LO); | |
| 1997 | else | |
| 1998 | rtx_io_l2clk_nedge = get_time(LO); | |
| 1999 | } | |
| 2000 | } | |
| 2001 | #endif | |
| 2002 | #endif | |
| 2003 | { | |
| 2004 | while (1) { | |
| 2005 | @(posedge clkgen_sii_cmp_port.$tcu_clk_stop__gclk); | |
| 2006 | sii_cmp_clkstp_pedge_t = get_time(LO); | |
| 2007 | sii_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2008 | sii_cmp_clkstp_pedge_cnt++; | |
| 2009 | } | |
| 2010 | } | |
| 2011 | { | |
| 2012 | while (1) { | |
| 2013 | @(negedge clkgen_sii_cmp_port.$tcu_clk_stop__gclk); | |
| 2014 | sii_cmp_clkstp_nedge_t = get_time(LO); | |
| 2015 | sii_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2016 | sii_cmp_clkstp_nedge_cnt++; | |
| 2017 | } | |
| 2018 | } | |
| 2019 | { | |
| 2020 | while (1) { | |
| 2021 | @(clkgen_sii_cmp_port.$l2clk); | |
| 2022 | if (clkgen_sii_cmp_port.$l2clk) | |
| 2023 | sii_cmp_l2clk_pedge = get_time(LO); | |
| 2024 | else | |
| 2025 | sii_cmp_l2clk_nedge = get_time(LO); | |
| 2026 | } | |
| 2027 | } | |
| 2028 | { | |
| 2029 | while (1) { | |
| 2030 | @(posedge clkgen_sii_io_port.$tcu_clk_stop__gclk); | |
| 2031 | sii_io_clkstp_pedge_t = get_time(LO); | |
| 2032 | sii_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2033 | sii_io_clkstp_pedge_cnt++; | |
| 2034 | } | |
| 2035 | } | |
| 2036 | { | |
| 2037 | while (1) { | |
| 2038 | @(negedge clkgen_sii_io_port.$tcu_clk_stop__gclk); | |
| 2039 | sii_io_clkstp_nedge_t = get_time(LO); | |
| 2040 | sii_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2041 | sii_io_clkstp_nedge_cnt++; | |
| 2042 | } | |
| 2043 | } | |
| 2044 | { | |
| 2045 | while (1) { | |
| 2046 | @(clkgen_sii_io_port.$l2clk); | |
| 2047 | if (clkgen_sii_io_port.$l2clk) | |
| 2048 | sii_io_l2clk_pedge = get_time(LO); | |
| 2049 | else | |
| 2050 | sii_io_l2clk_nedge = get_time(LO); | |
| 2051 | } | |
| 2052 | } | |
| 2053 | { | |
| 2054 | while (1) { | |
| 2055 | @(posedge clkgen_sio_cmp_port.$tcu_clk_stop__gclk); | |
| 2056 | sio_cmp_clkstp_pedge_t = get_time(LO); | |
| 2057 | sio_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2058 | sio_cmp_clkstp_pedge_cnt++; | |
| 2059 | } | |
| 2060 | } | |
| 2061 | { | |
| 2062 | while (1) { | |
| 2063 | @(negedge clkgen_sio_cmp_port.$tcu_clk_stop__gclk); | |
| 2064 | sio_cmp_clkstp_nedge_t = get_time(LO); | |
| 2065 | sio_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2066 | sio_cmp_clkstp_nedge_cnt++; | |
| 2067 | } | |
| 2068 | } | |
| 2069 | { | |
| 2070 | while (1) { | |
| 2071 | @(clkgen_sio_cmp_port.$l2clk); | |
| 2072 | if (clkgen_sio_cmp_port.$l2clk) | |
| 2073 | sio_cmp_l2clk_pedge = get_time(LO); | |
| 2074 | else | |
| 2075 | sio_cmp_l2clk_nedge = get_time(LO); | |
| 2076 | } | |
| 2077 | } | |
| 2078 | { | |
| 2079 | while (1) { | |
| 2080 | @(posedge clkgen_sio_io_port.$tcu_clk_stop__gclk); | |
| 2081 | sio_io_clkstp_pedge_t = get_time(LO); | |
| 2082 | sio_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2083 | sio_io_clkstp_pedge_cnt++; | |
| 2084 | } | |
| 2085 | } | |
| 2086 | { | |
| 2087 | while (1) { | |
| 2088 | @(negedge clkgen_sio_io_port.$tcu_clk_stop__gclk); | |
| 2089 | sio_io_clkstp_nedge_t = get_time(LO); | |
| 2090 | sio_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2091 | sio_io_clkstp_nedge_cnt++; | |
| 2092 | } | |
| 2093 | } | |
| 2094 | { | |
| 2095 | while (1) { | |
| 2096 | @(clkgen_sio_io_port.$l2clk); | |
| 2097 | if (clkgen_sio_io_port.$l2clk) | |
| 2098 | sio_io_l2clk_pedge = get_time(LO); | |
| 2099 | else | |
| 2100 | sio_io_l2clk_nedge = get_time(LO); | |
| 2101 | } | |
| 2102 | } | |
| 2103 | #ifndef RTL_NO_SPC0 | |
| 2104 | { | |
| 2105 | while (1) { | |
| 2106 | @(posedge clkgen_spc0_cmp_port.$tcu_clk_stop__gclk); | |
| 2107 | spc0_cmp_clkstp_pedge_t = get_time(LO); | |
| 2108 | spc0_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2109 | spc0_cmp_clkstp_pedge_cnt++; | |
| 2110 | } | |
| 2111 | } | |
| 2112 | { | |
| 2113 | while (1) { | |
| 2114 | @(negedge clkgen_spc0_cmp_port.$tcu_clk_stop__gclk); | |
| 2115 | spc0_cmp_clkstp_nedge_t = get_time(LO); | |
| 2116 | spc0_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2117 | spc0_cmp_clkstp_nedge_cnt++; | |
| 2118 | } | |
| 2119 | } | |
| 2120 | { | |
| 2121 | while (1) { | |
| 2122 | @(clkgen_spc0_cmp_port.$l2clk); | |
| 2123 | if (clkgen_spc0_cmp_port.$l2clk) | |
| 2124 | spc0_cmp_l2clk_pedge = get_time(LO); | |
| 2125 | else | |
| 2126 | spc0_cmp_l2clk_nedge = get_time(LO); | |
| 2127 | } | |
| 2128 | } | |
| 2129 | #endif | |
| 2130 | #ifndef RTL_NO_SPC1 | |
| 2131 | { | |
| 2132 | while (1) { | |
| 2133 | @(posedge clkgen_spc1_cmp_port.$tcu_clk_stop__gclk); | |
| 2134 | spc1_cmp_clkstp_pedge_t = get_time(LO); | |
| 2135 | spc1_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2136 | spc1_cmp_clkstp_pedge_cnt++; | |
| 2137 | } | |
| 2138 | } | |
| 2139 | { | |
| 2140 | while (1) { | |
| 2141 | @(negedge clkgen_spc1_cmp_port.$tcu_clk_stop__gclk); | |
| 2142 | spc1_cmp_clkstp_nedge_t = get_time(LO); | |
| 2143 | spc1_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2144 | spc1_cmp_clkstp_nedge_cnt++; | |
| 2145 | } | |
| 2146 | } | |
| 2147 | { | |
| 2148 | while (1) { | |
| 2149 | @(clkgen_spc1_cmp_port.$l2clk); | |
| 2150 | if (clkgen_spc1_cmp_port.$l2clk) | |
| 2151 | spc1_cmp_l2clk_pedge = get_time(LO); | |
| 2152 | else | |
| 2153 | spc1_cmp_l2clk_nedge = get_time(LO); | |
| 2154 | } | |
| 2155 | } | |
| 2156 | #endif | |
| 2157 | #ifndef RTL_NO_SPC2 | |
| 2158 | { | |
| 2159 | while (1) { | |
| 2160 | @(posedge clkgen_spc2_cmp_port.$tcu_clk_stop__gclk); | |
| 2161 | spc2_cmp_clkstp_pedge_t = get_time(LO); | |
| 2162 | spc2_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2163 | spc2_cmp_clkstp_pedge_cnt++; | |
| 2164 | } | |
| 2165 | } | |
| 2166 | { | |
| 2167 | while (1) { | |
| 2168 | @(negedge clkgen_spc2_cmp_port.$tcu_clk_stop__gclk); | |
| 2169 | spc2_cmp_clkstp_nedge_t = get_time(LO); | |
| 2170 | spc2_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2171 | spc2_cmp_clkstp_nedge_cnt++; | |
| 2172 | } | |
| 2173 | } | |
| 2174 | { | |
| 2175 | while (1) { | |
| 2176 | @(clkgen_spc2_cmp_port.$l2clk); | |
| 2177 | if (clkgen_spc2_cmp_port.$l2clk) | |
| 2178 | spc2_cmp_l2clk_pedge = get_time(LO); | |
| 2179 | else | |
| 2180 | spc2_cmp_l2clk_nedge = get_time(LO); | |
| 2181 | } | |
| 2182 | } | |
| 2183 | #endif | |
| 2184 | #ifndef RTL_NO_SPC3 | |
| 2185 | { | |
| 2186 | while (1) { | |
| 2187 | @(posedge clkgen_spc3_cmp_port.$tcu_clk_stop__gclk); | |
| 2188 | spc3_cmp_clkstp_pedge_t = get_time(LO); | |
| 2189 | spc3_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2190 | spc3_cmp_clkstp_pedge_cnt++; | |
| 2191 | } | |
| 2192 | } | |
| 2193 | { | |
| 2194 | while (1) { | |
| 2195 | @(negedge clkgen_spc3_cmp_port.$tcu_clk_stop__gclk); | |
| 2196 | spc3_cmp_clkstp_nedge_t = get_time(LO); | |
| 2197 | spc3_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2198 | spc3_cmp_clkstp_nedge_cnt++; | |
| 2199 | } | |
| 2200 | } | |
| 2201 | { | |
| 2202 | while (1) { | |
| 2203 | @(clkgen_spc3_cmp_port.$l2clk); | |
| 2204 | if (clkgen_spc3_cmp_port.$l2clk) | |
| 2205 | spc3_cmp_l2clk_pedge = get_time(LO); | |
| 2206 | else | |
| 2207 | spc3_cmp_l2clk_nedge = get_time(LO); | |
| 2208 | } | |
| 2209 | } | |
| 2210 | #endif | |
| 2211 | #ifndef RTL_NO_SPC4 | |
| 2212 | { | |
| 2213 | while (1) { | |
| 2214 | @(posedge clkgen_spc4_cmp_port.$tcu_clk_stop__gclk); | |
| 2215 | spc4_cmp_clkstp_pedge_t = get_time(LO); | |
| 2216 | spc4_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2217 | spc4_cmp_clkstp_pedge_cnt++; | |
| 2218 | } | |
| 2219 | } | |
| 2220 | { | |
| 2221 | while (1) { | |
| 2222 | @(negedge clkgen_spc4_cmp_port.$tcu_clk_stop__gclk); | |
| 2223 | spc4_cmp_clkstp_nedge_t = get_time(LO); | |
| 2224 | spc4_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2225 | spc4_cmp_clkstp_nedge_cnt++; | |
| 2226 | } | |
| 2227 | } | |
| 2228 | { | |
| 2229 | while (1) { | |
| 2230 | @(clkgen_spc4_cmp_port.$l2clk); | |
| 2231 | if (clkgen_spc4_cmp_port.$l2clk) | |
| 2232 | spc4_cmp_l2clk_pedge = get_time(LO); | |
| 2233 | else | |
| 2234 | spc4_cmp_l2clk_nedge = get_time(LO); | |
| 2235 | } | |
| 2236 | } | |
| 2237 | #endif | |
| 2238 | #ifndef RTL_NO_SPC5 | |
| 2239 | { | |
| 2240 | while (1) { | |
| 2241 | @(posedge clkgen_spc5_cmp_port.$tcu_clk_stop__gclk); | |
| 2242 | spc5_cmp_clkstp_pedge_t = get_time(LO); | |
| 2243 | spc5_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2244 | spc5_cmp_clkstp_pedge_cnt++; | |
| 2245 | } | |
| 2246 | } | |
| 2247 | { | |
| 2248 | while (1) { | |
| 2249 | @(negedge clkgen_spc5_cmp_port.$tcu_clk_stop__gclk); | |
| 2250 | spc5_cmp_clkstp_nedge_t = get_time(LO); | |
| 2251 | spc5_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2252 | spc5_cmp_clkstp_nedge_cnt++; | |
| 2253 | } | |
| 2254 | } | |
| 2255 | { | |
| 2256 | while (1) { | |
| 2257 | @(clkgen_spc5_cmp_port.$l2clk); | |
| 2258 | if (clkgen_spc5_cmp_port.$l2clk) | |
| 2259 | spc5_cmp_l2clk_pedge = get_time(LO); | |
| 2260 | else | |
| 2261 | spc5_cmp_l2clk_nedge = get_time(LO); | |
| 2262 | } | |
| 2263 | } | |
| 2264 | #endif | |
| 2265 | #ifndef RTL_NO_SPC6 | |
| 2266 | { | |
| 2267 | while (1) { | |
| 2268 | @(posedge clkgen_spc6_cmp_port.$tcu_clk_stop__gclk); | |
| 2269 | spc6_cmp_clkstp_pedge_t = get_time(LO); | |
| 2270 | spc6_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2271 | spc6_cmp_clkstp_pedge_cnt++; | |
| 2272 | } | |
| 2273 | } | |
| 2274 | { | |
| 2275 | while (1) { | |
| 2276 | @(negedge clkgen_spc6_cmp_port.$tcu_clk_stop__gclk); | |
| 2277 | spc6_cmp_clkstp_nedge_t = get_time(LO); | |
| 2278 | spc6_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2279 | spc6_cmp_clkstp_nedge_cnt++; | |
| 2280 | } | |
| 2281 | } | |
| 2282 | { | |
| 2283 | while (1) { | |
| 2284 | @(clkgen_spc6_cmp_port.$l2clk); | |
| 2285 | if (clkgen_spc6_cmp_port.$l2clk) | |
| 2286 | spc6_cmp_l2clk_pedge = get_time(LO); | |
| 2287 | else | |
| 2288 | spc6_cmp_l2clk_nedge = get_time(LO); | |
| 2289 | } | |
| 2290 | } | |
| 2291 | #endif | |
| 2292 | #ifndef RTL_NO_SPC7 | |
| 2293 | { | |
| 2294 | while (1) { | |
| 2295 | @(posedge clkgen_spc7_cmp_port.$tcu_clk_stop__gclk); | |
| 2296 | spc7_cmp_clkstp_pedge_t = get_time(LO); | |
| 2297 | spc7_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2298 | spc7_cmp_clkstp_pedge_cnt++; | |
| 2299 | } | |
| 2300 | } | |
| 2301 | { | |
| 2302 | while (1) { | |
| 2303 | @(negedge clkgen_spc7_cmp_port.$tcu_clk_stop__gclk); | |
| 2304 | spc7_cmp_clkstp_nedge_t = get_time(LO); | |
| 2305 | spc7_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2306 | spc7_cmp_clkstp_nedge_cnt++; | |
| 2307 | } | |
| 2308 | } | |
| 2309 | { | |
| 2310 | while (1) { | |
| 2311 | @(clkgen_spc7_cmp_port.$l2clk); | |
| 2312 | if (clkgen_spc7_cmp_port.$l2clk) | |
| 2313 | spc7_cmp_l2clk_pedge = get_time(LO); | |
| 2314 | else | |
| 2315 | spc7_cmp_l2clk_nedge = get_time(LO); | |
| 2316 | } | |
| 2317 | } | |
| 2318 | #endif | |
| 2319 | { | |
| 2320 | while (1) { | |
| 2321 | @(posedge clkgen_tcu_cmp_port.$tcu_clk_stop__gclk); | |
| 2322 | tcu_cmp_clkstp_pedge_t = get_time(LO); | |
| 2323 | tcu_cmp_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2324 | tcu_cmp_clkstp_pedge_cnt++; | |
| 2325 | } | |
| 2326 | } | |
| 2327 | { | |
| 2328 | while (1) { | |
| 2329 | @(negedge clkgen_tcu_cmp_port.$tcu_clk_stop__gclk); | |
| 2330 | tcu_cmp_clkstp_nedge_t = get_time(LO); | |
| 2331 | tcu_cmp_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2332 | tcu_cmp_clkstp_nedge_cnt++; | |
| 2333 | } | |
| 2334 | } | |
| 2335 | { | |
| 2336 | while (1) { | |
| 2337 | @(clkgen_tcu_cmp_port.$l2clk); | |
| 2338 | if (clkgen_tcu_cmp_port.$l2clk) | |
| 2339 | tcu_cmp_l2clk_pedge = get_time(LO); | |
| 2340 | else | |
| 2341 | tcu_cmp_l2clk_nedge = get_time(LO); | |
| 2342 | } | |
| 2343 | } | |
| 2344 | { | |
| 2345 | while (1) { | |
| 2346 | @(posedge clkgen_tcu_io_port.$tcu_clk_stop__gclk); | |
| 2347 | tcu_io_clkstp_pedge_t = get_time(LO); | |
| 2348 | tcu_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2349 | tcu_io_clkstp_pedge_cnt++; | |
| 2350 | } | |
| 2351 | } | |
| 2352 | { | |
| 2353 | while (1) { | |
| 2354 | @(negedge clkgen_tcu_io_port.$tcu_clk_stop__gclk); | |
| 2355 | tcu_io_clkstp_nedge_t = get_time(LO); | |
| 2356 | tcu_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2357 | tcu_io_clkstp_nedge_cnt++; | |
| 2358 | } | |
| 2359 | } | |
| 2360 | { | |
| 2361 | while (1) { | |
| 2362 | @(clkgen_tcu_io_port.$l2clk); | |
| 2363 | if (clkgen_tcu_io_port.$l2clk) | |
| 2364 | tcu_io_l2clk_pedge = get_time(LO); | |
| 2365 | else | |
| 2366 | tcu_io_l2clk_nedge = get_time(LO); | |
| 2367 | } | |
| 2368 | } | |
| 2369 | #ifndef FC_NO_NIU_T2 | |
| 2370 | #ifndef NIU_SYSTEMC_T2 | |
| 2371 | { | |
| 2372 | while (1) { | |
| 2373 | @(posedge clkgen_tds_io2x_port.$tcu_clk_stop__gclk); | |
| 2374 | tds_io2x_clkstp_pedge_t = get_time(LO); | |
| 2375 | tds_io2x_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2376 | tds_io2x_clkstp_pedge_cnt++; | |
| 2377 | } | |
| 2378 | } | |
| 2379 | { | |
| 2380 | while (1) { | |
| 2381 | @(negedge clkgen_tds_io2x_port.$tcu_clk_stop__gclk); | |
| 2382 | tds_io2x_clkstp_nedge_t = get_time(LO); | |
| 2383 | tds_io2x_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2384 | tds_io2x_clkstp_nedge_cnt++; | |
| 2385 | } | |
| 2386 | } | |
| 2387 | { | |
| 2388 | while (1) { | |
| 2389 | @(clkgen_tds_io2x_port.$l2clk); | |
| 2390 | if (clkgen_tds_io2x_port.$l2clk) | |
| 2391 | tds_io2x_l2clk_pedge = get_time(LO); | |
| 2392 | else | |
| 2393 | tds_io2x_l2clk_nedge = get_time(LO); | |
| 2394 | } | |
| 2395 | } | |
| 2396 | { | |
| 2397 | while (1) { | |
| 2398 | @(posedge clkgen_tds_io_port.$tcu_clk_stop__gclk); | |
| 2399 | tds_io_clkstp_pedge_t = get_time(LO); | |
| 2400 | tds_io_clkstp_pedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2401 | tds_io_clkstp_pedge_cnt++; | |
| 2402 | } | |
| 2403 | } | |
| 2404 | { | |
| 2405 | while (1) { | |
| 2406 | @(negedge clkgen_tds_io_port.$tcu_clk_stop__gclk); | |
| 2407 | tds_io_clkstp_nedge_t = get_time(LO); | |
| 2408 | tds_io_clkstp_nedge_c = get_cycle(ccu_clk_port.$cmp_pll_clk); | |
| 2409 | tds_io_clkstp_nedge_cnt++; | |
| 2410 | } | |
| 2411 | } | |
| 2412 | { | |
| 2413 | while (1) { | |
| 2414 | @(clkgen_tds_io_port.$l2clk); | |
| 2415 | if (clkgen_tds_io_port.$l2clk) | |
| 2416 | tds_io_l2clk_pedge = get_time(LO); | |
| 2417 | else | |
| 2418 | tds_io_l2clk_nedge = get_time(LO); | |
| 2419 | } | |
| 2420 | } | |
| 2421 | #endif | |
| 2422 | #endif | |
| 2423 | join none | |
| 2424 | } | |
| 2425 | ||
| 2426 | //################################################################# | |
| 2427 | //################################################################# | |
| 2428 | //####### tasks that check/use variables (ie. not DUT signals) #### | |
| 2429 | //################################################################# | |
| 2430 | //################################################################# | |
| 2431 | ||
| 2432 | //======================================================================== | |
| 2433 | // | |
| 2434 | //======================================================================== | |
| 2435 | function integer CLUSTER_hdrs_mon::is_any_hdr_clkstp_pedge_occur() { | |
| 2436 | integer count = 0; | |
| 2437 | ||
| 2438 | count += (ccu_cmp_clkstp_pedge_cnt > 0); | |
| 2439 | count += (ccu_io_clkstp_pedge_cnt > 0); | |
| 2440 | count += (ccx_cmp_clkstp_pedge_cnt > 0); | |
| 2441 | count += (db0_cmp_clkstp_pedge_cnt > 0); | |
| 2442 | count += (db0_io_clkstp_pedge_cnt > 0); | |
| 2443 | count += (db1_cmp_clkstp_pedge_cnt > 0); | |
| 2444 | count += (db1_io_clkstp_pedge_cnt > 0); | |
| 2445 | count += (dmu_io_clkstp_pedge_cnt > 0); | |
| 2446 | count += (efu_cmp_clkstp_pedge_cnt > 0); | |
| 2447 | count += (efu_io_clkstp_pedge_cnt > 0); | |
| 2448 | count += (l2b0_cmp_clkstp_pedge_cnt > 0); | |
| 2449 | count += (l2b1_cmp_clkstp_pedge_cnt > 0); | |
| 2450 | count += (l2b2_cmp_clkstp_pedge_cnt > 0); | |
| 2451 | count += (l2b3_cmp_clkstp_pedge_cnt > 0); | |
| 2452 | count += (l2b4_cmp_clkstp_pedge_cnt > 0); | |
| 2453 | count += (l2b5_cmp_clkstp_pedge_cnt > 0); | |
| 2454 | count += (l2b6_cmp_clkstp_pedge_cnt > 0); | |
| 2455 | count += (l2b7_cmp_clkstp_pedge_cnt > 0); | |
| 2456 | count += (l2d0_cmp_clkstp_pedge_cnt > 0); | |
| 2457 | count += (l2d1_cmp_clkstp_pedge_cnt > 0); | |
| 2458 | count += (l2d2_cmp_clkstp_pedge_cnt > 0); | |
| 2459 | count += (l2d3_cmp_clkstp_pedge_cnt > 0); | |
| 2460 | count += (l2d4_cmp_clkstp_pedge_cnt > 0); | |
| 2461 | count += (l2d5_cmp_clkstp_pedge_cnt > 0); | |
| 2462 | count += (l2d6_cmp_clkstp_pedge_cnt > 0); | |
| 2463 | count += (l2d7_cmp_clkstp_pedge_cnt > 0); | |
| 2464 | count += (l2t0_cmp_clkstp_pedge_cnt > 0); | |
| 2465 | count += (l2t1_cmp_clkstp_pedge_cnt > 0); | |
| 2466 | count += (l2t2_cmp_clkstp_pedge_cnt > 0); | |
| 2467 | count += (l2t3_cmp_clkstp_pedge_cnt > 0); | |
| 2468 | count += (l2t4_cmp_clkstp_pedge_cnt > 0); | |
| 2469 | count += (l2t5_cmp_clkstp_pedge_cnt > 0); | |
| 2470 | count += (l2t6_cmp_clkstp_pedge_cnt > 0); | |
| 2471 | count += (l2t7_cmp_clkstp_pedge_cnt > 0); | |
| 2472 | #ifndef FC_NO_NIU_T2 | |
| 2473 | #ifndef NIU_SYSTEMC_T2 | |
| 2474 | count += (mac_io_clkstp_pedge_cnt > 0); | |
| 2475 | #endif | |
| 2476 | #endif | |
| 2477 | count += (mcu0_cmp_clkstp_pedge_cnt > 0); | |
| 2478 | count += (mcu0_dr_clkstp_pedge_cnt > 0); | |
| 2479 | count += (mcu0_io_clkstp_pedge_cnt > 0); | |
| 2480 | count += (mcu1_cmp_clkstp_pedge_cnt > 0); | |
| 2481 | count += (mcu1_dr_clkstp_pedge_cnt > 0); | |
| 2482 | count += (mcu1_io_clkstp_pedge_cnt > 0); | |
| 2483 | count += (mcu2_cmp_clkstp_pedge_cnt > 0); | |
| 2484 | count += (mcu2_dr_clkstp_pedge_cnt > 0); | |
| 2485 | count += (mcu2_io_clkstp_pedge_cnt > 0); | |
| 2486 | count += (mcu3_cmp_clkstp_pedge_cnt > 0); | |
| 2487 | count += (mcu3_dr_clkstp_pedge_cnt > 0); | |
| 2488 | count += (mcu3_io_clkstp_pedge_cnt > 0); | |
| 2489 | count += (mio_0_cmp_clkstp_pedge_cnt > 0); | |
| 2490 | count += (mio_1_cmp_clkstp_pedge_cnt > 0); | |
| 2491 | count += (mio_2_cmp_clkstp_pedge_cnt > 0); | |
| 2492 | count += (mio_3_cmp_clkstp_pedge_cnt > 0); | |
| 2493 | count += (mio_io_clkstp_pedge_cnt > 0); | |
| 2494 | count += (ncu_cmp_clkstp_pedge_cnt > 0); | |
| 2495 | count += (ncu_io_clkstp_pedge_cnt > 0); | |
| 2496 | #ifndef FC_NO_PEU_VERA | |
| 2497 | #ifndef PEU_SYSTEMC_T2 | |
| 2498 | count += (peu_io_clkstp_pedge_cnt > 0); | |
| 2499 | count += (peu_pc_clkstp_pedge_cnt > 0); | |
| 2500 | #endif | |
| 2501 | #endif | |
| 2502 | #ifndef FC_NO_NIU_T2 | |
| 2503 | #ifndef NIU_SYSTEMC_T2 | |
| 2504 | count += (rdp_io2x_clkstp_pedge_cnt > 0); | |
| 2505 | count += (rdp_io_clkstp_pedge_cnt > 0); | |
| 2506 | count += (rtx_io2x_clkstp_pedge_cnt > 0); | |
| 2507 | count += (rtx_io_clkstp_pedge_cnt > 0); | |
| 2508 | #endif | |
| 2509 | #endif | |
| 2510 | count += (rst_cmp_clkstp_pedge_cnt > 0); | |
| 2511 | count += (rst_io_clkstp_pedge_cnt > 0); | |
| 2512 | count += (sii_cmp_clkstp_pedge_cnt > 0); | |
| 2513 | count += (sii_io_clkstp_pedge_cnt > 0); | |
| 2514 | count += (sio_cmp_clkstp_pedge_cnt > 0); | |
| 2515 | count += (sio_io_clkstp_pedge_cnt > 0); | |
| 2516 | count += (spc0_cmp_clkstp_pedge_cnt > 0); | |
| 2517 | count += (spc1_cmp_clkstp_pedge_cnt > 0); | |
| 2518 | count += (spc2_cmp_clkstp_pedge_cnt > 0); | |
| 2519 | count += (spc3_cmp_clkstp_pedge_cnt > 0); | |
| 2520 | count += (spc4_cmp_clkstp_pedge_cnt > 0); | |
| 2521 | count += (spc5_cmp_clkstp_pedge_cnt > 0); | |
| 2522 | count += (spc6_cmp_clkstp_pedge_cnt > 0); | |
| 2523 | count += (spc7_cmp_clkstp_pedge_cnt > 0); | |
| 2524 | count += (tcu_cmp_clkstp_pedge_cnt > 0); | |
| 2525 | count += (tcu_io_clkstp_pedge_cnt > 0); | |
| 2526 | #ifndef FC_NO_NIU_T2 | |
| 2527 | #ifndef NIU_SYSTEMC_T2 | |
| 2528 | count += (tds_io2x_clkstp_pedge_cnt > 0); | |
| 2529 | count += (tds_io_clkstp_pedge_cnt > 0); | |
| 2530 | #endif | |
| 2531 | #endif | |
| 2532 | is_any_hdr_clkstp_pedge_occur = (count)? 1 : 0; | |
| 2533 | } | |
| 2534 | ||
| 2535 | //======================================================================== | |
| 2536 | // | |
| 2537 | //======================================================================== | |
| 2538 | function integer CLUSTER_hdrs_mon::is_any_hdr_clkstp_nedge_occur() { | |
| 2539 | integer count = 0; | |
| 2540 | ||
| 2541 | count += (ccu_cmp_clkstp_nedge_cnt > 0); | |
| 2542 | count += (ccu_io_clkstp_nedge_cnt > 0); | |
| 2543 | count += (ccx_cmp_clkstp_nedge_cnt > 0); | |
| 2544 | count += (db0_cmp_clkstp_nedge_cnt > 0); | |
| 2545 | count += (db0_io_clkstp_nedge_cnt > 0); | |
| 2546 | count += (db1_cmp_clkstp_nedge_cnt > 0); | |
| 2547 | count += (db1_io_clkstp_nedge_cnt > 0); | |
| 2548 | count += (dmu_io_clkstp_nedge_cnt > 0); | |
| 2549 | count += (efu_cmp_clkstp_nedge_cnt > 0); | |
| 2550 | count += (efu_io_clkstp_nedge_cnt > 0); | |
| 2551 | count += (l2b0_cmp_clkstp_nedge_cnt > 0); | |
| 2552 | count += (l2b1_cmp_clkstp_nedge_cnt > 0); | |
| 2553 | count += (l2b2_cmp_clkstp_nedge_cnt > 0); | |
| 2554 | count += (l2b3_cmp_clkstp_nedge_cnt > 0); | |
| 2555 | count += (l2b4_cmp_clkstp_nedge_cnt > 0); | |
| 2556 | count += (l2b5_cmp_clkstp_nedge_cnt > 0); | |
| 2557 | count += (l2b6_cmp_clkstp_nedge_cnt > 0); | |
| 2558 | count += (l2b7_cmp_clkstp_nedge_cnt > 0); | |
| 2559 | count += (l2d0_cmp_clkstp_nedge_cnt > 0); | |
| 2560 | count += (l2d1_cmp_clkstp_nedge_cnt > 0); | |
| 2561 | count += (l2d2_cmp_clkstp_nedge_cnt > 0); | |
| 2562 | count += (l2d3_cmp_clkstp_nedge_cnt > 0); | |
| 2563 | count += (l2d4_cmp_clkstp_nedge_cnt > 0); | |
| 2564 | count += (l2d5_cmp_clkstp_nedge_cnt > 0); | |
| 2565 | count += (l2d6_cmp_clkstp_nedge_cnt > 0); | |
| 2566 | count += (l2d7_cmp_clkstp_nedge_cnt > 0); | |
| 2567 | count += (l2t0_cmp_clkstp_nedge_cnt > 0); | |
| 2568 | count += (l2t1_cmp_clkstp_nedge_cnt > 0); | |
| 2569 | count += (l2t2_cmp_clkstp_nedge_cnt > 0); | |
| 2570 | count += (l2t3_cmp_clkstp_nedge_cnt > 0); | |
| 2571 | count += (l2t4_cmp_clkstp_nedge_cnt > 0); | |
| 2572 | count += (l2t5_cmp_clkstp_nedge_cnt > 0); | |
| 2573 | count += (l2t6_cmp_clkstp_nedge_cnt > 0); | |
| 2574 | count += (l2t7_cmp_clkstp_nedge_cnt > 0); | |
| 2575 | #ifndef FC_NO_NIU_T2 | |
| 2576 | #ifndef NIU_SYSTEMC_T2 | |
| 2577 | count += (mac_io_clkstp_nedge_cnt > 0); | |
| 2578 | #endif | |
| 2579 | #endif | |
| 2580 | count += (mcu0_cmp_clkstp_nedge_cnt > 0); | |
| 2581 | count += (mcu0_dr_clkstp_nedge_cnt > 0); | |
| 2582 | count += (mcu0_io_clkstp_nedge_cnt > 0); | |
| 2583 | count += (mcu1_cmp_clkstp_nedge_cnt > 0); | |
| 2584 | count += (mcu1_dr_clkstp_nedge_cnt > 0); | |
| 2585 | count += (mcu1_io_clkstp_nedge_cnt > 0); | |
| 2586 | count += (mcu2_cmp_clkstp_nedge_cnt > 0); | |
| 2587 | count += (mcu2_dr_clkstp_nedge_cnt > 0); | |
| 2588 | count += (mcu2_io_clkstp_nedge_cnt > 0); | |
| 2589 | count += (mcu3_cmp_clkstp_nedge_cnt > 0); | |
| 2590 | count += (mcu3_dr_clkstp_nedge_cnt > 0); | |
| 2591 | count += (mcu3_io_clkstp_nedge_cnt > 0); | |
| 2592 | count += (mio_0_cmp_clkstp_nedge_cnt > 0); | |
| 2593 | count += (mio_1_cmp_clkstp_nedge_cnt > 0); | |
| 2594 | count += (mio_2_cmp_clkstp_nedge_cnt > 0); | |
| 2595 | count += (mio_3_cmp_clkstp_nedge_cnt > 0); | |
| 2596 | count += (mio_io_clkstp_nedge_cnt > 0); | |
| 2597 | count += (ncu_cmp_clkstp_nedge_cnt > 0); | |
| 2598 | count += (ncu_io_clkstp_nedge_cnt > 0); | |
| 2599 | #ifndef FC_NO_PEU_VERA | |
| 2600 | #ifndef PEU_SYSTEMC_T2 | |
| 2601 | count += (peu_io_clkstp_nedge_cnt > 0); | |
| 2602 | count += (peu_pc_clkstp_nedge_cnt > 0); | |
| 2603 | #endif | |
| 2604 | #endif | |
| 2605 | #ifndef FC_NO_NIU_T2 | |
| 2606 | #ifndef NIU_SYSTEMC_T2 | |
| 2607 | count += (rdp_io2x_clkstp_nedge_cnt > 0); | |
| 2608 | count += (rdp_io_clkstp_nedge_cnt > 0); | |
| 2609 | count += (rtx_io2x_clkstp_nedge_cnt > 0); | |
| 2610 | count += (rtx_io_clkstp_nedge_cnt > 0); | |
| 2611 | #endif | |
| 2612 | #endif | |
| 2613 | count += (rst_cmp_clkstp_nedge_cnt > 0); | |
| 2614 | count += (rst_io_clkstp_nedge_cnt > 0); | |
| 2615 | count += (sii_cmp_clkstp_nedge_cnt > 0); | |
| 2616 | count += (sii_io_clkstp_nedge_cnt > 0); | |
| 2617 | count += (sio_cmp_clkstp_nedge_cnt > 0); | |
| 2618 | count += (sio_io_clkstp_nedge_cnt > 0); | |
| 2619 | count += (spc0_cmp_clkstp_nedge_cnt > 0); | |
| 2620 | count += (spc1_cmp_clkstp_nedge_cnt > 0); | |
| 2621 | count += (spc2_cmp_clkstp_nedge_cnt > 0); | |
| 2622 | count += (spc3_cmp_clkstp_nedge_cnt > 0); | |
| 2623 | count += (spc4_cmp_clkstp_nedge_cnt > 0); | |
| 2624 | count += (spc5_cmp_clkstp_nedge_cnt > 0); | |
| 2625 | count += (spc6_cmp_clkstp_nedge_cnt > 0); | |
| 2626 | count += (spc7_cmp_clkstp_nedge_cnt > 0); | |
| 2627 | count += (tcu_cmp_clkstp_nedge_cnt > 0); | |
| 2628 | count += (tcu_io_clkstp_nedge_cnt > 0); | |
| 2629 | #ifndef FC_NO_NIU_T2 | |
| 2630 | #ifndef NIU_SYSTEMC_T2 | |
| 2631 | count += (tds_io2x_clkstp_nedge_cnt > 0); | |
| 2632 | count += (tds_io_clkstp_nedge_cnt > 0); | |
| 2633 | #endif | |
| 2634 | #endif | |
| 2635 | is_any_hdr_clkstp_nedge_occur = (count)? 1 : 0; | |
| 2636 | } | |
| 2637 | ||
| 2638 | //======================================================================== | |
| 2639 | // | |
| 2640 | //======================================================================== | |
| 2641 | function integer CLUSTER_hdrs_mon::is_any_hdr_clkstp_pedge_more_once() { | |
| 2642 | integer count = 0; | |
| 2643 | ||
| 2644 | count += (ccu_cmp_clkstp_pedge_cnt > 1); | |
| 2645 | count += (ccu_io_clkstp_pedge_cnt > 1); | |
| 2646 | count += (ccx_cmp_clkstp_pedge_cnt > 1); | |
| 2647 | count += (db0_cmp_clkstp_pedge_cnt > 1); | |
| 2648 | count += (db0_io_clkstp_pedge_cnt > 1); | |
| 2649 | count += (db1_cmp_clkstp_pedge_cnt > 1); | |
| 2650 | count += (db1_io_clkstp_pedge_cnt > 1); | |
| 2651 | count += (dmu_io_clkstp_pedge_cnt > 1); | |
| 2652 | count += (efu_cmp_clkstp_pedge_cnt > 1); | |
| 2653 | count += (efu_io_clkstp_pedge_cnt > 1); | |
| 2654 | count += (l2b0_cmp_clkstp_pedge_cnt > 1); | |
| 2655 | count += (l2b1_cmp_clkstp_pedge_cnt > 1); | |
| 2656 | count += (l2b2_cmp_clkstp_pedge_cnt > 1); | |
| 2657 | count += (l2b3_cmp_clkstp_pedge_cnt > 1); | |
| 2658 | count += (l2b4_cmp_clkstp_pedge_cnt > 1); | |
| 2659 | count += (l2b5_cmp_clkstp_pedge_cnt > 1); | |
| 2660 | count += (l2b6_cmp_clkstp_pedge_cnt > 1); | |
| 2661 | count += (l2b7_cmp_clkstp_pedge_cnt > 1); | |
| 2662 | count += (l2d0_cmp_clkstp_pedge_cnt > 1); | |
| 2663 | count += (l2d1_cmp_clkstp_pedge_cnt > 1); | |
| 2664 | count += (l2d2_cmp_clkstp_pedge_cnt > 1); | |
| 2665 | count += (l2d3_cmp_clkstp_pedge_cnt > 1); | |
| 2666 | count += (l2d4_cmp_clkstp_pedge_cnt > 1); | |
| 2667 | count += (l2d5_cmp_clkstp_pedge_cnt > 1); | |
| 2668 | count += (l2d6_cmp_clkstp_pedge_cnt > 1); | |
| 2669 | count += (l2d7_cmp_clkstp_pedge_cnt > 1); | |
| 2670 | count += (l2t0_cmp_clkstp_pedge_cnt > 1); | |
| 2671 | count += (l2t1_cmp_clkstp_pedge_cnt > 1); | |
| 2672 | count += (l2t2_cmp_clkstp_pedge_cnt > 1); | |
| 2673 | count += (l2t3_cmp_clkstp_pedge_cnt > 1); | |
| 2674 | count += (l2t4_cmp_clkstp_pedge_cnt > 1); | |
| 2675 | count += (l2t5_cmp_clkstp_pedge_cnt > 1); | |
| 2676 | count += (l2t6_cmp_clkstp_pedge_cnt > 1); | |
| 2677 | count += (l2t7_cmp_clkstp_pedge_cnt > 1); | |
| 2678 | #ifndef FC_NO_NIU_T2 | |
| 2679 | #ifndef NIU_SYSTEMC_T2 | |
| 2680 | count += (mac_io_clkstp_pedge_cnt > 1); | |
| 2681 | #endif | |
| 2682 | #endif | |
| 2683 | count += (mcu0_cmp_clkstp_pedge_cnt > 1); | |
| 2684 | count += (mcu0_dr_clkstp_pedge_cnt > 1); | |
| 2685 | count += (mcu0_io_clkstp_pedge_cnt > 1); | |
| 2686 | count += (mcu1_cmp_clkstp_pedge_cnt > 1); | |
| 2687 | count += (mcu1_dr_clkstp_pedge_cnt > 1); | |
| 2688 | count += (mcu1_io_clkstp_pedge_cnt > 1); | |
| 2689 | count += (mcu2_cmp_clkstp_pedge_cnt > 1); | |
| 2690 | count += (mcu2_dr_clkstp_pedge_cnt > 1); | |
| 2691 | count += (mcu2_io_clkstp_pedge_cnt > 1); | |
| 2692 | count += (mcu3_cmp_clkstp_pedge_cnt > 1); | |
| 2693 | count += (mcu3_dr_clkstp_pedge_cnt > 1); | |
| 2694 | count += (mcu3_io_clkstp_pedge_cnt > 1); | |
| 2695 | count += (mio_0_cmp_clkstp_pedge_cnt > 1); | |
| 2696 | count += (mio_1_cmp_clkstp_pedge_cnt > 1); | |
| 2697 | count += (mio_2_cmp_clkstp_pedge_cnt > 1); | |
| 2698 | count += (mio_3_cmp_clkstp_pedge_cnt > 1); | |
| 2699 | count += (mio_io_clkstp_pedge_cnt > 1); | |
| 2700 | count += (ncu_cmp_clkstp_pedge_cnt > 1); | |
| 2701 | count += (ncu_io_clkstp_pedge_cnt > 1); | |
| 2702 | #ifndef FC_NO_PEU_VERA | |
| 2703 | #ifndef PEU_SYSTEMC_T2 | |
| 2704 | count += (peu_io_clkstp_pedge_cnt > 1); | |
| 2705 | count += (peu_pc_clkstp_pedge_cnt > 1); | |
| 2706 | #endif | |
| 2707 | #endif | |
| 2708 | #ifndef FC_NO_NIU_T2 | |
| 2709 | #ifndef NIU_SYSTEMC_T2 | |
| 2710 | count += (rdp_io2x_clkstp_pedge_cnt > 1); | |
| 2711 | count += (rdp_io_clkstp_pedge_cnt > 1); | |
| 2712 | count += (rtx_io2x_clkstp_pedge_cnt > 1); | |
| 2713 | count += (rtx_io_clkstp_pedge_cnt > 1); | |
| 2714 | #endif | |
| 2715 | #endif | |
| 2716 | count += (rst_cmp_clkstp_pedge_cnt > 1); | |
| 2717 | count += (rst_io_clkstp_pedge_cnt > 1); | |
| 2718 | count += (sii_cmp_clkstp_pedge_cnt > 1); | |
| 2719 | count += (sii_io_clkstp_pedge_cnt > 1); | |
| 2720 | count += (sio_cmp_clkstp_pedge_cnt > 1); | |
| 2721 | count += (sio_io_clkstp_pedge_cnt > 1); | |
| 2722 | count += (spc0_cmp_clkstp_pedge_cnt > 1); | |
| 2723 | count += (spc1_cmp_clkstp_pedge_cnt > 1); | |
| 2724 | count += (spc2_cmp_clkstp_pedge_cnt > 1); | |
| 2725 | count += (spc3_cmp_clkstp_pedge_cnt > 1); | |
| 2726 | count += (spc4_cmp_clkstp_pedge_cnt > 1); | |
| 2727 | count += (spc5_cmp_clkstp_pedge_cnt > 1); | |
| 2728 | count += (spc6_cmp_clkstp_pedge_cnt > 1); | |
| 2729 | count += (spc7_cmp_clkstp_pedge_cnt > 1); | |
| 2730 | count += (tcu_cmp_clkstp_pedge_cnt > 1); | |
| 2731 | count += (tcu_io_clkstp_pedge_cnt > 1); | |
| 2732 | #ifndef FC_NO_NIU_T2 | |
| 2733 | #ifndef NIU_SYSTEMC_T2 | |
| 2734 | count += (tds_io2x_clkstp_pedge_cnt > 1); | |
| 2735 | count += (tds_io_clkstp_pedge_cnt > 1); | |
| 2736 | #endif | |
| 2737 | #endif | |
| 2738 | is_any_hdr_clkstp_pedge_more_once = (count)? 1 : 0; | |
| 2739 | } | |
| 2740 | ||
| 2741 | //======================================================================== | |
| 2742 | // | |
| 2743 | //======================================================================== | |
| 2744 | function integer CLUSTER_hdrs_mon::is_any_hdr_clkstp_nedge_more_once() { | |
| 2745 | integer count = 0; | |
| 2746 | ||
| 2747 | count += (ccu_cmp_clkstp_nedge_cnt > 1); | |
| 2748 | count += (ccu_io_clkstp_nedge_cnt > 1); | |
| 2749 | count += (ccx_cmp_clkstp_nedge_cnt > 1); | |
| 2750 | count += (db0_cmp_clkstp_nedge_cnt > 1); | |
| 2751 | count += (db0_io_clkstp_nedge_cnt > 1); | |
| 2752 | count += (db1_cmp_clkstp_nedge_cnt > 1); | |
| 2753 | count += (db1_io_clkstp_nedge_cnt > 1); | |
| 2754 | count += (dmu_io_clkstp_nedge_cnt > 1); | |
| 2755 | count += (efu_cmp_clkstp_nedge_cnt > 1); | |
| 2756 | count += (efu_io_clkstp_nedge_cnt > 1); | |
| 2757 | count += (l2b0_cmp_clkstp_nedge_cnt > 1); | |
| 2758 | count += (l2b1_cmp_clkstp_nedge_cnt > 1); | |
| 2759 | count += (l2b2_cmp_clkstp_nedge_cnt > 1); | |
| 2760 | count += (l2b3_cmp_clkstp_nedge_cnt > 1); | |
| 2761 | count += (l2b4_cmp_clkstp_nedge_cnt > 1); | |
| 2762 | count += (l2b5_cmp_clkstp_nedge_cnt > 1); | |
| 2763 | count += (l2b6_cmp_clkstp_nedge_cnt > 1); | |
| 2764 | count += (l2b7_cmp_clkstp_nedge_cnt > 1); | |
| 2765 | count += (l2d0_cmp_clkstp_nedge_cnt > 1); | |
| 2766 | count += (l2d1_cmp_clkstp_nedge_cnt > 1); | |
| 2767 | count += (l2d2_cmp_clkstp_nedge_cnt > 1); | |
| 2768 | count += (l2d3_cmp_clkstp_nedge_cnt > 1); | |
| 2769 | count += (l2d4_cmp_clkstp_nedge_cnt > 1); | |
| 2770 | count += (l2d5_cmp_clkstp_nedge_cnt > 1); | |
| 2771 | count += (l2d6_cmp_clkstp_nedge_cnt > 1); | |
| 2772 | count += (l2d7_cmp_clkstp_nedge_cnt > 1); | |
| 2773 | count += (l2t0_cmp_clkstp_nedge_cnt > 1); | |
| 2774 | count += (l2t1_cmp_clkstp_nedge_cnt > 1); | |
| 2775 | count += (l2t2_cmp_clkstp_nedge_cnt > 1); | |
| 2776 | count += (l2t3_cmp_clkstp_nedge_cnt > 1); | |
| 2777 | count += (l2t4_cmp_clkstp_nedge_cnt > 1); | |
| 2778 | count += (l2t5_cmp_clkstp_nedge_cnt > 1); | |
| 2779 | count += (l2t6_cmp_clkstp_nedge_cnt > 1); | |
| 2780 | count += (l2t7_cmp_clkstp_nedge_cnt > 1); | |
| 2781 | #ifndef FC_NO_NIU_T2 | |
| 2782 | #ifndef NIU_SYSTEMC_T2 | |
| 2783 | count += (mac_io_clkstp_nedge_cnt > 1); | |
| 2784 | #endif | |
| 2785 | #endif | |
| 2786 | count += (mcu0_cmp_clkstp_nedge_cnt > 1); | |
| 2787 | count += (mcu0_dr_clkstp_nedge_cnt > 1); | |
| 2788 | count += (mcu0_io_clkstp_nedge_cnt > 1); | |
| 2789 | count += (mcu1_cmp_clkstp_nedge_cnt > 1); | |
| 2790 | count += (mcu1_dr_clkstp_nedge_cnt > 1); | |
| 2791 | count += (mcu1_io_clkstp_nedge_cnt > 1); | |
| 2792 | count += (mcu2_cmp_clkstp_nedge_cnt > 1); | |
| 2793 | count += (mcu2_dr_clkstp_nedge_cnt > 1); | |
| 2794 | count += (mcu2_io_clkstp_nedge_cnt > 1); | |
| 2795 | count += (mcu3_cmp_clkstp_nedge_cnt > 1); | |
| 2796 | count += (mcu3_dr_clkstp_nedge_cnt > 1); | |
| 2797 | count += (mcu3_io_clkstp_nedge_cnt > 1); | |
| 2798 | count += (mio_0_cmp_clkstp_nedge_cnt > 1); | |
| 2799 | count += (mio_1_cmp_clkstp_nedge_cnt > 1); | |
| 2800 | count += (mio_2_cmp_clkstp_nedge_cnt > 1); | |
| 2801 | count += (mio_3_cmp_clkstp_nedge_cnt > 1); | |
| 2802 | count += (mio_io_clkstp_nedge_cnt > 1); | |
| 2803 | count += (ncu_cmp_clkstp_nedge_cnt > 1); | |
| 2804 | count += (ncu_io_clkstp_nedge_cnt > 1); | |
| 2805 | #ifndef FC_NO_PEU_VERA | |
| 2806 | #ifndef PEU_SYSTEMC_T2 | |
| 2807 | count += (peu_io_clkstp_nedge_cnt > 1); | |
| 2808 | count += (peu_pc_clkstp_nedge_cnt > 1); | |
| 2809 | #endif | |
| 2810 | #endif | |
| 2811 | #ifndef FC_NO_NIU_T2 | |
| 2812 | #ifndef NIU_SYSTEMC_T2 | |
| 2813 | count += (rdp_io2x_clkstp_nedge_cnt > 1); | |
| 2814 | count += (rdp_io_clkstp_nedge_cnt > 1); | |
| 2815 | count += (rtx_io2x_clkstp_nedge_cnt > 1); | |
| 2816 | count += (rtx_io_clkstp_nedge_cnt > 1); | |
| 2817 | #endif | |
| 2818 | #endif | |
| 2819 | count += (rst_cmp_clkstp_nedge_cnt > 1); | |
| 2820 | count += (rst_io_clkstp_nedge_cnt > 1); | |
| 2821 | count += (sii_cmp_clkstp_nedge_cnt > 1); | |
| 2822 | count += (sii_io_clkstp_nedge_cnt > 1); | |
| 2823 | count += (sio_cmp_clkstp_nedge_cnt > 1); | |
| 2824 | count += (sio_io_clkstp_nedge_cnt > 1); | |
| 2825 | count += (spc0_cmp_clkstp_nedge_cnt > 1); | |
| 2826 | count += (spc1_cmp_clkstp_nedge_cnt > 1); | |
| 2827 | count += (spc2_cmp_clkstp_nedge_cnt > 1); | |
| 2828 | count += (spc3_cmp_clkstp_nedge_cnt > 1); | |
| 2829 | count += (spc4_cmp_clkstp_nedge_cnt > 1); | |
| 2830 | count += (spc5_cmp_clkstp_nedge_cnt > 1); | |
| 2831 | count += (spc6_cmp_clkstp_nedge_cnt > 1); | |
| 2832 | count += (spc7_cmp_clkstp_nedge_cnt > 1); | |
| 2833 | count += (tcu_cmp_clkstp_nedge_cnt > 1); | |
| 2834 | count += (tcu_io_clkstp_nedge_cnt > 1); | |
| 2835 | #ifndef FC_NO_NIU_T2 | |
| 2836 | #ifndef NIU_SYSTEMC_T2 | |
| 2837 | count += (tds_io2x_clkstp_nedge_cnt > 1); | |
| 2838 | count += (tds_io_clkstp_nedge_cnt > 1); | |
| 2839 | #endif | |
| 2840 | #endif | |
| 2841 | is_any_hdr_clkstp_nedge_more_once = (count)? 1 : 0; | |
| 2842 | } | |
| 2843 | ||
| 2844 | //======================================================================== | |
| 2845 | // WHAT: return 1 if all l2clk are running, else return 0. | |
| 2846 | // l2lck is NOT running if the timestamp *_l2clk_pedge is OLDER than 1 sys clk period. | |
| 2847 | //======================================================================== | |
| 2848 | function integer CLUSTER_hdrs_mon::is_all_l2clk_running() { | |
| 2849 | integer count = 0; // counter for l2clk is NOT running | |
| 2850 | integer curr_time = get_time(LO); | |
| 2851 | ||
| 2852 | count += ((curr_time - ccu_cmp_l2clk_pedge) > sysclk_per); | |
| 2853 | count += ((curr_time - ccu_io_l2clk_pedge) > sysclk_per); | |
| 2854 | count += ((curr_time - ccx_cmp_l2clk_pedge) > sysclk_per); | |
| 2855 | count += ((curr_time - db0_cmp_l2clk_pedge) > sysclk_per); | |
| 2856 | count += ((curr_time - db0_io_l2clk_pedge) > sysclk_per); | |
| 2857 | count += ((curr_time - db1_cmp_l2clk_pedge) > sysclk_per); | |
| 2858 | count += ((curr_time - db1_io_l2clk_pedge) > sysclk_per); | |
| 2859 | count += ((curr_time - dmu_io_l2clk_pedge) > sysclk_per); | |
| 2860 | count += ((curr_time - efu_cmp_l2clk_pedge) > sysclk_per); | |
| 2861 | count += ((curr_time - efu_io_l2clk_pedge) > sysclk_per); | |
| 2862 | count += ((curr_time - l2b0_cmp_l2clk_pedge) > sysclk_per); | |
| 2863 | count += ((curr_time - l2b1_cmp_l2clk_pedge) > sysclk_per); | |
| 2864 | count += ((curr_time - l2b2_cmp_l2clk_pedge) > sysclk_per); | |
| 2865 | count += ((curr_time - l2b3_cmp_l2clk_pedge) > sysclk_per); | |
| 2866 | count += ((curr_time - l2b4_cmp_l2clk_pedge) > sysclk_per); | |
| 2867 | count += ((curr_time - l2b5_cmp_l2clk_pedge) > sysclk_per); | |
| 2868 | count += ((curr_time - l2b6_cmp_l2clk_pedge) > sysclk_per); | |
| 2869 | count += ((curr_time - l2b7_cmp_l2clk_pedge) > sysclk_per); | |
| 2870 | count += ((curr_time - l2d0_cmp_l2clk_pedge) > sysclk_per); | |
| 2871 | count += ((curr_time - l2d1_cmp_l2clk_pedge) > sysclk_per); | |
| 2872 | count += ((curr_time - l2d2_cmp_l2clk_pedge) > sysclk_per); | |
| 2873 | count += ((curr_time - l2d3_cmp_l2clk_pedge) > sysclk_per); | |
| 2874 | count += ((curr_time - l2d4_cmp_l2clk_pedge) > sysclk_per); | |
| 2875 | count += ((curr_time - l2d5_cmp_l2clk_pedge) > sysclk_per); | |
| 2876 | count += ((curr_time - l2d6_cmp_l2clk_pedge) > sysclk_per); | |
| 2877 | count += ((curr_time - l2d7_cmp_l2clk_pedge) > sysclk_per); | |
| 2878 | count += ((curr_time - l2t0_cmp_l2clk_pedge) > sysclk_per); | |
| 2879 | count += ((curr_time - l2t1_cmp_l2clk_pedge) > sysclk_per); | |
| 2880 | count += ((curr_time - l2t2_cmp_l2clk_pedge) > sysclk_per); | |
| 2881 | count += ((curr_time - l2t3_cmp_l2clk_pedge) > sysclk_per); | |
| 2882 | count += ((curr_time - l2t4_cmp_l2clk_pedge) > sysclk_per); | |
| 2883 | count += ((curr_time - l2t5_cmp_l2clk_pedge) > sysclk_per); | |
| 2884 | count += ((curr_time - l2t6_cmp_l2clk_pedge) > sysclk_per); | |
| 2885 | count += ((curr_time - l2t7_cmp_l2clk_pedge) > sysclk_per); | |
| 2886 | #ifndef FC_NO_NIU_T2 | |
| 2887 | #ifndef NIU_SYSTEMC_T2 | |
| 2888 | count += ((curr_time - mac_io_l2clk_pedge) > sysclk_per); | |
| 2889 | #endif | |
| 2890 | #endif | |
| 2891 | count += ((curr_time - mcu0_cmp_l2clk_pedge) > sysclk_per); | |
| 2892 | count += ((curr_time - mcu0_dr_l2clk_pedge) > sysclk_per); | |
| 2893 | count += ((curr_time - mcu0_io_l2clk_pedge) > sysclk_per); | |
| 2894 | count += ((curr_time - mcu1_cmp_l2clk_pedge) > sysclk_per); | |
| 2895 | count += ((curr_time - mcu1_dr_l2clk_pedge) > sysclk_per); | |
| 2896 | count += ((curr_time - mcu1_io_l2clk_pedge) > sysclk_per); | |
| 2897 | count += ((curr_time - mcu2_cmp_l2clk_pedge) > sysclk_per); | |
| 2898 | count += ((curr_time - mcu2_dr_l2clk_pedge) > sysclk_per); | |
| 2899 | count += ((curr_time - mcu2_io_l2clk_pedge) > sysclk_per); | |
| 2900 | count += ((curr_time - mcu3_cmp_l2clk_pedge) > sysclk_per); | |
| 2901 | count += ((curr_time - mcu3_dr_l2clk_pedge) > sysclk_per); | |
| 2902 | count += ((curr_time - mcu3_io_l2clk_pedge) > sysclk_per); | |
| 2903 | count += ((curr_time - mio_0_cmp_l2clk_pedge) > sysclk_per); | |
| 2904 | count += ((curr_time - mio_1_cmp_l2clk_pedge) > sysclk_per); | |
| 2905 | count += ((curr_time - mio_2_cmp_l2clk_pedge) > sysclk_per); | |
| 2906 | count += ((curr_time - mio_3_cmp_l2clk_pedge) > sysclk_per); | |
| 2907 | count += ((curr_time - mio_io_l2clk_pedge) > sysclk_per); | |
| 2908 | count += ((curr_time - ncu_cmp_l2clk_pedge) > sysclk_per); | |
| 2909 | count += ((curr_time - ncu_io_l2clk_pedge) > sysclk_per); | |
| 2910 | #ifndef FC_NO_PEU_VERA | |
| 2911 | #ifndef PEU_SYSTEMC_T2 | |
| 2912 | count += ((curr_time - peu_io_l2clk_pedge) > sysclk_per); | |
| 2913 | count += ((curr_time - peu_pc_l2clk_pedge) > sysclk_per); | |
| 2914 | #endif | |
| 2915 | #endif | |
| 2916 | #ifndef FC_NO_NIU_T2 | |
| 2917 | #ifndef NIU_SYSTEMC_T2 | |
| 2918 | count += ((curr_time - rdp_io2x_l2clk_pedge) > sysclk_per); | |
| 2919 | count += ((curr_time - rdp_io_l2clk_pedge) > sysclk_per); | |
| 2920 | count += ((curr_time - rtx_io2x_l2clk_pedge) > sysclk_per); | |
| 2921 | count += ((curr_time - rtx_io_l2clk_pedge) > sysclk_per); | |
| 2922 | #endif | |
| 2923 | #endif | |
| 2924 | count += ((curr_time - rst_cmp_l2clk_pedge) > sysclk_per); | |
| 2925 | count += ((curr_time - rst_io_l2clk_pedge) > sysclk_per); | |
| 2926 | count += ((curr_time - sii_cmp_l2clk_pedge) > sysclk_per); | |
| 2927 | count += ((curr_time - sii_io_l2clk_pedge) > sysclk_per); | |
| 2928 | count += ((curr_time - sio_cmp_l2clk_pedge) > sysclk_per); | |
| 2929 | count += ((curr_time - sio_io_l2clk_pedge) > sysclk_per); | |
| 2930 | #ifndef RTL_NO_SPC0 | |
| 2931 | count += ((curr_time - spc0_cmp_l2clk_pedge) > sysclk_per); | |
| 2932 | #endif | |
| 2933 | #ifndef RTL_NO_SPC1 | |
| 2934 | count += ((curr_time - spc1_cmp_l2clk_pedge) > sysclk_per); | |
| 2935 | #endif | |
| 2936 | #ifndef RTL_NO_SPC2 | |
| 2937 | count += ((curr_time - spc2_cmp_l2clk_pedge) > sysclk_per); | |
| 2938 | #endif | |
| 2939 | #ifndef RTL_NO_SPC3 | |
| 2940 | count += ((curr_time - spc3_cmp_l2clk_pedge) > sysclk_per); | |
| 2941 | #endif | |
| 2942 | #ifndef RTL_NO_SPC4 | |
| 2943 | count += ((curr_time - spc4_cmp_l2clk_pedge) > sysclk_per); | |
| 2944 | #endif | |
| 2945 | #ifndef RTL_NO_SPC5 | |
| 2946 | count += ((curr_time - spc5_cmp_l2clk_pedge) > sysclk_per); | |
| 2947 | #endif | |
| 2948 | #ifndef RTL_NO_SPC6 | |
| 2949 | count += ((curr_time - spc6_cmp_l2clk_pedge) > sysclk_per); | |
| 2950 | #endif | |
| 2951 | #ifndef RTL_NO_SPC7 | |
| 2952 | count += ((curr_time - spc7_cmp_l2clk_pedge) > sysclk_per); | |
| 2953 | #endif | |
| 2954 | count += ((curr_time - tcu_cmp_l2clk_pedge) > sysclk_per); | |
| 2955 | count += ((curr_time - tcu_io_l2clk_pedge) > sysclk_per); | |
| 2956 | #ifndef FC_NO_NIU_T2 | |
| 2957 | #ifndef NIU_SYSTEMC_T2 | |
| 2958 | count += ((curr_time - tds_io2x_l2clk_pedge) > sysclk_per); | |
| 2959 | count += ((curr_time - tds_io_l2clk_pedge) > sysclk_per); | |
| 2960 | #endif | |
| 2961 | #endif | |
| 2962 | is_all_l2clk_running = (count)? 0 : 1; // function return value | |
| 2963 | } | |
| 2964 | ||
| 2965 | //======================================================================== | |
| 2966 | // WHAT: return 1 if l2clk of all headers, except ccu/rst/tcu headers, are stopped. | |
| 2967 | // l2lck is running if the timestamp *_l2clk_pedge is NEWER than one sys clk per. | |
| 2968 | //======================================================================== | |
| 2969 | function integer CLUSTER_hdrs_mon::is_all_l2clk_stopped() { | |
| 2970 | integer count = 0; // counter for l2clk is NOT stopped (ie. running) | |
| 2971 | integer curr_time = get_time(LO); | |
| 2972 | ||
| 2973 | //count += ((curr_time - ccu_cmp_l2clk_pedge) < sysclk_per); // always running | |
| 2974 | //count += ((curr_time - ccu_io_l2clk_pedge) < sysclk_per); // always running | |
| 2975 | count += ((curr_time - ccx_cmp_l2clk_pedge) < sysclk_per); | |
| 2976 | count += ((curr_time - db0_cmp_l2clk_pedge) < sysclk_per); | |
| 2977 | count += ((curr_time - db0_io_l2clk_pedge) < sysclk_per); | |
| 2978 | count += ((curr_time - db1_cmp_l2clk_pedge) < sysclk_per); | |
| 2979 | count += ((curr_time - db1_io_l2clk_pedge) < sysclk_per); | |
| 2980 | count += ((curr_time - dmu_io_l2clk_pedge) < sysclk_per); | |
| 2981 | count += ((curr_time - efu_cmp_l2clk_pedge) < sysclk_per); | |
| 2982 | count += ((curr_time - efu_io_l2clk_pedge) < sysclk_per); | |
| 2983 | count += ((curr_time - l2b0_cmp_l2clk_pedge) < sysclk_per); | |
| 2984 | count += ((curr_time - l2b1_cmp_l2clk_pedge) < sysclk_per); | |
| 2985 | count += ((curr_time - l2b2_cmp_l2clk_pedge) < sysclk_per); | |
| 2986 | count += ((curr_time - l2b3_cmp_l2clk_pedge) < sysclk_per); | |
| 2987 | count += ((curr_time - l2b4_cmp_l2clk_pedge) < sysclk_per); | |
| 2988 | count += ((curr_time - l2b5_cmp_l2clk_pedge) < sysclk_per); | |
| 2989 | count += ((curr_time - l2b6_cmp_l2clk_pedge) < sysclk_per); | |
| 2990 | count += ((curr_time - l2b7_cmp_l2clk_pedge) < sysclk_per); | |
| 2991 | count += ((curr_time - l2d0_cmp_l2clk_pedge) < sysclk_per); | |
| 2992 | count += ((curr_time - l2d1_cmp_l2clk_pedge) < sysclk_per); | |
| 2993 | count += ((curr_time - l2d2_cmp_l2clk_pedge) < sysclk_per); | |
| 2994 | count += ((curr_time - l2d3_cmp_l2clk_pedge) < sysclk_per); | |
| 2995 | count += ((curr_time - l2d4_cmp_l2clk_pedge) < sysclk_per); | |
| 2996 | count += ((curr_time - l2d5_cmp_l2clk_pedge) < sysclk_per); | |
| 2997 | count += ((curr_time - l2d6_cmp_l2clk_pedge) < sysclk_per); | |
| 2998 | count += ((curr_time - l2d7_cmp_l2clk_pedge) < sysclk_per); | |
| 2999 | count += ((curr_time - l2t0_cmp_l2clk_pedge) < sysclk_per); | |
| 3000 | count += ((curr_time - l2t1_cmp_l2clk_pedge) < sysclk_per); | |
| 3001 | count += ((curr_time - l2t2_cmp_l2clk_pedge) < sysclk_per); | |
| 3002 | count += ((curr_time - l2t3_cmp_l2clk_pedge) < sysclk_per); | |
| 3003 | count += ((curr_time - l2t4_cmp_l2clk_pedge) < sysclk_per); | |
| 3004 | count += ((curr_time - l2t5_cmp_l2clk_pedge) < sysclk_per); | |
| 3005 | count += ((curr_time - l2t6_cmp_l2clk_pedge) < sysclk_per); | |
| 3006 | count += ((curr_time - l2t7_cmp_l2clk_pedge) < sysclk_per); | |
| 3007 | #ifndef FC_NO_NIU_T2 | |
| 3008 | #ifndef NIU_SYSTEMC_T2 | |
| 3009 | count += ((curr_time - mac_io_l2clk_pedge) < sysclk_per); | |
| 3010 | #endif | |
| 3011 | #endif | |
| 3012 | count += ((curr_time - mcu0_cmp_l2clk_pedge) < sysclk_per); | |
| 3013 | count += ((curr_time - mcu0_dr_l2clk_pedge) < sysclk_per); | |
| 3014 | count += ((curr_time - mcu0_io_l2clk_pedge) < sysclk_per); | |
| 3015 | count += ((curr_time - mcu1_cmp_l2clk_pedge) < sysclk_per); | |
| 3016 | count += ((curr_time - mcu1_dr_l2clk_pedge) < sysclk_per); | |
| 3017 | count += ((curr_time - mcu1_io_l2clk_pedge) < sysclk_per); | |
| 3018 | count += ((curr_time - mcu2_cmp_l2clk_pedge) < sysclk_per); | |
| 3019 | count += ((curr_time - mcu2_dr_l2clk_pedge) < sysclk_per); | |
| 3020 | count += ((curr_time - mcu2_io_l2clk_pedge) < sysclk_per); | |
| 3021 | count += ((curr_time - mcu3_cmp_l2clk_pedge) < sysclk_per); | |
| 3022 | count += ((curr_time - mcu3_dr_l2clk_pedge) < sysclk_per); | |
| 3023 | count += ((curr_time - mcu3_io_l2clk_pedge) < sysclk_per); | |
| 3024 | count += ((curr_time - mio_0_cmp_l2clk_pedge) < sysclk_per); | |
| 3025 | count += ((curr_time - mio_1_cmp_l2clk_pedge) < sysclk_per); | |
| 3026 | count += ((curr_time - mio_2_cmp_l2clk_pedge) < sysclk_per); | |
| 3027 | count += ((curr_time - mio_3_cmp_l2clk_pedge) < sysclk_per); | |
| 3028 | count += ((curr_time - mio_io_l2clk_pedge) < sysclk_per); | |
| 3029 | count += ((curr_time - ncu_cmp_l2clk_pedge) < sysclk_per); | |
| 3030 | count += ((curr_time - ncu_io_l2clk_pedge) < sysclk_per); | |
| 3031 | #ifndef FC_NO_PEU_VERA | |
| 3032 | #ifndef PEU_SYSTEMC_T2 | |
| 3033 | count += ((curr_time - peu_io_l2clk_pedge) < sysclk_per); | |
| 3034 | count += ((curr_time - peu_pc_l2clk_pedge) < sysclk_per); | |
| 3035 | #endif | |
| 3036 | #endif | |
| 3037 | #ifndef FC_NO_NIU_T2 | |
| 3038 | #ifndef NIU_SYSTEMC_T2 | |
| 3039 | count += ((curr_time - rdp_io2x_l2clk_pedge) < sysclk_per); | |
| 3040 | count += ((curr_time - rdp_io_l2clk_pedge) < sysclk_per); | |
| 3041 | count += ((curr_time - rtx_io2x_l2clk_pedge) < sysclk_per); | |
| 3042 | count += ((curr_time - rtx_io_l2clk_pedge) < sysclk_per); | |
| 3043 | #endif | |
| 3044 | #endif | |
| 3045 | //count += ((curr_time - rst_cmp_l2clk_pedge) < sysclk_per); // always running | |
| 3046 | //count += ((curr_time - rst_io_l2clk_pedge) < sysclk_per); // always running | |
| 3047 | count += ((curr_time - sii_cmp_l2clk_pedge) < sysclk_per); | |
| 3048 | count += ((curr_time - sii_io_l2clk_pedge) < sysclk_per); | |
| 3049 | count += ((curr_time - sio_cmp_l2clk_pedge) < sysclk_per); | |
| 3050 | count += ((curr_time - sio_io_l2clk_pedge) < sysclk_per); | |
| 3051 | #ifndef RTL_NO_SPC0 | |
| 3052 | count += ((curr_time - spc0_cmp_l2clk_pedge) < sysclk_per); | |
| 3053 | #endif | |
| 3054 | #ifndef RTL_NO_SPC1 | |
| 3055 | count += ((curr_time - spc1_cmp_l2clk_pedge) < sysclk_per); | |
| 3056 | #endif | |
| 3057 | #ifndef RTL_NO_SPC2 | |
| 3058 | count += ((curr_time - spc2_cmp_l2clk_pedge) < sysclk_per); | |
| 3059 | #endif | |
| 3060 | #ifndef RTL_NO_SPC3 | |
| 3061 | count += ((curr_time - spc3_cmp_l2clk_pedge) < sysclk_per); | |
| 3062 | #endif | |
| 3063 | #ifndef RTL_NO_SPC4 | |
| 3064 | count += ((curr_time - spc4_cmp_l2clk_pedge) < sysclk_per); | |
| 3065 | #endif | |
| 3066 | #ifndef RTL_NO_SPC5 | |
| 3067 | count += ((curr_time - spc5_cmp_l2clk_pedge) < sysclk_per); | |
| 3068 | #endif | |
| 3069 | #ifndef RTL_NO_SPC6 | |
| 3070 | count += ((curr_time - spc6_cmp_l2clk_pedge) < sysclk_per); | |
| 3071 | #endif | |
| 3072 | #ifndef RTL_NO_SPC7 | |
| 3073 | count += ((curr_time - spc7_cmp_l2clk_pedge) < sysclk_per); | |
| 3074 | #endif | |
| 3075 | //count += ((curr_time - tcu_cmp_l2clk_pedge) < sysclk_per); // always running | |
| 3076 | //count += ((curr_time - tcu_io_l2clk_pedge) < sysclk_per); // always running | |
| 3077 | #ifndef FC_NO_NIU_T2 | |
| 3078 | #ifndef NIU_SYSTEMC_T2 | |
| 3079 | count += ((curr_time - tds_io2x_l2clk_pedge) < sysclk_per); | |
| 3080 | count += ((curr_time - tds_io_l2clk_pedge) < sysclk_per); | |
| 3081 | #endif | |
| 3082 | #endif | |
| 3083 | is_all_l2clk_stopped = (count)? 0 : 1; // function return value | |
| 3084 | } | |
| 3085 | ||
| 3086 | //################################################################# | |
| 3087 | //################################################################# | |
| 3088 | //####### tasks that check/use the rtl signals ########## | |
| 3089 | //################################################################# | |
| 3090 | //################################################################# | |
| 3091 | ||
| 3092 | //======================================================================== | |
| 3093 | // WHAT: return 1 if tcu_clk_stop of all headers are asserted, except hdrs | |
| 3094 | // in ccu, rst and tcu. | |
| 3095 | //======================================================================== | |
| 3096 | function integer CLUSTER_hdrs_mon::is_all_clkstp_sigs_asserted() { | |
| 3097 | integer count = 0; // counter for hdr that clk_stop is NOT asserted | |
| 3098 | ||
| 3099 | //count += (clkgen_ccu_cmp_port.$tcu_clk_stop__gclk != 1); // never stop | |
| 3100 | //count += (clkgen_ccu_io_port.$tcu_clk_stop__gclk != 1); // never stop | |
| 3101 | count += (clkgen_ccx_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3102 | count += (clkgen_db0_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3103 | count += (clkgen_db0_io_port.$tcu_clk_stop__gclk != 1); | |
| 3104 | count += (clkgen_db1_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3105 | count += (clkgen_db1_io_port.$tcu_clk_stop__gclk != 1); | |
| 3106 | count += (clkgen_dmu_io_port.$tcu_clk_stop__gclk != 1); | |
| 3107 | count += (clkgen_efu_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3108 | count += (clkgen_efu_io_port.$tcu_clk_stop__gclk != 1); | |
| 3109 | count += (clkgen_l2b0_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3110 | count += (clkgen_l2b1_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3111 | count += (clkgen_l2b2_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3112 | count += (clkgen_l2b3_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3113 | count += (clkgen_l2b4_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3114 | count += (clkgen_l2b5_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3115 | count += (clkgen_l2b6_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3116 | count += (clkgen_l2b7_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3117 | count += (clkgen_l2d0_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3118 | count += (clkgen_l2d1_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3119 | count += (clkgen_l2d2_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3120 | count += (clkgen_l2d3_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3121 | count += (clkgen_l2d4_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3122 | count += (clkgen_l2d5_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3123 | count += (clkgen_l2d6_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3124 | count += (clkgen_l2d7_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3125 | count += (clkgen_l2t0_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3126 | count += (clkgen_l2t1_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3127 | count += (clkgen_l2t2_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3128 | count += (clkgen_l2t3_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3129 | count += (clkgen_l2t4_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3130 | count += (clkgen_l2t5_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3131 | count += (clkgen_l2t6_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3132 | count += (clkgen_l2t7_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3133 | #ifndef FC_NO_NIU_T2 | |
| 3134 | #ifndef NIU_SYSTEMC_T2 | |
| 3135 | count += (clkgen_mac_io_port.$tcu_clk_stop__gclk != 1); | |
| 3136 | #endif | |
| 3137 | #endif | |
| 3138 | count += (clkgen_mcu0_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3139 | count += (clkgen_mcu0_dr_port.$tcu_clk_stop__gclk != 1); | |
| 3140 | count += (clkgen_mcu0_io_port.$tcu_clk_stop__gclk != 1); | |
| 3141 | count += (clkgen_mcu1_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3142 | count += (clkgen_mcu1_dr_port.$tcu_clk_stop__gclk != 1); | |
| 3143 | count += (clkgen_mcu1_io_port.$tcu_clk_stop__gclk != 1); | |
| 3144 | count += (clkgen_mcu2_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3145 | count += (clkgen_mcu2_dr_port.$tcu_clk_stop__gclk != 1); | |
| 3146 | count += (clkgen_mcu2_io_port.$tcu_clk_stop__gclk != 1); | |
| 3147 | count += (clkgen_mcu3_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3148 | count += (clkgen_mcu3_dr_port.$tcu_clk_stop__gclk != 1); | |
| 3149 | count += (clkgen_mcu3_io_port.$tcu_clk_stop__gclk != 1); | |
| 3150 | count += (clkgen_mio_0_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3151 | count += (clkgen_mio_1_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3152 | count += (clkgen_mio_2_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3153 | count += (clkgen_mio_3_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3154 | count += (clkgen_mio_io_port.$tcu_clk_stop__gclk != 1); | |
| 3155 | count += (clkgen_ncu_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3156 | count += (clkgen_ncu_io_port.$tcu_clk_stop__gclk != 1); | |
| 3157 | #ifndef FC_NO_PEU_VERA | |
| 3158 | #ifndef PEU_SYSTEMC_T2 | |
| 3159 | count += (clkgen_peu_io_port.$tcu_clk_stop__gclk != 1); | |
| 3160 | count += (clkgen_peu_pc_port.$tcu_clk_stop__gclk != 1); | |
| 3161 | #endif | |
| 3162 | #endif | |
| 3163 | #ifndef FC_NO_NIU_T2 | |
| 3164 | #ifndef NIU_SYSTEMC_T2 | |
| 3165 | count += (clkgen_rdp_io2x_port.$tcu_clk_stop__gclk != 1); | |
| 3166 | count += (clkgen_rdp_io_port.$tcu_clk_stop__gclk != 1); | |
| 3167 | count += (clkgen_rtx_io2x_port.$tcu_clk_stop__gclk != 1); | |
| 3168 | count += (clkgen_rtx_io_port.$tcu_clk_stop__gclk != 1); | |
| 3169 | #endif | |
| 3170 | #endif | |
| 3171 | //count += (clkgen_rst_cmp_port.$tcu_clk_stop__gclk != 1); // not stopped | |
| 3172 | //count += (clkgen_rst_io_port.$tcu_clk_stop__gclk != 1); // not stopped | |
| 3173 | count += (clkgen_sii_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3174 | count += (clkgen_sii_io_port.$tcu_clk_stop__gclk != 1); | |
| 3175 | count += (clkgen_sio_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3176 | count += (clkgen_sio_io_port.$tcu_clk_stop__gclk != 1); | |
| 3177 | #ifndef RTL_NO_SPC0 | |
| 3178 | count += (clkgen_spc0_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3179 | #endif | |
| 3180 | #ifndef RTL_NO_SPC1 | |
| 3181 | count += (clkgen_spc1_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3182 | #endif | |
| 3183 | #ifndef RTL_NO_SPC2 | |
| 3184 | count += (clkgen_spc2_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3185 | #endif | |
| 3186 | #ifndef RTL_NO_SPC3 | |
| 3187 | count += (clkgen_spc3_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3188 | #endif | |
| 3189 | #ifndef RTL_NO_SPC4 | |
| 3190 | count += (clkgen_spc4_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3191 | #endif | |
| 3192 | #ifndef RTL_NO_SPC5 | |
| 3193 | count += (clkgen_spc5_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3194 | #endif | |
| 3195 | #ifndef RTL_NO_SPC6 | |
| 3196 | count += (clkgen_spc6_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3197 | #endif | |
| 3198 | #ifndef RTL_NO_SPC7 | |
| 3199 | count += (clkgen_spc7_cmp_port.$tcu_clk_stop__gclk != 1); | |
| 3200 | #endif | |
| 3201 | //count += (clkgen_tcu_cmp_port.$tcu_clk_stop__gclk != 1); // not stopped | |
| 3202 | //count += (clkgen_tcu_io_port.$tcu_clk_stop__gclk != 1); // not stopped | |
| 3203 | #ifndef FC_NO_NIU_T2 | |
| 3204 | #ifndef NIU_SYSTEMC_T2 | |
| 3205 | count += (clkgen_tds_io2x_port.$tcu_clk_stop__gclk != 1); | |
| 3206 | count += (clkgen_tds_io_port.$tcu_clk_stop__gclk != 1); | |
| 3207 | #endif | |
| 3208 | #endif | |
| 3209 | is_all_clkstp_sigs_asserted = (count)? 0 : 1; // function return value | |
| 3210 | } | |
| 3211 | ||
| 3212 | //======================================================================== | |
| 3213 | // WHAT: return 1 if tcu_clk_stop of all headers are de-asserted, including | |
| 3214 | // ccu, rst and tcu headers. | |
| 3215 | //======================================================================== | |
| 3216 | function integer CLUSTER_hdrs_mon::is_all_clkstp_sigs_deasserted() { | |
| 3217 | integer count = 0; // counter for hdr that clk_stop is asserted | |
| 3218 | ||
| 3219 | count += (clkgen_ccu_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3220 | count += (clkgen_ccu_io_port.$tcu_clk_stop__gclk != 0); | |
| 3221 | count += (clkgen_ccx_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3222 | count += (clkgen_db0_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3223 | count += (clkgen_db0_io_port.$tcu_clk_stop__gclk != 0); | |
| 3224 | count += (clkgen_db1_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3225 | count += (clkgen_db1_io_port.$tcu_clk_stop__gclk != 0); | |
| 3226 | count += (clkgen_dmu_io_port.$tcu_clk_stop__gclk != 0); | |
| 3227 | count += (clkgen_efu_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3228 | count += (clkgen_efu_io_port.$tcu_clk_stop__gclk != 0); | |
| 3229 | count += (clkgen_l2b0_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3230 | count += (clkgen_l2b1_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3231 | count += (clkgen_l2b2_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3232 | count += (clkgen_l2b3_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3233 | count += (clkgen_l2b4_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3234 | count += (clkgen_l2b5_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3235 | count += (clkgen_l2b6_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3236 | count += (clkgen_l2b7_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3237 | count += (clkgen_l2d0_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3238 | count += (clkgen_l2d1_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3239 | count += (clkgen_l2d2_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3240 | count += (clkgen_l2d3_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3241 | count += (clkgen_l2d4_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3242 | count += (clkgen_l2d5_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3243 | count += (clkgen_l2d6_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3244 | count += (clkgen_l2d7_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3245 | count += (clkgen_l2t0_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3246 | count += (clkgen_l2t1_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3247 | count += (clkgen_l2t2_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3248 | count += (clkgen_l2t3_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3249 | count += (clkgen_l2t4_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3250 | count += (clkgen_l2t5_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3251 | count += (clkgen_l2t6_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3252 | count += (clkgen_l2t7_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3253 | #ifndef FC_NO_NIU_T2 | |
| 3254 | #ifndef NIU_SYSTEMC_T2 | |
| 3255 | count += (clkgen_mac_io_port.$tcu_clk_stop__gclk != 0); | |
| 3256 | #endif | |
| 3257 | #endif | |
| 3258 | count += (clkgen_mcu0_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3259 | count += (clkgen_mcu0_dr_port.$tcu_clk_stop__gclk != 0); | |
| 3260 | count += (clkgen_mcu0_io_port.$tcu_clk_stop__gclk != 0); | |
| 3261 | count += (clkgen_mcu1_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3262 | count += (clkgen_mcu1_dr_port.$tcu_clk_stop__gclk != 0); | |
| 3263 | count += (clkgen_mcu1_io_port.$tcu_clk_stop__gclk != 0); | |
| 3264 | count += (clkgen_mcu2_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3265 | count += (clkgen_mcu2_dr_port.$tcu_clk_stop__gclk != 0); | |
| 3266 | count += (clkgen_mcu2_io_port.$tcu_clk_stop__gclk != 0); | |
| 3267 | count += (clkgen_mcu3_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3268 | count += (clkgen_mcu3_dr_port.$tcu_clk_stop__gclk != 0); | |
| 3269 | count += (clkgen_mcu3_io_port.$tcu_clk_stop__gclk != 0); | |
| 3270 | count += (clkgen_mio_0_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3271 | count += (clkgen_mio_1_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3272 | count += (clkgen_mio_2_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3273 | count += (clkgen_mio_3_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3274 | count += (clkgen_mio_io_port.$tcu_clk_stop__gclk != 0); | |
| 3275 | count += (clkgen_ncu_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3276 | count += (clkgen_ncu_io_port.$tcu_clk_stop__gclk != 0); | |
| 3277 | #ifndef FC_NO_PEU_VERA | |
| 3278 | #ifndef PEU_SYSTEMC_T2 | |
| 3279 | count += (clkgen_peu_io_port.$tcu_clk_stop__gclk != 0); | |
| 3280 | count += (clkgen_peu_pc_port.$tcu_clk_stop__gclk != 0); | |
| 3281 | #endif | |
| 3282 | #endif | |
| 3283 | #ifndef FC_NO_NIU_T2 | |
| 3284 | #ifndef NIU_SYSTEMC_T2 | |
| 3285 | count += (clkgen_rdp_io2x_port.$tcu_clk_stop__gclk != 0); | |
| 3286 | count += (clkgen_rdp_io_port.$tcu_clk_stop__gclk != 0); | |
| 3287 | count += (clkgen_rtx_io2x_port.$tcu_clk_stop__gclk != 0); | |
| 3288 | count += (clkgen_rtx_io_port.$tcu_clk_stop__gclk != 0); | |
| 3289 | #endif | |
| 3290 | #endif | |
| 3291 | count += (clkgen_rst_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3292 | count += (clkgen_rst_io_port.$tcu_clk_stop__gclk != 0); | |
| 3293 | count += (clkgen_sii_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3294 | count += (clkgen_sii_io_port.$tcu_clk_stop__gclk != 0); | |
| 3295 | count += (clkgen_sio_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3296 | count += (clkgen_sio_io_port.$tcu_clk_stop__gclk != 0); | |
| 3297 | #ifndef RTL_NO_SPC0 | |
| 3298 | count += (clkgen_spc0_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3299 | #endif | |
| 3300 | #ifndef RTL_NO_SPC1 | |
| 3301 | count += (clkgen_spc1_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3302 | #endif | |
| 3303 | #ifndef RTL_NO_SPC2 | |
| 3304 | count += (clkgen_spc2_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3305 | #endif | |
| 3306 | #ifndef RTL_NO_SPC3 | |
| 3307 | count += (clkgen_spc3_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3308 | #endif | |
| 3309 | #ifndef RTL_NO_SPC4 | |
| 3310 | count += (clkgen_spc4_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3311 | #endif | |
| 3312 | #ifndef RTL_NO_SPC5 | |
| 3313 | count += (clkgen_spc5_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3314 | #endif | |
| 3315 | #ifndef RTL_NO_SPC6 | |
| 3316 | count += (clkgen_spc6_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3317 | #endif | |
| 3318 | #ifndef RTL_NO_SPC7 | |
| 3319 | count += (clkgen_spc7_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3320 | #endif | |
| 3321 | count += (clkgen_tcu_cmp_port.$tcu_clk_stop__gclk != 0); | |
| 3322 | count += (clkgen_tcu_io_port.$tcu_clk_stop__gclk != 0); | |
| 3323 | #ifndef FC_NO_NIU_T2 | |
| 3324 | #ifndef NIU_SYSTEMC_T2 | |
| 3325 | count += (clkgen_tds_io2x_port.$tcu_clk_stop__gclk != 0); | |
| 3326 | count += (clkgen_tds_io_port.$tcu_clk_stop__gclk != 0); | |
| 3327 | #endif | |
| 3328 | #endif | |
| 3329 | is_all_clkstp_sigs_deasserted = (count)? 0 : 1; // function return value | |
| 3330 | } | |
| 3331 | ||
| 3332 | //============== end ================ | |
| 3333 | ||
| 3334 | #endif // end of else part of #ifndef TCU_SAT | |
| 3335 | ||
| 3336 |