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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / tcu / vera / classes / tcu_tasks.vr
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: tcu_tasks.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36#include <std_display_class.vrh>
37
38// TAP specific defines
39#include <systemTapDefines.vri>
40
41#include <tcu_top_defines.vri>
42
43// jtag_if interfaces
44#include <systemTap.if.vri>
45
46// other interfaces
47#include <tcu_top.vri>
48
49#include <systemTapClass.vrh>
50#include <tcu_siu_packet.vrh>
51#include <tcu_spc_packet.vrh>
52#include <ncu_defines.vri>
53#include <tcu_defines.vri>
54#include "pkg_top.vri"
55
56
57extern tcu_siu_packet tcu_siu_pkt;
58
59#ifndef FC_SCAN_BENCH
60extern tcu_spc_packet tcu_spc_pkt;
61#endif
62
63class SystemTap extends BaseSystemTap {
64 stci__port stci_port;
65 bscan__port bscan_port;
66 shscan__port shscan_port;
67 jt_scan_clk__port jt_scan_clk_port;
68#ifndef NO_MBIST_STUB
69 mbist__port mbist_port;
70#endif
71#ifndef NO_LBIST_STUB
72 lbist__port lbist_port;
73#endif
74 scan__port scan_port;
75 PKG_port pkg_port = pkg_bind;
76 efuse__port efuse_port;
77#ifndef FC_SCAN_BENCH
78 tcu_siu__port tcu_siu_port;
79 spc_debug__port spc_debug_port;
80 cmp__port cmp_port;
81#endif
82// bit [3:0] tap_state_reg;
83// string dispmonScope;
84// StandardDisplay dbg;
85
86 task new(StandardDisplay dbgIn) {
87 super.new(dbgIn);
88 dispmonScope = "tcu";
89 bscan_port = bscan_bind;
90 stci_port = stci_bind;
91 shscan_port = shscan_bind;
92 jt_scan_clk_port = jt_scan_clk_bind;
93#ifndef NO_MBIST_STUB
94 mbist_port = mbist_bind;
95#endif
96#ifndef NO_LBIST_STUB
97 lbist_port = lbist_bind;
98#endif
99 scan_port = scan_bind;
100 efuse_port = efuse_bind;
101#ifndef FC_SCAN_BENCH
102 tcu_siu_port = tcu_siu_bind;
103 spc_debug_port = spc_debug_bind;
104 cmp_port = cmp_bind;
105#endif
106 dbg.dispmon(dispmonScope, MON_INFO, "$Id: tcu_tasks.vr,v 1.3 2007/07/26 23:00:22 drp Exp $");
107#ifndef FC_BENCH // could not drive package pins becoz these are driven by vera
108 //scan_port.$ac_test_mode = 1'b0 async; // Disable AC manufacturing to start with. should not initialize
109 //scan_port.$scan_en = 1'b0 async; // Disable scan mode. should not initialize
110#endif //FC_BENCH ndef
111
112 // From TI SERDES spec scan config modes:
113 // 00: STCIMODE and UNBYPASS asyncronously reset to zero
114 // 10: Scan into shadow registers new value on each scan clock
115 // 11: Load/apply scanned shadow register values into primary flops on next scan clock
116 //scan_port.$srdes_scancfg = 2'b0 async; // Serial test and configuration interface for SERDES
117#ifndef FC_SCAN_BENCH
118 cmp_port.$tb_fusedata_init = ~{22'b0} async; // Efuse testbench override, set enabled to true
119#endif
120 }
121
122 //========================================================
123 // WHAT: reset JTAG TAP for POR reset seq according to PRM as follows:
124 // - Wait for fc bench drives PWRON_RST_L
125 // - Assert TRST_L, drives TMS to 1 and toggle TCK once.
126 // - Deassert TRST_L and toggle TCK five times.
127 // ASSUME: this task is called at time 0
128 // NOTE: this task is for fc bench only.
129 //========================================================
130 task fc_bench_jtag_POR_reset() {
131 TCU_rst_port tcu_rst_port = tcu_rst_bind;
132 bit value;
133 integer i;
134
135 dbg.dispmon(dispmonScope, MON_ALWAYS, "fc_bench_jtag_POR_reset(): reset JTAG TAP for POR reset seq");
136 //--- wait fc bench assert PWRON_RST_L ---
137 while (1) {
138 value = tcu_rst_port.$PWRON_RST_L async;
139 if ((value === 1'b0) || (value === 1'b1))
140 break;
141 else
142 @(tcu_rst_port.$PWRON_RST_L async);
143 }
144 //--- assert TRST_L, set TMS to 1 and toggle TCK once ----
145 tap_port.$trst_n = 1'b0 async;
146 tap_port.$tck2dut = 1'b0 async;
147 tap_port.$tms = 1'b1 async;
148 repeat (2) @(pkg_port.$clk);
149 delay (3);
150 tap_port.$tck2dut = 1'b1 async; // toggle TCK once
151 repeat (2) @(pkg_port.$clk);
152 delay (3);
153 tap_port.$tck2dut = 1'b0 async;
154 //--- deassert TRST_L and toggle TCK five times ----
155 repeat (2) @(pkg_port.$clk);
156 delay (3);
157 tap_port.$trst_n = 1'b1 async; // deassert TRST_L
158 repeat (2) @(pkg_port.$clk);
159 for (i = 0; i < 5; i++) { // toggle TCK five times
160 delay (3);
161 tap_port.$tck2dut = 1'b1 async;
162 repeat (2) @(pkg_port.$clk);
163 delay (3);
164 tap_port.$tck2dut = 1'b0 async;
165 repeat (2) @(pkg_port.$clk);
166 }
167 tap_state_reg = TAP_RESET;
168 }
169
170 // JTAG Private UCB
171 //////////////////////////////////////////////////////////////////
172 //// TAP_CREG_ADDR
173 task tap_creg_addr( bit [39:0] addr ) {
174 dbg.dispmon(dispmonScope, MON_INFO, psprintf("tap_creg_addr() (40'h%10h)", addr));
175 void = TapIRLoad(TAP_CREG_ADDR);
176 void = TapDRLoad(cnv2str(addr, 40));
177 TapGoto(TAP_UPDATE_DR);
178 TapGoto(TAP_IDLE);
179
180 dbg.dispmon(dispmonScope, MON_INFO, "... Done tap_creg_addr()");
181 }
182
183 //// TAP_CREG_WDATA
184 task tap_creg_wdata( bit [63:0] data ) {
185 dbg.dispmon(dispmonScope, MON_INFO, psprintf("tap_creg_wdata() (64'h%16h)", data));
186 void = TapIRLoad(TAP_CREG_WDATA);
187 void = TapDRLoad(cnv2str(data, 64));
188 TapGoto(TAP_UPDATE_DR);
189 TapGoto(TAP_IDLE);
190 dbg.dispmon(dispmonScope, MON_INFO, "... Done tap_creg_wdata()");
191 }
192
193 //// TAP_CREG_RDATA
194 // Expecting a NACK means we intentionally submitted an invalid address
195 function bit [63:0] tap_creg_rdata(integer time_out_limit=100, bit expectNack = 0) {
196 string rdata;
197 tap_creg_rdata = 64'bx;
198 dbg.dispmon(dispmonScope, MON_INFO, "tap_creg_rdata()");
199 void = TapIRLoad(TAP_NCU_READ); // Send read
200 TapGoto(TAP_IDLE);
201 void = TapIRLoad(TAP_CREG_RDATA); // Wait for read reply at data register
202 TapGoto(TAP_UPDATE_IR);
203 TapGoto(TAP_SHIFT_DR);
204 // Wait for read return, on invalid addresses this should give a NACK
205 if (TapWait4DataRdy(time_out_limit)) {
206 if (expectNack) {
207 // From N1 PRM: "Most locations will silently drop writes to unsupported
208 // addresses, and will return NACK on reads to unsupported addresses
209 // which is ignored by the TAP"
210 dbg.dispmon(dispmonScope, MON_INFO, "... UCB read NOT successful. Expecting a NACK during timeout ...");
211 } else {
212 dbg.dispmon(dispmonScope, MON_ERR, "... ERROR: UCB read timeout reached.");
213 }
214 } else {
215 dbg.dispmon(dispmonScope, MON_INFO, "... UCB read successful.");
216 rdata = TapDRGet(64);
217 tap_creg_rdata = rdata.atobin();
218 }
219 TapGoto(TAP_IDLE);
220 dbg.dispmon(dispmonScope, MON_INFO, "... Done tap_creg_rdata()");
221 }
222
223 //// TAP_CREG_SCRATCH
224 function bit [63:0] tap_creg_scratch(integer time_out_limit = 100, bit expectNack = 0) {
225 string rdata;
226 tap_creg_scratch = 64'bx;
227 dbg.dispmon(dispmonScope, MON_INFO, "tap_creg_scratch()");
228 void = TapIRLoad(TAP_CREG_SCRATCH);
229 TapGoto(TAP_UPDATE_IR);
230 TapGoto(TAP_IDLE);
231 TapGoto(TAP_SHIFT_DR);
232 // Wait for read return, on invalid addresses this should give a NACK
233 if (TapWait4DataRdy(time_out_limit)) {
234 if (expectNack) {
235 // From N1 PRM: "Most locations will silently drop writes to unsupported
236 // addresses, and will return NACK on reads to unsupported addresses
237 // which is ignored by the TAP"
238 dbg.dispmon(dispmonScope, MON_INFO, "... UCB read NOT successful.");
239 dbg.dispmon(dispmonScope, MON_INFO, "Expecting a NACK during timeout ...");
240 } else {
241 dbg.dispmon(dispmonScope, MON_ERR, "... ERROR: UCB read timeout reached.");
242 }
243 } else {
244 dbg.dispmon(dispmonScope, MON_INFO, "... UCB read successful.");
245 rdata = TapDRGet(64);
246 tap_creg_scratch = rdata.atobin();
247 }
248 TapGoto(TAP_IDLE);
249 dbg.dispmon(dispmonScope, MON_INFO, "... Done tap_creg_scratch()");
250 }
251
252 //// TAP_NCU_WRITE
253 task tap_iob_write() {
254 dbg.dispmon(dispmonScope, MON_INFO, "tap_iob_write()");
255 void = TapIRLoad(TAP_NCU_WRITE);
256 TapGoto(TAP_IDLE);
257 dbg.dispmon(dispmonScope, MON_INFO, "... Done tap_iob_write()");
258 }
259
260 //// TAP_NCU_READ
261 task tap_iob_read() {
262 dbg.dispmon(dispmonScope, MON_INFO, "tap_iob_read()");
263 void = TapIRLoad(TAP_NCU_READ);
264 TapGoto(TAP_IDLE);
265 dbg.dispmon(dispmonScope, MON_INFO, "... Done tap_iob_read()");
266 }
267
268 //// TAP_NCU_WADDR
269 task tap_iob_waddr( bit [39:0] addr ) {
270 dbg.dispmon(dispmonScope, MON_INFO, psprintf("tap_iob_waddr() ('h%0h)", addr));
271 void = TapIRLoad(TAP_NCU_WADDR);
272 void = TapDRLoad(cnv2str(addr, 40));
273 TapGoto(TAP_UPDATE_DR);
274 TapGoto(TAP_IDLE);
275 dbg.dispmon(dispmonScope, MON_INFO, "... Done tap_iob_waddr()");
276 }
277
278 //// TAP_NCU_WDATA
279 task tap_iob_wdata( bit [63:0] data ) {
280 dbg.dispmon(dispmonScope, MON_INFO, psprintf("tap_iob_wdata() ('h%0h)", data));
281 void = TapIRLoad(TAP_NCU_WDATA);
282 void = TapDRLoad(cnv2str(data, 64));
283 TapGoto(TAP_UPDATE_DR);
284 TapGoto(TAP_IDLE);
285 dbg.dispmon(dispmonScope, MON_INFO, "... Done tap_iob_wdata()");
286 }
287
288 //// TAP_NCU_RADDR
289 task tap_iob_raddr( bit [39:0] addr ) {
290 dbg.dispmon(dispmonScope, MON_INFO, psprintf("tap_iob_addr() ('h%0h)", addr));
291 void = TapIRLoad(TAP_NCU_RADDR);
292 void = TapDRLoad(cnv2str(addr, 40));
293 TapGoto(TAP_UPDATE_DR);
294 TapGoto(TAP_IDLE);
295 dbg.dispmon(dispmonScope, MON_INFO, "... Done tap_iob_raddr()");
296 }
297
298 //// Wrapper task: write to an CSR
299 task tap_write_csr(bit [39:0] addr, bit [63:0] wdata, string csr_name="") {
300 dbg.dispmon(dispmonScope, MON_INFO, psprintf("tap_write_csr(addr=0x%h, wdata=0x%h, name=%s)", addr, wdata, csr_name));
301 this.tap_creg_addr(addr);
302 this.tap_creg_wdata(wdata);
303 this.tap_iob_write();
304 }
305
306 //// Wrapper function: read an CSR
307 function bit [63:0] tap_read_csr(bit [39:0] addr, string csr_name="", integer time_out_limit=100, bit expectNack = 0) {
308 dbg.dispmon(dispmonScope, MON_INFO, psprintf("tap_read_csr(addr=0x%h, name=%s)", addr, csr_name));
309 this.tap_creg_addr(addr);
310 tap_read_csr = this.tap_creg_rdata(time_out_limit, expectNack);
311 }
312
313 // JTAG Private L2 access
314 //////////////////////////////////////////////////////////////////
315 //// TAP_L2_WRITE
316 task tap_l2_write( bit [39:0] addr, bit [63:0] data ) {
317 bit [63:0] header;
318
319 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("tap_l2_write() (addr: 40'h%10h, data: 64'h%16h)", addr, data));
320 header = {24'h820000, addr}; // write operation
321
322 // save to share packet
323 tcu_siu_pkt.header = header;
324 tcu_siu_pkt.payload = data;
325
326 tap_l2_addr (header); // load TAP_L2_ADDR instr
327 tap_l2_wrdata (data); // load TAP_L2_WRDATA instr
328 tap_l2_wr(); // load TAP_L2_WR instr
329 dbg.dispmon(dispmonScope, MON_ALWAYS, "... Done tap_l2_write()");
330 }
331
332 //////////////////////////////////////////////////////////////////
333 //// TAP_L2_READ
334 task tap_l2_read( bit [39:0] addr) {
335 bit [63:0] header;
336 bit [63:0] received_payload;
337 integer timeout = 100;
338
339 dbg.dispmon(dispmonScope, MON_INFO, psprintf("tap_l2_read() (40'h%10h)", addr));
340 header = {24'h810000, addr}; // read operation
341
342 tap_l2_addr (header); // load TAP_L2_ADDR instr
343 received_payload = tap_l2_rd(timeout,addr,1'b0); // load TAP_L2_RD instr
344
345 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("TAP_L2_READ received payload: (%x) Expected payload: (%x)", received_payload, tcu_siu_pkt.payload));
346
347 if (received_payload !== tcu_siu_pkt.payload) {
348 dbg.dispmon (dispmonScope, MON_ERR, psprintf ("tcu received wrong payload from SIU"));
349 }
350
351 dbg.dispmon(dispmonScope, MON_INFO, "... Done tap_l2_read()");
352 }
353
354 // added by Adam for checking read data 5/5/05
355 function bit[63:0] tap_l2_read_data( bit [39:0] addr) {
356 bit [63:0] header;
357 bit [63:0] received_payload;
358 integer timeout = 100;
359
360 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("tap_l2_read() (40'h%10h)", addr));
361 header = {24'h810000, addr}; // read operation
362
363 // save to share packet
364 tcu_siu_pkt.header = header;
365 tcu_siu_pkt.payload = 64'hx;
366
367 tap_l2_addr (header); // load TAP_L2_ADDR instr
368 received_payload = tap_l2_rd(timeout,addr,1'b0); // load TAP_L2_RD instr
369 tap_l2_read_data = received_payload;
370
371 dbg.dispmon(dispmonScope, MON_ALWAYS, "... Done tap_l2_read_data()");
372 }
373
374 //////////////////////////////////////////////////////////////////
375 //// TAP_L2_ADDR 0x58
376 task tap_l2_addr( bit [63:0] addr ) {
377 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("tap_l2_addr() (64'h%16h)", addr));
378 void = TapIRLoad(TAP_L2_ADDR);
379 void = TapDRLoad(cnv2str(addr, 64));
380 TapGoto(TAP_UPDATE_DR);
381 dbg.dispmon(dispmonScope, MON_ALWAYS, "... Done tap_l2_addr()");
382 }
383
384 //// TAP_L2_WRDATA 0x59
385 task tap_l2_wrdata( bit [63:0] data ) {
386 dbg.dispmon(dispmonScope, MON_INFO, psprintf("tap_l2_wrdata() (64'h%16h)", data));
387 void = TapIRLoad(TAP_L2_WRDATA);
388 void = TapDRLoad(cnv2str(data, 64));
389 TapGoto(TAP_UPDATE_DR);
390 dbg.dispmon(dispmonScope, MON_INFO, "... Done tap_l2_wrdata()");
391 }
392
393 //// TAP_L2_WR 0x5A
394 task tap_l2_wr() {
395 dbg.dispmon(dispmonScope, MON_INFO, "tap_l2_wr()");
396 void = TapIRLoad(TAP_L2_WR);
397 TapGoto(TAP_IDLE);
398 repeat(128) toggleDutTck(); // wait for 128 TCK clocks for transfer to complete
399 dbg.dispmon(dispmonScope, MON_INFO, "... Done tap_l2_wr()");
400 }
401
402 //// TAP_l2_RD 0x5B
403 // Expecting a NACK means we intentionally submitted an invalid address
404 function bit [63:0] tap_l2_rd(integer time_out_limit=100, bit [39:0] addr, bit expectNack = 0) {
405 string rdata;
406 tap_l2_rd = 64'bx;
407 dbg.dispmon(dispmonScope, MON_INFO, "tap_l2_rd()");
408 void = TapIRLoad(TAP_L2_RD); // send read request
409 TapGoto(TAP_UPDATE_IR);
410 TapGoto(TAP_IDLE);
411 repeat(64) toggleDutTck(); // wait for 64 TCK clocks for transfer the addr to L2 is complete
412 TapGoto(TAP_SHIFT_DR);
413 // Wait for read return, on invalid addresses this should give a NACK
414 if (TapWait4L2DataRdy(time_out_limit)) {
415 if (expectNack) {
416 // From N2 PRM: "Most locations will silently drop writes to unsupported
417 // addresses, and will return NACK on reads to unsupported addresses
418 // which is ignored by the TAP"
419 dbg.dispmon(dispmonScope, MON_INFO, "... L2 read NOT successful.");
420 dbg.dispmon(dispmonScope, MON_INFO, "Expecting a NACK during timeout ...");
421 } else {
422 dbg.dispmon(dispmonScope, MON_ERR, "... ERROR: L2 read timeout reached.");
423 }
424 } else {
425 dbg.dispmon(dispmonScope, MON_INFO, "... L2 read successful.");
426 // 1/10/06 asked o remove the following line.
427 // toggleDutTck(); // discard the sentinel bit
428 rdata = TapDRGet(64);
429 tap_l2_rd = rdata.atobin();
430 }
431 dbg.dispmon(dispmonScope, MON_INFO, "... Done tap_l2_rd()");
432 }
433
434 // JTAG Private MBIST
435 //////////////////////////////////////////////////////////////////
436 //// TAP_MBIST_BYPASS
437 function bit [(`NUM_MBIST_ENGINES-1):0] tapMbistBypass(bit [(`NUM_MBIST_ENGINES-1):0] bypassRegister) {
438 string scanOut;
439 dbg.dispmon(dispmonScope, MON_INFO, psprintf("tapMbistBypass() [Register='h%0h]", bypassRegister));
440 scanOut = TapIRLoad(TAP_MBIST_BYPASS);
441 scanOut = TapDRLoad(cnv2str(bypassRegister, `NUM_MBIST_ENGINES));
442 TapGoto(TAP_UPDATE_DR);
443 TapGoto(TAP_IDLE);
444 //@1 mbist_port.$mbist_bypass == bypassRegister; // Outbound bypass bits check
445 tapMbistBypass = scanOut.atobin();
446 dbg.dispmon(dispmonScope, MON_INFO, "... Done tapMbistBypass()");
447 }
448
449 //// TAP_MBIST_MODE
450 function bit [3:0] tapMbistMode(bit [3:0] modeRegister) {
451 string scanOut;
452 dbg.dispmon(dispmonScope, MON_INFO, psprintf("tapMbistMode() [Register='h%0h]", modeRegister));
453 scanOut = TapIRLoad(TAP_MBIST_MODE);
454 scanOut = TapDRLoad(cnv2str(modeRegister, 4));
455 TapGoto(TAP_UPDATE_DR);
456 TapGoto(TAP_IDLE);
457 //@1 mbist_port.$mbist_user == modeRegister[2]; // Outbound mode bit check
458 //@1 mbist_port.$mbist_bisi == modeRegister[1]; // Outbound mode bit check
459 //@1 mbist_port.$mbist_parallel == modeRegister[0]; // Outbound mode bit check
460 tapMbistMode = scanOut.atobin();
461 dbg.dispmon(dispmonScope, MON_INFO, "... Done tapMbistMode()");
462 }
463
464 //// TAP_MBIST_ABORT
465 task tapMbistAbort() {
466 dbg.dispmon(dispmonScope, MON_INFO, "tapMbistAbort()");
467 void = TapIRLoad(TAP_MBIST_ABORT);
468 TapGoto(TAP_UPDATE_IR);
469 TapGoto(TAP_IDLE);
470 dbg.dispmon(dispmonScope, MON_INFO, "... Done tapMbistAbort()");
471 }
472
473 //// TAP_MBIST_START
474 task tapMbistStart() {
475 dbg.dispmon(dispmonScope, MON_INFO, "tapMbistStart()");
476 void = TapIRLoad(TAP_MBIST_START);
477 TapGoto(TAP_UPDATE_IR);
478 TapGoto(TAP_IDLE);
479 dbg.dispmon(dispmonScope, MON_INFO, "... Done tapMbistStart()");
480 }
481
482
483 task tapMbistProtect() {
484 dbg.dispmon(dispmonScope, MON_INFO, "tapMbistStart()");
485 void = TapIRLoad(TAP_TP_ACCESS);
486 TapGoto(TAP_UPDATE_IR);
487 TapGoto(TAP_IDLE);
488 dbg.dispmon(dispmonScope, MON_INFO, "... Done tapMbistProtect()");
489 }
490
491 task tapMbistStopClock() {
492 dbg.dispmon(dispmonScope, MON_INFO, "tapMbistStart()");
493 void = TapIRLoad(TAP_CLOCK_DOMAIN);
494 void = TapDRLoad("00000000000000000000000000000001");
495 void = TapIRLoad(TAP_CLKSTP_DELAY);
496 void = TapDRLoad("0000111");
497 void = TapIRLoad(TAP_CLOCK_HSTOP);
498 TapGoto(TAP_UPDATE_IR);
499 TapGoto(TAP_IDLE);
500 dbg.dispmon(dispmonScope, MON_INFO, "... Done tapMbistStopClock()");
501 }
502
503 task tapMbistPlusStopClock(bit [31:0] clockdomain,bit [63:0] cycle_count) {
504 dbg.dispmon(dispmonScope, MON_INFO, "tapMbistStart()");
505 void = TapIRLoad(TAP_CLOCK_DOMAIN);
506 void = TapDRLoad(cnv2str(clockdomain, 32));
507 void = TapIRLoad(TAP_CLKSTP_DELAY);
508 void = TapDRLoad("0000111");
509 void = TapIRLoad(TAP_CYCLE_COUNT);
510 void = TapDRLoad(cnv2str(cycle_count,64));
511 void = TapIRLoad(TAP_MBIST_CLKSTPEN);
512 TapGoto(TAP_IDLE);
513 dbg.dispmon(dispmonScope, MON_INFO, "... Done tapMbistStopClock()");
514 }
515
516
517 task tapMbistPlusShiftRestart(bit[5:0] chainnumber) {
518 void = TapIRLoad(TAP_CHAINSEL);
519 void = TapDRLoad(cnv2str(chainnumber,6));
520 void = TapIRLoad(TAP_SERSCAN);
521 void = TapDRLoad(cnv2str(32'b0,32));
522 //this.tapMbistStartClock();
523 }
524
525 task tapMbistStartClock() {
526 bit [1:0] data;
527 string scanOut;
528 dbg.dispmon(dispmonScope, MON_INFO, "tapMbistStart()");
529 void = TapIRLoad(TAP_CLOCK_START);
530 TapGoto(TAP_UPDATE_IR);
531 TapGoto(TAP_IDLE);
532 dbg.dispmon(dispmonScope, MON_INFO, "... Done tapMbistStartClock()");
533 while (1) {
534 scanOut = TapIRLoad(TAP_CLOCK_STATUS);
535 scanOut = TapDRLoad(cnv2str(2'b00, 2));
536 TapGoto(TAP_UPDATE_DR);
537 TapGoto(TAP_IDLE);
538 data = scanOut.atobin();
539 if(data == 2'b01) {
540 return;
541 }
542 }
543 }
544
545 //// TAP_MBIST_RESULT
546 function bit [1:0] tapMbistResult(bit [1:0] resultRegister) {
547 string scanOut;
548 dbg.dispmon(dispmonScope, MON_INFO, "tapMbistResult()");
549 scanOut = TapIRLoad(TAP_MBIST_RESULT);
550 scanOut = TapDRLoad(cnv2str(resultRegister, 2));
551 TapGoto(TAP_UPDATE_DR);
552 TapGoto(TAP_IDLE);
553 tapMbistResult = scanOut.atobin();
554 dbg.dispmon(dispmonScope, MON_INFO, "... Done tapMbistResult()");
555 }
556
557 //// TAP_MBIST_DIAG
558 function string tapMbistDiag(string Diagnosis) {
559 string scanOut;
560 integer count;
561 integer length;
562 string local_128_string;
563 dbg.dispmon(dispmonScope, MON_INFO, "tapMbistDiag()");
564 scanOut = TapIRLoad(TAP_MBIST_DIAG);
565#if 0
566 length = Diagnosis.len();
567 while (length > 128)
568 {
569 local_128_string = Diagnosis.substr(length-128,length-1);
570 scanOut = TapDRLoad(local_128_string);
571 length = length - 128;
572 }
573 local_128_string = Diagnosis.substr(0,length-1);
574 scanOut = TapDRLoad(local_128_string);
575#else
576 scanOut = TapDRLoad(Diagnosis);
577#endif
578 TapGoto(TAP_UPDATE_DR);
579 TapGoto(TAP_IDLE);
580// TapGoto(TAP_UPDATE_IR);
581// TapGoto(TAP_IDLE);
582 dbg.dispmon(dispmonScope, MON_INFO, "... Done tapMbistDiag()");
583 tapMbistDiag = scanOut;
584 }
585
586 //// TAP_MBIST_GETDONE
587 function bit [(`NUM_MBIST_ENGINES-1):0] tapMbistGetdone(bit [(`NUM_MBIST_ENGINES-1):0] doneRegister) {
588 string scanOut;
589 dbg.dispmon(dispmonScope, MON_INFO, "tapMbistGetdone()");
590 scanOut = TapIRLoad(TAP_MBIST_GETDONE);
591 scanOut = TapDRLoad(cnv2str(doneRegister, `NUM_MBIST_ENGINES));
592 TapGoto(TAP_UPDATE_DR);
593 TapGoto(TAP_IDLE);
594 tapMbistGetdone = scanOut.atobin();
595 dbg.dispmon(dispmonScope, MON_INFO, "... Done tapMbistGetdone()");
596 }
597
598 //// TAP_MBIST_GETFAIL
599 function bit [(`NUM_MBIST_ENGINES-1):0] tapMbistGetfail(bit [(`NUM_MBIST_ENGINES-1):0] failRegister) {
600 string scanOut;
601 dbg.dispmon(dispmonScope, MON_INFO, "tapMbistGetfail()");
602 scanOut = TapIRLoad(TAP_MBIST_GETFAIL);
603 scanOut = TapDRLoad(cnv2str(failRegister, `NUM_MBIST_ENGINES));
604 TapGoto(TAP_UPDATE_DR);
605 TapGoto(TAP_IDLE);
606 tapMbistGetfail = scanOut.atobin();
607 dbg.dispmon(dispmonScope, MON_INFO, "... Done tapMbistGetfail()");
608 }
609
610 //// TAP_MBIST_CLKSTPEN
611 task tapMbistClkStopEn() {
612 dbg.dispmon(dispmonScope, MON_INFO, "tapMbistClkStopEn()");
613 void = TapIRLoad(TAP_MBIST_CLKSTPEN);
614 TapGoto(TAP_UPDATE_IR);
615 TapGoto(TAP_IDLE);
616 dbg.dispmon(dispmonScope, MON_INFO, "... Done tapMbistClkStopEn()");
617 }
618
619 //-------- Wait for an MBIST to complete --------------
620 function integer TapWait4MbistDone(integer mbist_engine_num, integer time_out_limit) {
621 integer i;
622 bit [(`NUM_MBIST_ENGINES-1):0] tcuRegDone = `NUM_MBIST_ENGINES'b0;
623
624 dbg.dispmon(dispmonScope, MON_INFO, psprintf("TAP wait for %0d MBIST DONE (TCK timeout: %0d cycles)", mbist_engine_num, time_out_limit));
625
626 tcuRegDone = tapMbistGetdone(`NUM_MBIST_ENGINES'b0);
627 // Wait for the MBIST DONE at which time the corresponding engine done bit is set to 1'b1
628 for (i=0; i < time_out_limit && tcuRegDone[mbist_engine_num] !== 1'b1; i++) {
629 tcuRegDone = tapMbistGetdone(`NUM_MBIST_ENGINES'b0);
630 }
631 if (tcuRegDone[mbist_engine_num] === 1'b1) {
632 TapWait4MbistDone = 0;
633 }
634 else {
635 TapWait4MbistDone = (i >= time_out_limit);
636 }
637 }
638
639 // JTAG Private CCU
640 //////////////////////////////////////////////////////////////////
641 //// TAP_PLL_BYPASS
642 task ccuPllBypass () {
643 dbg.dispmon(dispmonScope, MON_INFO, "ccuPllBypass()");
644 // N1 void = TapIRLoad(TAP_PLL_BYPASS);
645 // N1 TapGoto(TAP_UPDATE_IR);
646 // N1 TapGoto(TAP_IDLE);
647 //@1 scan_port.$tcu_pllbypass == 1'b1;
648 dbg.dispmon(dispmonScope, MON_INFO, "... Done ccuPllBypass()");
649 }
650
651 //// TAP_CLK_STOP_ID
652 task ccuClockStopId (bit [5:0] id) {
653 // N1 string inst = "";
654 // N1 sprintf(inst, "000000%b%s", id, TAP_CLK_STOP_ID);
655 // N1 dbg.dispmon(dispmonScope, MON_INFO, psprintf("ccuClockStopId() (inst: 'b%0b id: 6'b%06b)", inst, id));
656 // N1 void = TapIRLoad(inst);
657 // N1 TapGoto(TAP_UPDATE_IR);
658 // N1 TapGoto(TAP_IDLE);
659 // N1 dbg.dispmon(dispmonScope, MON_INFO, "... Done ccuClockStopId()");
660 }
661
662 // TAP_CLK_SEL
663 task ccuClockSelect ( bit [2:0] ioclk_domain, bit [2:0] ddrclk_domain, bit [2:0] cmpclk_domain ) {
664 // N1 string inst;
665 // N1
666 // N1 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("ccuClockSelect(\n\t\tcmpclk = %s,\n\t\tddrclk = %s,\n\t\tioclk = %s)"
667 // N1 , cnv_domain_2_string(cmpclk_domain)
668 // N1 , cnv_domain_2_string(ddrclk_domain)
669 // N1 , cnv_domain_2_string(ioclk_domain)
670 // N1 ));
671 // N1 sprintf(inst, "000%b%b%b%s", ioclk_domain, ddrclk_domain, cmpclk_domain, TAP_CLK_SEL);
672 // N1 dbg.dispmon(dispmonScope, MON_INFO, psprintf("inst: %s", inst));
673 // N1 void = TapIRLoad(inst);
674 // N1 TapGoto(TAP_UPDATE_IR);
675 // N1 TapGoto(TAP_IDLE);
676 // N1 dbg.dispmon(dispmonScope, MON_INFO, "... Done ccuClockSelect()");
677 }
678
679 // JTAG Private Shadow SCAN
680 //////////////////////////////////////////////////////////////////
681 function string tapShadowScan(integer delay, string cluster, bit[2:0] thread, integer length ) {
682 string scanInst;
683 string scanOut;
684
685 dbg.dispmon(dispmonScope, MON_ALWAYS, "tapShadowScan()");
686 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf ("SHADOW SCAN waiting for %0d TCK cycles", delay));
687 Delay (delay); // Start after given delay number of TCK cycles
688 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf ("Loading SHADOW SCAN %s_%3b Instruction", cluster, thread));
689 sprintf(scanInst, "%s%3b", cluster, thread);
690 void = TapIRLoad(scanInst);
691 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf ("Loaded SHADOW SCAN instruction : %s", scanInst));
692 TapGoto(TAP_UPDATE_IR);
693 TapCaptureData();
694 TapGoto(TAP_SHIFT_DR);
695 scanOut = TapDRGet(length);
696 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf ("SHADOW SCAN %s_%3b output :%s", cluster, thread, scanOut));
697 TapGoto(TAP_PAUSE_DR);
698 TapGoto(TAP_IDLE);
699 tapShadowScan = scanOut;
700 dbg.dispmon(dispmonScope, MON_ALWAYS, "... Done tapShadowScan()");
701 }
702
703 // Added by Adam for checking interface
704 function bit [65:0] tapShadowScanCheck( string cluster, bit[2:0] thread ) {
705 string scanInst;
706 string scanOut;
707 integer ScanShiftCount = 32;
708 integer aclkCount =0;
709 integer bclkCount =0;
710 bit [31:0] data = 32'b0;
711 bit [2:0] shscanid;
712 bit spc_se;
713 bit spc_pce_ov;
714 bit [7:0] spc_clk_stop;
715 bit l2t_se;
716 bit l2t_pce_ov;
717 bit [7:0] l2t_clk_stop;
718
719 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf ("Shadow scan clock check for cluster: %s thread: %3b", cluster, thread));
720
721 sprintf(scanInst, "%s%3b", cluster, thread);
722 void = TapIRLoad(scanInst);
723 TapGoto(TAP_UPDATE_IR);
724 TapCaptureData();
725
726 shscanid = shscan_port.$shscan_spc_shscanid async;
727 spc_se = shscan_port.$shscan_spc_se async;
728 spc_pce_ov = shscan_port.$shscan_spc_pce_ov async;
729 spc_clk_stop = shscan_port.$shscan_spc_clk_stop async;
730 l2t_se = shscan_port.$shscan_l2t_se async;
731 l2t_pce_ov = shscan_port.$shscan_l2t_pce_ov async;
732 l2t_clk_stop = shscan_port.$shscan_l2t_clk_stop async;
733
734 if (cluster === TAP_SPC_SHSCAN) {
735 if (shscanid !== thread)
736 dbg.dispmon(dispmonScope, MON_ERR, psprintf("...ERROR: shscanid does not match Expected=%0b, got=%0b",thread,shscanid));
737 if (spc_se !== 1'b0)
738 dbg.dispmon(dispmonScope, MON_ERR, psprintf("...ERROR: spc_se does not match Expected=0, got=%0b",spc_se));
739 if (spc_pce_ov !== 1'b1)
740 dbg.dispmon(dispmonScope, MON_ERR, psprintf("...ERROR: spc_pce_ov does not match Expected=1, got=%0b",spc_pce_ov));
741 if (spc_clk_stop !== {8{1'b1}})
742 dbg.dispmon(dispmonScope, MON_ERR, psprintf("...ERROR: spc_clk_stop does not match Expected=%0b, got=%0b",{8{1'b1}},spc_clk_stop));
743 if (l2t_se != 1'b0)
744 dbg.dispmon(dispmonScope, MON_ERR, psprintf("...ERROR: l2t_se does not match Expected=0, got=%0b",l2t_se));
745 if (l2t_pce_ov != 1'b0)
746 dbg.dispmon(dispmonScope, MON_ERR, psprintf("...ERROR: l2t_pce_ov does not match Expected=1, got=%0b",l2t_pce_ov));
747 if (l2t_clk_stop !== {8{1'b0}})
748 dbg.dispmon(dispmonScope, MON_ERR, psprintf("...ERROR: l2t_clk_stop does not match Expected=%0b, got=%0b",{8{1'b0}},l2t_clk_stop));
749 }
750 else if (cluster === TAP_SOC_SHSCAN) {
751 if (shscanid !== 3'b0)
752 dbg.dispmon(dispmonScope, MON_ERR, psprintf("...ERROR: shscanid does not match Expected=0, got=%0b",shscanid));
753 if (spc_se != 1'b0)
754 dbg.dispmon(dispmonScope, MON_ERR, psprintf("...ERROR: spc_se does not match Expected=0, got=%0b",spc_se));
755 if (spc_pce_ov != 1'b0)
756 dbg.dispmon(dispmonScope, MON_ERR, psprintf("...ERROR: spc_pce_ov does not match Expected=0, got=%0b",spc_pce_ov));
757 if (spc_clk_stop !== {8{1'b0}})
758 dbg.dispmon(dispmonScope, MON_ERR, psprintf("...ERROR: spc_clk_stop does not match Expected=%0b, got=%0b",{8{1'b0}},spc_clk_stop));
759 if (l2t_se != 1'b0)
760 dbg.dispmon(dispmonScope, MON_ERR, psprintf("...ERROR: l2t_se does not match Expected=0, got=%0b",l2t_se));
761 if (l2t_pce_ov != 1'b1)
762 dbg.dispmon(dispmonScope, MON_ERR, psprintf("...ERROR: l2t_pce_ov does not match Expected=1, got=%0b",l2t_pce_ov));
763 if (l2t_clk_stop !== {8{1'b1}})
764 dbg.dispmon(dispmonScope, MON_ERR, psprintf("...ERROR: l2t_clk_stop does not match Expected=%0b, got=%0b",{8{1'b1}},l2t_clk_stop));
765 }
766
767 fork
768 {
769 scanOut = TapDRLoad(cnv2str(data, ScanShiftCount));
770 }
771 {
772 // count the number of aclk
773 while(1) {
774 if (cluster === TAP_SPC_SHSCAN) {
775 @ (posedge shscan_port.$shscan_spc_aclk async);
776 spc_se = shscan_port.$shscan_spc_se async;
777 if (spc_se == 1'b1) {
778 aclkCount++;
779 dbg.dispmon(dispmonScope, MON_INFO, psprintf("aclkCount incremented %d",aclkCount));
780 }
781 }
782 else if (cluster === TAP_SOC_SHSCAN) {
783 @ (posedge shscan_port.$shscan_l2t_aclk async);
784 l2t_se = shscan_port.$shscan_l2t_se async;
785 if (l2t_se == 1'b1) {
786 aclkCount++;
787 dbg.dispmon(dispmonScope, MON_INFO, psprintf("aclkCount incremented %d",aclkCount));
788 }
789 }
790 }
791 }
792 {
793 // count the number of bclk
794 while(1) {
795 if (cluster === TAP_SPC_SHSCAN) {
796 @ (posedge shscan_port.$shscan_spc_bclk async);
797 if (spc_se == 1'b1) {
798 bclkCount++;
799 dbg.dispmon(dispmonScope, MON_INFO, psprintf("bclkCount incremented %d",bclkCount));
800 }
801 }
802 else if (cluster === TAP_SOC_SHSCAN) {
803 @ (posedge shscan_port.$shscan_l2t_bclk async);
804 if (l2t_se == 1'b1) {
805 bclkCount++;
806 dbg.dispmon(dispmonScope, MON_INFO, psprintf("bclkCount incremented %d",bclkCount));
807 }
808 }
809 }
810 }
811 join any
812 terminate;
813
814 if (cluster === TAP_SPC_SHSCAN) {
815 if (spc_se != 1'b1)
816 dbg.dispmon(dispmonScope, MON_ERR, psprintf("...ERROR: spc_se does not match Expected=1'b1 during spc shadow scan, got=%0b",spc_se));
817 }
818 else if (cluster === TAP_SOC_SHSCAN) {
819 if (l2t_se != 1'b1)
820 dbg.dispmon(dispmonScope, MON_ERR, psprintf("...ERROR: l2t_se does not match Expected=1'b1 during l2t shadow scan, got=%0b",l2t_se));
821 }
822
823 if ((aclkCount != ScanShiftCount) || (bclkCount != ScanShiftCount))
824 dbg.dispmon(dispmonScope, MON_ERR, psprintf("...ERROR: aclk=%0d, bclk=%0d,Expected=%0d",aclkCount,bclkCount,ScanShiftCount));
825 else
826 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf ("... Donce TapShadowScanCheck() for cluster: %s thread: %3b", cluster, thread));
827
828 tapShadowScanCheck = scanOut.atobin();
829 }
830
831 // JTAG Private SCAN
832 //////////////////////////////////////////////////////////////////
833 //-------- TAP_SCAN_PARALLEL -----------
834 //// N1: task tapScanDump(var bit [31:0] so_data[16]) {
835 //// N1: string inst;
836 //// N1: bit [31:0] xx_data[16];
837 //// N1: dbg.dispmon(dispmonScope, MON_INFO, "tapScanDump()");
838 //// N1: sprintf(inst, "%s%s", TAP_SCAN_PARALLEL_DUMP, TAP_SCAN_PARALLEL);
839 //// N1: void = TapIRLoad(inst);
840 //// N1: TapGoto(TAP_UPDATE_IR);
841 //// N1: TapDRPData(8, xx_data, so_data);
842 //// N1: dbg.dispmon(dispmonScope, MON_INFO, "... Done tapScanDump()");
843 //// N1: }
844 //// N1: function string tapScanParallel(string parallel_type, string scan_in_data) {
845 //// N1: string rdata;
846 //// N1: string inst;
847 //// N1: dbg.dispmon(dispmonScope, MON_INFO, psprintf("tapScanParallel() (length = %0d)", scan_in_data.len()));
848 //// N1: sprintf(inst, "%s%s", parallel_type, TAP_SCAN_PARALLEL);
849 //// N1: void = TapIRLoad(inst);
850 //// N1: TapGoto(TAP_UPDATE_IR);
851 //// N1: // Capture data & proceed to pause_dr
852 //// N1: TapCaptureData();
853 //// N1: rdata = TapDRLoad(scan_in_data);
854 //// N1: TapGoto(TAP_UPDATE_DR);
855 //// N1: TapGoto(TAP_IDLE);
856 //// N1: dbg.dispmon(dispmonScope, MON_INFO, "... Done tapScanParallel()");
857 //// N1: tapScanParallel = rdata;
858 //// N1: }
859
860 //-------- TAP_SCAN_SERIAL -----------
861 function integer tapSetupScanSerial(integer chain_timeout, bit[5:0] chain_sel) {
862 integer chain_idx, chain_total;
863 bit[11:0] chain_pat;
864 bit[11:0] chain_seen;
865 dbg.dispmon(dispmonScope, MON_INFO, psprintf("tapSetupScanSerial(): Chain: %0d, Enabled: %01b", chain_sel[4:0], chain_sel[5]));
866 tapSetupScanSerial = 0;
867 chain_idx = 0;
868 chain_total = 0;
869 chain_pat = 12'b1110_0011_0010;
870 chain_seen = 12'b0;
871 void = TapIRLoad(TAP_SCAN_SERIAL_SEL);
872 void = TapDRLoad(cnv2str(chain_sel,6));
873 void = TapIRLoad(TAP_SCAN_SERIAL);
874 TapGoto(TAP_SHIFT_DR);
875 repeat(chain_timeout) {
876 tap_port.$tdi = chain_pat[chain_idx];
877 toggleDutTck();
878 chain_seen[10:0] = chain_seen[11:1];
879 chain_seen[11] = tap_port.$tdo;
880 chain_idx = (chain_idx + 1) % 12;
881 chain_total = chain_total + 1;
882 tapSetupScanSerial = chain_total;
883 if (chain_seen === chain_pat) {
884 break;
885 }
886 }
887 tapSetupScanSerial = (tapSetupScanSerial>12) ? tapSetupScanSerial-12 : tapSetupScanSerial; // Cannot count the final word shift
888 void = TapIRLoad(TAP_BYPASS_INST);
889 TapGoto(TAP_IDLE);
890 dbg.dispmon(dispmonScope, MON_INFO, "... Done tapSetupScanSerial()");
891 }
892
893 //-------- TAP_SCAN_NSTEP -----------
894 //// N1: task tapScanNstep( bit [3:0] n_step, bit [2:0] domain ) {
895 //// N1: string inst;
896 //// N1: dbg.dispmon(dispmonScope, MON_INFO, psprintf("tapScanNstep(n=%0d, domain=%0b)"
897 //// N1: , n_step
898 //// N1: , domain
899 //// N1: ));
900 //// N1: sprintf(inst, "00000%b%b%s", n_step, domain, TAP_SCAN_NSTEP);
901 //// N1: dbg.dispmon(dispmonScope, MON_INFO, psprintf("Instruction: %s", inst));
902 //// N1: void = TapIRLoad(inst);
903 //// N1: TapGoto(TAP_UPDATE_IR);
904 //// N1: TapGoto(TAP_IDLE);
905 //// N1: dbg.dispmon(dispmonScope, MON_INFO, "... Done tapScanNstep()");
906 //// N1: }
907
908
909 //// TAP_FUSE_RVCLR
910 task tapFuseRvclr(bit enable, bit[5:0] rv_id) {
911 dbg.dispmon(dispmonScope, MON_INFO, "tapFuseRvclr()");
912 void = TapIRLoad(TAP_FUSE_RVCLR);
913 void = TapDRLoad(cnv2str({enable, rv_id}, 7));
914 TapGoto(TAP_UPDATE_DR);
915 TapGoto(TAP_IDLE);
916 dbg.dispmon(dispmonScope, MON_INFO, "... Done tapFuseRvclr()");
917 }
918
919 //----------- DMO access-----------
920 task DmoConfigAccess(bit[47:0] config_data) {
921 dbg.dispmon(dispmonScope, MON_INFO, "DmoConfigData");
922 void = TapIRLoad(TAP_DMO_CONFIG);
923 void = TapDRLoad(cnv2str(config_data, 48));
924 TapGoto(TAP_IDLE);
925 }
926
927 //// TAP_DMO_ACCESS
928 task tapDmoAccess() {
929 dbg.dispmon(dispmonScope, MON_INFO, "tapDmoAccess()");
930 void = TapIRLoad(TAP_DMO_ACCESS);
931 TapGoto(TAP_IDLE);
932 dbg.dispmon(dispmonScope, MON_INFO, "... Done tapDmoAccess()");
933 }
934
935 //// TAP_DMO_CLEAR
936 task tapDmoClear() {
937 dbg.dispmon(dispmonScope, MON_INFO, "tapDmoClear()");
938 void = TapIRLoad(TAP_DMO_CLEAR);
939 TapGoto(TAP_IDLE);
940 dbg.dispmon(dispmonScope, MON_INFO, "... Done tapDmoClear()");
941 }
942
943 // JTAG Private EFUSE
944 //////////////////////////////////////////////////////////////////
945 //-------- TAP_FUSE_READ -----------
946 task efuRead(bit[6:0] row_addr, bit[4:0] col_addr) {
947 dbg.dispmon(dispmonScope, MON_INFO, "efuRead()");
948
949 void = TapIRLoad(TAP_FUSE_ROW_ADDR);
950 void = TapDRLoad(cnv2str(row_addr, 7));
951 TapGoto(TAP_IDLE);
952
953 fork
954 {
955 @1 efuse_port.$efuse_rowaddr == row_addr;
956 }
957 {
958 toggleDutTck();
959 }
960 join
961 terminate;
962
963 void = TapIRLoad(TAP_FUSE_READ);
964 TapGoto(TAP_UPDATE_IR); // Note: UpdateIR is state just before Idle
965
966 fork
967 {
968 @1 efuse_port.$efuse_read_en == 1'b1; // Next cycle after UpdateIR (Idle) we should assert
969 @2 efuse_port.$efuse_read_en == 1'b0; // Following cycle we should deassert
970 }
971 {
972 TapGoto(TAP_IDLE); // Note: UpdateIR is state just before Idle
973 repeat (2) toggleDutTck();
974 }
975 join
976 terminate;
977
978 dbg.dispmon(dispmonScope, MON_INFO, "... Done efuRead()");
979 }
980
981 task efuColOne(bit[4:0] col_addr) {
982 dbg.dispmon(dispmonScope, MON_INFO, "efuColOne()");
983
984 void = TapIRLoad(TAP_FUSE_COL_ADDR);
985 void = TapDRLoad(cnv2str(col_addr, 5));
986 TapGoto(TAP_IDLE);
987
988 fork
989 {
990 //@1 efuse_port.$efuse_coladdr == col_addr;
991 @3 efuse_port.$efuse_sbc_efa_bit_addr == col_addr;
992 repeat (4) toggleDutTck();
993 }
994 join
995 terminate;
996
997 dbg.dispmon(dispmonScope, MON_INFO, "... Done efuColOne()");
998 }
999
1000 task efuReadOne(bit[6:0] row_addr, bit[4:0] col_addr, bit[2:0] read_mode) {
1001 dbg.dispmon(dispmonScope, MON_INFO, "efuReadMode()");
1002 void = TapIRLoad(TAP_FUSE_READ_MODE);
1003 void = TapDRLoad(cnv2str(read_mode, 3));
1004 TapGoto(TAP_IDLE);
1005
1006 fork
1007 {
1008 repeat(21) toggleDutTck();
1009 @@1,20 efuse_port.$efuse_read_mode == read_mode; // Check that readMode holds
1010 }
1011 join
1012 terminate;
1013
1014 void = TapIRLoad(TAP_FUSE_COL_ADDR);
1015 void = TapDRLoad(cnv2str(col_addr, 5));
1016 TapGoto(TAP_IDLE);
1017
1018 fork
1019 {
1020 repeat(3) toggleDutTck();
1021 //@1 efuse_port.$efuse_coladdr == col_addr;
1022 @3 efuse_port.$efuse_sbc_efa_bit_addr == col_addr;
1023 }
1024 join
1025 terminate;
1026
1027 dbg.dispmon(dispmonScope, MON_INFO, "efuRead()");
1028
1029 void = TapIRLoad(TAP_FUSE_ROW_ADDR);
1030 void = TapDRLoad(cnv2str(row_addr, 7));
1031 TapGoto(TAP_IDLE);
1032
1033 fork
1034 {
1035 repeat(3) toggleDutTck();
1036 //@1 efuse_port.$efuse_rowaddr == row_addr;
1037 @3 efuse_port.$efuse_sbc_efa_word_addr == row_addr;
1038 }
1039 join
1040 terminate;
1041
1042 dbg.dispmon(dispmonScope, MON_INFO, "... Done efuReadOne()");
1043 }
1044
1045 task efuReadData(bit[6:0] row_addr, bit[2:0] read_mode) {
1046 dbg.dispmon(dispmonScope, MON_INFO, "efuReadMode()");
1047 void = TapIRLoad(TAP_FUSE_READ_MODE);
1048 void = TapDRLoad(cnv2str(read_mode, 2));
1049 TapGoto(TAP_IDLE);
1050
1051 dbg.dispmon(dispmonScope, MON_INFO, "efuRead()");
1052
1053 void = TapIRLoad(TAP_FUSE_ROW_ADDR);
1054 void = TapDRLoad(cnv2str(row_addr, 7));
1055 TapGoto(TAP_IDLE);
1056
1057 void = TapIRLoad(TAP_FUSE_READ);
1058 TapGoto(TAP_IDLE); // Note: UpdateIR is state just before Idle
1059
1060 fork
1061 {
1062 repeat(6) toggleDutTck();
1063 @4 efuse_port.$efuse_efa_read_data == 32'hf0000803;
1064 @2 efuse_port.$efuse_read_data_ff == 32'hf0000803;
1065 }
1066 join
1067 terminate;
1068
1069 dbg.dispmon(dispmonScope, MON_INFO, "... Done efuReadData()");
1070 }
1071
1072 task efuTckShiftData(bit[6:0] row_addr, bit[2:0] read_mode) {
1073 dbg.dispmon(dispmonScope, MON_INFO, "efuReadMode()");
1074 void = TapIRLoad(TAP_FUSE_READ_MODE);
1075 void = TapDRLoad(cnv2str(read_mode, 2));
1076 TapGoto(TAP_IDLE);
1077
1078 dbg.dispmon(dispmonScope, MON_INFO, "efuRead()");
1079
1080 void = TapIRLoad(TAP_FUSE_ROW_ADDR);
1081 void = TapDRLoad(cnv2str(row_addr, 7));
1082 TapGoto(TAP_IDLE);
1083
1084 void = TapIRLoad(TAP_FUSE_READ);
1085 TapGoto(TAP_IDLE); // Note: UpdateIR is state just before Idle
1086
1087 fork
1088 {
1089 repeat(10) toggleDutTck();
1090 //@4 efuse_port.$efuse_efa_read_data == 32'hf0000803;
1091 @10 efuse_port.$efuse_read_data_ff == 32'hf0000803;
1092 }
1093 join
1094 terminate;
1095
1096 TapGoto(TAP_CAPTURE_DR);
1097 repeat(1) toggleDutTck();
1098
1099 //efuse_port.$efuse_tck_shft_data_ff == 32'hf0000803;
1100
1101 TapGoto(TAP_SHIFT_DR);
1102 repeat(30) toggleDutTck();
1103 TapGoto(TAP_IDLE);
1104
1105 dbg.dispmon(dispmonScope, MON_INFO, "... Done efuTckShiftData()");
1106 }
1107
1108 task efuTckShiftData_32(bit[6:0] row_addr, bit[2:0] read_mode) {
1109 dbg.dispmon(dispmonScope, MON_INFO, "efuReadMode()");
1110 void = TapIRLoad(TAP_FUSE_READ_MODE);
1111 void = TapDRLoad(cnv2str(read_mode, 2));
1112 TapGoto(TAP_IDLE);
1113
1114 dbg.dispmon(dispmonScope, MON_INFO, "efuRead()");
1115
1116 void = TapIRLoad(TAP_FUSE_ROW_ADDR);
1117 void = TapDRLoad(cnv2str(row_addr, 7));
1118 TapGoto(TAP_IDLE);
1119
1120 void = TapIRLoad(TAP_FUSE_READ);
1121 TapGoto(TAP_IDLE); // Note: UpdateIR is state just before Idle
1122
1123 //@4 efuse_port.$efuse_efa_read_data == 32'hf0000803;
1124 //@2 efuse_port.$efuse_read_data_ff == 32'hf0000803;
1125
1126 repeat(30) toggleDutTck();
1127
1128 TapGoto(TAP_CAPTURE_DR);
1129 repeat(1) toggleDutTck();
1130
1131 //efuse_port.$efuse_tck_shft_data_ff == 32'hf0000803;
1132
1133 TapGoto(TAP_SHIFT_DR);
1134 repeat(30) toggleDutTck();
1135 TapGoto(TAP_IDLE);
1136
1137 dbg.dispmon(dispmonScope, MON_INFO, "... Done efuTckShiftData()");
1138 }
1139
1140 task efuReadEn(bit[6:0] row_addr, bit[2:0] read_mode) {
1141 dbg.dispmon(dispmonScope, MON_INFO, "efuReadMode()");
1142 void = TapIRLoad(TAP_FUSE_READ_MODE);
1143 void = TapDRLoad(cnv2str(read_mode, 2));
1144 TapGoto(TAP_IDLE);
1145
1146 dbg.dispmon(dispmonScope, MON_INFO, "efuRead()");
1147
1148 void = TapIRLoad(TAP_FUSE_ROW_ADDR);
1149 void = TapDRLoad(cnv2str(row_addr, 7));
1150 TapGoto(TAP_IDLE);
1151
1152 void = TapIRLoad(TAP_FUSE_READ);
1153 TapGoto(TAP_UPDATE_IR); // Note: UpdateIR is state just before Idle
1154
1155 //@1 efuse_port.$efuse_read_en == 1'b1; // Next cycle after UpdateIR (Idle) we should assert
1156 //@2 efuse_port.$efuse_read_en == 1'b0; // Following cycle we should deassert
1157 //@2 efuse_port.$efuse_sbc_efa_read_en == 1'b1;
1158 fork
1159 {
1160 @4 efuse_port.$efuse_sbc_efa_read_en == 1'b1;
1161 repeat (4) toggleDutTck();
1162 }
1163 join
1164 terminate;
1165
1166 TapGoto(TAP_IDLE); // Note: UpdateIR is state just before Idle
1167
1168 dbg.dispmon(dispmonScope, MON_INFO, "... Done efuReadData()");
1169 }
1170
1171 task efuReadModeData(bit[2:0] read_mode) {
1172 dbg.dispmon(dispmonScope, MON_INFO, "efuReadMode()");
1173 void = TapIRLoad(TAP_FUSE_READ_MODE);
1174 void = TapDRLoad(cnv2str(read_mode, 3));
1175 TapGoto(TAP_IDLE);
1176
1177 fork
1178 {
1179 @@1,20 efuse_port.$efuse_read_mode == read_mode; // Check that readMode holds
1180 }
1181 {
1182 repeat(22) toggleDutTck();
1183 }
1184 join
1185 terminate;
1186
1187 dbg.dispmon(dispmonScope, MON_INFO, "... Done efuReadMode()");
1188 }
1189
1190 task efuProgOne(bit[6:0] row_addr, bit[4:0] col_addr, bit[2:0] read_mode) {
1191 efuse_port.$efuse_io_vpp = 1'b1;
1192 efuse_port.$efuse_io_pgrm_en = 1'b0 async;
1193
1194 dbg.dispmon(dispmonScope, MON_INFO, "efuReadMode()");
1195 void = TapIRLoad(TAP_FUSE_READ_MODE);
1196 void = TapDRLoad(cnv2str(read_mode, 2));
1197 TapGoto(TAP_IDLE);
1198
1199 void = TapIRLoad(TAP_FUSE_ROW_ADDR);
1200 void = TapDRLoad(cnv2str(row_addr, 7));
1201 TapGoto(TAP_IDLE);
1202
1203 dbg.dispmon(dispmonScope, MON_INFO, "efuColOne()");
1204
1205 void = TapIRLoad(TAP_FUSE_COL_ADDR);
1206 void = TapDRLoad(cnv2str(col_addr, 5));
1207 TapGoto(TAP_IDLE);
1208
1209 repeat(2) toggleDutTck();
1210
1211 efuse_port.$efuse_io_pgrm_en = 1'b1 async;
1212
1213 fork
1214 {
1215 repeat (3) toggleDutTck();
1216 }
1217 {
1218 @1 efuse_port.$efuse_pi_efa_prog_en == 1'b1;
1219 @1 efuse_port.$efuse_pwr_ok == 1'b1;
1220 @1 efuse_port.$efuse_por_n == 1'b1;
1221 }
1222 join
1223 terminate;
1224
1225 efuse_port.$efuse_io_pgrm_en = 1'b0 async;
1226
1227 dbg.dispmon(dispmonScope, MON_INFO, "efu read");
1228
1229 dbg.dispmon(dispmonScope, MON_INFO, "efuReadMode()");
1230 void = TapIRLoad(TAP_FUSE_READ_MODE);
1231 void = TapDRLoad(cnv2str(read_mode, 2));
1232 TapGoto(TAP_IDLE);
1233
1234 dbg.dispmon(dispmonScope, MON_INFO, "efu read");
1235
1236 void = TapIRLoad(TAP_FUSE_ROW_ADDR);
1237 void = TapDRLoad(cnv2str(row_addr, 7));
1238 TapGoto(TAP_IDLE);
1239
1240 void = TapIRLoad(TAP_FUSE_READ);
1241 TapGoto(TAP_UPDATE_IR); // Note: UpdateIR is state just before Idle
1242
1243 fork
1244 {
1245 repeat (10) toggleDutTck();
1246 @10 efuse_port.$efuse_read_data_ff == 32'h00000002;
1247 }
1248 join
1249 terminate;
1250
1251 TapGoto(TAP_IDLE); // Note: UpdateIR is state just before Idle
1252
1253 dbg.dispmon(dispmonScope, MON_INFO, "... Done efuReadData()");
1254 }
1255
1256 task efuProg32(bit[6:0] row_addr, bit[4:0] col_addr, bit[2:0] read_mode) {
1257 efuse_port.$efuse_io_vpp = 1'b1;
1258 efuse_port.$efuse_io_pgrm_en = 1'b0 async;
1259
1260 dbg.dispmon(dispmonScope, MON_INFO, "efuReadMode()");
1261 void = TapIRLoad(TAP_FUSE_READ_MODE);
1262 void = TapDRLoad(cnv2str(read_mode, 2));
1263 TapGoto(TAP_IDLE);
1264
1265 void = TapIRLoad(TAP_FUSE_ROW_ADDR);
1266 void = TapDRLoad(cnv2str(row_addr, 7));
1267 TapGoto(TAP_IDLE);
1268
1269 dbg.dispmon(dispmonScope, MON_INFO, "efuColOne()");
1270
1271 void = TapIRLoad(TAP_FUSE_COL_ADDR);
1272 void = TapDRLoad(cnv2str(col_addr, 5));
1273 TapGoto(TAP_IDLE);
1274
1275 repeat(2) toggleDutTck();
1276
1277 efuse_port.$efuse_io_pgrm_en = 1'b1 async;
1278 fork
1279 {
1280 repeat (3) toggleDutTck();
1281 }
1282 {
1283 @1 efuse_port.$efuse_pi_efa_prog_en == 1'b1;
1284 @1 efuse_port.$efuse_pwr_ok == 1'b1;
1285 @1 efuse_port.$efuse_por_n == 1'b1;
1286 }
1287 join
1288 terminate;
1289
1290 efuse_port.$efuse_io_pgrm_en = 1'b0 async;
1291
1292 dbg.dispmon(dispmonScope, MON_INFO, "efu read");
1293
1294 dbg.dispmon(dispmonScope, MON_INFO, "efuReadMode()");
1295 void = TapIRLoad(TAP_FUSE_READ_MODE);
1296 void = TapDRLoad(cnv2str(read_mode, 2));
1297 TapGoto(TAP_IDLE);
1298
1299 dbg.dispmon(dispmonScope, MON_INFO, "efu read");
1300
1301 void = TapIRLoad(TAP_FUSE_ROW_ADDR);
1302 void = TapDRLoad(cnv2str(row_addr, 7));
1303 TapGoto(TAP_IDLE);
1304
1305 void = TapIRLoad(TAP_FUSE_READ);
1306 TapGoto(TAP_IDLE); // Note: UpdateIR is state just before Idle
1307
1308 repeat(20) toggleDutTck();
1309
1310 dbg.dispmon(dispmonScope, MON_INFO, "... Done efuReadData()");
1311 }
1312
1313 task efuBypData(bit[31:0] byp_data) {
1314 bit [31:0] byp_data_inv;
1315
1316 byp_data_inv = {byp_data[0], byp_data[1], byp_data[2], byp_data[3], byp_data[4], byp_data[5],
1317 byp_data[6], byp_data[7], byp_data[8], byp_data[9], byp_data[10], byp_data[11],
1318 byp_data[12], byp_data[13], byp_data[14], byp_data[15], byp_data[16], byp_data[17],
1319 byp_data[18], byp_data[19], byp_data[20], byp_data[21], byp_data[22], byp_data[23],
1320 byp_data[24], byp_data[25], byp_data[26], byp_data[27], byp_data[28], byp_data[29],
1321 byp_data[30], byp_data[31]};
1322
1323 dbg.dispmon(dispmonScope, MON_INFO, "efuBypData");
1324 void = TapIRLoad(TAP_FUSE_BYPASS_DATA);
1325 void = TapDRLoad(cnv2str(byp_data_inv, 32));
1326 TapGoto(TAP_IDLE);
1327
1328 dbg.dispmon(dispmonScope, MON_INFO, "efuBypass");
1329 void = TapIRLoad(TAP_FUSE_BYPASS);
1330 TapGoto(TAP_IDLE);
1331 //@1 efuse_port.$efuse_fuse_bypass == 1'b1;
1332 //@1 efuse_port.$efuse_fuse_bypass == 1'b0;
1333 //efuse_port.$efu_ncu_coreavl_xfer_en == 1'b1;
1334 //repeat(20) toggleDutTck();
1335 dbg.dispmon(dispmonScope, MON_INFO, "... Done efuBypData()");
1336 }
1337
1338 task efuBypData_bankavl(bit[31:0] byp_data) {
1339 bit [31:0] byp_data_inv;
1340
1341 byp_data_inv = {byp_data[0], byp_data[1], byp_data[2], byp_data[3], byp_data[4], byp_data[5],
1342 byp_data[6], byp_data[7], byp_data[8], byp_data[9], byp_data[10], byp_data[11],
1343 byp_data[12], byp_data[13], byp_data[14], byp_data[15], byp_data[16], byp_data[17],
1344 byp_data[18], byp_data[19], byp_data[20], byp_data[21], byp_data[22], byp_data[23],
1345 byp_data[24], byp_data[25], byp_data[26], byp_data[27], byp_data[28], byp_data[29],
1346 byp_data[30], byp_data[31]};
1347
1348 dbg.dispmon(dispmonScope, MON_INFO, "efuBypData");
1349 void = TapIRLoad(TAP_FUSE_BYPASS_DATA);
1350 void = TapDRLoad(cnv2str(byp_data_inv, 32));
1351 TapGoto(TAP_IDLE);
1352
1353 dbg.dispmon(dispmonScope, MON_INFO, "efuBypass");
1354 void = TapIRLoad(TAP_FUSE_BYPASS);
1355 TapGoto(TAP_UPDATE_IR);
1356
1357 fork
1358 {
1359 repeat (5) toggleDutTck();
1360 }
1361 {
1362 @1 efuse_port.$efuse_fuse_bypass == 1'b1;
1363 @2 efuse_port.$efuse_fuse_bypass == 1'b0;
1364 @2 efuse_port.$efu_ncu_bankavl_xfer_en == 1'b1;
1365 }
1366 join
1367 terminate;
1368
1369 TapGoto(TAP_IDLE);
1370
1371 dbg.dispmon(dispmonScope, MON_INFO, "... Done efuBypData()");
1372 }
1373
1374 task efuBypData_l2t1(bit[31:0] byp_data) {
1375 bit [31:0] byp_data_inv;
1376
1377 byp_data_inv = {byp_data[0], byp_data[1], byp_data[2], byp_data[3], byp_data[4], byp_data[5],
1378 byp_data[6], byp_data[7], byp_data[8], byp_data[9], byp_data[10], byp_data[11],
1379 byp_data[12], byp_data[13], byp_data[14], byp_data[15], byp_data[16], byp_data[17],
1380 byp_data[18], byp_data[19], byp_data[20], byp_data[21], byp_data[22], byp_data[23],
1381 byp_data[24], byp_data[25], byp_data[26], byp_data[27], byp_data[28], byp_data[29],
1382 byp_data[30], byp_data[31]};
1383
1384 dbg.dispmon(dispmonScope, MON_INFO, "efuBypData");
1385 void = TapIRLoad(TAP_FUSE_BYPASS_DATA);
1386 void = TapDRLoad(cnv2str(byp_data_inv, 32));
1387 TapGoto(TAP_IDLE);
1388
1389 dbg.dispmon(dispmonScope, MON_INFO, "efuBypass");
1390 void = TapIRLoad(TAP_FUSE_BYPASS);
1391 TapGoto(TAP_UPDATE_IR);
1392
1393 fork
1394 {
1395 repeat (3) toggleDutTck();
1396 }
1397 {
1398 @1 efuse_port.$efuse_fuse_bypass == 1'b1;
1399 @2 efuse_port.$efuse_fuse_bypass == 1'b0;
1400 //@2 efuse_port.$efu_l2t1_fuse_xfer_en == 1'b1;
1401 }
1402 join
1403 terminate;
1404
1405 TapGoto(TAP_IDLE);
1406
1407 dbg.dispmon(dispmonScope, MON_INFO, "... Done efuBypData()");
1408 }
1409
1410 task efuBypData_new(bit[31:0] byp_data) {
1411 bit [31:0] byp_data_inv;
1412
1413 byp_data_inv = {byp_data[0], byp_data[1], byp_data[2], byp_data[3], byp_data[4], byp_data[5],
1414 byp_data[6], byp_data[7], byp_data[8], byp_data[9], byp_data[10], byp_data[11],
1415 byp_data[12], byp_data[13], byp_data[14], byp_data[15], byp_data[16], byp_data[17],
1416 byp_data[18], byp_data[19], byp_data[20], byp_data[21], byp_data[22], byp_data[23],
1417 byp_data[24], byp_data[25], byp_data[26], byp_data[27], byp_data[28], byp_data[29],
1418 byp_data[30], byp_data[31]};
1419
1420 dbg.dispmon(dispmonScope, MON_ALWAYS, "efuBypData...");
1421 void = TapIRLoad(TAP_FUSE_BYPASS_DATA);
1422 void = TapDRLoad(cnv2str(byp_data_inv, 32));
1423 TapGoto(TAP_IDLE);
1424
1425 dbg.dispmon(dispmonScope,MON_ALWAYS , "efuBypass...");
1426 void = TapIRLoad(TAP_FUSE_BYPASS);
1427 TapGoto(TAP_IDLE);
1428 dbg.dispmon(dispmonScope, MON_ALWAYS, "... Done efuBypData_new()");
1429 }
1430
1431 //-------- TAP_FUSE_BYPASS_DATA -----------
1432 task efuBypassData(bit[31:0] byp_data) {
1433 bit [31:0] byp_data_inv;
1434
1435 byp_data_inv = {byp_data[0], byp_data[1], byp_data[2], byp_data[3], byp_data[4], byp_data[5],
1436 byp_data[6], byp_data[7], byp_data[8], byp_data[9], byp_data[10], byp_data[11],
1437 byp_data[12], byp_data[13], byp_data[14], byp_data[15], byp_data[16], byp_data[17],
1438 byp_data[18], byp_data[19], byp_data[20], byp_data[21], byp_data[22], byp_data[23],
1439 byp_data[24], byp_data[25], byp_data[26], byp_data[27], byp_data[28], byp_data[29],
1440 byp_data[30], byp_data[31]};
1441 dbg.dispmon(dispmonScope, MON_INFO, "efuBypData");
1442 void = TapIRLoad(TAP_FUSE_BYPASS_DATA);
1443 void = TapDRLoad(cnv2str(byp_data_inv, 32));
1444 TapGoto(TAP_IDLE);
1445 dbg.dispmon(dispmonScope, MON_INFO, "... Done efuBypData()");
1446 }
1447
1448 //-------- TAP_FUSE_BYPASS -----------
1449 task efuBypass() {
1450 dbg.dispmon(dispmonScope, MON_INFO, "efuBypass()");
1451 void = TapIRLoad(TAP_FUSE_BYPASS);
1452 TapGoto(TAP_IDLE); // Note: UpdateIR is state just before Idle
1453 dbg.dispmon(dispmonScope, MON_INFO, "... Done efuBypass()");
1454 }
1455
1456 //-------- TAP_FUSE_READ_MODE -----------
1457 task efuReadMode(bit[1:0] readMode) {
1458 dbg.dispmon(dispmonScope, MON_INFO, "efuReadMode()");
1459 void = TapIRLoad(TAP_FUSE_READ_MODE);
1460 void = TapDRLoad(cnv2str(readMode, 2));
1461 TapGoto(TAP_IDLE);
1462 //@@1,20 efuse_port.$efuse_read_mode == readMode; // Check that readMode holds
1463 repeat(20) toggleDutTck();
1464 dbg.dispmon(dispmonScope, MON_INFO, "... Done efuReadMode()");
1465 }
1466
1467 //-------- TAP_FUSE_DEST_SAMPLE -----------
1468 task efuDestSample() {
1469 dbg.dispmon(dispmonScope, MON_ALWAYS, "efuDestSample()");
1470 void = TapIRLoad(TAP_FUSE_DEST_SAMPLE);
1471 TapGoto(TAP_UPDATE_IR); // Note: UpdateIR is state just before Idle
1472
1473 fork
1474 {
1475 @1 efuse_port.$efuse_dest_sample == 1'b1; // Next cycle after UpdateIR (Idle) we should assert
1476 @2 efuse_port.$efuse_dest_sample == 1'b0; // Following cycle we should deassert
1477 }
1478 {
1479 TapGoto(TAP_IDLE); // Note: UpdateIR is state just before Idle
1480 repeat(10) toggleDutTck();
1481 }
1482 join
1483 terminate;
1484
1485 dbg.dispmon(dispmonScope, MON_ALWAYS, "... Done efuDestSample()");
1486 }
1487
1488 //----------- Modelled on N1 in ios_mon.v -----------
1489 // Parallel data load (32bits x 16 words) used for testing parallel scan in different clock domains -csr
1490 task TapDRPData(integer preample, var bit [31:0] si_data[16], var bit [31:0] so_data[16]) {
1491 integer i, j;
1492 integer w=32;
1493 bit [31:0] d;
1494
1495 dbg.dispmon(dispmonScope, MON_INFO, psprintf("TapDRPData (p=%0d)", preample));
1496 if (tap_state_reg != TAP_SHIFT_DR)
1497 TapGoto(TAP_SHIFT_DR);
1498
1499 repeat (preample)
1500 toggleDutTck();
1501
1502 tap_port.$tdi <= 0;
1503 for (i=0; i<w; i++) {
1504 for (j=0; j<16; j++) {
1505 d = si_data[j];
1506 pkg_port.$DBG_DQ_out[DBG_DQ__INPUT__SCAN_IN__LSB + j] <= d[i]; // scan_port.$pscan_si[j] <= d[i]; // should be the same as before
1507 }
1508 void = TapNext((i == w-1) ? TAP_NEXT_ADVANCE : TAP_NEXT_REMAIN, d[i]);
1509 for (j=0; j<16; j++) {
1510 d = so_data[j];
1511 d[i] = scan_port.$pscan_so[j];
1512 so_data[j] = d;
1513 }
1514 }
1515 tap_port.$tdi <= 1'bx;
1516 TapGoto(TAP_PAUSE_DR);
1517 TapGoto(TAP_IDLE);
1518 }
1519
1520 //
1521 //// This will test serial/parallel scan under the control of the TCU unit (TEST_MODE = 1'b1)
1522 function integer n2MfgScanIO(integer maxChainSize) {
1523 integer scanIndex;
1524 integer scanCounter;
1525 integer scanCount[32];
1526 tap_port.$test_mode = 1'b1; // Send ourselves to MFG scan mode
1527 n2MfgScanIO = 0;
1528
1529 pkg_port.$DBG_DQ_out[DBG_DQ__INPUT__SCAN_EN] = 1'b1; // scan_port.$scan_en = 1'b1; // should be same as before
1530 pkg_port.$DBG_DQ_out[DBG_DQ__INPUT__SCAN_IN__MSB : DBG_DQ__INPUT__SCAN_IN__LSB] = 32'bx; // scan_port.$pscan_si = 32'bx; // Send us to an unknown state
1531 scan_port.$jtag_si = 32'bx; // Send us to an unknown state
1532
1533 for (scanIndex = 0; scanIndex < 32; scanIndex++) {
1534 scanCount[scanIndex] = 0;
1535 }
1536
1537 //--------- Load chains with all 1's --------------
1538 repeat(maxChainSize) {
1539 toggleDutTck();
1540 pkg_port.$DBG_DQ_out[DBG_DQ__INPUT__SCAN_IN__MSB : DBG_DQ__INPUT__SCAN_IN__LSB] = ~(32'b0); // scan_port.$pscan_si = ~(32'b0); // Set value at chip internals
1541 scan_port.$jtag_si = ~(32'b0); // Set value at chip internals
1542 }
1543
1544 toggleDutTck();
1545 toggleDutTck();
1546 scanCounter = 0;
1547 pkg_port.$DBG_DQ_out[DBG_DQ__INPUT__SCAN_IN__MSB : DBG_DQ__INPUT__SCAN_IN__LSB] = 32'b0; // scan_port.$pscan_si = 32'b0;
1548
1549 //--------- Save how long it takes zero to make it through --------------
1550 while ( (|(scan_port.$jtag_so) !== 1'b0) && (scanCounter < maxChainSize) ) {
1551 toggleDutTck();
1552 scanCounter++;
1553 for (scanIndex = 0; scanIndex < 32; scanIndex++) {
1554 if ( scan_port.$jtag_so[scanIndex] === 1'b1 ) scanCount[scanIndex] = scanCounter;
1555 if ( scan_port.$jtag_so[scanIndex] === 1'bx ) scanCount[scanIndex] = -1;
1556 if ( scan_port.$jtag_so[scanIndex] === 1'bz ) scanCount[scanIndex] = -1;
1557 }
1558 }
1559 for (scanIndex = 0; scanIndex < 32; scanIndex++) {
1560 n2MfgScanIO += scanCount[scanIndex] === -1; // Error if the scan length is not known
1561 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("Scanout[%0d] chain length: %0d", scanIndex, scanCount[scanIndex]));
1562 }
1563
1564 pkg_port.$DBG_DQ_out[DBG_DQ__INPUT__SCAN_EN] = 1'b0; // scan_port.$scan_en = 1'b0; // should be the same as before
1565 tap_port.$test_mode = 1'b0;
1566 repeat (10) toggleDutTck();
1567 }
1568
1569 // created for TCU Debug Interface to SPC core - Adam
1570 function bit[63:0] cregCoreRun (bit[63:0] CoreRunData) {
1571 bit[63:0] cregOut;
1572 this.tap_creg_addr(NCU_ASI_CORE_RUNNING_RW_REG);
1573 this.tap_creg_wdata(CoreRunData);
1574 this.tap_iob_write();
1575 cregOut = tap_creg_rdata();
1576 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("NCU_ASI_CORE_RUNNING_RW_REG: Expected:%h, Got=%h", CoreRunData, cregOut));
1577 // tcu_diag += (cregOut !== CoreRunData);
1578 }
1579
1580 function bit[7:0] tapDossStatus(bit [7:0] DossStatusReg) {
1581 string scanOut;
1582 scanOut = TapIRLoad(TAP_DOSS_STATUS);
1583 scanOut = TapDRLoad(cnv2str(DossStatusReg, 8));
1584 TapGoto(TAP_UPDATE_DR);
1585 TapGoto(TAP_IDLE);
1586 tapDossStatus = scanOut.atobin();
1587 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("... Done tapDossStatus()", tapDossStatus));
1588 }
1589
1590 task tapSSRequest() {
1591 void = TapIRLoad(TAP_SS_REQUEST);
1592 TapGoto(TAP_UPDATE_DR);
1593 TapGoto(TAP_IDLE);
1594 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("... Done tapSSRequest()"));
1595 }
1596
1597 function bit[63:0] tapCoreRunStatus(bit [63:0] doneRegister) {
1598 string scanOut;
1599 scanOut = TapIRLoad(TAP_CORE_RUN_STATUS);
1600 scanOut = TapDRLoad(cnv2str(doneRegister, 64));
1601 TapGoto(TAP_UPDATE_DR);
1602 TapGoto(TAP_IDLE);
1603 tapCoreRunStatus = scanOut.atobin();
1604 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("... Done tapCoreRunStatus()"));
1605 }
1606
1607 function bit [63:0] tapDossEnable(bit [63:0] DossEnableRegister) {
1608 string scanOut;
1609 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("tapDossEnable() [Register='h%0h]", DossEnableRegister));
1610 scanOut = TapIRLoad(TAP_DOSS_ENABLE);
1611 scanOut = TapDRLoad(cnv2str(DossEnableRegister, 64));
1612 TapGoto(TAP_UPDATE_DR);
1613 TapGoto(TAP_IDLE);
1614 tapDossEnable = scanOut.atobin();
1615 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("... Done tapDossEnable()"));
1616 }
1617
1618 function bit [1:0] tapDossMode(bit [1:0] DossModeRegister) {
1619 string scanOut;
1620 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("tapDossMode() [Register='b%2b]", DossModeRegister));
1621 scanOut = TapIRLoad(TAP_DOSS_MODE);
1622 scanOut = TapDRLoad(cnv2str(DossModeRegister, 2));
1623 TapGoto(TAP_UPDATE_DR);
1624 TapGoto(TAP_IDLE);
1625 tapDossMode = scanOut.atobin();
1626 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("... Done tapDossMode()"));
1627 }
1628
1629 function bit [7:0] tapCoreSel(bit [7:0] CoreSelRegister) {
1630 string scanOut;
1631 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("tapCoreSel() [Register=8'h%h]", CoreSelRegister));
1632 scanOut = TapIRLoad(TAP_CORE_SEL);
1633 scanOut = TapDRLoad(cnv2str(CoreSelRegister, 8));
1634 TapGoto(TAP_UPDATE_DR);
1635 TapGoto(TAP_IDLE);
1636 tapCoreSel = scanOut.atobin();
1637 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("... Done tapCoreSel()"));
1638 }
1639
1640 task tapClockHStop() {
1641 void = TapIRLoad(TAP_CLOCK_HSTOP);
1642 TapGoto(TAP_UPDATE_IR);
1643 TapGoto(TAP_IDLE);
1644 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("... Done tapClockHStop()"));
1645 }
1646
1647 task tapClockSStop() {
1648 void = TapIRLoad(TAP_CLOCK_SSTOP);
1649 TapGoto(TAP_UPDATE_IR);
1650 TapGoto(TAP_IDLE);
1651 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("... Done tapClockSStop()"));
1652 }
1653
1654 task tapClockStart() {
1655 void = TapIRLoad(TAP_CLOCK_START);
1656 TapGoto(TAP_UPDATE_IR);
1657 TapGoto(TAP_IDLE);
1658 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("... Done tapClockStart()"));
1659 }
1660
1661 function bit [31:0] tapDeCount(bit [31:0] dataRegisterValue) { // TCU Debug Event Counter register
1662 string scanOut;
1663 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("tapDeCount() [Register=32'h%h]", dataRegisterValue));
1664 scanOut = TapIRLoad(TAP_DE_COUNT);
1665 scanOut = TapDRLoad(cnv2str(dataRegisterValue, 32));
1666 TapGoto(TAP_UPDATE_DR);
1667 TapGoto(TAP_IDLE);
1668 tapDeCount = scanOut.atobin();
1669 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("... Done tapDeCount()"));
1670 }
1671
1672 function bit [3:0] tapTcuDcr(bit [3:0] dataRegisterValue) { // TCU Debug Control Register
1673 string scanOut;
1674 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("tapTcuDcr() [Register=4'h%h]", dataRegisterValue));
1675 scanOut = TapIRLoad(TAP_TCU_DCR);
1676 scanOut = TapDRLoad(cnv2str(dataRegisterValue, 4));
1677 TapGoto(TAP_UPDATE_DR);
1678 TapGoto(TAP_IDLE);
1679 tapTcuDcr = scanOut.atobin();
1680 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("... Done tapTcuDcr()"));
1681 }
1682
1683 function bit [63:0] tapCycleCount(bit [63:0] CycleCountRegister) {
1684 string scanOut;
1685 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("tapCycleCount() [Register=64'h%h]",CycleCountRegister));
1686 scanOut = TapIRLoad(TAP_CYCLE_COUNT);
1687 scanOut = TapDRLoad(cnv2str(CycleCountRegister, 64));
1688 TapGoto(TAP_UPDATE_DR);
1689 TapGoto(TAP_IDLE);
1690 tapCycleCount = scanOut.atobin();
1691 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("... Done tapCycleCount()"));
1692 }
1693
1694 function bit tapCSMode(bit CSModeRegister) {
1695 string scanOut;
1696 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("tapCSMode() [Register=1'b%1b]",CSModeRegister));
1697 scanOut = TapIRLoad(TAP_CS_MODE);
1698 scanOut = TapDRLoad(cnv2str(CSModeRegister, 1));
1699 TapGoto(TAP_UPDATE_DR);
1700 TapGoto(TAP_IDLE);
1701 tapCSMode = scanOut.atobin();
1702 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("... Done tapCSMode()"));
1703 }
1704
1705 function bit tapCSStatus(bit CSStatusRegister) {
1706 string scanOut;
1707 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("tapCSStatus() [Register=1'b%1b]",CSStatusRegister));
1708 scanOut = TapIRLoad(TAP_CS_STATUS);
1709 scanOut = TapDRLoad(cnv2str(CSStatusRegister, 1));
1710 TapGoto(TAP_UPDATE_DR);
1711 TapGoto(TAP_IDLE);
1712 tapCSStatus = scanOut.atobin();
1713 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("... Done tapCSStatus()"));
1714 }
1715
1716 function bit [1:0] tapClockStatus(bit [1:0] ClockStatusRegister) {
1717 string scanOut;
1718 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("tapClockStatus() [Register=2'b%2b]",ClockStatusRegister));
1719 scanOut = TapIRLoad(TAP_CLOCK_STATUS);
1720 scanOut = TapDRLoad(cnv2str(ClockStatusRegister, 2));
1721 TapGoto(TAP_UPDATE_DR);
1722 TapGoto(TAP_IDLE);
1723 tapClockStatus = scanOut.atobin();
1724 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("... Done tapClockStatus()"));
1725 }
1726
1727 function bit [6:0] tapClkStopDelay(bit [6:0] ClkStopDelayRegister) {
1728 string scanOut;
1729 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("tapClkStopDelay() [Register=7'h%h]",ClkStopDelayRegister));
1730 scanOut = TapIRLoad(TAP_CLKSTP_DELAY);
1731 scanOut = TapDRLoad(cnv2str(ClkStopDelayRegister, 7));
1732 TapGoto(TAP_UPDATE_DR);
1733 TapGoto(TAP_IDLE);
1734 tapClkStopDelay = scanOut.atobin();
1735 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("... Done tapClkStopDelay()"));
1736 }
1737
1738 function bit [31:0] tapClockDomain(bit [31:0] ClockDomainRegister) {
1739 string scanOut;
1740 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("tapClockDomain() [Register=32'h%h]",ClockDomainRegister));
1741 scanOut = TapIRLoad(TAP_CLOCK_DOMAIN);
1742 scanOut = TapDRLoad(cnv2str(ClockDomainRegister, 32));
1743 TapGoto(TAP_UPDATE_DR);
1744 TapGoto(TAP_IDLE);
1745 tapClockDomain = scanOut.atobin();
1746 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("... Done tapClockDomain()"));
1747 }
1748
1749 // check the length of the data register
1750 function integer tapDataRegLength(string tapRegister, string tapRegName, integer width, integer maxlength=256) {
1751 //32 bit number
1752 string checknumber = "10110011100011110000111110000010";
1753 string zerovector = "00000000000000000000000000000000";
1754 string TDO_out1;
1755 string TDO_out2;
1756 string TDO_out;
1757 string pos_match;
1758 integer len = 0;
1759 integer measured = 0;
1760
1761 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("Measure the data register length for %s instruction\n", tapRegName));
1762
1763 TDO_out = TapIRLoad(tapRegister);
1764 TapGoto(TAP_SHIFT_DR);
1765
1766 TDO_out2 = TapDRLoad(checknumber);
1767
1768 while((!measured) && (len < maxlength)) {
1769 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("Total Number of bits shifted-in: %1d\n",len+32));
1770 TDO_out1 = TDO_out2;
1771 TDO_out2 = TapDRLoad(zerovector);
1772 sprintf(TDO_out,"%s%s",TDO_out2,TDO_out1);
1773 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("DataRegisterLength shifted-out (%0d): %s\n", TDO_out.len(),TDO_out));
1774 if(TDO_out.match(checknumber)) {
1775 measured = 1;
1776 pos_match = TDO_out.postmatch();
1777 len += pos_match.len();
1778 } else
1779 len += zerovector.len();
1780 }
1781 if(len >= maxlength) {
1782 dbg.dispmon(dispmonScope, MON_ERR, psprintf("Data register length measurement failed with maxlength: %d\n", maxlength));
1783 dbg.dispmon(dispmonScope, MON_ERR, psprintf("You may retry by increaing the maxlength parameter\n"));
1784 len = -1;
1785 }
1786
1787 if (len != width) {
1788 dbg.dispmon(dispmonScope,MON_ERR, psprintf("ERROR: Data register length check for %s failed, Got=%d, Expected:=%d\n", tapRegName, len, width));
1789 }
1790 else {
1791 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("Data register length measured for %s instruction: %0d\n", tapRegName, len));
1792 }
1793
1794 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("... Done tapDataRegLength()"));
1795 tapDataRegLength = len;
1796 }
1797
1798 // Added for JTAG data register check - Adam
1799 function bit [79:0] tapDataRegCheckRead(string tapRegister, string tapRegName, integer width) {
1800 string scanOut;
1801 bit [79:0] tapDataRegOut;
1802 bit [79:0] tapDataIn;
1803
1804 scanOut = TapIRLoad(tapRegister);
1805 scanOut = TapDRLoad(cnv2str(tapDataIn, width));
1806 TapGoto(TAP_UPDATE_DR);
1807 TapGoto(TAP_IDLE);
1808 tapDataRegOut = scanOut.atobin();
1809 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("%s Register='h%0h", tapRegName,tapDataRegOut[width-1:0]));
1810 tapDataRegCheckRead = tapDataRegOut;
1811 }
1812
1813 function bit [79:0] tapDataRegCheck(string tapRegister, string tapRegName, integer width) {
1814 string scanOut;
1815 bit [79:0] tapDataRegOut, tapExpectDataRegOut;
1816 bit [79:0] tapDataIn;
1817 integer i=0;
1818
1819 scanOut = TapIRLoad(tapRegister);
1820 tapDataIn = {80{1'b1}};
1821
1822 for (i=0; i<3; i++) {
1823 tapExpectDataRegOut = ~tapDataIn;
1824 if (tapRegister == TAP_CLOCK_DOMAIN)
1825 tapExpectDataRegOut[79:24] = {56{1'b0}};
1826 scanOut = TapDRLoad(cnv2str(tapDataIn, width));
1827 TapGoto(TAP_UPDATE_DR);
1828 TapGoto(TAP_IDLE);
1829 tapDataRegOut = scanOut.atobin();
1830 if (i>0) {
1831 dbg.dispmon(dispmonScope, MON_ALWAYS, psprintf("%s Register='h%0h, Expected='h%0h\n", tapRegName,tapDataRegOut, tapExpectDataRegOut[width-1:0]));
1832 if (tapDataRegOut[width-1:0] !== tapExpectDataRegOut[width-1:0])
1833 dbg.dispmon(dispmonScope,MON_ERR, psprintf("ERROR: %s, Got='h%0h, Expected:='h%0h\n", tapRegName,tapDataRegOut[width-1:0], tapExpectDataRegOut[width-1:0]));
1834 }
1835 tapDataIn = ~tapDataIn;
1836 }
1837 tapDataRegCheck = tapDataRegOut;
1838 }
1839
1840 function bit [7:0] tapLbistBypass(bit [7:0] bypassRegister) {
1841 string scanOut;
1842 dbg.dispmon(dispmonScope, MON_INFO, psprintf("tapLbistBypass() [Register='h%0h]", bypassRegister));
1843 scanOut = TapIRLoad(TAP_LBIST_BYPASS);
1844 scanOut = TapDRLoad(cnv2str(bypassRegister, 8));
1845 TapGoto(TAP_UPDATE_DR);
1846 TapGoto(TAP_IDLE);
1847 tapLbistBypass = scanOut.atobin();
1848 dbg.dispmon(dispmonScope, MON_ALWAYS, "... Done tapLbistBypass()");
1849 }
1850
1851 function bit [1:0] tapLbistMode(bit [1:0] modeRegister) {
1852 string scanOut;
1853 dbg.dispmon(dispmonScope, MON_INFO, psprintf("tapLbistMode() [Register='h%0h]", modeRegister));
1854 scanOut = TapIRLoad(TAP_LBIST_MODE);
1855 scanOut = TapDRLoad(cnv2str(modeRegister, 2));
1856 TapGoto(TAP_UPDATE_DR);
1857 TapGoto(TAP_IDLE);
1858 tapLbistMode = scanOut.atobin();
1859 dbg.dispmon(dispmonScope, MON_ALWAYS, "... Done tapLbistMode()");
1860 }
1861
1862 task tapLbistAccess() {
1863 dbg.dispmon(dispmonScope, MON_INFO, "tapLbistDiag()");
1864 void = TapIRLoad(TAP_LBIST_ACCESS);
1865 TapGoto(TAP_UPDATE_IR);
1866 TapGoto(TAP_IDLE);
1867 dbg.dispmon(dispmonScope, MON_ALWAYS, "... Done tapLbistAccess()");
1868 }
1869
1870 task tapLbistStart() {
1871 dbg.dispmon(dispmonScope, MON_INFO, "tapLbistStart()");
1872 void = TapIRLoad(TAP_LBIST_START);
1873 TapGoto(TAP_UPDATE_IR);
1874 TapGoto(TAP_IDLE);
1875 dbg.dispmon(dispmonScope, MON_ALWAYS, "... Done tapLbistStart()");
1876 }
1877
1878 task tapLbistAbort() {
1879 dbg.dispmon(dispmonScope, MON_INFO, "tapLbistAbort()");
1880 void = TapIRLoad(TAP_LBIST_ABORT);
1881 TapGoto(TAP_UPDATE_IR);
1882 TapGoto(TAP_IDLE);
1883 dbg.dispmon(dispmonScope, MON_ALWAYS, "... Done tapLbistAbort()");
1884 }
1885
1886
1887 function bit [7:0] tapLbistGetdone(bit [7:0] doneRegister) {
1888 string scanOut;
1889 dbg.dispmon(dispmonScope, MON_INFO, "tapLbistGetdone()");
1890 scanOut = TapIRLoad(TAP_LBIST_GETDONE);
1891 scanOut = TapDRLoad(cnv2str(doneRegister, 8));
1892 TapGoto(TAP_UPDATE_DR);
1893 TapGoto(TAP_IDLE);
1894 tapLbistGetdone = scanOut.atobin();
1895 dbg.dispmon(dispmonScope, MON_ALWAYS, "... Done tapLbistGetdone()");
1896 }
1897
1898 task tapStciAccess() {
1899 dbg.dispmon(dispmonScope, MON_INFO, "tapStciAccess()");
1900 void = TapIRLoad(TAP_STCI_ACCESS);
1901 TapGoto(TAP_UPDATE_IR);
1902 TapGoto(TAP_IDLE);
1903 dbg.dispmon(dispmonScope, MON_ALWAYS, "... Done tapStciAccess()");
1904 }
1905
1906 task tapStciClear() {
1907 dbg.dispmon(dispmonScope, MON_INFO, "tapStciClear()");
1908 void = TapIRLoad(TAP_STCI_CLEAR);
1909 TapGoto(TAP_UPDATE_IR);
1910 TapGoto(TAP_IDLE);
1911 dbg.dispmon(dispmonScope, MON_ALWAYS, "... Done tapStciClear()");
1912 }
1913
1914 function bit tapJtporStatus(bit JtporStatusRegister) {
1915 string scanOut;
1916 dbg.dispmon(dispmonScope, MON_INFO, "tapJtporStatus()");
1917 scanOut = TapIRLoad(TAP_JTPOR_STATUS);
1918 scanOut = TapDRLoad(cnv2str(JtporStatusRegister, 1));
1919 TapGoto(TAP_UPDATE_DR);
1920 TapGoto(TAP_IDLE);
1921 tapJtporStatus = scanOut.atobin();
1922 dbg.dispmon(dispmonScope, MON_INFO, "... Done tapJtporStatus()");
1923 }
1924
1925 task tapDMOAccess() {
1926 dbg.dispmon(dispmonScope, MON_INFO, "tapDMOAccess()");
1927 void = TapIRLoad(TAP_DMO_ACCESS);
1928 TapGoto(TAP_UPDATE_IR);
1929 TapGoto(TAP_IDLE);
1930 dbg.dispmon(dispmonScope, MON_ALWAYS, "... Done tapDMOAccess()");
1931 }
1932
1933 task tapDMOClear() {
1934 dbg.dispmon(dispmonScope, MON_INFO, "tapDMOClear()");
1935 void = TapIRLoad(TAP_DMO_CLEAR);
1936 TapGoto(TAP_UPDATE_IR);
1937 TapGoto(TAP_IDLE);
1938 dbg.dispmon(dispmonScope, MON_ALWAYS, "... Done tapDMOClear()");
1939 }
1940
1941 /// efu functions/tasks added by Adam
1942 task EfuReadMode(bit[2:0] readMode) {
1943 dbg.dispmon(dispmonScope, MON_INFO, "EfuReadMode()");
1944 void = TapIRLoad(TAP_FUSE_READ_MODE);
1945 void = TapDRLoad(cnv2str(readMode, 3));
1946 TapGoto(TAP_IDLE);
1947 //@@1,20 efuse_port.$efuse_read_mode == readMode; // Check that readMode holds
1948 repeat(20) toggleDutTck();
1949 dbg.dispmon(dispmonScope, MON_INFO, "... Done EfuReadMode()");
1950 }
1951
1952 task EfuRowAddr(bit[6:0] RowAddr) {
1953 dbg.dispmon(dispmonScope, MON_INFO, "EfuRowAddr()");
1954 void = TapIRLoad(TAP_FUSE_ROW_ADDR);
1955 void = TapDRLoad(cnv2str(RowAddr, 7));
1956 TapGoto(TAP_IDLE);
1957 dbg.dispmon(dispmonScope, MON_INFO, "... Done EfuRowAddr()");
1958 }
1959
1960 task EfuColAddr(bit[4:0] ColumnAddr) {
1961 dbg.dispmon(dispmonScope, MON_INFO, "EfuColumnAddr()");
1962 void = TapIRLoad(TAP_FUSE_COL_ADDR);
1963 void = TapDRLoad(cnv2str(ColumnAddr, 5));
1964 TapGoto(TAP_IDLE);
1965 dbg.dispmon(dispmonScope, MON_INFO, "... Done EfuColAddr()");
1966 }
1967
1968 function bit[31:0] EfuReadData(integer addr) {
1969 bit[6:0] row_addr;
1970 bit[31:0] tdo_data, tdo_data_inv;
1971 string tdo_data_str="";
1972 integer i;
1973 bit tdo_out;
1974
1975 dbg.dispmon(dispmonScope, MON_INFO, "EfuReadData()");
1976 row_addr = addr;
1977 void = TapIRLoad(TAP_FUSE_ROW_ADDR);
1978 void = TapDRLoad(cnv2str(row_addr, 7));
1979 //TapGoto(TAP_IDLE);dont need this.
1980 void = TapIRLoad(TAP_FUSE_READ);
1981 TapGoto(TAP_IDLE); // Note: UpdateIR is state just before Idle
1982 repeat(50) toggleDutTck();//chin's change
1983 //repeat(30) toggleDutTck();not enough delay to get right value
1984 TapGoto(TAP_CAPTURE_DR);
1985
1986 fork
1987 {
1988 while (1) {
1989 @ (posedge efuse_port.$efuse_shiftdr async);
1990 if (efuse_port.$efuse_shiftdr != 1'b1) {
1991 dbg.dispmon(dispmonScope, MON_ERR, psprintf("During EfuReadData efuse_shiftdr signal not asserted"));
1992 }
1993 }
1994 }
1995 {
1996 tdo_data_str = TapDRGet(32);
1997 tdo_data = tdo_data_str.atobin();
1998 for (i=0;i<32;i++) {
1999 tdo_data_inv[31-i] = tdo_data[i];
2000 }
2001 }
2002 join any
2003 terminate;
2004
2005 TapGoto(TAP_IDLE);
2006 dbg.dispmon(dispmonScope, MON_INFO, "... Done EfuReadData()");
2007 EfuReadData = tdo_data_inv;
2008 }
2009
2010 function bit[31:0] EfuDestReadData() {
2011 bit[31:0] tdo_data, tdo_data_inv;
2012 string tdo_data_str="";
2013 integer i;
2014 bit tdo_out;
2015
2016 dbg.dispmon(dispmonScope,MON_ALWAYS , "EfuDestReadData()");
2017 repeat(5) toggleDutTck();
2018 TapGoto(TAP_CAPTURE_DR);
2019
2020 fork
2021 {
2022 while (1) {
2023 @ (posedge efuse_port.$efuse_shiftdr async);
2024 if (efuse_port.$efuse_shiftdr != 1'b1) {
2025 dbg.dispmon(dispmonScope, MON_ERR, psprintf("During EfuDestReadData efuse_shiftdr signal not asserted"));
2026 }
2027 }
2028 }
2029 {
2030 tdo_data_str = TapDRGet(32);
2031 tdo_data = tdo_data_str.atobin();
2032 for (i=0;i<32;i++) {
2033 tdo_data_inv[31-i] = tdo_data[i];
2034 }
2035 }
2036 join any
2037 terminate;
2038
2039 TapGoto(TAP_IDLE);
2040 dbg.dispmon(dispmonScope, MON_ALWAYS, "... Done EfuDestReadData()");
2041 EfuDestReadData = tdo_data_inv;
2042 }
2043
2044
2045 function bit[31:0] EfuDestReadDataInv() {
2046 bit[31:0] tdo_data;
2047 string tdo_data_str="";
2048 integer i;
2049 bit tdo_out;
2050
2051 dbg.dispmon(dispmonScope,MON_ALWAYS , "EfuDestReadDataInv()");
2052 repeat(5) toggleDutTck();
2053 TapGoto(TAP_CAPTURE_DR);
2054
2055 fork
2056 {
2057 while (1) {
2058 @ (posedge efuse_port.$efuse_shiftdr async);
2059 if (efuse_port.$efuse_shiftdr != 1'b1) {
2060 dbg.dispmon(dispmonScope, MON_ERR, psprintf("During EfuDestReadDataInv efuse_shiftdr signal not asserted"));
2061 }
2062 }
2063 }
2064 {
2065 tdo_data_str = TapDRGet(32);
2066 tdo_data = tdo_data_str.atobin();
2067 }
2068 join any
2069 terminate;
2070
2071 TapGoto(TAP_IDLE);
2072 dbg.dispmon(dispmonScope, MON_ALWAYS, "... Done EfuDestReadDataInv()");
2073 EfuDestReadDataInv = tdo_data;
2074 }
2075
2076
2077 function string EfaBlockIdStr(bit[5:0] BlockID) {
2078 string BlockNameStr[64];
2079
2080 BlockNameStr[0]="Core0I$"; BlockNameStr[1]="Core0D$"; BlockNameStr[2]="Core1I$"; BlockNameStr[3]="Core1D$";
2081 BlockNameStr[4]="Core2I$"; BlockNameStr[5]="Core2D$"; BlockNameStr[6]="Core3I$"; BlockNameStr[7]="Core3D$";
2082 BlockNameStr[8]="Core4I$"; BlockNameStr[9]="Core4D$"; BlockNameStr[10]="Core5I$"; BlockNameStr[11]="Core5D$";
2083 BlockNameStr[12]="Core6I$"; BlockNameStr[13]="Core6D$"; BlockNameStr[14]="Core7I$"; BlockNameStr[15]="Core7D$";
2084 BlockNameStr[16]="L2T0"; BlockNameStr[17]="L2T1"; BlockNameStr[18]="L2T2"; BlockNameStr[19]="L2T3";
2085 BlockNameStr[20]="L2T4"; BlockNameStr[21]="L2T5"; BlockNameStr[22]="L2T6"; BlockNameStr[23]="L2T7";
2086 BlockNameStr[24]="L2D0"; BlockNameStr[25]="L2D1"; BlockNameStr[26]="L2D2"; BlockNameStr[27]="L2D3";
2087 BlockNameStr[28]="L2D4"; BlockNameStr[29]="L2D5"; BlockNameStr[30]="L2D6"; BlockNameStr[31]="L2D7";
2088 BlockNameStr[32]="CoreAvail"; BlockNameStr[33]="L2BankAvail"; BlockNameStr[34]="SerNum0"; BlockNameStr[35]="SerNum1";
2089 BlockNameStr[36]="SerNum2"; BlockNameStr[37]="NIU_mac1_sf"; BlockNameStr[38]="NIU_mac1_ro"; BlockNameStr[39]="NIU_mac0_sf";
2090 BlockNameStr[40]="NIU_mac0_ro"; BlockNameStr[41]="NIU_ipp0"; BlockNameStr[42]="NIU_ipp1"; BlockNameStr[43]="NIU_cfifo0";
2091 BlockNameStr[44]="NIU_cfifo1"; BlockNameStr[45]="NIU_4k";BlockNameStr[46]="NIU_ram";BlockNameStr[47]="NIU_ram0";
2092 BlockNameStr[48]="NIU_ram1"; BlockNameStr[49]="DMU";
2093
2094 if (BlockID > 44) {
2095 EfaBlockIdStr = "Unknown Block ID";
2096 } else {
2097 EfaBlockIdStr = BlockNameStr[BlockID];
2098 }
2099 }
2100
2101 //===============================================================
2102 // WHAT: program CCU's PLL_CTL reg
2103 // ARGS: cmpdr_ratio must be "2.00" to "5.25"
2104 //===============================================================
2105 task tap_config_ccu_pll_ctl_reg(string cmpdr_ratio) {
2106 bit [63:0] data, rd_data;
2107 bit [5:0] pll_div2;
2108 bit [6:0] pll_div4;
2109
2110 case (cmpdr_ratio) {
2111 "2.00": pll_div2 = 6'h7;
2112 "2.25": pll_div2 = 6'h8;
2113 "2.50": pll_div2 = 6'h9;
2114 "2.75": pll_div2 = 6'ha;
2115 "3.00": pll_div2 = 6'hb;
2116 "3.25": pll_div2 = 6'hc;
2117 "3.50": pll_div2 = 6'hd;
2118 "3.75": pll_div2 = 6'he;
2119 "4.00": pll_div2 = 6'hf;
2120 "4.25": pll_div2 = 6'h10;
2121 "4.50": pll_div2 = 6'h11;
2122 "4.75": pll_div2 = 6'h12;
2123 "5.00": pll_div2 = 6'h13;
2124 "5.25": pll_div2 = 6'h14;
2125 default: {
2126 dbg.dispmon(dispmonScope, MON_ERR, psprintf("change_ccu_clk_freq(cmpdr_ratio=%s) <= bad arg. Ignore", cmpdr_ratio));
2127 return;
2128 }
2129 }
2130 dbg.dispmon(dispmonScope, MON_INFO, psprintf("tap_config_ccu_pll_ctl_reg(cmpdr_ratio=%s)", cmpdr_ratio));
2131 pll_div4 = pll_div2 + 7'h1;
2132 data = this.tap_read_csr(40'h83_0000_0000, "PLL_CTL");
2133 data[11:6] = pll_div2;
2134 data[24:18] = pll_div4;
2135 data[32] = 1'b1; // change bit is set to 1
2136 this.tap_write_csr(40'h83_0000_0000, data, "PLL_CTL");
2137 rd_data = this.tap_read_csr(40'h83_0000_0000, "PLL_CTL");
2138 }
2139
2140 //===============================================================
2141 // WHAT: poll tap_clock_status until getting value 10 indicating clks stopped
2142 // ARGs: timeout_val is number of readings of tap_clock_status
2143 // RETURN: 0: no error (ie. sucess), non-zero: timeout/failure
2144 //===============================================================
2145 function integer poll_tap_clock_status_til_clkstop(integer timeout_val=500) {
2146 bit [1:0] data;
2147 integer num_rds=0;
2148
2149 dbg.dispmon(dispmonScope, MON_INFO, "poll tap_clock_status until getting 10 indicate all clks stopped");
2150 while (1) {
2151 data = this.tapClockStatus(2'b00);
2152 if (data === 2'b10) {
2153 poll_tap_clock_status_til_clkstop = 0; // no error
2154 return;
2155 }
2156 num_rds++;
2157 if (num_rds == timeout_val) {
2158 dbg.dispmon(dispmonScope, MON_ERR, psprintf("polling tap_clock_status for 2'b10 (ie. clks stopped) is time out after %0d rds", timeout_val));
2159 poll_tap_clock_status_til_clkstop = 1; // timeout
2160 return;
2161 }
2162 }
2163 }
2164
2165 //===============================================================
2166 // WHAT: poll tap_clock_status until getting 01 indicating all clks started
2167 // ARGs: timeout_val is number of readings of tap_clock_status
2168 // RETURN: 0: no error (ie. sucess), non-zero: timeout/failure
2169 //===============================================================
2170 function integer poll_tap_clock_status_til_clkstart(integer timeout_val=500) {
2171 bit [1:0] data;
2172 integer num_rds=0;
2173
2174 dbg.dispmon(dispmonScope, MON_INFO, "poll tap_clock_status until getting 01 indicating all clks started");
2175 while (1) {
2176 data = this.tapClockStatus(2'b00);
2177 if (data === 2'b01) {
2178 poll_tap_clock_status_til_clkstart = 0; // no error
2179 return;
2180 }
2181 num_rds++;
2182 if (num_rds == timeout_val) {
2183 dbg.dispmon(dispmonScope, MON_ERR, psprintf("polling tap_clock_status for 2'b01 (ie. clks started) is time out after %0d rds", timeout_val));
2184 poll_tap_clock_status_til_clkstart = 1; // timeout
2185 return;
2186 }
2187 }
2188 }
2189
2190} // end of class SystemTap
2191
2192
2193 /// random number generator - Adam
2194 enum Range = full, medium, small ;
2195
2196 class rng {
2197 bit [63:0] base_bit = 1;
2198 rand bit [63:0] rand_num;
2199 randc bit [7:0] randc_num;
2200 rand Range range;
2201 integer MaxBits,MedBits,MinBits ;
2202
2203 constraint bit_range {
2204 (range == small) => rand_num in { 0: 7};
2205 (range == medium) => rand_num in { 0: 255};
2206 (range == full) => rand_num in { 0: (base_bit<<MaxBits)-1};
2207 }
2208
2209 task new(integer max_bits) {
2210 MaxBits = max_bits;
2211 }
2212 }
2213
2214
Full OpenSPARC design & verification tarball including full HDL.