projects / OpenSPARC-T2-DV / blame
| Commit | Line | Data |
|---|---|---|
| 86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: cluster_hdr.bind.vri | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | #ifndef INC_CLUSTER_HDR_BIND_VRI | |
| 36 | #define INC_CLUSTER_HDR_BIND_VRI | |
| 37 | ||
| 38 | #include "cluster_hdr.port.vri" | |
| 39 | #include "cluster_hdr.if.vri" | |
| 40 | ||
| 41 | // | |
| 42 | // WARNING: this file is generated by script gen_cluster_hdr.pl. Do not modify. | |
| 43 | // | |
| 44 | ||
| 45 | //####################################################### | |
| 46 | //### bind DR and IO2X clock ports for ccu_mon ###### | |
| 47 | //####################################################### | |
| 48 | bind CLKGEN_port clkgen_ccumon_dr_bind { | |
| 49 | aclk__gclk void; | |
| 50 | aclk_wmr__gclk void; | |
| 51 | array_wr_inhibit__gclk void; | |
| 52 | bclk__gclk void; | |
| 53 | ccu_cmp_slow_sync_en__gclk void; | |
| 54 | ccu_div_ph__gclk void; | |
| 55 | ccu_dr_sync_en__gclk void; | |
| 56 | ccu_io2x_sync_en__gclk void; | |
| 57 | ccu_serdes_dtm__gclk void; | |
| 58 | ccu_slow_cmp_sync_en__gclk void; | |
| 59 | clk_ext__gclk void; | |
| 60 | cluster_arst_l__gclk void; | |
| 61 | cluster_div_en__gclk void; | |
| 62 | cmp_slow_sync_en__gclk void; | |
| 63 | dr_sync_en__gclk void; | |
| 64 | gclk void; | |
| 65 | io2x_sync_en__gclk void; | |
| 66 | l2clk__gclk void; | |
| 67 | pce_ov__gclk void; | |
| 68 | por___gclk void; | |
| 69 | rst_por___gclk void; | |
| 70 | rst_wmr___gclk void; | |
| 71 | rst_wmr_protect__gclk void; | |
| 72 | scan_en__gclk void; | |
| 73 | scan_in__gclk void; | |
| 74 | scan_out__gclk void; | |
| 75 | slow_cmp_sync_en__gclk void; | |
| 76 | tcu_aclk__gclk void; | |
| 77 | tcu_atpg_mode__gclk void; | |
| 78 | tcu_bclk__gclk void; | |
| 79 | tcu_clk_stop__gclk void; | |
| 80 | tcu_div_bypass__gclk void; | |
| 81 | tcu_pce_ov__gclk void; | |
| 82 | tcu_wr_inhibit__gclk void; | |
| 83 | wmr___gclk void; | |
| 84 | wmr_protect__gclk void; | |
| 85 | pc_clk__gclk void; | |
| 86 | pc_clk_sel__gclk void; | |
| 87 | test_clk__gclk void; | |
| 88 | test_clk_sel__gclk void; | |
| 89 | aclk__l2clk void; | |
| 90 | aclk_wmr__l2clk void; | |
| 91 | array_wr_inhibit__l2clk void; | |
| 92 | bclk__l2clk void; | |
| 93 | cmp_slow_sync_en__l2clk void; | |
| 94 | dr_sync_en__l2clk void; | |
| 95 | io2x_sync_en__l2clk void; | |
| 96 | l2clk clkgen_ccumon_dr_l2clk_if.l2clk; | |
| 97 | pce_ov__l2clk void; | |
| 98 | por___l2clk void; | |
| 99 | scan_out__l2clk void; | |
| 100 | slow_cmp_sync_en__l2clk void; | |
| 101 | wmr___l2clk void; | |
| 102 | wmr_protect__l2clk void; | |
| 103 | } | |
| 104 | ||
| 105 | bind CLKGEN_port clkgen_ccumon_io2x_bind { | |
| 106 | aclk__gclk void; | |
| 107 | aclk_wmr__gclk void; | |
| 108 | array_wr_inhibit__gclk void; | |
| 109 | bclk__gclk void; | |
| 110 | ccu_cmp_slow_sync_en__gclk void; | |
| 111 | ccu_div_ph__gclk void; | |
| 112 | ccu_dr_sync_en__gclk void; | |
| 113 | ccu_io2x_sync_en__gclk void; | |
| 114 | ccu_serdes_dtm__gclk void; | |
| 115 | ccu_slow_cmp_sync_en__gclk void; | |
| 116 | clk_ext__gclk void; | |
| 117 | cluster_arst_l__gclk void; | |
| 118 | cluster_div_en__gclk void; | |
| 119 | cmp_slow_sync_en__gclk void; | |
| 120 | dr_sync_en__gclk void; | |
| 121 | gclk void; | |
| 122 | io2x_sync_en__gclk void; | |
| 123 | l2clk__gclk void; | |
| 124 | pce_ov__gclk void; | |
| 125 | por___gclk void; | |
| 126 | rst_por___gclk void; | |
| 127 | rst_wmr___gclk void; | |
| 128 | rst_wmr_protect__gclk void; | |
| 129 | scan_en__gclk void; | |
| 130 | scan_in__gclk void; | |
| 131 | scan_out__gclk void; | |
| 132 | slow_cmp_sync_en__gclk void; | |
| 133 | tcu_aclk__gclk void; | |
| 134 | tcu_atpg_mode__gclk void; | |
| 135 | tcu_bclk__gclk void; | |
| 136 | tcu_clk_stop__gclk void; | |
| 137 | tcu_div_bypass__gclk void; | |
| 138 | tcu_pce_ov__gclk void; | |
| 139 | tcu_wr_inhibit__gclk void; | |
| 140 | wmr___gclk void; | |
| 141 | wmr_protect__gclk void; | |
| 142 | pc_clk__gclk void; | |
| 143 | pc_clk_sel__gclk void; | |
| 144 | test_clk__gclk void; | |
| 145 | test_clk_sel__gclk void; | |
| 146 | aclk__l2clk void; | |
| 147 | aclk_wmr__l2clk void; | |
| 148 | array_wr_inhibit__l2clk void; | |
| 149 | bclk__l2clk void; | |
| 150 | cmp_slow_sync_en__l2clk void; | |
| 151 | dr_sync_en__l2clk void; | |
| 152 | io2x_sync_en__l2clk void; | |
| 153 | l2clk clkgen_ccumon_io2x_l2clk_if.l2clk; | |
| 154 | pce_ov__l2clk void; | |
| 155 | por___l2clk void; | |
| 156 | scan_out__l2clk void; | |
| 157 | slow_cmp_sync_en__l2clk void; | |
| 158 | wmr___l2clk void; | |
| 159 | wmr_protect__l2clk void; | |
| 160 | } | |
| 161 | ||
| 162 | //####################################################### | |
| 163 | //### port bindings for blocks in TCU SAT ### | |
| 164 | //####################################################### | |
| 165 | ||
| 166 | //----- port binding for clkgen_ccu_cmp ----- | |
| 167 | ||
| 168 | bind CLKGEN_port clkgen_ccu_cmp_bind { | |
| 169 | //---gclk is Vera interface CLOCK--- | |
| 170 | aclk__gclk clkgen_ccu_cmp_gclk_if.aclk; | |
| 171 | aclk_wmr__gclk clkgen_ccu_cmp_gclk_if.aclk_wmr; | |
| 172 | array_wr_inhibit__gclk clkgen_ccu_cmp_gclk_if.array_wr_inhibit; | |
| 173 | bclk__gclk clkgen_ccu_cmp_gclk_if.bclk; | |
| 174 | ccu_cmp_slow_sync_en__gclk clkgen_ccu_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 175 | ccu_div_ph__gclk clkgen_ccu_cmp_gclk_if.ccu_div_ph; | |
| 176 | ccu_dr_sync_en__gclk void; | |
| 177 | ccu_io2x_sync_en__gclk void; | |
| 178 | ccu_serdes_dtm__gclk clkgen_ccu_cmp_gclk_if.ccu_serdes_dtm; | |
| 179 | ccu_slow_cmp_sync_en__gclk clkgen_ccu_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 180 | clk_ext__gclk clkgen_ccu_cmp_gclk_if.clk_ext; | |
| 181 | cluster_arst_l__gclk clkgen_ccu_cmp_gclk_if.cluster_arst_l; | |
| 182 | cluster_div_en__gclk clkgen_ccu_cmp_gclk_if.cluster_div_en; | |
| 183 | cmp_slow_sync_en__gclk clkgen_ccu_cmp_gclk_if.cmp_slow_sync_en; | |
| 184 | dr_sync_en__gclk void; | |
| 185 | gclk clkgen_ccu_cmp_gclk_if.gclk; | |
| 186 | io2x_sync_en__gclk void; | |
| 187 | l2clk__gclk clkgen_ccu_cmp_gclk_if.l2clk; | |
| 188 | pce_ov__gclk clkgen_ccu_cmp_gclk_if.pce_ov; | |
| 189 | por___gclk clkgen_ccu_cmp_gclk_if.por_; | |
| 190 | rst_por___gclk clkgen_ccu_cmp_gclk_if.rst_por_; | |
| 191 | rst_wmr___gclk clkgen_ccu_cmp_gclk_if.rst_wmr_; | |
| 192 | rst_wmr_protect__gclk clkgen_ccu_cmp_gclk_if.rst_wmr_protect; | |
| 193 | scan_en__gclk clkgen_ccu_cmp_gclk_if.scan_en; | |
| 194 | scan_in__gclk clkgen_ccu_cmp_gclk_if.scan_in; | |
| 195 | scan_out__gclk clkgen_ccu_cmp_gclk_if.scan_out; | |
| 196 | slow_cmp_sync_en__gclk clkgen_ccu_cmp_gclk_if.slow_cmp_sync_en; | |
| 197 | tcu_aclk__gclk clkgen_ccu_cmp_gclk_if.tcu_aclk; | |
| 198 | tcu_atpg_mode__gclk clkgen_ccu_cmp_gclk_if.tcu_atpg_mode; | |
| 199 | tcu_bclk__gclk clkgen_ccu_cmp_gclk_if.tcu_bclk; | |
| 200 | tcu_clk_stop__gclk clkgen_ccu_cmp_gclk_if.tcu_clk_stop; | |
| 201 | tcu_div_bypass__gclk clkgen_ccu_cmp_gclk_if.tcu_div_bypass; | |
| 202 | tcu_pce_ov__gclk clkgen_ccu_cmp_gclk_if.tcu_pce_ov; | |
| 203 | tcu_wr_inhibit__gclk clkgen_ccu_cmp_gclk_if.tcu_wr_inhibit; | |
| 204 | wmr___gclk clkgen_ccu_cmp_gclk_if.wmr_; | |
| 205 | wmr_protect__gclk clkgen_ccu_cmp_gclk_if.wmr_protect; | |
| 206 | pc_clk__gclk void; | |
| 207 | pc_clk_sel__gclk void; | |
| 208 | test_clk__gclk void; | |
| 209 | test_clk_sel__gclk void; | |
| 210 | ||
| 211 | //---l2clk is Vera interface CLOCK--- | |
| 212 | aclk__l2clk clkgen_ccu_cmp_l2clk_if.aclk; | |
| 213 | aclk_wmr__l2clk clkgen_ccu_cmp_l2clk_if.aclk_wmr; | |
| 214 | array_wr_inhibit__l2clk clkgen_ccu_cmp_l2clk_if.array_wr_inhibit; | |
| 215 | bclk__l2clk clkgen_ccu_cmp_l2clk_if.bclk; | |
| 216 | cmp_slow_sync_en__l2clk clkgen_ccu_cmp_l2clk_if.cmp_slow_sync_en; | |
| 217 | dr_sync_en__l2clk void; | |
| 218 | io2x_sync_en__l2clk void; | |
| 219 | l2clk clkgen_ccu_cmp_l2clk_if.l2clk; | |
| 220 | pce_ov__l2clk clkgen_ccu_cmp_l2clk_if.pce_ov; | |
| 221 | por___l2clk clkgen_ccu_cmp_l2clk_if.por_; | |
| 222 | scan_out__l2clk clkgen_ccu_cmp_l2clk_if.scan_out; | |
| 223 | slow_cmp_sync_en__l2clk clkgen_ccu_cmp_l2clk_if.slow_cmp_sync_en; | |
| 224 | wmr___l2clk clkgen_ccu_cmp_l2clk_if.wmr_; | |
| 225 | wmr_protect__l2clk clkgen_ccu_cmp_l2clk_if.wmr_protect; | |
| 226 | } | |
| 227 | ||
| 228 | //----- port binding for clkgen_ccu_io ----- | |
| 229 | ||
| 230 | bind CLKGEN_port clkgen_ccu_io_bind { | |
| 231 | //---gclk is Vera interface CLOCK--- | |
| 232 | aclk__gclk clkgen_ccu_io_gclk_if.aclk; | |
| 233 | aclk_wmr__gclk clkgen_ccu_io_gclk_if.aclk_wmr; | |
| 234 | array_wr_inhibit__gclk clkgen_ccu_io_gclk_if.array_wr_inhibit; | |
| 235 | bclk__gclk clkgen_ccu_io_gclk_if.bclk; | |
| 236 | ccu_cmp_slow_sync_en__gclk clkgen_ccu_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 237 | ccu_div_ph__gclk clkgen_ccu_io_gclk_if.ccu_div_ph; | |
| 238 | ccu_dr_sync_en__gclk void; | |
| 239 | ccu_io2x_sync_en__gclk void; | |
| 240 | ccu_serdes_dtm__gclk clkgen_ccu_io_gclk_if.ccu_serdes_dtm; | |
| 241 | ccu_slow_cmp_sync_en__gclk clkgen_ccu_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 242 | clk_ext__gclk clkgen_ccu_io_gclk_if.clk_ext; | |
| 243 | cluster_arst_l__gclk clkgen_ccu_io_gclk_if.cluster_arst_l; | |
| 244 | cluster_div_en__gclk clkgen_ccu_io_gclk_if.cluster_div_en; | |
| 245 | cmp_slow_sync_en__gclk clkgen_ccu_io_gclk_if.cmp_slow_sync_en; | |
| 246 | dr_sync_en__gclk void; | |
| 247 | gclk clkgen_ccu_io_gclk_if.gclk; | |
| 248 | io2x_sync_en__gclk void; | |
| 249 | l2clk__gclk clkgen_ccu_io_gclk_if.l2clk; | |
| 250 | pce_ov__gclk clkgen_ccu_io_gclk_if.pce_ov; | |
| 251 | por___gclk clkgen_ccu_io_gclk_if.por_; | |
| 252 | rst_por___gclk clkgen_ccu_io_gclk_if.rst_por_; | |
| 253 | rst_wmr___gclk clkgen_ccu_io_gclk_if.rst_wmr_; | |
| 254 | rst_wmr_protect__gclk clkgen_ccu_io_gclk_if.rst_wmr_protect; | |
| 255 | scan_en__gclk clkgen_ccu_io_gclk_if.scan_en; | |
| 256 | scan_in__gclk clkgen_ccu_io_gclk_if.scan_in; | |
| 257 | scan_out__gclk clkgen_ccu_io_gclk_if.scan_out; | |
| 258 | slow_cmp_sync_en__gclk clkgen_ccu_io_gclk_if.slow_cmp_sync_en; | |
| 259 | tcu_aclk__gclk clkgen_ccu_io_gclk_if.tcu_aclk; | |
| 260 | tcu_atpg_mode__gclk clkgen_ccu_io_gclk_if.tcu_atpg_mode; | |
| 261 | tcu_bclk__gclk clkgen_ccu_io_gclk_if.tcu_bclk; | |
| 262 | tcu_clk_stop__gclk clkgen_ccu_io_gclk_if.tcu_clk_stop; | |
| 263 | tcu_div_bypass__gclk clkgen_ccu_io_gclk_if.tcu_div_bypass; | |
| 264 | tcu_pce_ov__gclk clkgen_ccu_io_gclk_if.tcu_pce_ov; | |
| 265 | tcu_wr_inhibit__gclk clkgen_ccu_io_gclk_if.tcu_wr_inhibit; | |
| 266 | wmr___gclk clkgen_ccu_io_gclk_if.wmr_; | |
| 267 | wmr_protect__gclk clkgen_ccu_io_gclk_if.wmr_protect; | |
| 268 | pc_clk__gclk void; | |
| 269 | pc_clk_sel__gclk void; | |
| 270 | test_clk__gclk void; | |
| 271 | test_clk_sel__gclk void; | |
| 272 | ||
| 273 | //---l2clk is Vera interface CLOCK--- | |
| 274 | aclk__l2clk clkgen_ccu_io_l2clk_if.aclk; | |
| 275 | aclk_wmr__l2clk clkgen_ccu_io_l2clk_if.aclk_wmr; | |
| 276 | array_wr_inhibit__l2clk clkgen_ccu_io_l2clk_if.array_wr_inhibit; | |
| 277 | bclk__l2clk clkgen_ccu_io_l2clk_if.bclk; | |
| 278 | cmp_slow_sync_en__l2clk clkgen_ccu_io_l2clk_if.cmp_slow_sync_en; | |
| 279 | dr_sync_en__l2clk void; | |
| 280 | io2x_sync_en__l2clk void; | |
| 281 | l2clk clkgen_ccu_io_l2clk_if.l2clk; | |
| 282 | pce_ov__l2clk clkgen_ccu_io_l2clk_if.pce_ov; | |
| 283 | por___l2clk clkgen_ccu_io_l2clk_if.por_; | |
| 284 | scan_out__l2clk clkgen_ccu_io_l2clk_if.scan_out; | |
| 285 | slow_cmp_sync_en__l2clk clkgen_ccu_io_l2clk_if.slow_cmp_sync_en; | |
| 286 | wmr___l2clk clkgen_ccu_io_l2clk_if.wmr_; | |
| 287 | wmr_protect__l2clk clkgen_ccu_io_l2clk_if.wmr_protect; | |
| 288 | } | |
| 289 | ||
| 290 | //----- port binding for clkgen_db0_cmp ----- | |
| 291 | ||
| 292 | bind CLKGEN_port clkgen_db0_cmp_bind { | |
| 293 | //---gclk is Vera interface CLOCK--- | |
| 294 | aclk__gclk clkgen_db0_cmp_gclk_if.aclk; | |
| 295 | aclk_wmr__gclk clkgen_db0_cmp_gclk_if.aclk_wmr; | |
| 296 | array_wr_inhibit__gclk clkgen_db0_cmp_gclk_if.array_wr_inhibit; | |
| 297 | bclk__gclk clkgen_db0_cmp_gclk_if.bclk; | |
| 298 | ccu_cmp_slow_sync_en__gclk clkgen_db0_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 299 | ccu_div_ph__gclk clkgen_db0_cmp_gclk_if.ccu_div_ph; | |
| 300 | ccu_dr_sync_en__gclk clkgen_db0_cmp_gclk_if.ccu_dr_sync_en; | |
| 301 | ccu_io2x_sync_en__gclk clkgen_db0_cmp_gclk_if.ccu_io2x_sync_en; | |
| 302 | ccu_serdes_dtm__gclk clkgen_db0_cmp_gclk_if.ccu_serdes_dtm; | |
| 303 | ccu_slow_cmp_sync_en__gclk clkgen_db0_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 304 | clk_ext__gclk clkgen_db0_cmp_gclk_if.clk_ext; | |
| 305 | cluster_arst_l__gclk clkgen_db0_cmp_gclk_if.cluster_arst_l; | |
| 306 | cluster_div_en__gclk clkgen_db0_cmp_gclk_if.cluster_div_en; | |
| 307 | cmp_slow_sync_en__gclk clkgen_db0_cmp_gclk_if.cmp_slow_sync_en; | |
| 308 | dr_sync_en__gclk clkgen_db0_cmp_gclk_if.dr_sync_en; | |
| 309 | gclk clkgen_db0_cmp_gclk_if.gclk; | |
| 310 | io2x_sync_en__gclk clkgen_db0_cmp_gclk_if.io2x_sync_en; | |
| 311 | l2clk__gclk clkgen_db0_cmp_gclk_if.l2clk; | |
| 312 | pce_ov__gclk clkgen_db0_cmp_gclk_if.pce_ov; | |
| 313 | por___gclk clkgen_db0_cmp_gclk_if.por_; | |
| 314 | rst_por___gclk clkgen_db0_cmp_gclk_if.rst_por_; | |
| 315 | rst_wmr___gclk clkgen_db0_cmp_gclk_if.rst_wmr_; | |
| 316 | rst_wmr_protect__gclk clkgen_db0_cmp_gclk_if.rst_wmr_protect; | |
| 317 | scan_en__gclk clkgen_db0_cmp_gclk_if.scan_en; | |
| 318 | scan_in__gclk clkgen_db0_cmp_gclk_if.scan_in; | |
| 319 | scan_out__gclk clkgen_db0_cmp_gclk_if.scan_out; | |
| 320 | slow_cmp_sync_en__gclk clkgen_db0_cmp_gclk_if.slow_cmp_sync_en; | |
| 321 | tcu_aclk__gclk clkgen_db0_cmp_gclk_if.tcu_aclk; | |
| 322 | tcu_atpg_mode__gclk clkgen_db0_cmp_gclk_if.tcu_atpg_mode; | |
| 323 | tcu_bclk__gclk clkgen_db0_cmp_gclk_if.tcu_bclk; | |
| 324 | tcu_clk_stop__gclk clkgen_db0_cmp_gclk_if.tcu_clk_stop; | |
| 325 | tcu_div_bypass__gclk clkgen_db0_cmp_gclk_if.tcu_div_bypass; | |
| 326 | tcu_pce_ov__gclk clkgen_db0_cmp_gclk_if.tcu_pce_ov; | |
| 327 | tcu_wr_inhibit__gclk clkgen_db0_cmp_gclk_if.tcu_wr_inhibit; | |
| 328 | wmr___gclk clkgen_db0_cmp_gclk_if.wmr_; | |
| 329 | wmr_protect__gclk clkgen_db0_cmp_gclk_if.wmr_protect; | |
| 330 | pc_clk__gclk void; | |
| 331 | pc_clk_sel__gclk void; | |
| 332 | test_clk__gclk void; | |
| 333 | test_clk_sel__gclk void; | |
| 334 | ||
| 335 | //---l2clk is Vera interface CLOCK--- | |
| 336 | aclk__l2clk clkgen_db0_cmp_l2clk_if.aclk; | |
| 337 | aclk_wmr__l2clk clkgen_db0_cmp_l2clk_if.aclk_wmr; | |
| 338 | array_wr_inhibit__l2clk clkgen_db0_cmp_l2clk_if.array_wr_inhibit; | |
| 339 | bclk__l2clk clkgen_db0_cmp_l2clk_if.bclk; | |
| 340 | cmp_slow_sync_en__l2clk clkgen_db0_cmp_l2clk_if.cmp_slow_sync_en; | |
| 341 | dr_sync_en__l2clk clkgen_db0_cmp_l2clk_if.dr_sync_en; | |
| 342 | io2x_sync_en__l2clk clkgen_db0_cmp_l2clk_if.io2x_sync_en; | |
| 343 | l2clk clkgen_db0_cmp_l2clk_if.l2clk; | |
| 344 | pce_ov__l2clk clkgen_db0_cmp_l2clk_if.pce_ov; | |
| 345 | por___l2clk clkgen_db0_cmp_l2clk_if.por_; | |
| 346 | scan_out__l2clk clkgen_db0_cmp_l2clk_if.scan_out; | |
| 347 | slow_cmp_sync_en__l2clk clkgen_db0_cmp_l2clk_if.slow_cmp_sync_en; | |
| 348 | wmr___l2clk clkgen_db0_cmp_l2clk_if.wmr_; | |
| 349 | wmr_protect__l2clk clkgen_db0_cmp_l2clk_if.wmr_protect; | |
| 350 | } | |
| 351 | ||
| 352 | //----- port binding for clkgen_db0_io ----- | |
| 353 | ||
| 354 | bind CLKGEN_port clkgen_db0_io_bind { | |
| 355 | //---gclk is Vera interface CLOCK--- | |
| 356 | aclk__gclk clkgen_db0_io_gclk_if.aclk; | |
| 357 | aclk_wmr__gclk clkgen_db0_io_gclk_if.aclk_wmr; | |
| 358 | array_wr_inhibit__gclk clkgen_db0_io_gclk_if.array_wr_inhibit; | |
| 359 | bclk__gclk clkgen_db0_io_gclk_if.bclk; | |
| 360 | ccu_cmp_slow_sync_en__gclk clkgen_db0_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 361 | ccu_div_ph__gclk clkgen_db0_io_gclk_if.ccu_div_ph; | |
| 362 | ccu_dr_sync_en__gclk void; | |
| 363 | ccu_io2x_sync_en__gclk void; | |
| 364 | ccu_serdes_dtm__gclk clkgen_db0_io_gclk_if.ccu_serdes_dtm; | |
| 365 | ccu_slow_cmp_sync_en__gclk clkgen_db0_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 366 | clk_ext__gclk clkgen_db0_io_gclk_if.clk_ext; | |
| 367 | cluster_arst_l__gclk clkgen_db0_io_gclk_if.cluster_arst_l; | |
| 368 | cluster_div_en__gclk clkgen_db0_io_gclk_if.cluster_div_en; | |
| 369 | cmp_slow_sync_en__gclk clkgen_db0_io_gclk_if.cmp_slow_sync_en; | |
| 370 | dr_sync_en__gclk void; | |
| 371 | gclk clkgen_db0_io_gclk_if.gclk; | |
| 372 | io2x_sync_en__gclk void; | |
| 373 | l2clk__gclk clkgen_db0_io_gclk_if.l2clk; | |
| 374 | pce_ov__gclk clkgen_db0_io_gclk_if.pce_ov; | |
| 375 | por___gclk clkgen_db0_io_gclk_if.por_; | |
| 376 | rst_por___gclk clkgen_db0_io_gclk_if.rst_por_; | |
| 377 | rst_wmr___gclk clkgen_db0_io_gclk_if.rst_wmr_; | |
| 378 | rst_wmr_protect__gclk clkgen_db0_io_gclk_if.rst_wmr_protect; | |
| 379 | scan_en__gclk clkgen_db0_io_gclk_if.scan_en; | |
| 380 | scan_in__gclk clkgen_db0_io_gclk_if.scan_in; | |
| 381 | scan_out__gclk clkgen_db0_io_gclk_if.scan_out; | |
| 382 | slow_cmp_sync_en__gclk clkgen_db0_io_gclk_if.slow_cmp_sync_en; | |
| 383 | tcu_aclk__gclk clkgen_db0_io_gclk_if.tcu_aclk; | |
| 384 | tcu_atpg_mode__gclk clkgen_db0_io_gclk_if.tcu_atpg_mode; | |
| 385 | tcu_bclk__gclk clkgen_db0_io_gclk_if.tcu_bclk; | |
| 386 | tcu_clk_stop__gclk clkgen_db0_io_gclk_if.tcu_clk_stop; | |
| 387 | tcu_div_bypass__gclk clkgen_db0_io_gclk_if.tcu_div_bypass; | |
| 388 | tcu_pce_ov__gclk clkgen_db0_io_gclk_if.tcu_pce_ov; | |
| 389 | tcu_wr_inhibit__gclk clkgen_db0_io_gclk_if.tcu_wr_inhibit; | |
| 390 | wmr___gclk clkgen_db0_io_gclk_if.wmr_; | |
| 391 | wmr_protect__gclk clkgen_db0_io_gclk_if.wmr_protect; | |
| 392 | pc_clk__gclk void; | |
| 393 | pc_clk_sel__gclk void; | |
| 394 | test_clk__gclk void; | |
| 395 | test_clk_sel__gclk void; | |
| 396 | ||
| 397 | //---l2clk is Vera interface CLOCK--- | |
| 398 | aclk__l2clk clkgen_db0_io_l2clk_if.aclk; | |
| 399 | aclk_wmr__l2clk clkgen_db0_io_l2clk_if.aclk_wmr; | |
| 400 | array_wr_inhibit__l2clk clkgen_db0_io_l2clk_if.array_wr_inhibit; | |
| 401 | bclk__l2clk clkgen_db0_io_l2clk_if.bclk; | |
| 402 | cmp_slow_sync_en__l2clk clkgen_db0_io_l2clk_if.cmp_slow_sync_en; | |
| 403 | dr_sync_en__l2clk void; | |
| 404 | io2x_sync_en__l2clk void; | |
| 405 | l2clk clkgen_db0_io_l2clk_if.l2clk; | |
| 406 | pce_ov__l2clk clkgen_db0_io_l2clk_if.pce_ov; | |
| 407 | por___l2clk clkgen_db0_io_l2clk_if.por_; | |
| 408 | scan_out__l2clk clkgen_db0_io_l2clk_if.scan_out; | |
| 409 | slow_cmp_sync_en__l2clk clkgen_db0_io_l2clk_if.slow_cmp_sync_en; | |
| 410 | wmr___l2clk clkgen_db0_io_l2clk_if.wmr_; | |
| 411 | wmr_protect__l2clk clkgen_db0_io_l2clk_if.wmr_protect; | |
| 412 | } | |
| 413 | ||
| 414 | //----- port binding for clkgen_db1_cmp ----- | |
| 415 | ||
| 416 | bind CLKGEN_port clkgen_db1_cmp_bind { | |
| 417 | //---gclk is Vera interface CLOCK--- | |
| 418 | aclk__gclk clkgen_db1_cmp_gclk_if.aclk; | |
| 419 | aclk_wmr__gclk clkgen_db1_cmp_gclk_if.aclk_wmr; | |
| 420 | array_wr_inhibit__gclk clkgen_db1_cmp_gclk_if.array_wr_inhibit; | |
| 421 | bclk__gclk clkgen_db1_cmp_gclk_if.bclk; | |
| 422 | ccu_cmp_slow_sync_en__gclk clkgen_db1_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 423 | ccu_div_ph__gclk clkgen_db1_cmp_gclk_if.ccu_div_ph; | |
| 424 | ccu_dr_sync_en__gclk clkgen_db1_cmp_gclk_if.ccu_dr_sync_en; | |
| 425 | ccu_io2x_sync_en__gclk clkgen_db1_cmp_gclk_if.ccu_io2x_sync_en; | |
| 426 | ccu_serdes_dtm__gclk clkgen_db1_cmp_gclk_if.ccu_serdes_dtm; | |
| 427 | ccu_slow_cmp_sync_en__gclk clkgen_db1_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 428 | clk_ext__gclk clkgen_db1_cmp_gclk_if.clk_ext; | |
| 429 | cluster_arst_l__gclk clkgen_db1_cmp_gclk_if.cluster_arst_l; | |
| 430 | cluster_div_en__gclk clkgen_db1_cmp_gclk_if.cluster_div_en; | |
| 431 | cmp_slow_sync_en__gclk clkgen_db1_cmp_gclk_if.cmp_slow_sync_en; | |
| 432 | dr_sync_en__gclk clkgen_db1_cmp_gclk_if.dr_sync_en; | |
| 433 | gclk clkgen_db1_cmp_gclk_if.gclk; | |
| 434 | io2x_sync_en__gclk clkgen_db1_cmp_gclk_if.io2x_sync_en; | |
| 435 | l2clk__gclk clkgen_db1_cmp_gclk_if.l2clk; | |
| 436 | pce_ov__gclk clkgen_db1_cmp_gclk_if.pce_ov; | |
| 437 | por___gclk clkgen_db1_cmp_gclk_if.por_; | |
| 438 | rst_por___gclk clkgen_db1_cmp_gclk_if.rst_por_; | |
| 439 | rst_wmr___gclk clkgen_db1_cmp_gclk_if.rst_wmr_; | |
| 440 | rst_wmr_protect__gclk clkgen_db1_cmp_gclk_if.rst_wmr_protect; | |
| 441 | scan_en__gclk clkgen_db1_cmp_gclk_if.scan_en; | |
| 442 | scan_in__gclk clkgen_db1_cmp_gclk_if.scan_in; | |
| 443 | scan_out__gclk clkgen_db1_cmp_gclk_if.scan_out; | |
| 444 | slow_cmp_sync_en__gclk clkgen_db1_cmp_gclk_if.slow_cmp_sync_en; | |
| 445 | tcu_aclk__gclk clkgen_db1_cmp_gclk_if.tcu_aclk; | |
| 446 | tcu_atpg_mode__gclk clkgen_db1_cmp_gclk_if.tcu_atpg_mode; | |
| 447 | tcu_bclk__gclk clkgen_db1_cmp_gclk_if.tcu_bclk; | |
| 448 | tcu_clk_stop__gclk clkgen_db1_cmp_gclk_if.tcu_clk_stop; | |
| 449 | tcu_div_bypass__gclk clkgen_db1_cmp_gclk_if.tcu_div_bypass; | |
| 450 | tcu_pce_ov__gclk clkgen_db1_cmp_gclk_if.tcu_pce_ov; | |
| 451 | tcu_wr_inhibit__gclk clkgen_db1_cmp_gclk_if.tcu_wr_inhibit; | |
| 452 | wmr___gclk clkgen_db1_cmp_gclk_if.wmr_; | |
| 453 | wmr_protect__gclk clkgen_db1_cmp_gclk_if.wmr_protect; | |
| 454 | pc_clk__gclk void; | |
| 455 | pc_clk_sel__gclk void; | |
| 456 | test_clk__gclk void; | |
| 457 | test_clk_sel__gclk void; | |
| 458 | ||
| 459 | //---l2clk is Vera interface CLOCK--- | |
| 460 | aclk__l2clk clkgen_db1_cmp_l2clk_if.aclk; | |
| 461 | aclk_wmr__l2clk clkgen_db1_cmp_l2clk_if.aclk_wmr; | |
| 462 | array_wr_inhibit__l2clk clkgen_db1_cmp_l2clk_if.array_wr_inhibit; | |
| 463 | bclk__l2clk clkgen_db1_cmp_l2clk_if.bclk; | |
| 464 | cmp_slow_sync_en__l2clk clkgen_db1_cmp_l2clk_if.cmp_slow_sync_en; | |
| 465 | dr_sync_en__l2clk clkgen_db1_cmp_l2clk_if.dr_sync_en; | |
| 466 | io2x_sync_en__l2clk clkgen_db1_cmp_l2clk_if.io2x_sync_en; | |
| 467 | l2clk clkgen_db1_cmp_l2clk_if.l2clk; | |
| 468 | pce_ov__l2clk clkgen_db1_cmp_l2clk_if.pce_ov; | |
| 469 | por___l2clk clkgen_db1_cmp_l2clk_if.por_; | |
| 470 | scan_out__l2clk clkgen_db1_cmp_l2clk_if.scan_out; | |
| 471 | slow_cmp_sync_en__l2clk clkgen_db1_cmp_l2clk_if.slow_cmp_sync_en; | |
| 472 | wmr___l2clk clkgen_db1_cmp_l2clk_if.wmr_; | |
| 473 | wmr_protect__l2clk clkgen_db1_cmp_l2clk_if.wmr_protect; | |
| 474 | } | |
| 475 | ||
| 476 | //----- port binding for clkgen_db1_io ----- | |
| 477 | ||
| 478 | bind CLKGEN_port clkgen_db1_io_bind { | |
| 479 | //---gclk is Vera interface CLOCK--- | |
| 480 | aclk__gclk clkgen_db1_io_gclk_if.aclk; | |
| 481 | aclk_wmr__gclk clkgen_db1_io_gclk_if.aclk_wmr; | |
| 482 | array_wr_inhibit__gclk clkgen_db1_io_gclk_if.array_wr_inhibit; | |
| 483 | bclk__gclk clkgen_db1_io_gclk_if.bclk; | |
| 484 | ccu_cmp_slow_sync_en__gclk clkgen_db1_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 485 | ccu_div_ph__gclk clkgen_db1_io_gclk_if.ccu_div_ph; | |
| 486 | ccu_dr_sync_en__gclk void; | |
| 487 | ccu_io2x_sync_en__gclk void; | |
| 488 | ccu_serdes_dtm__gclk clkgen_db1_io_gclk_if.ccu_serdes_dtm; | |
| 489 | ccu_slow_cmp_sync_en__gclk clkgen_db1_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 490 | clk_ext__gclk clkgen_db1_io_gclk_if.clk_ext; | |
| 491 | cluster_arst_l__gclk clkgen_db1_io_gclk_if.cluster_arst_l; | |
| 492 | cluster_div_en__gclk clkgen_db1_io_gclk_if.cluster_div_en; | |
| 493 | cmp_slow_sync_en__gclk clkgen_db1_io_gclk_if.cmp_slow_sync_en; | |
| 494 | dr_sync_en__gclk void; | |
| 495 | gclk clkgen_db1_io_gclk_if.gclk; | |
| 496 | io2x_sync_en__gclk void; | |
| 497 | l2clk__gclk clkgen_db1_io_gclk_if.l2clk; | |
| 498 | pce_ov__gclk clkgen_db1_io_gclk_if.pce_ov; | |
| 499 | por___gclk clkgen_db1_io_gclk_if.por_; | |
| 500 | rst_por___gclk clkgen_db1_io_gclk_if.rst_por_; | |
| 501 | rst_wmr___gclk clkgen_db1_io_gclk_if.rst_wmr_; | |
| 502 | rst_wmr_protect__gclk clkgen_db1_io_gclk_if.rst_wmr_protect; | |
| 503 | scan_en__gclk clkgen_db1_io_gclk_if.scan_en; | |
| 504 | scan_in__gclk clkgen_db1_io_gclk_if.scan_in; | |
| 505 | scan_out__gclk clkgen_db1_io_gclk_if.scan_out; | |
| 506 | slow_cmp_sync_en__gclk clkgen_db1_io_gclk_if.slow_cmp_sync_en; | |
| 507 | tcu_aclk__gclk clkgen_db1_io_gclk_if.tcu_aclk; | |
| 508 | tcu_atpg_mode__gclk clkgen_db1_io_gclk_if.tcu_atpg_mode; | |
| 509 | tcu_bclk__gclk clkgen_db1_io_gclk_if.tcu_bclk; | |
| 510 | tcu_clk_stop__gclk clkgen_db1_io_gclk_if.tcu_clk_stop; | |
| 511 | tcu_div_bypass__gclk clkgen_db1_io_gclk_if.tcu_div_bypass; | |
| 512 | tcu_pce_ov__gclk clkgen_db1_io_gclk_if.tcu_pce_ov; | |
| 513 | tcu_wr_inhibit__gclk clkgen_db1_io_gclk_if.tcu_wr_inhibit; | |
| 514 | wmr___gclk clkgen_db1_io_gclk_if.wmr_; | |
| 515 | wmr_protect__gclk clkgen_db1_io_gclk_if.wmr_protect; | |
| 516 | pc_clk__gclk void; | |
| 517 | pc_clk_sel__gclk void; | |
| 518 | test_clk__gclk void; | |
| 519 | test_clk_sel__gclk void; | |
| 520 | ||
| 521 | //---l2clk is Vera interface CLOCK--- | |
| 522 | aclk__l2clk clkgen_db1_io_l2clk_if.aclk; | |
| 523 | aclk_wmr__l2clk clkgen_db1_io_l2clk_if.aclk_wmr; | |
| 524 | array_wr_inhibit__l2clk clkgen_db1_io_l2clk_if.array_wr_inhibit; | |
| 525 | bclk__l2clk clkgen_db1_io_l2clk_if.bclk; | |
| 526 | cmp_slow_sync_en__l2clk clkgen_db1_io_l2clk_if.cmp_slow_sync_en; | |
| 527 | dr_sync_en__l2clk void; | |
| 528 | io2x_sync_en__l2clk void; | |
| 529 | l2clk clkgen_db1_io_l2clk_if.l2clk; | |
| 530 | pce_ov__l2clk clkgen_db1_io_l2clk_if.pce_ov; | |
| 531 | por___l2clk clkgen_db1_io_l2clk_if.por_; | |
| 532 | scan_out__l2clk clkgen_db1_io_l2clk_if.scan_out; | |
| 533 | slow_cmp_sync_en__l2clk clkgen_db1_io_l2clk_if.slow_cmp_sync_en; | |
| 534 | wmr___l2clk clkgen_db1_io_l2clk_if.wmr_; | |
| 535 | wmr_protect__l2clk clkgen_db1_io_l2clk_if.wmr_protect; | |
| 536 | } | |
| 537 | ||
| 538 | //----- port binding for clkgen_efu_io ----- | |
| 539 | ||
| 540 | bind CLKGEN_port clkgen_efu_io_bind { | |
| 541 | //---gclk is Vera interface CLOCK--- | |
| 542 | aclk__gclk clkgen_efu_io_gclk_if.aclk; | |
| 543 | aclk_wmr__gclk clkgen_efu_io_gclk_if.aclk_wmr; | |
| 544 | array_wr_inhibit__gclk clkgen_efu_io_gclk_if.array_wr_inhibit; | |
| 545 | bclk__gclk clkgen_efu_io_gclk_if.bclk; | |
| 546 | ccu_cmp_slow_sync_en__gclk clkgen_efu_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 547 | ccu_div_ph__gclk clkgen_efu_io_gclk_if.ccu_div_ph; | |
| 548 | ccu_dr_sync_en__gclk void; | |
| 549 | ccu_io2x_sync_en__gclk void; | |
| 550 | ccu_serdes_dtm__gclk clkgen_efu_io_gclk_if.ccu_serdes_dtm; | |
| 551 | ccu_slow_cmp_sync_en__gclk clkgen_efu_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 552 | clk_ext__gclk clkgen_efu_io_gclk_if.clk_ext; | |
| 553 | cluster_arst_l__gclk clkgen_efu_io_gclk_if.cluster_arst_l; | |
| 554 | cluster_div_en__gclk clkgen_efu_io_gclk_if.cluster_div_en; | |
| 555 | cmp_slow_sync_en__gclk clkgen_efu_io_gclk_if.cmp_slow_sync_en; | |
| 556 | dr_sync_en__gclk void; | |
| 557 | gclk clkgen_efu_io_gclk_if.gclk; | |
| 558 | io2x_sync_en__gclk void; | |
| 559 | l2clk__gclk clkgen_efu_io_gclk_if.l2clk; | |
| 560 | pce_ov__gclk clkgen_efu_io_gclk_if.pce_ov; | |
| 561 | por___gclk clkgen_efu_io_gclk_if.por_; | |
| 562 | rst_por___gclk clkgen_efu_io_gclk_if.rst_por_; | |
| 563 | rst_wmr___gclk clkgen_efu_io_gclk_if.rst_wmr_; | |
| 564 | rst_wmr_protect__gclk clkgen_efu_io_gclk_if.rst_wmr_protect; | |
| 565 | scan_en__gclk clkgen_efu_io_gclk_if.scan_en; | |
| 566 | scan_in__gclk clkgen_efu_io_gclk_if.scan_in; | |
| 567 | scan_out__gclk clkgen_efu_io_gclk_if.scan_out; | |
| 568 | slow_cmp_sync_en__gclk clkgen_efu_io_gclk_if.slow_cmp_sync_en; | |
| 569 | tcu_aclk__gclk clkgen_efu_io_gclk_if.tcu_aclk; | |
| 570 | tcu_atpg_mode__gclk clkgen_efu_io_gclk_if.tcu_atpg_mode; | |
| 571 | tcu_bclk__gclk clkgen_efu_io_gclk_if.tcu_bclk; | |
| 572 | tcu_clk_stop__gclk clkgen_efu_io_gclk_if.tcu_clk_stop; | |
| 573 | tcu_div_bypass__gclk clkgen_efu_io_gclk_if.tcu_div_bypass; | |
| 574 | tcu_pce_ov__gclk clkgen_efu_io_gclk_if.tcu_pce_ov; | |
| 575 | tcu_wr_inhibit__gclk clkgen_efu_io_gclk_if.tcu_wr_inhibit; | |
| 576 | wmr___gclk clkgen_efu_io_gclk_if.wmr_; | |
| 577 | wmr_protect__gclk clkgen_efu_io_gclk_if.wmr_protect; | |
| 578 | pc_clk__gclk void; | |
| 579 | pc_clk_sel__gclk void; | |
| 580 | test_clk__gclk void; | |
| 581 | test_clk_sel__gclk void; | |
| 582 | ||
| 583 | //---l2clk is Vera interface CLOCK--- | |
| 584 | aclk__l2clk clkgen_efu_io_l2clk_if.aclk; | |
| 585 | aclk_wmr__l2clk clkgen_efu_io_l2clk_if.aclk_wmr; | |
| 586 | array_wr_inhibit__l2clk clkgen_efu_io_l2clk_if.array_wr_inhibit; | |
| 587 | bclk__l2clk clkgen_efu_io_l2clk_if.bclk; | |
| 588 | cmp_slow_sync_en__l2clk clkgen_efu_io_l2clk_if.cmp_slow_sync_en; | |
| 589 | dr_sync_en__l2clk void; | |
| 590 | io2x_sync_en__l2clk void; | |
| 591 | l2clk clkgen_efu_io_l2clk_if.l2clk; | |
| 592 | pce_ov__l2clk clkgen_efu_io_l2clk_if.pce_ov; | |
| 593 | por___l2clk clkgen_efu_io_l2clk_if.por_; | |
| 594 | scan_out__l2clk clkgen_efu_io_l2clk_if.scan_out; | |
| 595 | slow_cmp_sync_en__l2clk clkgen_efu_io_l2clk_if.slow_cmp_sync_en; | |
| 596 | wmr___l2clk clkgen_efu_io_l2clk_if.wmr_; | |
| 597 | wmr_protect__l2clk clkgen_efu_io_l2clk_if.wmr_protect; | |
| 598 | } | |
| 599 | ||
| 600 | //----- port binding for clkgen_efu_cmp ----- | |
| 601 | ||
| 602 | bind CLKGEN_port clkgen_efu_cmp_bind { | |
| 603 | //---gclk is Vera interface CLOCK--- | |
| 604 | aclk__gclk clkgen_efu_cmp_gclk_if.aclk; | |
| 605 | aclk_wmr__gclk clkgen_efu_cmp_gclk_if.aclk_wmr; | |
| 606 | array_wr_inhibit__gclk clkgen_efu_cmp_gclk_if.array_wr_inhibit; | |
| 607 | bclk__gclk clkgen_efu_cmp_gclk_if.bclk; | |
| 608 | ccu_cmp_slow_sync_en__gclk clkgen_efu_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 609 | ccu_div_ph__gclk clkgen_efu_cmp_gclk_if.ccu_div_ph; | |
| 610 | ccu_dr_sync_en__gclk void; | |
| 611 | ccu_io2x_sync_en__gclk void; | |
| 612 | ccu_serdes_dtm__gclk clkgen_efu_cmp_gclk_if.ccu_serdes_dtm; | |
| 613 | ccu_slow_cmp_sync_en__gclk clkgen_efu_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 614 | clk_ext__gclk clkgen_efu_cmp_gclk_if.clk_ext; | |
| 615 | cluster_arst_l__gclk clkgen_efu_cmp_gclk_if.cluster_arst_l; | |
| 616 | cluster_div_en__gclk clkgen_efu_cmp_gclk_if.cluster_div_en; | |
| 617 | cmp_slow_sync_en__gclk clkgen_efu_cmp_gclk_if.cmp_slow_sync_en; | |
| 618 | dr_sync_en__gclk void; | |
| 619 | gclk clkgen_efu_cmp_gclk_if.gclk; | |
| 620 | io2x_sync_en__gclk void; | |
| 621 | l2clk__gclk clkgen_efu_cmp_gclk_if.l2clk; | |
| 622 | pce_ov__gclk clkgen_efu_cmp_gclk_if.pce_ov; | |
| 623 | por___gclk clkgen_efu_cmp_gclk_if.por_; | |
| 624 | rst_por___gclk clkgen_efu_cmp_gclk_if.rst_por_; | |
| 625 | rst_wmr___gclk clkgen_efu_cmp_gclk_if.rst_wmr_; | |
| 626 | rst_wmr_protect__gclk clkgen_efu_cmp_gclk_if.rst_wmr_protect; | |
| 627 | scan_en__gclk clkgen_efu_cmp_gclk_if.scan_en; | |
| 628 | scan_in__gclk clkgen_efu_cmp_gclk_if.scan_in; | |
| 629 | scan_out__gclk clkgen_efu_cmp_gclk_if.scan_out; | |
| 630 | slow_cmp_sync_en__gclk clkgen_efu_cmp_gclk_if.slow_cmp_sync_en; | |
| 631 | tcu_aclk__gclk clkgen_efu_cmp_gclk_if.tcu_aclk; | |
| 632 | tcu_atpg_mode__gclk clkgen_efu_cmp_gclk_if.tcu_atpg_mode; | |
| 633 | tcu_bclk__gclk clkgen_efu_cmp_gclk_if.tcu_bclk; | |
| 634 | tcu_clk_stop__gclk clkgen_efu_cmp_gclk_if.tcu_clk_stop; | |
| 635 | tcu_div_bypass__gclk clkgen_efu_cmp_gclk_if.tcu_div_bypass; | |
| 636 | tcu_pce_ov__gclk clkgen_efu_cmp_gclk_if.tcu_pce_ov; | |
| 637 | tcu_wr_inhibit__gclk clkgen_efu_cmp_gclk_if.tcu_wr_inhibit; | |
| 638 | wmr___gclk clkgen_efu_cmp_gclk_if.wmr_; | |
| 639 | wmr_protect__gclk clkgen_efu_cmp_gclk_if.wmr_protect; | |
| 640 | pc_clk__gclk void; | |
| 641 | pc_clk_sel__gclk void; | |
| 642 | test_clk__gclk void; | |
| 643 | test_clk_sel__gclk void; | |
| 644 | ||
| 645 | //---l2clk is Vera interface CLOCK--- | |
| 646 | aclk__l2clk clkgen_efu_cmp_l2clk_if.aclk; | |
| 647 | aclk_wmr__l2clk clkgen_efu_cmp_l2clk_if.aclk_wmr; | |
| 648 | array_wr_inhibit__l2clk clkgen_efu_cmp_l2clk_if.array_wr_inhibit; | |
| 649 | bclk__l2clk clkgen_efu_cmp_l2clk_if.bclk; | |
| 650 | cmp_slow_sync_en__l2clk clkgen_efu_cmp_l2clk_if.cmp_slow_sync_en; | |
| 651 | dr_sync_en__l2clk void; | |
| 652 | io2x_sync_en__l2clk void; | |
| 653 | l2clk clkgen_efu_cmp_l2clk_if.l2clk; | |
| 654 | pce_ov__l2clk clkgen_efu_cmp_l2clk_if.pce_ov; | |
| 655 | por___l2clk clkgen_efu_cmp_l2clk_if.por_; | |
| 656 | scan_out__l2clk clkgen_efu_cmp_l2clk_if.scan_out; | |
| 657 | slow_cmp_sync_en__l2clk clkgen_efu_cmp_l2clk_if.slow_cmp_sync_en; | |
| 658 | wmr___l2clk clkgen_efu_cmp_l2clk_if.wmr_; | |
| 659 | wmr_protect__l2clk clkgen_efu_cmp_l2clk_if.wmr_protect; | |
| 660 | } | |
| 661 | ||
| 662 | //----- port binding for clkgen_mio_0_cmp ----- | |
| 663 | ||
| 664 | bind CLKGEN_port clkgen_mio_0_cmp_bind { | |
| 665 | //---gclk is Vera interface CLOCK--- | |
| 666 | aclk__gclk clkgen_mio_0_cmp_gclk_if.aclk; | |
| 667 | aclk_wmr__gclk clkgen_mio_0_cmp_gclk_if.aclk_wmr; | |
| 668 | array_wr_inhibit__gclk clkgen_mio_0_cmp_gclk_if.array_wr_inhibit; | |
| 669 | bclk__gclk clkgen_mio_0_cmp_gclk_if.bclk; | |
| 670 | ccu_cmp_slow_sync_en__gclk clkgen_mio_0_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 671 | ccu_div_ph__gclk clkgen_mio_0_cmp_gclk_if.ccu_div_ph; | |
| 672 | ccu_dr_sync_en__gclk void; | |
| 673 | ccu_io2x_sync_en__gclk void; | |
| 674 | ccu_serdes_dtm__gclk clkgen_mio_0_cmp_gclk_if.ccu_serdes_dtm; | |
| 675 | ccu_slow_cmp_sync_en__gclk clkgen_mio_0_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 676 | clk_ext__gclk clkgen_mio_0_cmp_gclk_if.clk_ext; | |
| 677 | cluster_arst_l__gclk clkgen_mio_0_cmp_gclk_if.cluster_arst_l; | |
| 678 | cluster_div_en__gclk clkgen_mio_0_cmp_gclk_if.cluster_div_en; | |
| 679 | cmp_slow_sync_en__gclk clkgen_mio_0_cmp_gclk_if.cmp_slow_sync_en; | |
| 680 | dr_sync_en__gclk void; | |
| 681 | gclk clkgen_mio_0_cmp_gclk_if.gclk; | |
| 682 | io2x_sync_en__gclk void; | |
| 683 | l2clk__gclk clkgen_mio_0_cmp_gclk_if.l2clk; | |
| 684 | pce_ov__gclk clkgen_mio_0_cmp_gclk_if.pce_ov; | |
| 685 | por___gclk clkgen_mio_0_cmp_gclk_if.por_; | |
| 686 | rst_por___gclk clkgen_mio_0_cmp_gclk_if.rst_por_; | |
| 687 | rst_wmr___gclk clkgen_mio_0_cmp_gclk_if.rst_wmr_; | |
| 688 | rst_wmr_protect__gclk clkgen_mio_0_cmp_gclk_if.rst_wmr_protect; | |
| 689 | scan_en__gclk clkgen_mio_0_cmp_gclk_if.scan_en; | |
| 690 | scan_in__gclk clkgen_mio_0_cmp_gclk_if.scan_in; | |
| 691 | scan_out__gclk clkgen_mio_0_cmp_gclk_if.scan_out; | |
| 692 | slow_cmp_sync_en__gclk clkgen_mio_0_cmp_gclk_if.slow_cmp_sync_en; | |
| 693 | tcu_aclk__gclk clkgen_mio_0_cmp_gclk_if.tcu_aclk; | |
| 694 | tcu_atpg_mode__gclk clkgen_mio_0_cmp_gclk_if.tcu_atpg_mode; | |
| 695 | tcu_bclk__gclk clkgen_mio_0_cmp_gclk_if.tcu_bclk; | |
| 696 | tcu_clk_stop__gclk clkgen_mio_0_cmp_gclk_if.tcu_clk_stop; | |
| 697 | tcu_div_bypass__gclk clkgen_mio_0_cmp_gclk_if.tcu_div_bypass; | |
| 698 | tcu_pce_ov__gclk clkgen_mio_0_cmp_gclk_if.tcu_pce_ov; | |
| 699 | tcu_wr_inhibit__gclk clkgen_mio_0_cmp_gclk_if.tcu_wr_inhibit; | |
| 700 | wmr___gclk clkgen_mio_0_cmp_gclk_if.wmr_; | |
| 701 | wmr_protect__gclk clkgen_mio_0_cmp_gclk_if.wmr_protect; | |
| 702 | pc_clk__gclk void; | |
| 703 | pc_clk_sel__gclk void; | |
| 704 | test_clk__gclk void; | |
| 705 | test_clk_sel__gclk void; | |
| 706 | ||
| 707 | //---l2clk is Vera interface CLOCK--- | |
| 708 | aclk__l2clk clkgen_mio_0_cmp_l2clk_if.aclk; | |
| 709 | aclk_wmr__l2clk clkgen_mio_0_cmp_l2clk_if.aclk_wmr; | |
| 710 | array_wr_inhibit__l2clk clkgen_mio_0_cmp_l2clk_if.array_wr_inhibit; | |
| 711 | bclk__l2clk clkgen_mio_0_cmp_l2clk_if.bclk; | |
| 712 | cmp_slow_sync_en__l2clk clkgen_mio_0_cmp_l2clk_if.cmp_slow_sync_en; | |
| 713 | dr_sync_en__l2clk void; | |
| 714 | io2x_sync_en__l2clk void; | |
| 715 | l2clk clkgen_mio_0_cmp_l2clk_if.l2clk; | |
| 716 | pce_ov__l2clk clkgen_mio_0_cmp_l2clk_if.pce_ov; | |
| 717 | por___l2clk clkgen_mio_0_cmp_l2clk_if.por_; | |
| 718 | scan_out__l2clk clkgen_mio_0_cmp_l2clk_if.scan_out; | |
| 719 | slow_cmp_sync_en__l2clk clkgen_mio_0_cmp_l2clk_if.slow_cmp_sync_en; | |
| 720 | wmr___l2clk clkgen_mio_0_cmp_l2clk_if.wmr_; | |
| 721 | wmr_protect__l2clk clkgen_mio_0_cmp_l2clk_if.wmr_protect; | |
| 722 | } | |
| 723 | ||
| 724 | //----- port binding for clkgen_mio_1_cmp ----- | |
| 725 | ||
| 726 | bind CLKGEN_port clkgen_mio_1_cmp_bind { | |
| 727 | //---gclk is Vera interface CLOCK--- | |
| 728 | aclk__gclk clkgen_mio_1_cmp_gclk_if.aclk; | |
| 729 | aclk_wmr__gclk clkgen_mio_1_cmp_gclk_if.aclk_wmr; | |
| 730 | array_wr_inhibit__gclk clkgen_mio_1_cmp_gclk_if.array_wr_inhibit; | |
| 731 | bclk__gclk clkgen_mio_1_cmp_gclk_if.bclk; | |
| 732 | ccu_cmp_slow_sync_en__gclk clkgen_mio_1_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 733 | ccu_div_ph__gclk clkgen_mio_1_cmp_gclk_if.ccu_div_ph; | |
| 734 | ccu_dr_sync_en__gclk void; | |
| 735 | ccu_io2x_sync_en__gclk void; | |
| 736 | ccu_serdes_dtm__gclk clkgen_mio_1_cmp_gclk_if.ccu_serdes_dtm; | |
| 737 | ccu_slow_cmp_sync_en__gclk clkgen_mio_1_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 738 | clk_ext__gclk clkgen_mio_1_cmp_gclk_if.clk_ext; | |
| 739 | cluster_arst_l__gclk clkgen_mio_1_cmp_gclk_if.cluster_arst_l; | |
| 740 | cluster_div_en__gclk clkgen_mio_1_cmp_gclk_if.cluster_div_en; | |
| 741 | cmp_slow_sync_en__gclk clkgen_mio_1_cmp_gclk_if.cmp_slow_sync_en; | |
| 742 | dr_sync_en__gclk void; | |
| 743 | gclk clkgen_mio_1_cmp_gclk_if.gclk; | |
| 744 | io2x_sync_en__gclk void; | |
| 745 | l2clk__gclk clkgen_mio_1_cmp_gclk_if.l2clk; | |
| 746 | pce_ov__gclk clkgen_mio_1_cmp_gclk_if.pce_ov; | |
| 747 | por___gclk clkgen_mio_1_cmp_gclk_if.por_; | |
| 748 | rst_por___gclk clkgen_mio_1_cmp_gclk_if.rst_por_; | |
| 749 | rst_wmr___gclk clkgen_mio_1_cmp_gclk_if.rst_wmr_; | |
| 750 | rst_wmr_protect__gclk clkgen_mio_1_cmp_gclk_if.rst_wmr_protect; | |
| 751 | scan_en__gclk clkgen_mio_1_cmp_gclk_if.scan_en; | |
| 752 | scan_in__gclk clkgen_mio_1_cmp_gclk_if.scan_in; | |
| 753 | scan_out__gclk clkgen_mio_1_cmp_gclk_if.scan_out; | |
| 754 | slow_cmp_sync_en__gclk clkgen_mio_1_cmp_gclk_if.slow_cmp_sync_en; | |
| 755 | tcu_aclk__gclk clkgen_mio_1_cmp_gclk_if.tcu_aclk; | |
| 756 | tcu_atpg_mode__gclk clkgen_mio_1_cmp_gclk_if.tcu_atpg_mode; | |
| 757 | tcu_bclk__gclk clkgen_mio_1_cmp_gclk_if.tcu_bclk; | |
| 758 | tcu_clk_stop__gclk clkgen_mio_1_cmp_gclk_if.tcu_clk_stop; | |
| 759 | tcu_div_bypass__gclk clkgen_mio_1_cmp_gclk_if.tcu_div_bypass; | |
| 760 | tcu_pce_ov__gclk clkgen_mio_1_cmp_gclk_if.tcu_pce_ov; | |
| 761 | tcu_wr_inhibit__gclk clkgen_mio_1_cmp_gclk_if.tcu_wr_inhibit; | |
| 762 | wmr___gclk clkgen_mio_1_cmp_gclk_if.wmr_; | |
| 763 | wmr_protect__gclk clkgen_mio_1_cmp_gclk_if.wmr_protect; | |
| 764 | pc_clk__gclk void; | |
| 765 | pc_clk_sel__gclk void; | |
| 766 | test_clk__gclk void; | |
| 767 | test_clk_sel__gclk void; | |
| 768 | ||
| 769 | //---l2clk is Vera interface CLOCK--- | |
| 770 | aclk__l2clk clkgen_mio_1_cmp_l2clk_if.aclk; | |
| 771 | aclk_wmr__l2clk clkgen_mio_1_cmp_l2clk_if.aclk_wmr; | |
| 772 | array_wr_inhibit__l2clk clkgen_mio_1_cmp_l2clk_if.array_wr_inhibit; | |
| 773 | bclk__l2clk clkgen_mio_1_cmp_l2clk_if.bclk; | |
| 774 | cmp_slow_sync_en__l2clk clkgen_mio_1_cmp_l2clk_if.cmp_slow_sync_en; | |
| 775 | dr_sync_en__l2clk void; | |
| 776 | io2x_sync_en__l2clk void; | |
| 777 | l2clk clkgen_mio_1_cmp_l2clk_if.l2clk; | |
| 778 | pce_ov__l2clk clkgen_mio_1_cmp_l2clk_if.pce_ov; | |
| 779 | por___l2clk clkgen_mio_1_cmp_l2clk_if.por_; | |
| 780 | scan_out__l2clk clkgen_mio_1_cmp_l2clk_if.scan_out; | |
| 781 | slow_cmp_sync_en__l2clk clkgen_mio_1_cmp_l2clk_if.slow_cmp_sync_en; | |
| 782 | wmr___l2clk clkgen_mio_1_cmp_l2clk_if.wmr_; | |
| 783 | wmr_protect__l2clk clkgen_mio_1_cmp_l2clk_if.wmr_protect; | |
| 784 | } | |
| 785 | ||
| 786 | //----- port binding for clkgen_mio_2_cmp ----- | |
| 787 | ||
| 788 | bind CLKGEN_port clkgen_mio_2_cmp_bind { | |
| 789 | //---gclk is Vera interface CLOCK--- | |
| 790 | aclk__gclk clkgen_mio_2_cmp_gclk_if.aclk; | |
| 791 | aclk_wmr__gclk clkgen_mio_2_cmp_gclk_if.aclk_wmr; | |
| 792 | array_wr_inhibit__gclk clkgen_mio_2_cmp_gclk_if.array_wr_inhibit; | |
| 793 | bclk__gclk clkgen_mio_2_cmp_gclk_if.bclk; | |
| 794 | ccu_cmp_slow_sync_en__gclk clkgen_mio_2_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 795 | ccu_div_ph__gclk clkgen_mio_2_cmp_gclk_if.ccu_div_ph; | |
| 796 | ccu_dr_sync_en__gclk void; | |
| 797 | ccu_io2x_sync_en__gclk void; | |
| 798 | ccu_serdes_dtm__gclk clkgen_mio_2_cmp_gclk_if.ccu_serdes_dtm; | |
| 799 | ccu_slow_cmp_sync_en__gclk clkgen_mio_2_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 800 | clk_ext__gclk clkgen_mio_2_cmp_gclk_if.clk_ext; | |
| 801 | cluster_arst_l__gclk clkgen_mio_2_cmp_gclk_if.cluster_arst_l; | |
| 802 | cluster_div_en__gclk clkgen_mio_2_cmp_gclk_if.cluster_div_en; | |
| 803 | cmp_slow_sync_en__gclk clkgen_mio_2_cmp_gclk_if.cmp_slow_sync_en; | |
| 804 | dr_sync_en__gclk void; | |
| 805 | gclk clkgen_mio_2_cmp_gclk_if.gclk; | |
| 806 | io2x_sync_en__gclk void; | |
| 807 | l2clk__gclk clkgen_mio_2_cmp_gclk_if.l2clk; | |
| 808 | pce_ov__gclk clkgen_mio_2_cmp_gclk_if.pce_ov; | |
| 809 | por___gclk clkgen_mio_2_cmp_gclk_if.por_; | |
| 810 | rst_por___gclk clkgen_mio_2_cmp_gclk_if.rst_por_; | |
| 811 | rst_wmr___gclk clkgen_mio_2_cmp_gclk_if.rst_wmr_; | |
| 812 | rst_wmr_protect__gclk clkgen_mio_2_cmp_gclk_if.rst_wmr_protect; | |
| 813 | scan_en__gclk clkgen_mio_2_cmp_gclk_if.scan_en; | |
| 814 | scan_in__gclk clkgen_mio_2_cmp_gclk_if.scan_in; | |
| 815 | scan_out__gclk clkgen_mio_2_cmp_gclk_if.scan_out; | |
| 816 | slow_cmp_sync_en__gclk clkgen_mio_2_cmp_gclk_if.slow_cmp_sync_en; | |
| 817 | tcu_aclk__gclk clkgen_mio_2_cmp_gclk_if.tcu_aclk; | |
| 818 | tcu_atpg_mode__gclk clkgen_mio_2_cmp_gclk_if.tcu_atpg_mode; | |
| 819 | tcu_bclk__gclk clkgen_mio_2_cmp_gclk_if.tcu_bclk; | |
| 820 | tcu_clk_stop__gclk clkgen_mio_2_cmp_gclk_if.tcu_clk_stop; | |
| 821 | tcu_div_bypass__gclk clkgen_mio_2_cmp_gclk_if.tcu_div_bypass; | |
| 822 | tcu_pce_ov__gclk clkgen_mio_2_cmp_gclk_if.tcu_pce_ov; | |
| 823 | tcu_wr_inhibit__gclk clkgen_mio_2_cmp_gclk_if.tcu_wr_inhibit; | |
| 824 | wmr___gclk clkgen_mio_2_cmp_gclk_if.wmr_; | |
| 825 | wmr_protect__gclk clkgen_mio_2_cmp_gclk_if.wmr_protect; | |
| 826 | pc_clk__gclk void; | |
| 827 | pc_clk_sel__gclk void; | |
| 828 | test_clk__gclk void; | |
| 829 | test_clk_sel__gclk void; | |
| 830 | ||
| 831 | //---l2clk is Vera interface CLOCK--- | |
| 832 | aclk__l2clk clkgen_mio_2_cmp_l2clk_if.aclk; | |
| 833 | aclk_wmr__l2clk clkgen_mio_2_cmp_l2clk_if.aclk_wmr; | |
| 834 | array_wr_inhibit__l2clk clkgen_mio_2_cmp_l2clk_if.array_wr_inhibit; | |
| 835 | bclk__l2clk clkgen_mio_2_cmp_l2clk_if.bclk; | |
| 836 | cmp_slow_sync_en__l2clk clkgen_mio_2_cmp_l2clk_if.cmp_slow_sync_en; | |
| 837 | dr_sync_en__l2clk void; | |
| 838 | io2x_sync_en__l2clk void; | |
| 839 | l2clk clkgen_mio_2_cmp_l2clk_if.l2clk; | |
| 840 | pce_ov__l2clk clkgen_mio_2_cmp_l2clk_if.pce_ov; | |
| 841 | por___l2clk clkgen_mio_2_cmp_l2clk_if.por_; | |
| 842 | scan_out__l2clk clkgen_mio_2_cmp_l2clk_if.scan_out; | |
| 843 | slow_cmp_sync_en__l2clk clkgen_mio_2_cmp_l2clk_if.slow_cmp_sync_en; | |
| 844 | wmr___l2clk clkgen_mio_2_cmp_l2clk_if.wmr_; | |
| 845 | wmr_protect__l2clk clkgen_mio_2_cmp_l2clk_if.wmr_protect; | |
| 846 | } | |
| 847 | ||
| 848 | //----- port binding for clkgen_mio_3_cmp ----- | |
| 849 | ||
| 850 | bind CLKGEN_port clkgen_mio_3_cmp_bind { | |
| 851 | //---gclk is Vera interface CLOCK--- | |
| 852 | aclk__gclk clkgen_mio_3_cmp_gclk_if.aclk; | |
| 853 | aclk_wmr__gclk clkgen_mio_3_cmp_gclk_if.aclk_wmr; | |
| 854 | array_wr_inhibit__gclk clkgen_mio_3_cmp_gclk_if.array_wr_inhibit; | |
| 855 | bclk__gclk clkgen_mio_3_cmp_gclk_if.bclk; | |
| 856 | ccu_cmp_slow_sync_en__gclk clkgen_mio_3_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 857 | ccu_div_ph__gclk clkgen_mio_3_cmp_gclk_if.ccu_div_ph; | |
| 858 | ccu_dr_sync_en__gclk void; | |
| 859 | ccu_io2x_sync_en__gclk void; | |
| 860 | ccu_serdes_dtm__gclk clkgen_mio_3_cmp_gclk_if.ccu_serdes_dtm; | |
| 861 | ccu_slow_cmp_sync_en__gclk clkgen_mio_3_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 862 | clk_ext__gclk clkgen_mio_3_cmp_gclk_if.clk_ext; | |
| 863 | cluster_arst_l__gclk clkgen_mio_3_cmp_gclk_if.cluster_arst_l; | |
| 864 | cluster_div_en__gclk clkgen_mio_3_cmp_gclk_if.cluster_div_en; | |
| 865 | cmp_slow_sync_en__gclk clkgen_mio_3_cmp_gclk_if.cmp_slow_sync_en; | |
| 866 | dr_sync_en__gclk void; | |
| 867 | gclk clkgen_mio_3_cmp_gclk_if.gclk; | |
| 868 | io2x_sync_en__gclk void; | |
| 869 | l2clk__gclk clkgen_mio_3_cmp_gclk_if.l2clk; | |
| 870 | pce_ov__gclk clkgen_mio_3_cmp_gclk_if.pce_ov; | |
| 871 | por___gclk clkgen_mio_3_cmp_gclk_if.por_; | |
| 872 | rst_por___gclk clkgen_mio_3_cmp_gclk_if.rst_por_; | |
| 873 | rst_wmr___gclk clkgen_mio_3_cmp_gclk_if.rst_wmr_; | |
| 874 | rst_wmr_protect__gclk clkgen_mio_3_cmp_gclk_if.rst_wmr_protect; | |
| 875 | scan_en__gclk clkgen_mio_3_cmp_gclk_if.scan_en; | |
| 876 | scan_in__gclk clkgen_mio_3_cmp_gclk_if.scan_in; | |
| 877 | scan_out__gclk clkgen_mio_3_cmp_gclk_if.scan_out; | |
| 878 | slow_cmp_sync_en__gclk clkgen_mio_3_cmp_gclk_if.slow_cmp_sync_en; | |
| 879 | tcu_aclk__gclk clkgen_mio_3_cmp_gclk_if.tcu_aclk; | |
| 880 | tcu_atpg_mode__gclk clkgen_mio_3_cmp_gclk_if.tcu_atpg_mode; | |
| 881 | tcu_bclk__gclk clkgen_mio_3_cmp_gclk_if.tcu_bclk; | |
| 882 | tcu_clk_stop__gclk clkgen_mio_3_cmp_gclk_if.tcu_clk_stop; | |
| 883 | tcu_div_bypass__gclk clkgen_mio_3_cmp_gclk_if.tcu_div_bypass; | |
| 884 | tcu_pce_ov__gclk clkgen_mio_3_cmp_gclk_if.tcu_pce_ov; | |
| 885 | tcu_wr_inhibit__gclk clkgen_mio_3_cmp_gclk_if.tcu_wr_inhibit; | |
| 886 | wmr___gclk clkgen_mio_3_cmp_gclk_if.wmr_; | |
| 887 | wmr_protect__gclk clkgen_mio_3_cmp_gclk_if.wmr_protect; | |
| 888 | pc_clk__gclk void; | |
| 889 | pc_clk_sel__gclk void; | |
| 890 | test_clk__gclk void; | |
| 891 | test_clk_sel__gclk void; | |
| 892 | ||
| 893 | //---l2clk is Vera interface CLOCK--- | |
| 894 | aclk__l2clk clkgen_mio_3_cmp_l2clk_if.aclk; | |
| 895 | aclk_wmr__l2clk clkgen_mio_3_cmp_l2clk_if.aclk_wmr; | |
| 896 | array_wr_inhibit__l2clk clkgen_mio_3_cmp_l2clk_if.array_wr_inhibit; | |
| 897 | bclk__l2clk clkgen_mio_3_cmp_l2clk_if.bclk; | |
| 898 | cmp_slow_sync_en__l2clk clkgen_mio_3_cmp_l2clk_if.cmp_slow_sync_en; | |
| 899 | dr_sync_en__l2clk void; | |
| 900 | io2x_sync_en__l2clk void; | |
| 901 | l2clk clkgen_mio_3_cmp_l2clk_if.l2clk; | |
| 902 | pce_ov__l2clk clkgen_mio_3_cmp_l2clk_if.pce_ov; | |
| 903 | por___l2clk clkgen_mio_3_cmp_l2clk_if.por_; | |
| 904 | scan_out__l2clk clkgen_mio_3_cmp_l2clk_if.scan_out; | |
| 905 | slow_cmp_sync_en__l2clk clkgen_mio_3_cmp_l2clk_if.slow_cmp_sync_en; | |
| 906 | wmr___l2clk clkgen_mio_3_cmp_l2clk_if.wmr_; | |
| 907 | wmr_protect__l2clk clkgen_mio_3_cmp_l2clk_if.wmr_protect; | |
| 908 | } | |
| 909 | ||
| 910 | //----- port binding for clkgen_mio_io ----- | |
| 911 | ||
| 912 | bind CLKGEN_port clkgen_mio_io_bind { | |
| 913 | //---gclk is Vera interface CLOCK--- | |
| 914 | aclk__gclk clkgen_mio_io_gclk_if.aclk; | |
| 915 | aclk_wmr__gclk clkgen_mio_io_gclk_if.aclk_wmr; | |
| 916 | array_wr_inhibit__gclk clkgen_mio_io_gclk_if.array_wr_inhibit; | |
| 917 | bclk__gclk clkgen_mio_io_gclk_if.bclk; | |
| 918 | ccu_cmp_slow_sync_en__gclk clkgen_mio_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 919 | ccu_div_ph__gclk clkgen_mio_io_gclk_if.ccu_div_ph; | |
| 920 | ccu_dr_sync_en__gclk void; | |
| 921 | ccu_io2x_sync_en__gclk void; | |
| 922 | ccu_serdes_dtm__gclk clkgen_mio_io_gclk_if.ccu_serdes_dtm; | |
| 923 | ccu_slow_cmp_sync_en__gclk clkgen_mio_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 924 | clk_ext__gclk clkgen_mio_io_gclk_if.clk_ext; | |
| 925 | cluster_arst_l__gclk clkgen_mio_io_gclk_if.cluster_arst_l; | |
| 926 | cluster_div_en__gclk clkgen_mio_io_gclk_if.cluster_div_en; | |
| 927 | cmp_slow_sync_en__gclk clkgen_mio_io_gclk_if.cmp_slow_sync_en; | |
| 928 | dr_sync_en__gclk void; | |
| 929 | gclk clkgen_mio_io_gclk_if.gclk; | |
| 930 | io2x_sync_en__gclk void; | |
| 931 | l2clk__gclk clkgen_mio_io_gclk_if.l2clk; | |
| 932 | pce_ov__gclk clkgen_mio_io_gclk_if.pce_ov; | |
| 933 | por___gclk clkgen_mio_io_gclk_if.por_; | |
| 934 | rst_por___gclk clkgen_mio_io_gclk_if.rst_por_; | |
| 935 | rst_wmr___gclk clkgen_mio_io_gclk_if.rst_wmr_; | |
| 936 | rst_wmr_protect__gclk clkgen_mio_io_gclk_if.rst_wmr_protect; | |
| 937 | scan_en__gclk clkgen_mio_io_gclk_if.scan_en; | |
| 938 | scan_in__gclk clkgen_mio_io_gclk_if.scan_in; | |
| 939 | scan_out__gclk clkgen_mio_io_gclk_if.scan_out; | |
| 940 | slow_cmp_sync_en__gclk clkgen_mio_io_gclk_if.slow_cmp_sync_en; | |
| 941 | tcu_aclk__gclk clkgen_mio_io_gclk_if.tcu_aclk; | |
| 942 | tcu_atpg_mode__gclk clkgen_mio_io_gclk_if.tcu_atpg_mode; | |
| 943 | tcu_bclk__gclk clkgen_mio_io_gclk_if.tcu_bclk; | |
| 944 | tcu_clk_stop__gclk clkgen_mio_io_gclk_if.tcu_clk_stop; | |
| 945 | tcu_div_bypass__gclk clkgen_mio_io_gclk_if.tcu_div_bypass; | |
| 946 | tcu_pce_ov__gclk clkgen_mio_io_gclk_if.tcu_pce_ov; | |
| 947 | tcu_wr_inhibit__gclk clkgen_mio_io_gclk_if.tcu_wr_inhibit; | |
| 948 | wmr___gclk clkgen_mio_io_gclk_if.wmr_; | |
| 949 | wmr_protect__gclk clkgen_mio_io_gclk_if.wmr_protect; | |
| 950 | pc_clk__gclk void; | |
| 951 | pc_clk_sel__gclk void; | |
| 952 | test_clk__gclk void; | |
| 953 | test_clk_sel__gclk void; | |
| 954 | ||
| 955 | //---l2clk is Vera interface CLOCK--- | |
| 956 | aclk__l2clk clkgen_mio_io_l2clk_if.aclk; | |
| 957 | aclk_wmr__l2clk clkgen_mio_io_l2clk_if.aclk_wmr; | |
| 958 | array_wr_inhibit__l2clk clkgen_mio_io_l2clk_if.array_wr_inhibit; | |
| 959 | bclk__l2clk clkgen_mio_io_l2clk_if.bclk; | |
| 960 | cmp_slow_sync_en__l2clk clkgen_mio_io_l2clk_if.cmp_slow_sync_en; | |
| 961 | dr_sync_en__l2clk void; | |
| 962 | io2x_sync_en__l2clk void; | |
| 963 | l2clk clkgen_mio_io_l2clk_if.l2clk; | |
| 964 | pce_ov__l2clk clkgen_mio_io_l2clk_if.pce_ov; | |
| 965 | por___l2clk clkgen_mio_io_l2clk_if.por_; | |
| 966 | scan_out__l2clk clkgen_mio_io_l2clk_if.scan_out; | |
| 967 | slow_cmp_sync_en__l2clk clkgen_mio_io_l2clk_if.slow_cmp_sync_en; | |
| 968 | wmr___l2clk clkgen_mio_io_l2clk_if.wmr_; | |
| 969 | wmr_protect__l2clk clkgen_mio_io_l2clk_if.wmr_protect; | |
| 970 | } | |
| 971 | ||
| 972 | //----- port binding for clkgen_ncu_cmp ----- | |
| 973 | ||
| 974 | bind CLKGEN_port clkgen_ncu_cmp_bind { | |
| 975 | //---gclk is Vera interface CLOCK--- | |
| 976 | aclk__gclk clkgen_ncu_cmp_gclk_if.aclk; | |
| 977 | aclk_wmr__gclk clkgen_ncu_cmp_gclk_if.aclk_wmr; | |
| 978 | array_wr_inhibit__gclk clkgen_ncu_cmp_gclk_if.array_wr_inhibit; | |
| 979 | bclk__gclk clkgen_ncu_cmp_gclk_if.bclk; | |
| 980 | ccu_cmp_slow_sync_en__gclk clkgen_ncu_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 981 | ccu_div_ph__gclk clkgen_ncu_cmp_gclk_if.ccu_div_ph; | |
| 982 | ccu_dr_sync_en__gclk void; | |
| 983 | ccu_io2x_sync_en__gclk void; | |
| 984 | ccu_serdes_dtm__gclk clkgen_ncu_cmp_gclk_if.ccu_serdes_dtm; | |
| 985 | ccu_slow_cmp_sync_en__gclk clkgen_ncu_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 986 | clk_ext__gclk clkgen_ncu_cmp_gclk_if.clk_ext; | |
| 987 | cluster_arst_l__gclk clkgen_ncu_cmp_gclk_if.cluster_arst_l; | |
| 988 | cluster_div_en__gclk clkgen_ncu_cmp_gclk_if.cluster_div_en; | |
| 989 | cmp_slow_sync_en__gclk clkgen_ncu_cmp_gclk_if.cmp_slow_sync_en; | |
| 990 | dr_sync_en__gclk void; | |
| 991 | gclk clkgen_ncu_cmp_gclk_if.gclk; | |
| 992 | io2x_sync_en__gclk void; | |
| 993 | l2clk__gclk clkgen_ncu_cmp_gclk_if.l2clk; | |
| 994 | pce_ov__gclk clkgen_ncu_cmp_gclk_if.pce_ov; | |
| 995 | por___gclk clkgen_ncu_cmp_gclk_if.por_; | |
| 996 | rst_por___gclk clkgen_ncu_cmp_gclk_if.rst_por_; | |
| 997 | rst_wmr___gclk clkgen_ncu_cmp_gclk_if.rst_wmr_; | |
| 998 | rst_wmr_protect__gclk clkgen_ncu_cmp_gclk_if.rst_wmr_protect; | |
| 999 | scan_en__gclk clkgen_ncu_cmp_gclk_if.scan_en; | |
| 1000 | scan_in__gclk clkgen_ncu_cmp_gclk_if.scan_in; | |
| 1001 | scan_out__gclk clkgen_ncu_cmp_gclk_if.scan_out; | |
| 1002 | slow_cmp_sync_en__gclk clkgen_ncu_cmp_gclk_if.slow_cmp_sync_en; | |
| 1003 | tcu_aclk__gclk clkgen_ncu_cmp_gclk_if.tcu_aclk; | |
| 1004 | tcu_atpg_mode__gclk clkgen_ncu_cmp_gclk_if.tcu_atpg_mode; | |
| 1005 | tcu_bclk__gclk clkgen_ncu_cmp_gclk_if.tcu_bclk; | |
| 1006 | tcu_clk_stop__gclk clkgen_ncu_cmp_gclk_if.tcu_clk_stop; | |
| 1007 | tcu_div_bypass__gclk clkgen_ncu_cmp_gclk_if.tcu_div_bypass; | |
| 1008 | tcu_pce_ov__gclk clkgen_ncu_cmp_gclk_if.tcu_pce_ov; | |
| 1009 | tcu_wr_inhibit__gclk clkgen_ncu_cmp_gclk_if.tcu_wr_inhibit; | |
| 1010 | wmr___gclk clkgen_ncu_cmp_gclk_if.wmr_; | |
| 1011 | wmr_protect__gclk clkgen_ncu_cmp_gclk_if.wmr_protect; | |
| 1012 | pc_clk__gclk void; | |
| 1013 | pc_clk_sel__gclk void; | |
| 1014 | test_clk__gclk void; | |
| 1015 | test_clk_sel__gclk void; | |
| 1016 | ||
| 1017 | //---l2clk is Vera interface CLOCK--- | |
| 1018 | aclk__l2clk clkgen_ncu_cmp_l2clk_if.aclk; | |
| 1019 | aclk_wmr__l2clk clkgen_ncu_cmp_l2clk_if.aclk_wmr; | |
| 1020 | array_wr_inhibit__l2clk clkgen_ncu_cmp_l2clk_if.array_wr_inhibit; | |
| 1021 | bclk__l2clk clkgen_ncu_cmp_l2clk_if.bclk; | |
| 1022 | cmp_slow_sync_en__l2clk clkgen_ncu_cmp_l2clk_if.cmp_slow_sync_en; | |
| 1023 | dr_sync_en__l2clk void; | |
| 1024 | io2x_sync_en__l2clk void; | |
| 1025 | l2clk clkgen_ncu_cmp_l2clk_if.l2clk; | |
| 1026 | pce_ov__l2clk clkgen_ncu_cmp_l2clk_if.pce_ov; | |
| 1027 | por___l2clk clkgen_ncu_cmp_l2clk_if.por_; | |
| 1028 | scan_out__l2clk clkgen_ncu_cmp_l2clk_if.scan_out; | |
| 1029 | slow_cmp_sync_en__l2clk clkgen_ncu_cmp_l2clk_if.slow_cmp_sync_en; | |
| 1030 | wmr___l2clk clkgen_ncu_cmp_l2clk_if.wmr_; | |
| 1031 | wmr_protect__l2clk clkgen_ncu_cmp_l2clk_if.wmr_protect; | |
| 1032 | } | |
| 1033 | ||
| 1034 | //----- port binding for clkgen_ncu_io ----- | |
| 1035 | ||
| 1036 | bind CLKGEN_port clkgen_ncu_io_bind { | |
| 1037 | //---gclk is Vera interface CLOCK--- | |
| 1038 | aclk__gclk clkgen_ncu_io_gclk_if.aclk; | |
| 1039 | aclk_wmr__gclk clkgen_ncu_io_gclk_if.aclk_wmr; | |
| 1040 | array_wr_inhibit__gclk clkgen_ncu_io_gclk_if.array_wr_inhibit; | |
| 1041 | bclk__gclk clkgen_ncu_io_gclk_if.bclk; | |
| 1042 | ccu_cmp_slow_sync_en__gclk clkgen_ncu_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 1043 | ccu_div_ph__gclk clkgen_ncu_io_gclk_if.ccu_div_ph; | |
| 1044 | ccu_dr_sync_en__gclk void; | |
| 1045 | ccu_io2x_sync_en__gclk void; | |
| 1046 | ccu_serdes_dtm__gclk clkgen_ncu_io_gclk_if.ccu_serdes_dtm; | |
| 1047 | ccu_slow_cmp_sync_en__gclk clkgen_ncu_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 1048 | clk_ext__gclk clkgen_ncu_io_gclk_if.clk_ext; | |
| 1049 | cluster_arst_l__gclk clkgen_ncu_io_gclk_if.cluster_arst_l; | |
| 1050 | cluster_div_en__gclk clkgen_ncu_io_gclk_if.cluster_div_en; | |
| 1051 | cmp_slow_sync_en__gclk clkgen_ncu_io_gclk_if.cmp_slow_sync_en; | |
| 1052 | dr_sync_en__gclk void; | |
| 1053 | gclk clkgen_ncu_io_gclk_if.gclk; | |
| 1054 | io2x_sync_en__gclk void; | |
| 1055 | l2clk__gclk clkgen_ncu_io_gclk_if.l2clk; | |
| 1056 | pce_ov__gclk clkgen_ncu_io_gclk_if.pce_ov; | |
| 1057 | por___gclk clkgen_ncu_io_gclk_if.por_; | |
| 1058 | rst_por___gclk clkgen_ncu_io_gclk_if.rst_por_; | |
| 1059 | rst_wmr___gclk clkgen_ncu_io_gclk_if.rst_wmr_; | |
| 1060 | rst_wmr_protect__gclk clkgen_ncu_io_gclk_if.rst_wmr_protect; | |
| 1061 | scan_en__gclk clkgen_ncu_io_gclk_if.scan_en; | |
| 1062 | scan_in__gclk clkgen_ncu_io_gclk_if.scan_in; | |
| 1063 | scan_out__gclk clkgen_ncu_io_gclk_if.scan_out; | |
| 1064 | slow_cmp_sync_en__gclk clkgen_ncu_io_gclk_if.slow_cmp_sync_en; | |
| 1065 | tcu_aclk__gclk clkgen_ncu_io_gclk_if.tcu_aclk; | |
| 1066 | tcu_atpg_mode__gclk clkgen_ncu_io_gclk_if.tcu_atpg_mode; | |
| 1067 | tcu_bclk__gclk clkgen_ncu_io_gclk_if.tcu_bclk; | |
| 1068 | tcu_clk_stop__gclk clkgen_ncu_io_gclk_if.tcu_clk_stop; | |
| 1069 | tcu_div_bypass__gclk clkgen_ncu_io_gclk_if.tcu_div_bypass; | |
| 1070 | tcu_pce_ov__gclk clkgen_ncu_io_gclk_if.tcu_pce_ov; | |
| 1071 | tcu_wr_inhibit__gclk clkgen_ncu_io_gclk_if.tcu_wr_inhibit; | |
| 1072 | wmr___gclk clkgen_ncu_io_gclk_if.wmr_; | |
| 1073 | wmr_protect__gclk clkgen_ncu_io_gclk_if.wmr_protect; | |
| 1074 | pc_clk__gclk void; | |
| 1075 | pc_clk_sel__gclk void; | |
| 1076 | test_clk__gclk void; | |
| 1077 | test_clk_sel__gclk void; | |
| 1078 | ||
| 1079 | //---l2clk is Vera interface CLOCK--- | |
| 1080 | aclk__l2clk clkgen_ncu_io_l2clk_if.aclk; | |
| 1081 | aclk_wmr__l2clk clkgen_ncu_io_l2clk_if.aclk_wmr; | |
| 1082 | array_wr_inhibit__l2clk clkgen_ncu_io_l2clk_if.array_wr_inhibit; | |
| 1083 | bclk__l2clk clkgen_ncu_io_l2clk_if.bclk; | |
| 1084 | cmp_slow_sync_en__l2clk clkgen_ncu_io_l2clk_if.cmp_slow_sync_en; | |
| 1085 | dr_sync_en__l2clk void; | |
| 1086 | io2x_sync_en__l2clk void; | |
| 1087 | l2clk clkgen_ncu_io_l2clk_if.l2clk; | |
| 1088 | pce_ov__l2clk clkgen_ncu_io_l2clk_if.pce_ov; | |
| 1089 | por___l2clk clkgen_ncu_io_l2clk_if.por_; | |
| 1090 | scan_out__l2clk clkgen_ncu_io_l2clk_if.scan_out; | |
| 1091 | slow_cmp_sync_en__l2clk clkgen_ncu_io_l2clk_if.slow_cmp_sync_en; | |
| 1092 | wmr___l2clk clkgen_ncu_io_l2clk_if.wmr_; | |
| 1093 | wmr_protect__l2clk clkgen_ncu_io_l2clk_if.wmr_protect; | |
| 1094 | } | |
| 1095 | ||
| 1096 | //----- port binding for clkgen_rst_cmp ----- | |
| 1097 | ||
| 1098 | bind CLKGEN_port clkgen_rst_cmp_bind { | |
| 1099 | //---gclk is Vera interface CLOCK--- | |
| 1100 | aclk__gclk clkgen_rst_cmp_gclk_if.aclk; | |
| 1101 | aclk_wmr__gclk clkgen_rst_cmp_gclk_if.aclk_wmr; | |
| 1102 | array_wr_inhibit__gclk clkgen_rst_cmp_gclk_if.array_wr_inhibit; | |
| 1103 | bclk__gclk clkgen_rst_cmp_gclk_if.bclk; | |
| 1104 | ccu_cmp_slow_sync_en__gclk clkgen_rst_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 1105 | ccu_div_ph__gclk clkgen_rst_cmp_gclk_if.ccu_div_ph; | |
| 1106 | ccu_dr_sync_en__gclk void; | |
| 1107 | ccu_io2x_sync_en__gclk void; | |
| 1108 | ccu_serdes_dtm__gclk clkgen_rst_cmp_gclk_if.ccu_serdes_dtm; | |
| 1109 | ccu_slow_cmp_sync_en__gclk clkgen_rst_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 1110 | clk_ext__gclk clkgen_rst_cmp_gclk_if.clk_ext; | |
| 1111 | cluster_arst_l__gclk clkgen_rst_cmp_gclk_if.cluster_arst_l; | |
| 1112 | cluster_div_en__gclk clkgen_rst_cmp_gclk_if.cluster_div_en; | |
| 1113 | cmp_slow_sync_en__gclk clkgen_rst_cmp_gclk_if.cmp_slow_sync_en; | |
| 1114 | dr_sync_en__gclk void; | |
| 1115 | gclk clkgen_rst_cmp_gclk_if.gclk; | |
| 1116 | io2x_sync_en__gclk void; | |
| 1117 | l2clk__gclk clkgen_rst_cmp_gclk_if.l2clk; | |
| 1118 | pce_ov__gclk clkgen_rst_cmp_gclk_if.pce_ov; | |
| 1119 | por___gclk clkgen_rst_cmp_gclk_if.por_; | |
| 1120 | rst_por___gclk clkgen_rst_cmp_gclk_if.rst_por_; | |
| 1121 | rst_wmr___gclk clkgen_rst_cmp_gclk_if.rst_wmr_; | |
| 1122 | rst_wmr_protect__gclk clkgen_rst_cmp_gclk_if.rst_wmr_protect; | |
| 1123 | scan_en__gclk clkgen_rst_cmp_gclk_if.scan_en; | |
| 1124 | scan_in__gclk clkgen_rst_cmp_gclk_if.scan_in; | |
| 1125 | scan_out__gclk clkgen_rst_cmp_gclk_if.scan_out; | |
| 1126 | slow_cmp_sync_en__gclk clkgen_rst_cmp_gclk_if.slow_cmp_sync_en; | |
| 1127 | tcu_aclk__gclk clkgen_rst_cmp_gclk_if.tcu_aclk; | |
| 1128 | tcu_atpg_mode__gclk clkgen_rst_cmp_gclk_if.tcu_atpg_mode; | |
| 1129 | tcu_bclk__gclk clkgen_rst_cmp_gclk_if.tcu_bclk; | |
| 1130 | tcu_clk_stop__gclk clkgen_rst_cmp_gclk_if.tcu_clk_stop; | |
| 1131 | tcu_div_bypass__gclk clkgen_rst_cmp_gclk_if.tcu_div_bypass; | |
| 1132 | tcu_pce_ov__gclk clkgen_rst_cmp_gclk_if.tcu_pce_ov; | |
| 1133 | tcu_wr_inhibit__gclk clkgen_rst_cmp_gclk_if.tcu_wr_inhibit; | |
| 1134 | wmr___gclk clkgen_rst_cmp_gclk_if.wmr_; | |
| 1135 | wmr_protect__gclk clkgen_rst_cmp_gclk_if.wmr_protect; | |
| 1136 | pc_clk__gclk void; | |
| 1137 | pc_clk_sel__gclk void; | |
| 1138 | test_clk__gclk void; | |
| 1139 | test_clk_sel__gclk void; | |
| 1140 | ||
| 1141 | //---l2clk is Vera interface CLOCK--- | |
| 1142 | aclk__l2clk clkgen_rst_cmp_l2clk_if.aclk; | |
| 1143 | aclk_wmr__l2clk clkgen_rst_cmp_l2clk_if.aclk_wmr; | |
| 1144 | array_wr_inhibit__l2clk clkgen_rst_cmp_l2clk_if.array_wr_inhibit; | |
| 1145 | bclk__l2clk clkgen_rst_cmp_l2clk_if.bclk; | |
| 1146 | cmp_slow_sync_en__l2clk clkgen_rst_cmp_l2clk_if.cmp_slow_sync_en; | |
| 1147 | dr_sync_en__l2clk void; | |
| 1148 | io2x_sync_en__l2clk void; | |
| 1149 | l2clk clkgen_rst_cmp_l2clk_if.l2clk; | |
| 1150 | pce_ov__l2clk clkgen_rst_cmp_l2clk_if.pce_ov; | |
| 1151 | por___l2clk clkgen_rst_cmp_l2clk_if.por_; | |
| 1152 | scan_out__l2clk clkgen_rst_cmp_l2clk_if.scan_out; | |
| 1153 | slow_cmp_sync_en__l2clk clkgen_rst_cmp_l2clk_if.slow_cmp_sync_en; | |
| 1154 | wmr___l2clk clkgen_rst_cmp_l2clk_if.wmr_; | |
| 1155 | wmr_protect__l2clk clkgen_rst_cmp_l2clk_if.wmr_protect; | |
| 1156 | } | |
| 1157 | ||
| 1158 | //----- port binding for clkgen_rst_io ----- | |
| 1159 | ||
| 1160 | bind CLKGEN_port clkgen_rst_io_bind { | |
| 1161 | //---gclk is Vera interface CLOCK--- | |
| 1162 | aclk__gclk clkgen_rst_io_gclk_if.aclk; | |
| 1163 | aclk_wmr__gclk clkgen_rst_io_gclk_if.aclk_wmr; | |
| 1164 | array_wr_inhibit__gclk clkgen_rst_io_gclk_if.array_wr_inhibit; | |
| 1165 | bclk__gclk clkgen_rst_io_gclk_if.bclk; | |
| 1166 | ccu_cmp_slow_sync_en__gclk clkgen_rst_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 1167 | ccu_div_ph__gclk clkgen_rst_io_gclk_if.ccu_div_ph; | |
| 1168 | ccu_dr_sync_en__gclk void; | |
| 1169 | ccu_io2x_sync_en__gclk void; | |
| 1170 | ccu_serdes_dtm__gclk clkgen_rst_io_gclk_if.ccu_serdes_dtm; | |
| 1171 | ccu_slow_cmp_sync_en__gclk clkgen_rst_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 1172 | clk_ext__gclk clkgen_rst_io_gclk_if.clk_ext; | |
| 1173 | cluster_arst_l__gclk clkgen_rst_io_gclk_if.cluster_arst_l; | |
| 1174 | cluster_div_en__gclk clkgen_rst_io_gclk_if.cluster_div_en; | |
| 1175 | cmp_slow_sync_en__gclk clkgen_rst_io_gclk_if.cmp_slow_sync_en; | |
| 1176 | dr_sync_en__gclk void; | |
| 1177 | gclk clkgen_rst_io_gclk_if.gclk; | |
| 1178 | io2x_sync_en__gclk void; | |
| 1179 | l2clk__gclk clkgen_rst_io_gclk_if.l2clk; | |
| 1180 | pce_ov__gclk clkgen_rst_io_gclk_if.pce_ov; | |
| 1181 | por___gclk clkgen_rst_io_gclk_if.por_; | |
| 1182 | rst_por___gclk clkgen_rst_io_gclk_if.rst_por_; | |
| 1183 | rst_wmr___gclk clkgen_rst_io_gclk_if.rst_wmr_; | |
| 1184 | rst_wmr_protect__gclk clkgen_rst_io_gclk_if.rst_wmr_protect; | |
| 1185 | scan_en__gclk clkgen_rst_io_gclk_if.scan_en; | |
| 1186 | scan_in__gclk clkgen_rst_io_gclk_if.scan_in; | |
| 1187 | scan_out__gclk clkgen_rst_io_gclk_if.scan_out; | |
| 1188 | slow_cmp_sync_en__gclk clkgen_rst_io_gclk_if.slow_cmp_sync_en; | |
| 1189 | tcu_aclk__gclk clkgen_rst_io_gclk_if.tcu_aclk; | |
| 1190 | tcu_atpg_mode__gclk clkgen_rst_io_gclk_if.tcu_atpg_mode; | |
| 1191 | tcu_bclk__gclk clkgen_rst_io_gclk_if.tcu_bclk; | |
| 1192 | tcu_clk_stop__gclk clkgen_rst_io_gclk_if.tcu_clk_stop; | |
| 1193 | tcu_div_bypass__gclk clkgen_rst_io_gclk_if.tcu_div_bypass; | |
| 1194 | tcu_pce_ov__gclk clkgen_rst_io_gclk_if.tcu_pce_ov; | |
| 1195 | tcu_wr_inhibit__gclk clkgen_rst_io_gclk_if.tcu_wr_inhibit; | |
| 1196 | wmr___gclk clkgen_rst_io_gclk_if.wmr_; | |
| 1197 | wmr_protect__gclk clkgen_rst_io_gclk_if.wmr_protect; | |
| 1198 | pc_clk__gclk void; | |
| 1199 | pc_clk_sel__gclk void; | |
| 1200 | test_clk__gclk void; | |
| 1201 | test_clk_sel__gclk void; | |
| 1202 | ||
| 1203 | //---l2clk is Vera interface CLOCK--- | |
| 1204 | aclk__l2clk clkgen_rst_io_l2clk_if.aclk; | |
| 1205 | aclk_wmr__l2clk clkgen_rst_io_l2clk_if.aclk_wmr; | |
| 1206 | array_wr_inhibit__l2clk clkgen_rst_io_l2clk_if.array_wr_inhibit; | |
| 1207 | bclk__l2clk clkgen_rst_io_l2clk_if.bclk; | |
| 1208 | cmp_slow_sync_en__l2clk clkgen_rst_io_l2clk_if.cmp_slow_sync_en; | |
| 1209 | dr_sync_en__l2clk void; | |
| 1210 | io2x_sync_en__l2clk void; | |
| 1211 | l2clk clkgen_rst_io_l2clk_if.l2clk; | |
| 1212 | pce_ov__l2clk clkgen_rst_io_l2clk_if.pce_ov; | |
| 1213 | por___l2clk clkgen_rst_io_l2clk_if.por_; | |
| 1214 | scan_out__l2clk clkgen_rst_io_l2clk_if.scan_out; | |
| 1215 | slow_cmp_sync_en__l2clk clkgen_rst_io_l2clk_if.slow_cmp_sync_en; | |
| 1216 | wmr___l2clk clkgen_rst_io_l2clk_if.wmr_; | |
| 1217 | wmr_protect__l2clk clkgen_rst_io_l2clk_if.wmr_protect; | |
| 1218 | } | |
| 1219 | ||
| 1220 | //----- port binding for clkgen_tcu_cmp ----- | |
| 1221 | ||
| 1222 | bind CLKGEN_port clkgen_tcu_cmp_bind { | |
| 1223 | //---gclk is Vera interface CLOCK--- | |
| 1224 | aclk__gclk clkgen_tcu_cmp_gclk_if.aclk; | |
| 1225 | aclk_wmr__gclk clkgen_tcu_cmp_gclk_if.aclk_wmr; | |
| 1226 | array_wr_inhibit__gclk clkgen_tcu_cmp_gclk_if.array_wr_inhibit; | |
| 1227 | bclk__gclk clkgen_tcu_cmp_gclk_if.bclk; | |
| 1228 | ccu_cmp_slow_sync_en__gclk clkgen_tcu_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 1229 | ccu_div_ph__gclk clkgen_tcu_cmp_gclk_if.ccu_div_ph; | |
| 1230 | ccu_dr_sync_en__gclk clkgen_tcu_cmp_gclk_if.ccu_dr_sync_en; | |
| 1231 | ccu_io2x_sync_en__gclk clkgen_tcu_cmp_gclk_if.ccu_io2x_sync_en; | |
| 1232 | ccu_serdes_dtm__gclk clkgen_tcu_cmp_gclk_if.ccu_serdes_dtm; | |
| 1233 | ccu_slow_cmp_sync_en__gclk clkgen_tcu_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 1234 | clk_ext__gclk clkgen_tcu_cmp_gclk_if.clk_ext; | |
| 1235 | cluster_arst_l__gclk clkgen_tcu_cmp_gclk_if.cluster_arst_l; | |
| 1236 | cluster_div_en__gclk clkgen_tcu_cmp_gclk_if.cluster_div_en; | |
| 1237 | cmp_slow_sync_en__gclk clkgen_tcu_cmp_gclk_if.cmp_slow_sync_en; | |
| 1238 | dr_sync_en__gclk clkgen_tcu_cmp_gclk_if.dr_sync_en; | |
| 1239 | gclk clkgen_tcu_cmp_gclk_if.gclk; | |
| 1240 | io2x_sync_en__gclk clkgen_tcu_cmp_gclk_if.io2x_sync_en; | |
| 1241 | l2clk__gclk clkgen_tcu_cmp_gclk_if.l2clk; | |
| 1242 | pce_ov__gclk clkgen_tcu_cmp_gclk_if.pce_ov; | |
| 1243 | por___gclk clkgen_tcu_cmp_gclk_if.por_; | |
| 1244 | rst_por___gclk clkgen_tcu_cmp_gclk_if.rst_por_; | |
| 1245 | rst_wmr___gclk clkgen_tcu_cmp_gclk_if.rst_wmr_; | |
| 1246 | rst_wmr_protect__gclk clkgen_tcu_cmp_gclk_if.rst_wmr_protect; | |
| 1247 | scan_en__gclk clkgen_tcu_cmp_gclk_if.scan_en; | |
| 1248 | scan_in__gclk clkgen_tcu_cmp_gclk_if.scan_in; | |
| 1249 | scan_out__gclk clkgen_tcu_cmp_gclk_if.scan_out; | |
| 1250 | slow_cmp_sync_en__gclk clkgen_tcu_cmp_gclk_if.slow_cmp_sync_en; | |
| 1251 | tcu_aclk__gclk clkgen_tcu_cmp_gclk_if.tcu_aclk; | |
| 1252 | tcu_atpg_mode__gclk clkgen_tcu_cmp_gclk_if.tcu_atpg_mode; | |
| 1253 | tcu_bclk__gclk clkgen_tcu_cmp_gclk_if.tcu_bclk; | |
| 1254 | tcu_clk_stop__gclk clkgen_tcu_cmp_gclk_if.tcu_clk_stop; | |
| 1255 | tcu_div_bypass__gclk clkgen_tcu_cmp_gclk_if.tcu_div_bypass; | |
| 1256 | tcu_pce_ov__gclk clkgen_tcu_cmp_gclk_if.tcu_pce_ov; | |
| 1257 | tcu_wr_inhibit__gclk clkgen_tcu_cmp_gclk_if.tcu_wr_inhibit; | |
| 1258 | wmr___gclk clkgen_tcu_cmp_gclk_if.wmr_; | |
| 1259 | wmr_protect__gclk clkgen_tcu_cmp_gclk_if.wmr_protect; | |
| 1260 | pc_clk__gclk void; | |
| 1261 | pc_clk_sel__gclk void; | |
| 1262 | test_clk__gclk void; | |
| 1263 | test_clk_sel__gclk void; | |
| 1264 | ||
| 1265 | //---l2clk is Vera interface CLOCK--- | |
| 1266 | aclk__l2clk clkgen_tcu_cmp_l2clk_if.aclk; | |
| 1267 | aclk_wmr__l2clk clkgen_tcu_cmp_l2clk_if.aclk_wmr; | |
| 1268 | array_wr_inhibit__l2clk clkgen_tcu_cmp_l2clk_if.array_wr_inhibit; | |
| 1269 | bclk__l2clk clkgen_tcu_cmp_l2clk_if.bclk; | |
| 1270 | cmp_slow_sync_en__l2clk clkgen_tcu_cmp_l2clk_if.cmp_slow_sync_en; | |
| 1271 | dr_sync_en__l2clk clkgen_tcu_cmp_l2clk_if.dr_sync_en; | |
| 1272 | io2x_sync_en__l2clk clkgen_tcu_cmp_l2clk_if.io2x_sync_en; | |
| 1273 | l2clk clkgen_tcu_cmp_l2clk_if.l2clk; | |
| 1274 | pce_ov__l2clk clkgen_tcu_cmp_l2clk_if.pce_ov; | |
| 1275 | por___l2clk clkgen_tcu_cmp_l2clk_if.por_; | |
| 1276 | scan_out__l2clk clkgen_tcu_cmp_l2clk_if.scan_out; | |
| 1277 | slow_cmp_sync_en__l2clk clkgen_tcu_cmp_l2clk_if.slow_cmp_sync_en; | |
| 1278 | wmr___l2clk clkgen_tcu_cmp_l2clk_if.wmr_; | |
| 1279 | wmr_protect__l2clk clkgen_tcu_cmp_l2clk_if.wmr_protect; | |
| 1280 | } | |
| 1281 | ||
| 1282 | //----- port binding for clkgen_tcu_io ----- | |
| 1283 | ||
| 1284 | bind CLKGEN_port clkgen_tcu_io_bind { | |
| 1285 | //---gclk is Vera interface CLOCK--- | |
| 1286 | aclk__gclk clkgen_tcu_io_gclk_if.aclk; | |
| 1287 | aclk_wmr__gclk clkgen_tcu_io_gclk_if.aclk_wmr; | |
| 1288 | array_wr_inhibit__gclk clkgen_tcu_io_gclk_if.array_wr_inhibit; | |
| 1289 | bclk__gclk clkgen_tcu_io_gclk_if.bclk; | |
| 1290 | ccu_cmp_slow_sync_en__gclk clkgen_tcu_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 1291 | ccu_div_ph__gclk clkgen_tcu_io_gclk_if.ccu_div_ph; | |
| 1292 | ccu_dr_sync_en__gclk void; | |
| 1293 | ccu_io2x_sync_en__gclk void; | |
| 1294 | ccu_serdes_dtm__gclk clkgen_tcu_io_gclk_if.ccu_serdes_dtm; | |
| 1295 | ccu_slow_cmp_sync_en__gclk clkgen_tcu_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 1296 | clk_ext__gclk clkgen_tcu_io_gclk_if.clk_ext; | |
| 1297 | cluster_arst_l__gclk clkgen_tcu_io_gclk_if.cluster_arst_l; | |
| 1298 | cluster_div_en__gclk clkgen_tcu_io_gclk_if.cluster_div_en; | |
| 1299 | cmp_slow_sync_en__gclk clkgen_tcu_io_gclk_if.cmp_slow_sync_en; | |
| 1300 | dr_sync_en__gclk void; | |
| 1301 | gclk clkgen_tcu_io_gclk_if.gclk; | |
| 1302 | io2x_sync_en__gclk void; | |
| 1303 | l2clk__gclk clkgen_tcu_io_gclk_if.l2clk; | |
| 1304 | pce_ov__gclk clkgen_tcu_io_gclk_if.pce_ov; | |
| 1305 | por___gclk clkgen_tcu_io_gclk_if.por_; | |
| 1306 | rst_por___gclk clkgen_tcu_io_gclk_if.rst_por_; | |
| 1307 | rst_wmr___gclk clkgen_tcu_io_gclk_if.rst_wmr_; | |
| 1308 | rst_wmr_protect__gclk clkgen_tcu_io_gclk_if.rst_wmr_protect; | |
| 1309 | scan_en__gclk clkgen_tcu_io_gclk_if.scan_en; | |
| 1310 | scan_in__gclk clkgen_tcu_io_gclk_if.scan_in; | |
| 1311 | scan_out__gclk clkgen_tcu_io_gclk_if.scan_out; | |
| 1312 | slow_cmp_sync_en__gclk clkgen_tcu_io_gclk_if.slow_cmp_sync_en; | |
| 1313 | tcu_aclk__gclk clkgen_tcu_io_gclk_if.tcu_aclk; | |
| 1314 | tcu_atpg_mode__gclk clkgen_tcu_io_gclk_if.tcu_atpg_mode; | |
| 1315 | tcu_bclk__gclk clkgen_tcu_io_gclk_if.tcu_bclk; | |
| 1316 | tcu_clk_stop__gclk clkgen_tcu_io_gclk_if.tcu_clk_stop; | |
| 1317 | tcu_div_bypass__gclk clkgen_tcu_io_gclk_if.tcu_div_bypass; | |
| 1318 | tcu_pce_ov__gclk clkgen_tcu_io_gclk_if.tcu_pce_ov; | |
| 1319 | tcu_wr_inhibit__gclk clkgen_tcu_io_gclk_if.tcu_wr_inhibit; | |
| 1320 | wmr___gclk clkgen_tcu_io_gclk_if.wmr_; | |
| 1321 | wmr_protect__gclk clkgen_tcu_io_gclk_if.wmr_protect; | |
| 1322 | pc_clk__gclk void; | |
| 1323 | pc_clk_sel__gclk void; | |
| 1324 | test_clk__gclk void; | |
| 1325 | test_clk_sel__gclk void; | |
| 1326 | ||
| 1327 | //---l2clk is Vera interface CLOCK--- | |
| 1328 | aclk__l2clk clkgen_tcu_io_l2clk_if.aclk; | |
| 1329 | aclk_wmr__l2clk clkgen_tcu_io_l2clk_if.aclk_wmr; | |
| 1330 | array_wr_inhibit__l2clk clkgen_tcu_io_l2clk_if.array_wr_inhibit; | |
| 1331 | bclk__l2clk clkgen_tcu_io_l2clk_if.bclk; | |
| 1332 | cmp_slow_sync_en__l2clk clkgen_tcu_io_l2clk_if.cmp_slow_sync_en; | |
| 1333 | dr_sync_en__l2clk void; | |
| 1334 | io2x_sync_en__l2clk void; | |
| 1335 | l2clk clkgen_tcu_io_l2clk_if.l2clk; | |
| 1336 | pce_ov__l2clk clkgen_tcu_io_l2clk_if.pce_ov; | |
| 1337 | por___l2clk clkgen_tcu_io_l2clk_if.por_; | |
| 1338 | scan_out__l2clk clkgen_tcu_io_l2clk_if.scan_out; | |
| 1339 | slow_cmp_sync_en__l2clk clkgen_tcu_io_l2clk_if.slow_cmp_sync_en; | |
| 1340 | wmr___l2clk clkgen_tcu_io_l2clk_if.wmr_; | |
| 1341 | wmr_protect__l2clk clkgen_tcu_io_l2clk_if.wmr_protect; | |
| 1342 | } | |
| 1343 | ||
| 1344 | //####################################################### | |
| 1345 | //### port bindings for blocks not in TCU SAT ### | |
| 1346 | //####################################################### | |
| 1347 | ||
| 1348 | #ifdef FC_BENCH | |
| 1349 | ||
| 1350 | //----- port binding for clkgen_ccx_cmp ----- | |
| 1351 | ||
| 1352 | bind CLKGEN_port clkgen_ccx_cmp_bind { | |
| 1353 | //---gclk is Vera interface CLOCK--- | |
| 1354 | aclk__gclk clkgen_ccx_cmp_gclk_if.aclk; | |
| 1355 | aclk_wmr__gclk clkgen_ccx_cmp_gclk_if.aclk_wmr; | |
| 1356 | array_wr_inhibit__gclk clkgen_ccx_cmp_gclk_if.array_wr_inhibit; | |
| 1357 | bclk__gclk clkgen_ccx_cmp_gclk_if.bclk; | |
| 1358 | ccu_cmp_slow_sync_en__gclk clkgen_ccx_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 1359 | ccu_div_ph__gclk clkgen_ccx_cmp_gclk_if.ccu_div_ph; | |
| 1360 | ccu_dr_sync_en__gclk void; | |
| 1361 | ccu_io2x_sync_en__gclk void; | |
| 1362 | ccu_serdes_dtm__gclk clkgen_ccx_cmp_gclk_if.ccu_serdes_dtm; | |
| 1363 | ccu_slow_cmp_sync_en__gclk clkgen_ccx_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 1364 | clk_ext__gclk clkgen_ccx_cmp_gclk_if.clk_ext; | |
| 1365 | cluster_arst_l__gclk clkgen_ccx_cmp_gclk_if.cluster_arst_l; | |
| 1366 | cluster_div_en__gclk clkgen_ccx_cmp_gclk_if.cluster_div_en; | |
| 1367 | cmp_slow_sync_en__gclk clkgen_ccx_cmp_gclk_if.cmp_slow_sync_en; | |
| 1368 | dr_sync_en__gclk void; | |
| 1369 | gclk clkgen_ccx_cmp_gclk_if.gclk; | |
| 1370 | io2x_sync_en__gclk void; | |
| 1371 | l2clk__gclk clkgen_ccx_cmp_gclk_if.l2clk; | |
| 1372 | pce_ov__gclk clkgen_ccx_cmp_gclk_if.pce_ov; | |
| 1373 | por___gclk clkgen_ccx_cmp_gclk_if.por_; | |
| 1374 | rst_por___gclk clkgen_ccx_cmp_gclk_if.rst_por_; | |
| 1375 | rst_wmr___gclk clkgen_ccx_cmp_gclk_if.rst_wmr_; | |
| 1376 | rst_wmr_protect__gclk clkgen_ccx_cmp_gclk_if.rst_wmr_protect; | |
| 1377 | scan_en__gclk clkgen_ccx_cmp_gclk_if.scan_en; | |
| 1378 | scan_in__gclk clkgen_ccx_cmp_gclk_if.scan_in; | |
| 1379 | scan_out__gclk clkgen_ccx_cmp_gclk_if.scan_out; | |
| 1380 | slow_cmp_sync_en__gclk clkgen_ccx_cmp_gclk_if.slow_cmp_sync_en; | |
| 1381 | tcu_aclk__gclk clkgen_ccx_cmp_gclk_if.tcu_aclk; | |
| 1382 | tcu_atpg_mode__gclk clkgen_ccx_cmp_gclk_if.tcu_atpg_mode; | |
| 1383 | tcu_bclk__gclk clkgen_ccx_cmp_gclk_if.tcu_bclk; | |
| 1384 | tcu_clk_stop__gclk clkgen_ccx_cmp_gclk_if.tcu_clk_stop; | |
| 1385 | tcu_div_bypass__gclk clkgen_ccx_cmp_gclk_if.tcu_div_bypass; | |
| 1386 | tcu_pce_ov__gclk clkgen_ccx_cmp_gclk_if.tcu_pce_ov; | |
| 1387 | tcu_wr_inhibit__gclk clkgen_ccx_cmp_gclk_if.tcu_wr_inhibit; | |
| 1388 | wmr___gclk clkgen_ccx_cmp_gclk_if.wmr_; | |
| 1389 | wmr_protect__gclk clkgen_ccx_cmp_gclk_if.wmr_protect; | |
| 1390 | pc_clk__gclk void; | |
| 1391 | pc_clk_sel__gclk void; | |
| 1392 | test_clk__gclk void; | |
| 1393 | test_clk_sel__gclk void; | |
| 1394 | ||
| 1395 | //---l2clk is Vera interface CLOCK--- | |
| 1396 | aclk__l2clk clkgen_ccx_cmp_l2clk_if.aclk; | |
| 1397 | aclk_wmr__l2clk clkgen_ccx_cmp_l2clk_if.aclk_wmr; | |
| 1398 | array_wr_inhibit__l2clk clkgen_ccx_cmp_l2clk_if.array_wr_inhibit; | |
| 1399 | bclk__l2clk clkgen_ccx_cmp_l2clk_if.bclk; | |
| 1400 | cmp_slow_sync_en__l2clk clkgen_ccx_cmp_l2clk_if.cmp_slow_sync_en; | |
| 1401 | dr_sync_en__l2clk void; | |
| 1402 | io2x_sync_en__l2clk void; | |
| 1403 | l2clk clkgen_ccx_cmp_l2clk_if.l2clk; | |
| 1404 | pce_ov__l2clk clkgen_ccx_cmp_l2clk_if.pce_ov; | |
| 1405 | por___l2clk clkgen_ccx_cmp_l2clk_if.por_; | |
| 1406 | scan_out__l2clk clkgen_ccx_cmp_l2clk_if.scan_out; | |
| 1407 | slow_cmp_sync_en__l2clk clkgen_ccx_cmp_l2clk_if.slow_cmp_sync_en; | |
| 1408 | wmr___l2clk clkgen_ccx_cmp_l2clk_if.wmr_; | |
| 1409 | wmr_protect__l2clk clkgen_ccx_cmp_l2clk_if.wmr_protect; | |
| 1410 | } | |
| 1411 | ||
| 1412 | //----- port binding for clkgen_dmu_io ----- | |
| 1413 | ||
| 1414 | bind CLKGEN_port clkgen_dmu_io_bind { | |
| 1415 | //---gclk is Vera interface CLOCK--- | |
| 1416 | aclk__gclk clkgen_dmu_io_gclk_if.aclk; | |
| 1417 | aclk_wmr__gclk clkgen_dmu_io_gclk_if.aclk_wmr; | |
| 1418 | array_wr_inhibit__gclk clkgen_dmu_io_gclk_if.array_wr_inhibit; | |
| 1419 | bclk__gclk clkgen_dmu_io_gclk_if.bclk; | |
| 1420 | ccu_cmp_slow_sync_en__gclk clkgen_dmu_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 1421 | ccu_div_ph__gclk clkgen_dmu_io_gclk_if.ccu_div_ph; | |
| 1422 | ccu_dr_sync_en__gclk void; | |
| 1423 | ccu_io2x_sync_en__gclk void; | |
| 1424 | ccu_serdes_dtm__gclk clkgen_dmu_io_gclk_if.ccu_serdes_dtm; | |
| 1425 | ccu_slow_cmp_sync_en__gclk clkgen_dmu_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 1426 | clk_ext__gclk clkgen_dmu_io_gclk_if.clk_ext; | |
| 1427 | cluster_arst_l__gclk clkgen_dmu_io_gclk_if.cluster_arst_l; | |
| 1428 | cluster_div_en__gclk clkgen_dmu_io_gclk_if.cluster_div_en; | |
| 1429 | cmp_slow_sync_en__gclk clkgen_dmu_io_gclk_if.cmp_slow_sync_en; | |
| 1430 | dr_sync_en__gclk void; | |
| 1431 | gclk clkgen_dmu_io_gclk_if.gclk; | |
| 1432 | io2x_sync_en__gclk void; | |
| 1433 | l2clk__gclk clkgen_dmu_io_gclk_if.l2clk; | |
| 1434 | pce_ov__gclk clkgen_dmu_io_gclk_if.pce_ov; | |
| 1435 | por___gclk clkgen_dmu_io_gclk_if.por_; | |
| 1436 | rst_por___gclk clkgen_dmu_io_gclk_if.rst_por_; | |
| 1437 | rst_wmr___gclk clkgen_dmu_io_gclk_if.rst_wmr_; | |
| 1438 | rst_wmr_protect__gclk clkgen_dmu_io_gclk_if.rst_wmr_protect; | |
| 1439 | scan_en__gclk clkgen_dmu_io_gclk_if.scan_en; | |
| 1440 | scan_in__gclk clkgen_dmu_io_gclk_if.scan_in; | |
| 1441 | scan_out__gclk clkgen_dmu_io_gclk_if.scan_out; | |
| 1442 | slow_cmp_sync_en__gclk clkgen_dmu_io_gclk_if.slow_cmp_sync_en; | |
| 1443 | tcu_aclk__gclk clkgen_dmu_io_gclk_if.tcu_aclk; | |
| 1444 | tcu_atpg_mode__gclk clkgen_dmu_io_gclk_if.tcu_atpg_mode; | |
| 1445 | tcu_bclk__gclk clkgen_dmu_io_gclk_if.tcu_bclk; | |
| 1446 | tcu_clk_stop__gclk clkgen_dmu_io_gclk_if.tcu_clk_stop; | |
| 1447 | tcu_div_bypass__gclk clkgen_dmu_io_gclk_if.tcu_div_bypass; | |
| 1448 | tcu_pce_ov__gclk clkgen_dmu_io_gclk_if.tcu_pce_ov; | |
| 1449 | tcu_wr_inhibit__gclk clkgen_dmu_io_gclk_if.tcu_wr_inhibit; | |
| 1450 | wmr___gclk clkgen_dmu_io_gclk_if.wmr_; | |
| 1451 | wmr_protect__gclk clkgen_dmu_io_gclk_if.wmr_protect; | |
| 1452 | pc_clk__gclk void; | |
| 1453 | pc_clk_sel__gclk void; | |
| 1454 | test_clk__gclk void; | |
| 1455 | test_clk_sel__gclk void; | |
| 1456 | ||
| 1457 | //---l2clk is Vera interface CLOCK--- | |
| 1458 | aclk__l2clk clkgen_dmu_io_l2clk_if.aclk; | |
| 1459 | aclk_wmr__l2clk clkgen_dmu_io_l2clk_if.aclk_wmr; | |
| 1460 | array_wr_inhibit__l2clk clkgen_dmu_io_l2clk_if.array_wr_inhibit; | |
| 1461 | bclk__l2clk clkgen_dmu_io_l2clk_if.bclk; | |
| 1462 | cmp_slow_sync_en__l2clk clkgen_dmu_io_l2clk_if.cmp_slow_sync_en; | |
| 1463 | dr_sync_en__l2clk void; | |
| 1464 | io2x_sync_en__l2clk void; | |
| 1465 | l2clk clkgen_dmu_io_l2clk_if.l2clk; | |
| 1466 | pce_ov__l2clk clkgen_dmu_io_l2clk_if.pce_ov; | |
| 1467 | por___l2clk clkgen_dmu_io_l2clk_if.por_; | |
| 1468 | scan_out__l2clk clkgen_dmu_io_l2clk_if.scan_out; | |
| 1469 | slow_cmp_sync_en__l2clk clkgen_dmu_io_l2clk_if.slow_cmp_sync_en; | |
| 1470 | wmr___l2clk clkgen_dmu_io_l2clk_if.wmr_; | |
| 1471 | wmr_protect__l2clk clkgen_dmu_io_l2clk_if.wmr_protect; | |
| 1472 | } | |
| 1473 | ||
| 1474 | //----- port binding for clkgen_l2b0_cmp ----- | |
| 1475 | ||
| 1476 | bind CLKGEN_port clkgen_l2b0_cmp_bind { | |
| 1477 | //---gclk is Vera interface CLOCK--- | |
| 1478 | aclk__gclk clkgen_l2b0_cmp_gclk_if.aclk; | |
| 1479 | aclk_wmr__gclk clkgen_l2b0_cmp_gclk_if.aclk_wmr; | |
| 1480 | array_wr_inhibit__gclk clkgen_l2b0_cmp_gclk_if.array_wr_inhibit; | |
| 1481 | bclk__gclk clkgen_l2b0_cmp_gclk_if.bclk; | |
| 1482 | ccu_cmp_slow_sync_en__gclk clkgen_l2b0_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 1483 | ccu_div_ph__gclk clkgen_l2b0_cmp_gclk_if.ccu_div_ph; | |
| 1484 | ccu_dr_sync_en__gclk void; | |
| 1485 | ccu_io2x_sync_en__gclk void; | |
| 1486 | ccu_serdes_dtm__gclk clkgen_l2b0_cmp_gclk_if.ccu_serdes_dtm; | |
| 1487 | ccu_slow_cmp_sync_en__gclk clkgen_l2b0_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 1488 | clk_ext__gclk clkgen_l2b0_cmp_gclk_if.clk_ext; | |
| 1489 | cluster_arst_l__gclk clkgen_l2b0_cmp_gclk_if.cluster_arst_l; | |
| 1490 | cluster_div_en__gclk clkgen_l2b0_cmp_gclk_if.cluster_div_en; | |
| 1491 | cmp_slow_sync_en__gclk clkgen_l2b0_cmp_gclk_if.cmp_slow_sync_en; | |
| 1492 | dr_sync_en__gclk void; | |
| 1493 | gclk clkgen_l2b0_cmp_gclk_if.gclk; | |
| 1494 | io2x_sync_en__gclk void; | |
| 1495 | l2clk__gclk clkgen_l2b0_cmp_gclk_if.l2clk; | |
| 1496 | pce_ov__gclk clkgen_l2b0_cmp_gclk_if.pce_ov; | |
| 1497 | por___gclk clkgen_l2b0_cmp_gclk_if.por_; | |
| 1498 | rst_por___gclk clkgen_l2b0_cmp_gclk_if.rst_por_; | |
| 1499 | rst_wmr___gclk clkgen_l2b0_cmp_gclk_if.rst_wmr_; | |
| 1500 | rst_wmr_protect__gclk clkgen_l2b0_cmp_gclk_if.rst_wmr_protect; | |
| 1501 | scan_en__gclk clkgen_l2b0_cmp_gclk_if.scan_en; | |
| 1502 | scan_in__gclk clkgen_l2b0_cmp_gclk_if.scan_in; | |
| 1503 | scan_out__gclk clkgen_l2b0_cmp_gclk_if.scan_out; | |
| 1504 | slow_cmp_sync_en__gclk clkgen_l2b0_cmp_gclk_if.slow_cmp_sync_en; | |
| 1505 | tcu_aclk__gclk clkgen_l2b0_cmp_gclk_if.tcu_aclk; | |
| 1506 | tcu_atpg_mode__gclk clkgen_l2b0_cmp_gclk_if.tcu_atpg_mode; | |
| 1507 | tcu_bclk__gclk clkgen_l2b0_cmp_gclk_if.tcu_bclk; | |
| 1508 | tcu_clk_stop__gclk clkgen_l2b0_cmp_gclk_if.tcu_clk_stop; | |
| 1509 | tcu_div_bypass__gclk clkgen_l2b0_cmp_gclk_if.tcu_div_bypass; | |
| 1510 | tcu_pce_ov__gclk clkgen_l2b0_cmp_gclk_if.tcu_pce_ov; | |
| 1511 | tcu_wr_inhibit__gclk clkgen_l2b0_cmp_gclk_if.tcu_wr_inhibit; | |
| 1512 | wmr___gclk clkgen_l2b0_cmp_gclk_if.wmr_; | |
| 1513 | wmr_protect__gclk clkgen_l2b0_cmp_gclk_if.wmr_protect; | |
| 1514 | pc_clk__gclk void; | |
| 1515 | pc_clk_sel__gclk void; | |
| 1516 | test_clk__gclk void; | |
| 1517 | test_clk_sel__gclk void; | |
| 1518 | ||
| 1519 | //---l2clk is Vera interface CLOCK--- | |
| 1520 | aclk__l2clk clkgen_l2b0_cmp_l2clk_if.aclk; | |
| 1521 | aclk_wmr__l2clk clkgen_l2b0_cmp_l2clk_if.aclk_wmr; | |
| 1522 | array_wr_inhibit__l2clk clkgen_l2b0_cmp_l2clk_if.array_wr_inhibit; | |
| 1523 | bclk__l2clk clkgen_l2b0_cmp_l2clk_if.bclk; | |
| 1524 | cmp_slow_sync_en__l2clk clkgen_l2b0_cmp_l2clk_if.cmp_slow_sync_en; | |
| 1525 | dr_sync_en__l2clk void; | |
| 1526 | io2x_sync_en__l2clk void; | |
| 1527 | l2clk clkgen_l2b0_cmp_l2clk_if.l2clk; | |
| 1528 | pce_ov__l2clk clkgen_l2b0_cmp_l2clk_if.pce_ov; | |
| 1529 | por___l2clk clkgen_l2b0_cmp_l2clk_if.por_; | |
| 1530 | scan_out__l2clk clkgen_l2b0_cmp_l2clk_if.scan_out; | |
| 1531 | slow_cmp_sync_en__l2clk clkgen_l2b0_cmp_l2clk_if.slow_cmp_sync_en; | |
| 1532 | wmr___l2clk clkgen_l2b0_cmp_l2clk_if.wmr_; | |
| 1533 | wmr_protect__l2clk clkgen_l2b0_cmp_l2clk_if.wmr_protect; | |
| 1534 | } | |
| 1535 | ||
| 1536 | //----- port binding for clkgen_l2b1_cmp ----- | |
| 1537 | ||
| 1538 | bind CLKGEN_port clkgen_l2b1_cmp_bind { | |
| 1539 | //---gclk is Vera interface CLOCK--- | |
| 1540 | aclk__gclk clkgen_l2b1_cmp_gclk_if.aclk; | |
| 1541 | aclk_wmr__gclk clkgen_l2b1_cmp_gclk_if.aclk_wmr; | |
| 1542 | array_wr_inhibit__gclk clkgen_l2b1_cmp_gclk_if.array_wr_inhibit; | |
| 1543 | bclk__gclk clkgen_l2b1_cmp_gclk_if.bclk; | |
| 1544 | ccu_cmp_slow_sync_en__gclk clkgen_l2b1_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 1545 | ccu_div_ph__gclk clkgen_l2b1_cmp_gclk_if.ccu_div_ph; | |
| 1546 | ccu_dr_sync_en__gclk void; | |
| 1547 | ccu_io2x_sync_en__gclk void; | |
| 1548 | ccu_serdes_dtm__gclk clkgen_l2b1_cmp_gclk_if.ccu_serdes_dtm; | |
| 1549 | ccu_slow_cmp_sync_en__gclk clkgen_l2b1_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 1550 | clk_ext__gclk clkgen_l2b1_cmp_gclk_if.clk_ext; | |
| 1551 | cluster_arst_l__gclk clkgen_l2b1_cmp_gclk_if.cluster_arst_l; | |
| 1552 | cluster_div_en__gclk clkgen_l2b1_cmp_gclk_if.cluster_div_en; | |
| 1553 | cmp_slow_sync_en__gclk clkgen_l2b1_cmp_gclk_if.cmp_slow_sync_en; | |
| 1554 | dr_sync_en__gclk void; | |
| 1555 | gclk clkgen_l2b1_cmp_gclk_if.gclk; | |
| 1556 | io2x_sync_en__gclk void; | |
| 1557 | l2clk__gclk clkgen_l2b1_cmp_gclk_if.l2clk; | |
| 1558 | pce_ov__gclk clkgen_l2b1_cmp_gclk_if.pce_ov; | |
| 1559 | por___gclk clkgen_l2b1_cmp_gclk_if.por_; | |
| 1560 | rst_por___gclk clkgen_l2b1_cmp_gclk_if.rst_por_; | |
| 1561 | rst_wmr___gclk clkgen_l2b1_cmp_gclk_if.rst_wmr_; | |
| 1562 | rst_wmr_protect__gclk clkgen_l2b1_cmp_gclk_if.rst_wmr_protect; | |
| 1563 | scan_en__gclk clkgen_l2b1_cmp_gclk_if.scan_en; | |
| 1564 | scan_in__gclk clkgen_l2b1_cmp_gclk_if.scan_in; | |
| 1565 | scan_out__gclk clkgen_l2b1_cmp_gclk_if.scan_out; | |
| 1566 | slow_cmp_sync_en__gclk clkgen_l2b1_cmp_gclk_if.slow_cmp_sync_en; | |
| 1567 | tcu_aclk__gclk clkgen_l2b1_cmp_gclk_if.tcu_aclk; | |
| 1568 | tcu_atpg_mode__gclk clkgen_l2b1_cmp_gclk_if.tcu_atpg_mode; | |
| 1569 | tcu_bclk__gclk clkgen_l2b1_cmp_gclk_if.tcu_bclk; | |
| 1570 | tcu_clk_stop__gclk clkgen_l2b1_cmp_gclk_if.tcu_clk_stop; | |
| 1571 | tcu_div_bypass__gclk clkgen_l2b1_cmp_gclk_if.tcu_div_bypass; | |
| 1572 | tcu_pce_ov__gclk clkgen_l2b1_cmp_gclk_if.tcu_pce_ov; | |
| 1573 | tcu_wr_inhibit__gclk clkgen_l2b1_cmp_gclk_if.tcu_wr_inhibit; | |
| 1574 | wmr___gclk clkgen_l2b1_cmp_gclk_if.wmr_; | |
| 1575 | wmr_protect__gclk clkgen_l2b1_cmp_gclk_if.wmr_protect; | |
| 1576 | pc_clk__gclk void; | |
| 1577 | pc_clk_sel__gclk void; | |
| 1578 | test_clk__gclk void; | |
| 1579 | test_clk_sel__gclk void; | |
| 1580 | ||
| 1581 | //---l2clk is Vera interface CLOCK--- | |
| 1582 | aclk__l2clk clkgen_l2b1_cmp_l2clk_if.aclk; | |
| 1583 | aclk_wmr__l2clk clkgen_l2b1_cmp_l2clk_if.aclk_wmr; | |
| 1584 | array_wr_inhibit__l2clk clkgen_l2b1_cmp_l2clk_if.array_wr_inhibit; | |
| 1585 | bclk__l2clk clkgen_l2b1_cmp_l2clk_if.bclk; | |
| 1586 | cmp_slow_sync_en__l2clk clkgen_l2b1_cmp_l2clk_if.cmp_slow_sync_en; | |
| 1587 | dr_sync_en__l2clk void; | |
| 1588 | io2x_sync_en__l2clk void; | |
| 1589 | l2clk clkgen_l2b1_cmp_l2clk_if.l2clk; | |
| 1590 | pce_ov__l2clk clkgen_l2b1_cmp_l2clk_if.pce_ov; | |
| 1591 | por___l2clk clkgen_l2b1_cmp_l2clk_if.por_; | |
| 1592 | scan_out__l2clk clkgen_l2b1_cmp_l2clk_if.scan_out; | |
| 1593 | slow_cmp_sync_en__l2clk clkgen_l2b1_cmp_l2clk_if.slow_cmp_sync_en; | |
| 1594 | wmr___l2clk clkgen_l2b1_cmp_l2clk_if.wmr_; | |
| 1595 | wmr_protect__l2clk clkgen_l2b1_cmp_l2clk_if.wmr_protect; | |
| 1596 | } | |
| 1597 | ||
| 1598 | //----- port binding for clkgen_l2b2_cmp ----- | |
| 1599 | ||
| 1600 | bind CLKGEN_port clkgen_l2b2_cmp_bind { | |
| 1601 | //---gclk is Vera interface CLOCK--- | |
| 1602 | aclk__gclk clkgen_l2b2_cmp_gclk_if.aclk; | |
| 1603 | aclk_wmr__gclk clkgen_l2b2_cmp_gclk_if.aclk_wmr; | |
| 1604 | array_wr_inhibit__gclk clkgen_l2b2_cmp_gclk_if.array_wr_inhibit; | |
| 1605 | bclk__gclk clkgen_l2b2_cmp_gclk_if.bclk; | |
| 1606 | ccu_cmp_slow_sync_en__gclk clkgen_l2b2_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 1607 | ccu_div_ph__gclk clkgen_l2b2_cmp_gclk_if.ccu_div_ph; | |
| 1608 | ccu_dr_sync_en__gclk void; | |
| 1609 | ccu_io2x_sync_en__gclk void; | |
| 1610 | ccu_serdes_dtm__gclk clkgen_l2b2_cmp_gclk_if.ccu_serdes_dtm; | |
| 1611 | ccu_slow_cmp_sync_en__gclk clkgen_l2b2_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 1612 | clk_ext__gclk clkgen_l2b2_cmp_gclk_if.clk_ext; | |
| 1613 | cluster_arst_l__gclk clkgen_l2b2_cmp_gclk_if.cluster_arst_l; | |
| 1614 | cluster_div_en__gclk clkgen_l2b2_cmp_gclk_if.cluster_div_en; | |
| 1615 | cmp_slow_sync_en__gclk clkgen_l2b2_cmp_gclk_if.cmp_slow_sync_en; | |
| 1616 | dr_sync_en__gclk void; | |
| 1617 | gclk clkgen_l2b2_cmp_gclk_if.gclk; | |
| 1618 | io2x_sync_en__gclk void; | |
| 1619 | l2clk__gclk clkgen_l2b2_cmp_gclk_if.l2clk; | |
| 1620 | pce_ov__gclk clkgen_l2b2_cmp_gclk_if.pce_ov; | |
| 1621 | por___gclk clkgen_l2b2_cmp_gclk_if.por_; | |
| 1622 | rst_por___gclk clkgen_l2b2_cmp_gclk_if.rst_por_; | |
| 1623 | rst_wmr___gclk clkgen_l2b2_cmp_gclk_if.rst_wmr_; | |
| 1624 | rst_wmr_protect__gclk clkgen_l2b2_cmp_gclk_if.rst_wmr_protect; | |
| 1625 | scan_en__gclk clkgen_l2b2_cmp_gclk_if.scan_en; | |
| 1626 | scan_in__gclk clkgen_l2b2_cmp_gclk_if.scan_in; | |
| 1627 | scan_out__gclk clkgen_l2b2_cmp_gclk_if.scan_out; | |
| 1628 | slow_cmp_sync_en__gclk clkgen_l2b2_cmp_gclk_if.slow_cmp_sync_en; | |
| 1629 | tcu_aclk__gclk clkgen_l2b2_cmp_gclk_if.tcu_aclk; | |
| 1630 | tcu_atpg_mode__gclk clkgen_l2b2_cmp_gclk_if.tcu_atpg_mode; | |
| 1631 | tcu_bclk__gclk clkgen_l2b2_cmp_gclk_if.tcu_bclk; | |
| 1632 | tcu_clk_stop__gclk clkgen_l2b2_cmp_gclk_if.tcu_clk_stop; | |
| 1633 | tcu_div_bypass__gclk clkgen_l2b2_cmp_gclk_if.tcu_div_bypass; | |
| 1634 | tcu_pce_ov__gclk clkgen_l2b2_cmp_gclk_if.tcu_pce_ov; | |
| 1635 | tcu_wr_inhibit__gclk clkgen_l2b2_cmp_gclk_if.tcu_wr_inhibit; | |
| 1636 | wmr___gclk clkgen_l2b2_cmp_gclk_if.wmr_; | |
| 1637 | wmr_protect__gclk clkgen_l2b2_cmp_gclk_if.wmr_protect; | |
| 1638 | pc_clk__gclk void; | |
| 1639 | pc_clk_sel__gclk void; | |
| 1640 | test_clk__gclk void; | |
| 1641 | test_clk_sel__gclk void; | |
| 1642 | ||
| 1643 | //---l2clk is Vera interface CLOCK--- | |
| 1644 | aclk__l2clk clkgen_l2b2_cmp_l2clk_if.aclk; | |
| 1645 | aclk_wmr__l2clk clkgen_l2b2_cmp_l2clk_if.aclk_wmr; | |
| 1646 | array_wr_inhibit__l2clk clkgen_l2b2_cmp_l2clk_if.array_wr_inhibit; | |
| 1647 | bclk__l2clk clkgen_l2b2_cmp_l2clk_if.bclk; | |
| 1648 | cmp_slow_sync_en__l2clk clkgen_l2b2_cmp_l2clk_if.cmp_slow_sync_en; | |
| 1649 | dr_sync_en__l2clk void; | |
| 1650 | io2x_sync_en__l2clk void; | |
| 1651 | l2clk clkgen_l2b2_cmp_l2clk_if.l2clk; | |
| 1652 | pce_ov__l2clk clkgen_l2b2_cmp_l2clk_if.pce_ov; | |
| 1653 | por___l2clk clkgen_l2b2_cmp_l2clk_if.por_; | |
| 1654 | scan_out__l2clk clkgen_l2b2_cmp_l2clk_if.scan_out; | |
| 1655 | slow_cmp_sync_en__l2clk clkgen_l2b2_cmp_l2clk_if.slow_cmp_sync_en; | |
| 1656 | wmr___l2clk clkgen_l2b2_cmp_l2clk_if.wmr_; | |
| 1657 | wmr_protect__l2clk clkgen_l2b2_cmp_l2clk_if.wmr_protect; | |
| 1658 | } | |
| 1659 | ||
| 1660 | //----- port binding for clkgen_l2b3_cmp ----- | |
| 1661 | ||
| 1662 | bind CLKGEN_port clkgen_l2b3_cmp_bind { | |
| 1663 | //---gclk is Vera interface CLOCK--- | |
| 1664 | aclk__gclk clkgen_l2b3_cmp_gclk_if.aclk; | |
| 1665 | aclk_wmr__gclk clkgen_l2b3_cmp_gclk_if.aclk_wmr; | |
| 1666 | array_wr_inhibit__gclk clkgen_l2b3_cmp_gclk_if.array_wr_inhibit; | |
| 1667 | bclk__gclk clkgen_l2b3_cmp_gclk_if.bclk; | |
| 1668 | ccu_cmp_slow_sync_en__gclk clkgen_l2b3_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 1669 | ccu_div_ph__gclk clkgen_l2b3_cmp_gclk_if.ccu_div_ph; | |
| 1670 | ccu_dr_sync_en__gclk void; | |
| 1671 | ccu_io2x_sync_en__gclk void; | |
| 1672 | ccu_serdes_dtm__gclk clkgen_l2b3_cmp_gclk_if.ccu_serdes_dtm; | |
| 1673 | ccu_slow_cmp_sync_en__gclk clkgen_l2b3_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 1674 | clk_ext__gclk clkgen_l2b3_cmp_gclk_if.clk_ext; | |
| 1675 | cluster_arst_l__gclk clkgen_l2b3_cmp_gclk_if.cluster_arst_l; | |
| 1676 | cluster_div_en__gclk clkgen_l2b3_cmp_gclk_if.cluster_div_en; | |
| 1677 | cmp_slow_sync_en__gclk clkgen_l2b3_cmp_gclk_if.cmp_slow_sync_en; | |
| 1678 | dr_sync_en__gclk void; | |
| 1679 | gclk clkgen_l2b3_cmp_gclk_if.gclk; | |
| 1680 | io2x_sync_en__gclk void; | |
| 1681 | l2clk__gclk clkgen_l2b3_cmp_gclk_if.l2clk; | |
| 1682 | pce_ov__gclk clkgen_l2b3_cmp_gclk_if.pce_ov; | |
| 1683 | por___gclk clkgen_l2b3_cmp_gclk_if.por_; | |
| 1684 | rst_por___gclk clkgen_l2b3_cmp_gclk_if.rst_por_; | |
| 1685 | rst_wmr___gclk clkgen_l2b3_cmp_gclk_if.rst_wmr_; | |
| 1686 | rst_wmr_protect__gclk clkgen_l2b3_cmp_gclk_if.rst_wmr_protect; | |
| 1687 | scan_en__gclk clkgen_l2b3_cmp_gclk_if.scan_en; | |
| 1688 | scan_in__gclk clkgen_l2b3_cmp_gclk_if.scan_in; | |
| 1689 | scan_out__gclk clkgen_l2b3_cmp_gclk_if.scan_out; | |
| 1690 | slow_cmp_sync_en__gclk clkgen_l2b3_cmp_gclk_if.slow_cmp_sync_en; | |
| 1691 | tcu_aclk__gclk clkgen_l2b3_cmp_gclk_if.tcu_aclk; | |
| 1692 | tcu_atpg_mode__gclk clkgen_l2b3_cmp_gclk_if.tcu_atpg_mode; | |
| 1693 | tcu_bclk__gclk clkgen_l2b3_cmp_gclk_if.tcu_bclk; | |
| 1694 | tcu_clk_stop__gclk clkgen_l2b3_cmp_gclk_if.tcu_clk_stop; | |
| 1695 | tcu_div_bypass__gclk clkgen_l2b3_cmp_gclk_if.tcu_div_bypass; | |
| 1696 | tcu_pce_ov__gclk clkgen_l2b3_cmp_gclk_if.tcu_pce_ov; | |
| 1697 | tcu_wr_inhibit__gclk clkgen_l2b3_cmp_gclk_if.tcu_wr_inhibit; | |
| 1698 | wmr___gclk clkgen_l2b3_cmp_gclk_if.wmr_; | |
| 1699 | wmr_protect__gclk clkgen_l2b3_cmp_gclk_if.wmr_protect; | |
| 1700 | pc_clk__gclk void; | |
| 1701 | pc_clk_sel__gclk void; | |
| 1702 | test_clk__gclk void; | |
| 1703 | test_clk_sel__gclk void; | |
| 1704 | ||
| 1705 | //---l2clk is Vera interface CLOCK--- | |
| 1706 | aclk__l2clk clkgen_l2b3_cmp_l2clk_if.aclk; | |
| 1707 | aclk_wmr__l2clk clkgen_l2b3_cmp_l2clk_if.aclk_wmr; | |
| 1708 | array_wr_inhibit__l2clk clkgen_l2b3_cmp_l2clk_if.array_wr_inhibit; | |
| 1709 | bclk__l2clk clkgen_l2b3_cmp_l2clk_if.bclk; | |
| 1710 | cmp_slow_sync_en__l2clk clkgen_l2b3_cmp_l2clk_if.cmp_slow_sync_en; | |
| 1711 | dr_sync_en__l2clk void; | |
| 1712 | io2x_sync_en__l2clk void; | |
| 1713 | l2clk clkgen_l2b3_cmp_l2clk_if.l2clk; | |
| 1714 | pce_ov__l2clk clkgen_l2b3_cmp_l2clk_if.pce_ov; | |
| 1715 | por___l2clk clkgen_l2b3_cmp_l2clk_if.por_; | |
| 1716 | scan_out__l2clk clkgen_l2b3_cmp_l2clk_if.scan_out; | |
| 1717 | slow_cmp_sync_en__l2clk clkgen_l2b3_cmp_l2clk_if.slow_cmp_sync_en; | |
| 1718 | wmr___l2clk clkgen_l2b3_cmp_l2clk_if.wmr_; | |
| 1719 | wmr_protect__l2clk clkgen_l2b3_cmp_l2clk_if.wmr_protect; | |
| 1720 | } | |
| 1721 | ||
| 1722 | //----- port binding for clkgen_l2b4_cmp ----- | |
| 1723 | ||
| 1724 | bind CLKGEN_port clkgen_l2b4_cmp_bind { | |
| 1725 | //---gclk is Vera interface CLOCK--- | |
| 1726 | aclk__gclk clkgen_l2b4_cmp_gclk_if.aclk; | |
| 1727 | aclk_wmr__gclk clkgen_l2b4_cmp_gclk_if.aclk_wmr; | |
| 1728 | array_wr_inhibit__gclk clkgen_l2b4_cmp_gclk_if.array_wr_inhibit; | |
| 1729 | bclk__gclk clkgen_l2b4_cmp_gclk_if.bclk; | |
| 1730 | ccu_cmp_slow_sync_en__gclk clkgen_l2b4_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 1731 | ccu_div_ph__gclk clkgen_l2b4_cmp_gclk_if.ccu_div_ph; | |
| 1732 | ccu_dr_sync_en__gclk void; | |
| 1733 | ccu_io2x_sync_en__gclk void; | |
| 1734 | ccu_serdes_dtm__gclk clkgen_l2b4_cmp_gclk_if.ccu_serdes_dtm; | |
| 1735 | ccu_slow_cmp_sync_en__gclk clkgen_l2b4_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 1736 | clk_ext__gclk clkgen_l2b4_cmp_gclk_if.clk_ext; | |
| 1737 | cluster_arst_l__gclk clkgen_l2b4_cmp_gclk_if.cluster_arst_l; | |
| 1738 | cluster_div_en__gclk clkgen_l2b4_cmp_gclk_if.cluster_div_en; | |
| 1739 | cmp_slow_sync_en__gclk clkgen_l2b4_cmp_gclk_if.cmp_slow_sync_en; | |
| 1740 | dr_sync_en__gclk void; | |
| 1741 | gclk clkgen_l2b4_cmp_gclk_if.gclk; | |
| 1742 | io2x_sync_en__gclk void; | |
| 1743 | l2clk__gclk clkgen_l2b4_cmp_gclk_if.l2clk; | |
| 1744 | pce_ov__gclk clkgen_l2b4_cmp_gclk_if.pce_ov; | |
| 1745 | por___gclk clkgen_l2b4_cmp_gclk_if.por_; | |
| 1746 | rst_por___gclk clkgen_l2b4_cmp_gclk_if.rst_por_; | |
| 1747 | rst_wmr___gclk clkgen_l2b4_cmp_gclk_if.rst_wmr_; | |
| 1748 | rst_wmr_protect__gclk clkgen_l2b4_cmp_gclk_if.rst_wmr_protect; | |
| 1749 | scan_en__gclk clkgen_l2b4_cmp_gclk_if.scan_en; | |
| 1750 | scan_in__gclk clkgen_l2b4_cmp_gclk_if.scan_in; | |
| 1751 | scan_out__gclk clkgen_l2b4_cmp_gclk_if.scan_out; | |
| 1752 | slow_cmp_sync_en__gclk clkgen_l2b4_cmp_gclk_if.slow_cmp_sync_en; | |
| 1753 | tcu_aclk__gclk clkgen_l2b4_cmp_gclk_if.tcu_aclk; | |
| 1754 | tcu_atpg_mode__gclk clkgen_l2b4_cmp_gclk_if.tcu_atpg_mode; | |
| 1755 | tcu_bclk__gclk clkgen_l2b4_cmp_gclk_if.tcu_bclk; | |
| 1756 | tcu_clk_stop__gclk clkgen_l2b4_cmp_gclk_if.tcu_clk_stop; | |
| 1757 | tcu_div_bypass__gclk clkgen_l2b4_cmp_gclk_if.tcu_div_bypass; | |
| 1758 | tcu_pce_ov__gclk clkgen_l2b4_cmp_gclk_if.tcu_pce_ov; | |
| 1759 | tcu_wr_inhibit__gclk clkgen_l2b4_cmp_gclk_if.tcu_wr_inhibit; | |
| 1760 | wmr___gclk clkgen_l2b4_cmp_gclk_if.wmr_; | |
| 1761 | wmr_protect__gclk clkgen_l2b4_cmp_gclk_if.wmr_protect; | |
| 1762 | pc_clk__gclk void; | |
| 1763 | pc_clk_sel__gclk void; | |
| 1764 | test_clk__gclk void; | |
| 1765 | test_clk_sel__gclk void; | |
| 1766 | ||
| 1767 | //---l2clk is Vera interface CLOCK--- | |
| 1768 | aclk__l2clk clkgen_l2b4_cmp_l2clk_if.aclk; | |
| 1769 | aclk_wmr__l2clk clkgen_l2b4_cmp_l2clk_if.aclk_wmr; | |
| 1770 | array_wr_inhibit__l2clk clkgen_l2b4_cmp_l2clk_if.array_wr_inhibit; | |
| 1771 | bclk__l2clk clkgen_l2b4_cmp_l2clk_if.bclk; | |
| 1772 | cmp_slow_sync_en__l2clk clkgen_l2b4_cmp_l2clk_if.cmp_slow_sync_en; | |
| 1773 | dr_sync_en__l2clk void; | |
| 1774 | io2x_sync_en__l2clk void; | |
| 1775 | l2clk clkgen_l2b4_cmp_l2clk_if.l2clk; | |
| 1776 | pce_ov__l2clk clkgen_l2b4_cmp_l2clk_if.pce_ov; | |
| 1777 | por___l2clk clkgen_l2b4_cmp_l2clk_if.por_; | |
| 1778 | scan_out__l2clk clkgen_l2b4_cmp_l2clk_if.scan_out; | |
| 1779 | slow_cmp_sync_en__l2clk clkgen_l2b4_cmp_l2clk_if.slow_cmp_sync_en; | |
| 1780 | wmr___l2clk clkgen_l2b4_cmp_l2clk_if.wmr_; | |
| 1781 | wmr_protect__l2clk clkgen_l2b4_cmp_l2clk_if.wmr_protect; | |
| 1782 | } | |
| 1783 | ||
| 1784 | //----- port binding for clkgen_l2b5_cmp ----- | |
| 1785 | ||
| 1786 | bind CLKGEN_port clkgen_l2b5_cmp_bind { | |
| 1787 | //---gclk is Vera interface CLOCK--- | |
| 1788 | aclk__gclk clkgen_l2b5_cmp_gclk_if.aclk; | |
| 1789 | aclk_wmr__gclk clkgen_l2b5_cmp_gclk_if.aclk_wmr; | |
| 1790 | array_wr_inhibit__gclk clkgen_l2b5_cmp_gclk_if.array_wr_inhibit; | |
| 1791 | bclk__gclk clkgen_l2b5_cmp_gclk_if.bclk; | |
| 1792 | ccu_cmp_slow_sync_en__gclk clkgen_l2b5_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 1793 | ccu_div_ph__gclk clkgen_l2b5_cmp_gclk_if.ccu_div_ph; | |
| 1794 | ccu_dr_sync_en__gclk void; | |
| 1795 | ccu_io2x_sync_en__gclk void; | |
| 1796 | ccu_serdes_dtm__gclk clkgen_l2b5_cmp_gclk_if.ccu_serdes_dtm; | |
| 1797 | ccu_slow_cmp_sync_en__gclk clkgen_l2b5_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 1798 | clk_ext__gclk clkgen_l2b5_cmp_gclk_if.clk_ext; | |
| 1799 | cluster_arst_l__gclk clkgen_l2b5_cmp_gclk_if.cluster_arst_l; | |
| 1800 | cluster_div_en__gclk clkgen_l2b5_cmp_gclk_if.cluster_div_en; | |
| 1801 | cmp_slow_sync_en__gclk clkgen_l2b5_cmp_gclk_if.cmp_slow_sync_en; | |
| 1802 | dr_sync_en__gclk void; | |
| 1803 | gclk clkgen_l2b5_cmp_gclk_if.gclk; | |
| 1804 | io2x_sync_en__gclk void; | |
| 1805 | l2clk__gclk clkgen_l2b5_cmp_gclk_if.l2clk; | |
| 1806 | pce_ov__gclk clkgen_l2b5_cmp_gclk_if.pce_ov; | |
| 1807 | por___gclk clkgen_l2b5_cmp_gclk_if.por_; | |
| 1808 | rst_por___gclk clkgen_l2b5_cmp_gclk_if.rst_por_; | |
| 1809 | rst_wmr___gclk clkgen_l2b5_cmp_gclk_if.rst_wmr_; | |
| 1810 | rst_wmr_protect__gclk clkgen_l2b5_cmp_gclk_if.rst_wmr_protect; | |
| 1811 | scan_en__gclk clkgen_l2b5_cmp_gclk_if.scan_en; | |
| 1812 | scan_in__gclk clkgen_l2b5_cmp_gclk_if.scan_in; | |
| 1813 | scan_out__gclk clkgen_l2b5_cmp_gclk_if.scan_out; | |
| 1814 | slow_cmp_sync_en__gclk clkgen_l2b5_cmp_gclk_if.slow_cmp_sync_en; | |
| 1815 | tcu_aclk__gclk clkgen_l2b5_cmp_gclk_if.tcu_aclk; | |
| 1816 | tcu_atpg_mode__gclk clkgen_l2b5_cmp_gclk_if.tcu_atpg_mode; | |
| 1817 | tcu_bclk__gclk clkgen_l2b5_cmp_gclk_if.tcu_bclk; | |
| 1818 | tcu_clk_stop__gclk clkgen_l2b5_cmp_gclk_if.tcu_clk_stop; | |
| 1819 | tcu_div_bypass__gclk clkgen_l2b5_cmp_gclk_if.tcu_div_bypass; | |
| 1820 | tcu_pce_ov__gclk clkgen_l2b5_cmp_gclk_if.tcu_pce_ov; | |
| 1821 | tcu_wr_inhibit__gclk clkgen_l2b5_cmp_gclk_if.tcu_wr_inhibit; | |
| 1822 | wmr___gclk clkgen_l2b5_cmp_gclk_if.wmr_; | |
| 1823 | wmr_protect__gclk clkgen_l2b5_cmp_gclk_if.wmr_protect; | |
| 1824 | pc_clk__gclk void; | |
| 1825 | pc_clk_sel__gclk void; | |
| 1826 | test_clk__gclk void; | |
| 1827 | test_clk_sel__gclk void; | |
| 1828 | ||
| 1829 | //---l2clk is Vera interface CLOCK--- | |
| 1830 | aclk__l2clk clkgen_l2b5_cmp_l2clk_if.aclk; | |
| 1831 | aclk_wmr__l2clk clkgen_l2b5_cmp_l2clk_if.aclk_wmr; | |
| 1832 | array_wr_inhibit__l2clk clkgen_l2b5_cmp_l2clk_if.array_wr_inhibit; | |
| 1833 | bclk__l2clk clkgen_l2b5_cmp_l2clk_if.bclk; | |
| 1834 | cmp_slow_sync_en__l2clk clkgen_l2b5_cmp_l2clk_if.cmp_slow_sync_en; | |
| 1835 | dr_sync_en__l2clk void; | |
| 1836 | io2x_sync_en__l2clk void; | |
| 1837 | l2clk clkgen_l2b5_cmp_l2clk_if.l2clk; | |
| 1838 | pce_ov__l2clk clkgen_l2b5_cmp_l2clk_if.pce_ov; | |
| 1839 | por___l2clk clkgen_l2b5_cmp_l2clk_if.por_; | |
| 1840 | scan_out__l2clk clkgen_l2b5_cmp_l2clk_if.scan_out; | |
| 1841 | slow_cmp_sync_en__l2clk clkgen_l2b5_cmp_l2clk_if.slow_cmp_sync_en; | |
| 1842 | wmr___l2clk clkgen_l2b5_cmp_l2clk_if.wmr_; | |
| 1843 | wmr_protect__l2clk clkgen_l2b5_cmp_l2clk_if.wmr_protect; | |
| 1844 | } | |
| 1845 | ||
| 1846 | //----- port binding for clkgen_l2b6_cmp ----- | |
| 1847 | ||
| 1848 | bind CLKGEN_port clkgen_l2b6_cmp_bind { | |
| 1849 | //---gclk is Vera interface CLOCK--- | |
| 1850 | aclk__gclk clkgen_l2b6_cmp_gclk_if.aclk; | |
| 1851 | aclk_wmr__gclk clkgen_l2b6_cmp_gclk_if.aclk_wmr; | |
| 1852 | array_wr_inhibit__gclk clkgen_l2b6_cmp_gclk_if.array_wr_inhibit; | |
| 1853 | bclk__gclk clkgen_l2b6_cmp_gclk_if.bclk; | |
| 1854 | ccu_cmp_slow_sync_en__gclk clkgen_l2b6_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 1855 | ccu_div_ph__gclk clkgen_l2b6_cmp_gclk_if.ccu_div_ph; | |
| 1856 | ccu_dr_sync_en__gclk void; | |
| 1857 | ccu_io2x_sync_en__gclk void; | |
| 1858 | ccu_serdes_dtm__gclk clkgen_l2b6_cmp_gclk_if.ccu_serdes_dtm; | |
| 1859 | ccu_slow_cmp_sync_en__gclk clkgen_l2b6_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 1860 | clk_ext__gclk clkgen_l2b6_cmp_gclk_if.clk_ext; | |
| 1861 | cluster_arst_l__gclk clkgen_l2b6_cmp_gclk_if.cluster_arst_l; | |
| 1862 | cluster_div_en__gclk clkgen_l2b6_cmp_gclk_if.cluster_div_en; | |
| 1863 | cmp_slow_sync_en__gclk clkgen_l2b6_cmp_gclk_if.cmp_slow_sync_en; | |
| 1864 | dr_sync_en__gclk void; | |
| 1865 | gclk clkgen_l2b6_cmp_gclk_if.gclk; | |
| 1866 | io2x_sync_en__gclk void; | |
| 1867 | l2clk__gclk clkgen_l2b6_cmp_gclk_if.l2clk; | |
| 1868 | pce_ov__gclk clkgen_l2b6_cmp_gclk_if.pce_ov; | |
| 1869 | por___gclk clkgen_l2b6_cmp_gclk_if.por_; | |
| 1870 | rst_por___gclk clkgen_l2b6_cmp_gclk_if.rst_por_; | |
| 1871 | rst_wmr___gclk clkgen_l2b6_cmp_gclk_if.rst_wmr_; | |
| 1872 | rst_wmr_protect__gclk clkgen_l2b6_cmp_gclk_if.rst_wmr_protect; | |
| 1873 | scan_en__gclk clkgen_l2b6_cmp_gclk_if.scan_en; | |
| 1874 | scan_in__gclk clkgen_l2b6_cmp_gclk_if.scan_in; | |
| 1875 | scan_out__gclk clkgen_l2b6_cmp_gclk_if.scan_out; | |
| 1876 | slow_cmp_sync_en__gclk clkgen_l2b6_cmp_gclk_if.slow_cmp_sync_en; | |
| 1877 | tcu_aclk__gclk clkgen_l2b6_cmp_gclk_if.tcu_aclk; | |
| 1878 | tcu_atpg_mode__gclk clkgen_l2b6_cmp_gclk_if.tcu_atpg_mode; | |
| 1879 | tcu_bclk__gclk clkgen_l2b6_cmp_gclk_if.tcu_bclk; | |
| 1880 | tcu_clk_stop__gclk clkgen_l2b6_cmp_gclk_if.tcu_clk_stop; | |
| 1881 | tcu_div_bypass__gclk clkgen_l2b6_cmp_gclk_if.tcu_div_bypass; | |
| 1882 | tcu_pce_ov__gclk clkgen_l2b6_cmp_gclk_if.tcu_pce_ov; | |
| 1883 | tcu_wr_inhibit__gclk clkgen_l2b6_cmp_gclk_if.tcu_wr_inhibit; | |
| 1884 | wmr___gclk clkgen_l2b6_cmp_gclk_if.wmr_; | |
| 1885 | wmr_protect__gclk clkgen_l2b6_cmp_gclk_if.wmr_protect; | |
| 1886 | pc_clk__gclk void; | |
| 1887 | pc_clk_sel__gclk void; | |
| 1888 | test_clk__gclk void; | |
| 1889 | test_clk_sel__gclk void; | |
| 1890 | ||
| 1891 | //---l2clk is Vera interface CLOCK--- | |
| 1892 | aclk__l2clk clkgen_l2b6_cmp_l2clk_if.aclk; | |
| 1893 | aclk_wmr__l2clk clkgen_l2b6_cmp_l2clk_if.aclk_wmr; | |
| 1894 | array_wr_inhibit__l2clk clkgen_l2b6_cmp_l2clk_if.array_wr_inhibit; | |
| 1895 | bclk__l2clk clkgen_l2b6_cmp_l2clk_if.bclk; | |
| 1896 | cmp_slow_sync_en__l2clk clkgen_l2b6_cmp_l2clk_if.cmp_slow_sync_en; | |
| 1897 | dr_sync_en__l2clk void; | |
| 1898 | io2x_sync_en__l2clk void; | |
| 1899 | l2clk clkgen_l2b6_cmp_l2clk_if.l2clk; | |
| 1900 | pce_ov__l2clk clkgen_l2b6_cmp_l2clk_if.pce_ov; | |
| 1901 | por___l2clk clkgen_l2b6_cmp_l2clk_if.por_; | |
| 1902 | scan_out__l2clk clkgen_l2b6_cmp_l2clk_if.scan_out; | |
| 1903 | slow_cmp_sync_en__l2clk clkgen_l2b6_cmp_l2clk_if.slow_cmp_sync_en; | |
| 1904 | wmr___l2clk clkgen_l2b6_cmp_l2clk_if.wmr_; | |
| 1905 | wmr_protect__l2clk clkgen_l2b6_cmp_l2clk_if.wmr_protect; | |
| 1906 | } | |
| 1907 | ||
| 1908 | //----- port binding for clkgen_l2b7_cmp ----- | |
| 1909 | ||
| 1910 | bind CLKGEN_port clkgen_l2b7_cmp_bind { | |
| 1911 | //---gclk is Vera interface CLOCK--- | |
| 1912 | aclk__gclk clkgen_l2b7_cmp_gclk_if.aclk; | |
| 1913 | aclk_wmr__gclk clkgen_l2b7_cmp_gclk_if.aclk_wmr; | |
| 1914 | array_wr_inhibit__gclk clkgen_l2b7_cmp_gclk_if.array_wr_inhibit; | |
| 1915 | bclk__gclk clkgen_l2b7_cmp_gclk_if.bclk; | |
| 1916 | ccu_cmp_slow_sync_en__gclk clkgen_l2b7_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 1917 | ccu_div_ph__gclk clkgen_l2b7_cmp_gclk_if.ccu_div_ph; | |
| 1918 | ccu_dr_sync_en__gclk void; | |
| 1919 | ccu_io2x_sync_en__gclk void; | |
| 1920 | ccu_serdes_dtm__gclk clkgen_l2b7_cmp_gclk_if.ccu_serdes_dtm; | |
| 1921 | ccu_slow_cmp_sync_en__gclk clkgen_l2b7_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 1922 | clk_ext__gclk clkgen_l2b7_cmp_gclk_if.clk_ext; | |
| 1923 | cluster_arst_l__gclk clkgen_l2b7_cmp_gclk_if.cluster_arst_l; | |
| 1924 | cluster_div_en__gclk clkgen_l2b7_cmp_gclk_if.cluster_div_en; | |
| 1925 | cmp_slow_sync_en__gclk clkgen_l2b7_cmp_gclk_if.cmp_slow_sync_en; | |
| 1926 | dr_sync_en__gclk void; | |
| 1927 | gclk clkgen_l2b7_cmp_gclk_if.gclk; | |
| 1928 | io2x_sync_en__gclk void; | |
| 1929 | l2clk__gclk clkgen_l2b7_cmp_gclk_if.l2clk; | |
| 1930 | pce_ov__gclk clkgen_l2b7_cmp_gclk_if.pce_ov; | |
| 1931 | por___gclk clkgen_l2b7_cmp_gclk_if.por_; | |
| 1932 | rst_por___gclk clkgen_l2b7_cmp_gclk_if.rst_por_; | |
| 1933 | rst_wmr___gclk clkgen_l2b7_cmp_gclk_if.rst_wmr_; | |
| 1934 | rst_wmr_protect__gclk clkgen_l2b7_cmp_gclk_if.rst_wmr_protect; | |
| 1935 | scan_en__gclk clkgen_l2b7_cmp_gclk_if.scan_en; | |
| 1936 | scan_in__gclk clkgen_l2b7_cmp_gclk_if.scan_in; | |
| 1937 | scan_out__gclk clkgen_l2b7_cmp_gclk_if.scan_out; | |
| 1938 | slow_cmp_sync_en__gclk clkgen_l2b7_cmp_gclk_if.slow_cmp_sync_en; | |
| 1939 | tcu_aclk__gclk clkgen_l2b7_cmp_gclk_if.tcu_aclk; | |
| 1940 | tcu_atpg_mode__gclk clkgen_l2b7_cmp_gclk_if.tcu_atpg_mode; | |
| 1941 | tcu_bclk__gclk clkgen_l2b7_cmp_gclk_if.tcu_bclk; | |
| 1942 | tcu_clk_stop__gclk clkgen_l2b7_cmp_gclk_if.tcu_clk_stop; | |
| 1943 | tcu_div_bypass__gclk clkgen_l2b7_cmp_gclk_if.tcu_div_bypass; | |
| 1944 | tcu_pce_ov__gclk clkgen_l2b7_cmp_gclk_if.tcu_pce_ov; | |
| 1945 | tcu_wr_inhibit__gclk clkgen_l2b7_cmp_gclk_if.tcu_wr_inhibit; | |
| 1946 | wmr___gclk clkgen_l2b7_cmp_gclk_if.wmr_; | |
| 1947 | wmr_protect__gclk clkgen_l2b7_cmp_gclk_if.wmr_protect; | |
| 1948 | pc_clk__gclk void; | |
| 1949 | pc_clk_sel__gclk void; | |
| 1950 | test_clk__gclk void; | |
| 1951 | test_clk_sel__gclk void; | |
| 1952 | ||
| 1953 | //---l2clk is Vera interface CLOCK--- | |
| 1954 | aclk__l2clk clkgen_l2b7_cmp_l2clk_if.aclk; | |
| 1955 | aclk_wmr__l2clk clkgen_l2b7_cmp_l2clk_if.aclk_wmr; | |
| 1956 | array_wr_inhibit__l2clk clkgen_l2b7_cmp_l2clk_if.array_wr_inhibit; | |
| 1957 | bclk__l2clk clkgen_l2b7_cmp_l2clk_if.bclk; | |
| 1958 | cmp_slow_sync_en__l2clk clkgen_l2b7_cmp_l2clk_if.cmp_slow_sync_en; | |
| 1959 | dr_sync_en__l2clk void; | |
| 1960 | io2x_sync_en__l2clk void; | |
| 1961 | l2clk clkgen_l2b7_cmp_l2clk_if.l2clk; | |
| 1962 | pce_ov__l2clk clkgen_l2b7_cmp_l2clk_if.pce_ov; | |
| 1963 | por___l2clk clkgen_l2b7_cmp_l2clk_if.por_; | |
| 1964 | scan_out__l2clk clkgen_l2b7_cmp_l2clk_if.scan_out; | |
| 1965 | slow_cmp_sync_en__l2clk clkgen_l2b7_cmp_l2clk_if.slow_cmp_sync_en; | |
| 1966 | wmr___l2clk clkgen_l2b7_cmp_l2clk_if.wmr_; | |
| 1967 | wmr_protect__l2clk clkgen_l2b7_cmp_l2clk_if.wmr_protect; | |
| 1968 | } | |
| 1969 | ||
| 1970 | //----- port binding for clkgen_l2d0_cmp ----- | |
| 1971 | ||
| 1972 | bind CLKGEN_port clkgen_l2d0_cmp_bind { | |
| 1973 | //---gclk is Vera interface CLOCK--- | |
| 1974 | aclk__gclk clkgen_l2d0_cmp_gclk_if.aclk; | |
| 1975 | aclk_wmr__gclk clkgen_l2d0_cmp_gclk_if.aclk_wmr; | |
| 1976 | array_wr_inhibit__gclk clkgen_l2d0_cmp_gclk_if.array_wr_inhibit; | |
| 1977 | bclk__gclk clkgen_l2d0_cmp_gclk_if.bclk; | |
| 1978 | ccu_cmp_slow_sync_en__gclk clkgen_l2d0_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 1979 | ccu_div_ph__gclk clkgen_l2d0_cmp_gclk_if.ccu_div_ph; | |
| 1980 | ccu_dr_sync_en__gclk void; | |
| 1981 | ccu_io2x_sync_en__gclk void; | |
| 1982 | ccu_serdes_dtm__gclk void; | |
| 1983 | ccu_slow_cmp_sync_en__gclk clkgen_l2d0_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 1984 | clk_ext__gclk void; | |
| 1985 | cluster_arst_l__gclk clkgen_l2d0_cmp_gclk_if.cluster_arst_l; | |
| 1986 | cluster_div_en__gclk clkgen_l2d0_cmp_gclk_if.cluster_div_en; | |
| 1987 | cmp_slow_sync_en__gclk clkgen_l2d0_cmp_gclk_if.cmp_slow_sync_en; | |
| 1988 | dr_sync_en__gclk void; | |
| 1989 | gclk clkgen_l2d0_cmp_gclk_if.gclk; | |
| 1990 | io2x_sync_en__gclk void; | |
| 1991 | l2clk__gclk clkgen_l2d0_cmp_gclk_if.l2clk; | |
| 1992 | pce_ov__gclk clkgen_l2d0_cmp_gclk_if.pce_ov; | |
| 1993 | por___gclk clkgen_l2d0_cmp_gclk_if.por_; | |
| 1994 | rst_por___gclk clkgen_l2d0_cmp_gclk_if.rst_por_; | |
| 1995 | rst_wmr___gclk clkgen_l2d0_cmp_gclk_if.rst_wmr_; | |
| 1996 | rst_wmr_protect__gclk clkgen_l2d0_cmp_gclk_if.rst_wmr_protect; | |
| 1997 | scan_en__gclk clkgen_l2d0_cmp_gclk_if.scan_en; | |
| 1998 | scan_in__gclk clkgen_l2d0_cmp_gclk_if.scan_in; | |
| 1999 | scan_out__gclk clkgen_l2d0_cmp_gclk_if.scan_out; | |
| 2000 | slow_cmp_sync_en__gclk clkgen_l2d0_cmp_gclk_if.slow_cmp_sync_en; | |
| 2001 | tcu_aclk__gclk clkgen_l2d0_cmp_gclk_if.tcu_aclk; | |
| 2002 | tcu_atpg_mode__gclk clkgen_l2d0_cmp_gclk_if.tcu_atpg_mode; | |
| 2003 | tcu_bclk__gclk clkgen_l2d0_cmp_gclk_if.tcu_bclk; | |
| 2004 | tcu_clk_stop__gclk clkgen_l2d0_cmp_gclk_if.tcu_clk_stop; | |
| 2005 | tcu_div_bypass__gclk clkgen_l2d0_cmp_gclk_if.tcu_div_bypass; | |
| 2006 | tcu_pce_ov__gclk clkgen_l2d0_cmp_gclk_if.tcu_pce_ov; | |
| 2007 | tcu_wr_inhibit__gclk clkgen_l2d0_cmp_gclk_if.tcu_wr_inhibit; | |
| 2008 | wmr___gclk clkgen_l2d0_cmp_gclk_if.wmr_; | |
| 2009 | wmr_protect__gclk clkgen_l2d0_cmp_gclk_if.wmr_protect; | |
| 2010 | pc_clk__gclk void; | |
| 2011 | pc_clk_sel__gclk void; | |
| 2012 | test_clk__gclk void; | |
| 2013 | test_clk_sel__gclk void; | |
| 2014 | ||
| 2015 | //---l2clk is Vera interface CLOCK--- | |
| 2016 | aclk__l2clk clkgen_l2d0_cmp_l2clk_if.aclk; | |
| 2017 | aclk_wmr__l2clk clkgen_l2d0_cmp_l2clk_if.aclk_wmr; | |
| 2018 | array_wr_inhibit__l2clk clkgen_l2d0_cmp_l2clk_if.array_wr_inhibit; | |
| 2019 | bclk__l2clk clkgen_l2d0_cmp_l2clk_if.bclk; | |
| 2020 | cmp_slow_sync_en__l2clk clkgen_l2d0_cmp_l2clk_if.cmp_slow_sync_en; | |
| 2021 | dr_sync_en__l2clk void; | |
| 2022 | io2x_sync_en__l2clk void; | |
| 2023 | l2clk clkgen_l2d0_cmp_l2clk_if.l2clk; | |
| 2024 | pce_ov__l2clk clkgen_l2d0_cmp_l2clk_if.pce_ov; | |
| 2025 | por___l2clk clkgen_l2d0_cmp_l2clk_if.por_; | |
| 2026 | scan_out__l2clk clkgen_l2d0_cmp_l2clk_if.scan_out; | |
| 2027 | slow_cmp_sync_en__l2clk clkgen_l2d0_cmp_l2clk_if.slow_cmp_sync_en; | |
| 2028 | wmr___l2clk clkgen_l2d0_cmp_l2clk_if.wmr_; | |
| 2029 | wmr_protect__l2clk clkgen_l2d0_cmp_l2clk_if.wmr_protect; | |
| 2030 | } | |
| 2031 | ||
| 2032 | //----- port binding for clkgen_l2d1_cmp ----- | |
| 2033 | ||
| 2034 | bind CLKGEN_port clkgen_l2d1_cmp_bind { | |
| 2035 | //---gclk is Vera interface CLOCK--- | |
| 2036 | aclk__gclk clkgen_l2d1_cmp_gclk_if.aclk; | |
| 2037 | aclk_wmr__gclk clkgen_l2d1_cmp_gclk_if.aclk_wmr; | |
| 2038 | array_wr_inhibit__gclk clkgen_l2d1_cmp_gclk_if.array_wr_inhibit; | |
| 2039 | bclk__gclk clkgen_l2d1_cmp_gclk_if.bclk; | |
| 2040 | ccu_cmp_slow_sync_en__gclk clkgen_l2d1_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 2041 | ccu_div_ph__gclk clkgen_l2d1_cmp_gclk_if.ccu_div_ph; | |
| 2042 | ccu_dr_sync_en__gclk void; | |
| 2043 | ccu_io2x_sync_en__gclk void; | |
| 2044 | ccu_serdes_dtm__gclk void; | |
| 2045 | ccu_slow_cmp_sync_en__gclk clkgen_l2d1_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 2046 | clk_ext__gclk void; | |
| 2047 | cluster_arst_l__gclk clkgen_l2d1_cmp_gclk_if.cluster_arst_l; | |
| 2048 | cluster_div_en__gclk clkgen_l2d1_cmp_gclk_if.cluster_div_en; | |
| 2049 | cmp_slow_sync_en__gclk clkgen_l2d1_cmp_gclk_if.cmp_slow_sync_en; | |
| 2050 | dr_sync_en__gclk void; | |
| 2051 | gclk clkgen_l2d1_cmp_gclk_if.gclk; | |
| 2052 | io2x_sync_en__gclk void; | |
| 2053 | l2clk__gclk clkgen_l2d1_cmp_gclk_if.l2clk; | |
| 2054 | pce_ov__gclk clkgen_l2d1_cmp_gclk_if.pce_ov; | |
| 2055 | por___gclk clkgen_l2d1_cmp_gclk_if.por_; | |
| 2056 | rst_por___gclk clkgen_l2d1_cmp_gclk_if.rst_por_; | |
| 2057 | rst_wmr___gclk clkgen_l2d1_cmp_gclk_if.rst_wmr_; | |
| 2058 | rst_wmr_protect__gclk clkgen_l2d1_cmp_gclk_if.rst_wmr_protect; | |
| 2059 | scan_en__gclk clkgen_l2d1_cmp_gclk_if.scan_en; | |
| 2060 | scan_in__gclk clkgen_l2d1_cmp_gclk_if.scan_in; | |
| 2061 | scan_out__gclk clkgen_l2d1_cmp_gclk_if.scan_out; | |
| 2062 | slow_cmp_sync_en__gclk clkgen_l2d1_cmp_gclk_if.slow_cmp_sync_en; | |
| 2063 | tcu_aclk__gclk clkgen_l2d1_cmp_gclk_if.tcu_aclk; | |
| 2064 | tcu_atpg_mode__gclk clkgen_l2d1_cmp_gclk_if.tcu_atpg_mode; | |
| 2065 | tcu_bclk__gclk clkgen_l2d1_cmp_gclk_if.tcu_bclk; | |
| 2066 | tcu_clk_stop__gclk clkgen_l2d1_cmp_gclk_if.tcu_clk_stop; | |
| 2067 | tcu_div_bypass__gclk clkgen_l2d1_cmp_gclk_if.tcu_div_bypass; | |
| 2068 | tcu_pce_ov__gclk clkgen_l2d1_cmp_gclk_if.tcu_pce_ov; | |
| 2069 | tcu_wr_inhibit__gclk clkgen_l2d1_cmp_gclk_if.tcu_wr_inhibit; | |
| 2070 | wmr___gclk clkgen_l2d1_cmp_gclk_if.wmr_; | |
| 2071 | wmr_protect__gclk clkgen_l2d1_cmp_gclk_if.wmr_protect; | |
| 2072 | pc_clk__gclk void; | |
| 2073 | pc_clk_sel__gclk void; | |
| 2074 | test_clk__gclk void; | |
| 2075 | test_clk_sel__gclk void; | |
| 2076 | ||
| 2077 | //---l2clk is Vera interface CLOCK--- | |
| 2078 | aclk__l2clk clkgen_l2d1_cmp_l2clk_if.aclk; | |
| 2079 | aclk_wmr__l2clk clkgen_l2d1_cmp_l2clk_if.aclk_wmr; | |
| 2080 | array_wr_inhibit__l2clk clkgen_l2d1_cmp_l2clk_if.array_wr_inhibit; | |
| 2081 | bclk__l2clk clkgen_l2d1_cmp_l2clk_if.bclk; | |
| 2082 | cmp_slow_sync_en__l2clk clkgen_l2d1_cmp_l2clk_if.cmp_slow_sync_en; | |
| 2083 | dr_sync_en__l2clk void; | |
| 2084 | io2x_sync_en__l2clk void; | |
| 2085 | l2clk clkgen_l2d1_cmp_l2clk_if.l2clk; | |
| 2086 | pce_ov__l2clk clkgen_l2d1_cmp_l2clk_if.pce_ov; | |
| 2087 | por___l2clk clkgen_l2d1_cmp_l2clk_if.por_; | |
| 2088 | scan_out__l2clk clkgen_l2d1_cmp_l2clk_if.scan_out; | |
| 2089 | slow_cmp_sync_en__l2clk clkgen_l2d1_cmp_l2clk_if.slow_cmp_sync_en; | |
| 2090 | wmr___l2clk clkgen_l2d1_cmp_l2clk_if.wmr_; | |
| 2091 | wmr_protect__l2clk clkgen_l2d1_cmp_l2clk_if.wmr_protect; | |
| 2092 | } | |
| 2093 | ||
| 2094 | //----- port binding for clkgen_l2d2_cmp ----- | |
| 2095 | ||
| 2096 | bind CLKGEN_port clkgen_l2d2_cmp_bind { | |
| 2097 | //---gclk is Vera interface CLOCK--- | |
| 2098 | aclk__gclk clkgen_l2d2_cmp_gclk_if.aclk; | |
| 2099 | aclk_wmr__gclk clkgen_l2d2_cmp_gclk_if.aclk_wmr; | |
| 2100 | array_wr_inhibit__gclk clkgen_l2d2_cmp_gclk_if.array_wr_inhibit; | |
| 2101 | bclk__gclk clkgen_l2d2_cmp_gclk_if.bclk; | |
| 2102 | ccu_cmp_slow_sync_en__gclk clkgen_l2d2_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 2103 | ccu_div_ph__gclk clkgen_l2d2_cmp_gclk_if.ccu_div_ph; | |
| 2104 | ccu_dr_sync_en__gclk void; | |
| 2105 | ccu_io2x_sync_en__gclk void; | |
| 2106 | ccu_serdes_dtm__gclk void; | |
| 2107 | ccu_slow_cmp_sync_en__gclk clkgen_l2d2_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 2108 | clk_ext__gclk void; | |
| 2109 | cluster_arst_l__gclk clkgen_l2d2_cmp_gclk_if.cluster_arst_l; | |
| 2110 | cluster_div_en__gclk clkgen_l2d2_cmp_gclk_if.cluster_div_en; | |
| 2111 | cmp_slow_sync_en__gclk clkgen_l2d2_cmp_gclk_if.cmp_slow_sync_en; | |
| 2112 | dr_sync_en__gclk void; | |
| 2113 | gclk clkgen_l2d2_cmp_gclk_if.gclk; | |
| 2114 | io2x_sync_en__gclk void; | |
| 2115 | l2clk__gclk clkgen_l2d2_cmp_gclk_if.l2clk; | |
| 2116 | pce_ov__gclk clkgen_l2d2_cmp_gclk_if.pce_ov; | |
| 2117 | por___gclk clkgen_l2d2_cmp_gclk_if.por_; | |
| 2118 | rst_por___gclk clkgen_l2d2_cmp_gclk_if.rst_por_; | |
| 2119 | rst_wmr___gclk clkgen_l2d2_cmp_gclk_if.rst_wmr_; | |
| 2120 | rst_wmr_protect__gclk clkgen_l2d2_cmp_gclk_if.rst_wmr_protect; | |
| 2121 | scan_en__gclk clkgen_l2d2_cmp_gclk_if.scan_en; | |
| 2122 | scan_in__gclk clkgen_l2d2_cmp_gclk_if.scan_in; | |
| 2123 | scan_out__gclk clkgen_l2d2_cmp_gclk_if.scan_out; | |
| 2124 | slow_cmp_sync_en__gclk clkgen_l2d2_cmp_gclk_if.slow_cmp_sync_en; | |
| 2125 | tcu_aclk__gclk clkgen_l2d2_cmp_gclk_if.tcu_aclk; | |
| 2126 | tcu_atpg_mode__gclk clkgen_l2d2_cmp_gclk_if.tcu_atpg_mode; | |
| 2127 | tcu_bclk__gclk clkgen_l2d2_cmp_gclk_if.tcu_bclk; | |
| 2128 | tcu_clk_stop__gclk clkgen_l2d2_cmp_gclk_if.tcu_clk_stop; | |
| 2129 | tcu_div_bypass__gclk clkgen_l2d2_cmp_gclk_if.tcu_div_bypass; | |
| 2130 | tcu_pce_ov__gclk clkgen_l2d2_cmp_gclk_if.tcu_pce_ov; | |
| 2131 | tcu_wr_inhibit__gclk clkgen_l2d2_cmp_gclk_if.tcu_wr_inhibit; | |
| 2132 | wmr___gclk clkgen_l2d2_cmp_gclk_if.wmr_; | |
| 2133 | wmr_protect__gclk clkgen_l2d2_cmp_gclk_if.wmr_protect; | |
| 2134 | pc_clk__gclk void; | |
| 2135 | pc_clk_sel__gclk void; | |
| 2136 | test_clk__gclk void; | |
| 2137 | test_clk_sel__gclk void; | |
| 2138 | ||
| 2139 | //---l2clk is Vera interface CLOCK--- | |
| 2140 | aclk__l2clk clkgen_l2d2_cmp_l2clk_if.aclk; | |
| 2141 | aclk_wmr__l2clk clkgen_l2d2_cmp_l2clk_if.aclk_wmr; | |
| 2142 | array_wr_inhibit__l2clk clkgen_l2d2_cmp_l2clk_if.array_wr_inhibit; | |
| 2143 | bclk__l2clk clkgen_l2d2_cmp_l2clk_if.bclk; | |
| 2144 | cmp_slow_sync_en__l2clk clkgen_l2d2_cmp_l2clk_if.cmp_slow_sync_en; | |
| 2145 | dr_sync_en__l2clk void; | |
| 2146 | io2x_sync_en__l2clk void; | |
| 2147 | l2clk clkgen_l2d2_cmp_l2clk_if.l2clk; | |
| 2148 | pce_ov__l2clk clkgen_l2d2_cmp_l2clk_if.pce_ov; | |
| 2149 | por___l2clk clkgen_l2d2_cmp_l2clk_if.por_; | |
| 2150 | scan_out__l2clk clkgen_l2d2_cmp_l2clk_if.scan_out; | |
| 2151 | slow_cmp_sync_en__l2clk clkgen_l2d2_cmp_l2clk_if.slow_cmp_sync_en; | |
| 2152 | wmr___l2clk clkgen_l2d2_cmp_l2clk_if.wmr_; | |
| 2153 | wmr_protect__l2clk clkgen_l2d2_cmp_l2clk_if.wmr_protect; | |
| 2154 | } | |
| 2155 | ||
| 2156 | //----- port binding for clkgen_l2d3_cmp ----- | |
| 2157 | ||
| 2158 | bind CLKGEN_port clkgen_l2d3_cmp_bind { | |
| 2159 | //---gclk is Vera interface CLOCK--- | |
| 2160 | aclk__gclk clkgen_l2d3_cmp_gclk_if.aclk; | |
| 2161 | aclk_wmr__gclk clkgen_l2d3_cmp_gclk_if.aclk_wmr; | |
| 2162 | array_wr_inhibit__gclk clkgen_l2d3_cmp_gclk_if.array_wr_inhibit; | |
| 2163 | bclk__gclk clkgen_l2d3_cmp_gclk_if.bclk; | |
| 2164 | ccu_cmp_slow_sync_en__gclk clkgen_l2d3_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 2165 | ccu_div_ph__gclk clkgen_l2d3_cmp_gclk_if.ccu_div_ph; | |
| 2166 | ccu_dr_sync_en__gclk void; | |
| 2167 | ccu_io2x_sync_en__gclk void; | |
| 2168 | ccu_serdes_dtm__gclk void; | |
| 2169 | ccu_slow_cmp_sync_en__gclk clkgen_l2d3_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 2170 | clk_ext__gclk void; | |
| 2171 | cluster_arst_l__gclk clkgen_l2d3_cmp_gclk_if.cluster_arst_l; | |
| 2172 | cluster_div_en__gclk clkgen_l2d3_cmp_gclk_if.cluster_div_en; | |
| 2173 | cmp_slow_sync_en__gclk clkgen_l2d3_cmp_gclk_if.cmp_slow_sync_en; | |
| 2174 | dr_sync_en__gclk void; | |
| 2175 | gclk clkgen_l2d3_cmp_gclk_if.gclk; | |
| 2176 | io2x_sync_en__gclk void; | |
| 2177 | l2clk__gclk clkgen_l2d3_cmp_gclk_if.l2clk; | |
| 2178 | pce_ov__gclk clkgen_l2d3_cmp_gclk_if.pce_ov; | |
| 2179 | por___gclk clkgen_l2d3_cmp_gclk_if.por_; | |
| 2180 | rst_por___gclk clkgen_l2d3_cmp_gclk_if.rst_por_; | |
| 2181 | rst_wmr___gclk clkgen_l2d3_cmp_gclk_if.rst_wmr_; | |
| 2182 | rst_wmr_protect__gclk clkgen_l2d3_cmp_gclk_if.rst_wmr_protect; | |
| 2183 | scan_en__gclk clkgen_l2d3_cmp_gclk_if.scan_en; | |
| 2184 | scan_in__gclk clkgen_l2d3_cmp_gclk_if.scan_in; | |
| 2185 | scan_out__gclk clkgen_l2d3_cmp_gclk_if.scan_out; | |
| 2186 | slow_cmp_sync_en__gclk clkgen_l2d3_cmp_gclk_if.slow_cmp_sync_en; | |
| 2187 | tcu_aclk__gclk clkgen_l2d3_cmp_gclk_if.tcu_aclk; | |
| 2188 | tcu_atpg_mode__gclk clkgen_l2d3_cmp_gclk_if.tcu_atpg_mode; | |
| 2189 | tcu_bclk__gclk clkgen_l2d3_cmp_gclk_if.tcu_bclk; | |
| 2190 | tcu_clk_stop__gclk clkgen_l2d3_cmp_gclk_if.tcu_clk_stop; | |
| 2191 | tcu_div_bypass__gclk clkgen_l2d3_cmp_gclk_if.tcu_div_bypass; | |
| 2192 | tcu_pce_ov__gclk clkgen_l2d3_cmp_gclk_if.tcu_pce_ov; | |
| 2193 | tcu_wr_inhibit__gclk clkgen_l2d3_cmp_gclk_if.tcu_wr_inhibit; | |
| 2194 | wmr___gclk clkgen_l2d3_cmp_gclk_if.wmr_; | |
| 2195 | wmr_protect__gclk clkgen_l2d3_cmp_gclk_if.wmr_protect; | |
| 2196 | pc_clk__gclk void; | |
| 2197 | pc_clk_sel__gclk void; | |
| 2198 | test_clk__gclk void; | |
| 2199 | test_clk_sel__gclk void; | |
| 2200 | ||
| 2201 | //---l2clk is Vera interface CLOCK--- | |
| 2202 | aclk__l2clk clkgen_l2d3_cmp_l2clk_if.aclk; | |
| 2203 | aclk_wmr__l2clk clkgen_l2d3_cmp_l2clk_if.aclk_wmr; | |
| 2204 | array_wr_inhibit__l2clk clkgen_l2d3_cmp_l2clk_if.array_wr_inhibit; | |
| 2205 | bclk__l2clk clkgen_l2d3_cmp_l2clk_if.bclk; | |
| 2206 | cmp_slow_sync_en__l2clk clkgen_l2d3_cmp_l2clk_if.cmp_slow_sync_en; | |
| 2207 | dr_sync_en__l2clk void; | |
| 2208 | io2x_sync_en__l2clk void; | |
| 2209 | l2clk clkgen_l2d3_cmp_l2clk_if.l2clk; | |
| 2210 | pce_ov__l2clk clkgen_l2d3_cmp_l2clk_if.pce_ov; | |
| 2211 | por___l2clk clkgen_l2d3_cmp_l2clk_if.por_; | |
| 2212 | scan_out__l2clk clkgen_l2d3_cmp_l2clk_if.scan_out; | |
| 2213 | slow_cmp_sync_en__l2clk clkgen_l2d3_cmp_l2clk_if.slow_cmp_sync_en; | |
| 2214 | wmr___l2clk clkgen_l2d3_cmp_l2clk_if.wmr_; | |
| 2215 | wmr_protect__l2clk clkgen_l2d3_cmp_l2clk_if.wmr_protect; | |
| 2216 | } | |
| 2217 | ||
| 2218 | //----- port binding for clkgen_l2d4_cmp ----- | |
| 2219 | ||
| 2220 | bind CLKGEN_port clkgen_l2d4_cmp_bind { | |
| 2221 | //---gclk is Vera interface CLOCK--- | |
| 2222 | aclk__gclk clkgen_l2d4_cmp_gclk_if.aclk; | |
| 2223 | aclk_wmr__gclk clkgen_l2d4_cmp_gclk_if.aclk_wmr; | |
| 2224 | array_wr_inhibit__gclk clkgen_l2d4_cmp_gclk_if.array_wr_inhibit; | |
| 2225 | bclk__gclk clkgen_l2d4_cmp_gclk_if.bclk; | |
| 2226 | ccu_cmp_slow_sync_en__gclk clkgen_l2d4_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 2227 | ccu_div_ph__gclk clkgen_l2d4_cmp_gclk_if.ccu_div_ph; | |
| 2228 | ccu_dr_sync_en__gclk void; | |
| 2229 | ccu_io2x_sync_en__gclk void; | |
| 2230 | ccu_serdes_dtm__gclk void; | |
| 2231 | ccu_slow_cmp_sync_en__gclk clkgen_l2d4_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 2232 | clk_ext__gclk void; | |
| 2233 | cluster_arst_l__gclk clkgen_l2d4_cmp_gclk_if.cluster_arst_l; | |
| 2234 | cluster_div_en__gclk clkgen_l2d4_cmp_gclk_if.cluster_div_en; | |
| 2235 | cmp_slow_sync_en__gclk clkgen_l2d4_cmp_gclk_if.cmp_slow_sync_en; | |
| 2236 | dr_sync_en__gclk void; | |
| 2237 | gclk clkgen_l2d4_cmp_gclk_if.gclk; | |
| 2238 | io2x_sync_en__gclk void; | |
| 2239 | l2clk__gclk clkgen_l2d4_cmp_gclk_if.l2clk; | |
| 2240 | pce_ov__gclk clkgen_l2d4_cmp_gclk_if.pce_ov; | |
| 2241 | por___gclk clkgen_l2d4_cmp_gclk_if.por_; | |
| 2242 | rst_por___gclk clkgen_l2d4_cmp_gclk_if.rst_por_; | |
| 2243 | rst_wmr___gclk clkgen_l2d4_cmp_gclk_if.rst_wmr_; | |
| 2244 | rst_wmr_protect__gclk clkgen_l2d4_cmp_gclk_if.rst_wmr_protect; | |
| 2245 | scan_en__gclk clkgen_l2d4_cmp_gclk_if.scan_en; | |
| 2246 | scan_in__gclk clkgen_l2d4_cmp_gclk_if.scan_in; | |
| 2247 | scan_out__gclk clkgen_l2d4_cmp_gclk_if.scan_out; | |
| 2248 | slow_cmp_sync_en__gclk clkgen_l2d4_cmp_gclk_if.slow_cmp_sync_en; | |
| 2249 | tcu_aclk__gclk clkgen_l2d4_cmp_gclk_if.tcu_aclk; | |
| 2250 | tcu_atpg_mode__gclk clkgen_l2d4_cmp_gclk_if.tcu_atpg_mode; | |
| 2251 | tcu_bclk__gclk clkgen_l2d4_cmp_gclk_if.tcu_bclk; | |
| 2252 | tcu_clk_stop__gclk clkgen_l2d4_cmp_gclk_if.tcu_clk_stop; | |
| 2253 | tcu_div_bypass__gclk clkgen_l2d4_cmp_gclk_if.tcu_div_bypass; | |
| 2254 | tcu_pce_ov__gclk clkgen_l2d4_cmp_gclk_if.tcu_pce_ov; | |
| 2255 | tcu_wr_inhibit__gclk clkgen_l2d4_cmp_gclk_if.tcu_wr_inhibit; | |
| 2256 | wmr___gclk clkgen_l2d4_cmp_gclk_if.wmr_; | |
| 2257 | wmr_protect__gclk clkgen_l2d4_cmp_gclk_if.wmr_protect; | |
| 2258 | pc_clk__gclk void; | |
| 2259 | pc_clk_sel__gclk void; | |
| 2260 | test_clk__gclk void; | |
| 2261 | test_clk_sel__gclk void; | |
| 2262 | ||
| 2263 | //---l2clk is Vera interface CLOCK--- | |
| 2264 | aclk__l2clk clkgen_l2d4_cmp_l2clk_if.aclk; | |
| 2265 | aclk_wmr__l2clk clkgen_l2d4_cmp_l2clk_if.aclk_wmr; | |
| 2266 | array_wr_inhibit__l2clk clkgen_l2d4_cmp_l2clk_if.array_wr_inhibit; | |
| 2267 | bclk__l2clk clkgen_l2d4_cmp_l2clk_if.bclk; | |
| 2268 | cmp_slow_sync_en__l2clk clkgen_l2d4_cmp_l2clk_if.cmp_slow_sync_en; | |
| 2269 | dr_sync_en__l2clk void; | |
| 2270 | io2x_sync_en__l2clk void; | |
| 2271 | l2clk clkgen_l2d4_cmp_l2clk_if.l2clk; | |
| 2272 | pce_ov__l2clk clkgen_l2d4_cmp_l2clk_if.pce_ov; | |
| 2273 | por___l2clk clkgen_l2d4_cmp_l2clk_if.por_; | |
| 2274 | scan_out__l2clk clkgen_l2d4_cmp_l2clk_if.scan_out; | |
| 2275 | slow_cmp_sync_en__l2clk clkgen_l2d4_cmp_l2clk_if.slow_cmp_sync_en; | |
| 2276 | wmr___l2clk clkgen_l2d4_cmp_l2clk_if.wmr_; | |
| 2277 | wmr_protect__l2clk clkgen_l2d4_cmp_l2clk_if.wmr_protect; | |
| 2278 | } | |
| 2279 | ||
| 2280 | //----- port binding for clkgen_l2d5_cmp ----- | |
| 2281 | ||
| 2282 | bind CLKGEN_port clkgen_l2d5_cmp_bind { | |
| 2283 | //---gclk is Vera interface CLOCK--- | |
| 2284 | aclk__gclk clkgen_l2d5_cmp_gclk_if.aclk; | |
| 2285 | aclk_wmr__gclk clkgen_l2d5_cmp_gclk_if.aclk_wmr; | |
| 2286 | array_wr_inhibit__gclk clkgen_l2d5_cmp_gclk_if.array_wr_inhibit; | |
| 2287 | bclk__gclk clkgen_l2d5_cmp_gclk_if.bclk; | |
| 2288 | ccu_cmp_slow_sync_en__gclk clkgen_l2d5_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 2289 | ccu_div_ph__gclk clkgen_l2d5_cmp_gclk_if.ccu_div_ph; | |
| 2290 | ccu_dr_sync_en__gclk void; | |
| 2291 | ccu_io2x_sync_en__gclk void; | |
| 2292 | ccu_serdes_dtm__gclk void; | |
| 2293 | ccu_slow_cmp_sync_en__gclk clkgen_l2d5_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 2294 | clk_ext__gclk void; | |
| 2295 | cluster_arst_l__gclk clkgen_l2d5_cmp_gclk_if.cluster_arst_l; | |
| 2296 | cluster_div_en__gclk clkgen_l2d5_cmp_gclk_if.cluster_div_en; | |
| 2297 | cmp_slow_sync_en__gclk clkgen_l2d5_cmp_gclk_if.cmp_slow_sync_en; | |
| 2298 | dr_sync_en__gclk void; | |
| 2299 | gclk clkgen_l2d5_cmp_gclk_if.gclk; | |
| 2300 | io2x_sync_en__gclk void; | |
| 2301 | l2clk__gclk clkgen_l2d5_cmp_gclk_if.l2clk; | |
| 2302 | pce_ov__gclk clkgen_l2d5_cmp_gclk_if.pce_ov; | |
| 2303 | por___gclk clkgen_l2d5_cmp_gclk_if.por_; | |
| 2304 | rst_por___gclk clkgen_l2d5_cmp_gclk_if.rst_por_; | |
| 2305 | rst_wmr___gclk clkgen_l2d5_cmp_gclk_if.rst_wmr_; | |
| 2306 | rst_wmr_protect__gclk clkgen_l2d5_cmp_gclk_if.rst_wmr_protect; | |
| 2307 | scan_en__gclk clkgen_l2d5_cmp_gclk_if.scan_en; | |
| 2308 | scan_in__gclk clkgen_l2d5_cmp_gclk_if.scan_in; | |
| 2309 | scan_out__gclk clkgen_l2d5_cmp_gclk_if.scan_out; | |
| 2310 | slow_cmp_sync_en__gclk clkgen_l2d5_cmp_gclk_if.slow_cmp_sync_en; | |
| 2311 | tcu_aclk__gclk clkgen_l2d5_cmp_gclk_if.tcu_aclk; | |
| 2312 | tcu_atpg_mode__gclk clkgen_l2d5_cmp_gclk_if.tcu_atpg_mode; | |
| 2313 | tcu_bclk__gclk clkgen_l2d5_cmp_gclk_if.tcu_bclk; | |
| 2314 | tcu_clk_stop__gclk clkgen_l2d5_cmp_gclk_if.tcu_clk_stop; | |
| 2315 | tcu_div_bypass__gclk clkgen_l2d5_cmp_gclk_if.tcu_div_bypass; | |
| 2316 | tcu_pce_ov__gclk clkgen_l2d5_cmp_gclk_if.tcu_pce_ov; | |
| 2317 | tcu_wr_inhibit__gclk clkgen_l2d5_cmp_gclk_if.tcu_wr_inhibit; | |
| 2318 | wmr___gclk clkgen_l2d5_cmp_gclk_if.wmr_; | |
| 2319 | wmr_protect__gclk clkgen_l2d5_cmp_gclk_if.wmr_protect; | |
| 2320 | pc_clk__gclk void; | |
| 2321 | pc_clk_sel__gclk void; | |
| 2322 | test_clk__gclk void; | |
| 2323 | test_clk_sel__gclk void; | |
| 2324 | ||
| 2325 | //---l2clk is Vera interface CLOCK--- | |
| 2326 | aclk__l2clk clkgen_l2d5_cmp_l2clk_if.aclk; | |
| 2327 | aclk_wmr__l2clk clkgen_l2d5_cmp_l2clk_if.aclk_wmr; | |
| 2328 | array_wr_inhibit__l2clk clkgen_l2d5_cmp_l2clk_if.array_wr_inhibit; | |
| 2329 | bclk__l2clk clkgen_l2d5_cmp_l2clk_if.bclk; | |
| 2330 | cmp_slow_sync_en__l2clk clkgen_l2d5_cmp_l2clk_if.cmp_slow_sync_en; | |
| 2331 | dr_sync_en__l2clk void; | |
| 2332 | io2x_sync_en__l2clk void; | |
| 2333 | l2clk clkgen_l2d5_cmp_l2clk_if.l2clk; | |
| 2334 | pce_ov__l2clk clkgen_l2d5_cmp_l2clk_if.pce_ov; | |
| 2335 | por___l2clk clkgen_l2d5_cmp_l2clk_if.por_; | |
| 2336 | scan_out__l2clk clkgen_l2d5_cmp_l2clk_if.scan_out; | |
| 2337 | slow_cmp_sync_en__l2clk clkgen_l2d5_cmp_l2clk_if.slow_cmp_sync_en; | |
| 2338 | wmr___l2clk clkgen_l2d5_cmp_l2clk_if.wmr_; | |
| 2339 | wmr_protect__l2clk clkgen_l2d5_cmp_l2clk_if.wmr_protect; | |
| 2340 | } | |
| 2341 | ||
| 2342 | //----- port binding for clkgen_l2d6_cmp ----- | |
| 2343 | ||
| 2344 | bind CLKGEN_port clkgen_l2d6_cmp_bind { | |
| 2345 | //---gclk is Vera interface CLOCK--- | |
| 2346 | aclk__gclk clkgen_l2d6_cmp_gclk_if.aclk; | |
| 2347 | aclk_wmr__gclk clkgen_l2d6_cmp_gclk_if.aclk_wmr; | |
| 2348 | array_wr_inhibit__gclk clkgen_l2d6_cmp_gclk_if.array_wr_inhibit; | |
| 2349 | bclk__gclk clkgen_l2d6_cmp_gclk_if.bclk; | |
| 2350 | ccu_cmp_slow_sync_en__gclk clkgen_l2d6_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 2351 | ccu_div_ph__gclk clkgen_l2d6_cmp_gclk_if.ccu_div_ph; | |
| 2352 | ccu_dr_sync_en__gclk void; | |
| 2353 | ccu_io2x_sync_en__gclk void; | |
| 2354 | ccu_serdes_dtm__gclk void; | |
| 2355 | ccu_slow_cmp_sync_en__gclk clkgen_l2d6_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 2356 | clk_ext__gclk void; | |
| 2357 | cluster_arst_l__gclk clkgen_l2d6_cmp_gclk_if.cluster_arst_l; | |
| 2358 | cluster_div_en__gclk clkgen_l2d6_cmp_gclk_if.cluster_div_en; | |
| 2359 | cmp_slow_sync_en__gclk clkgen_l2d6_cmp_gclk_if.cmp_slow_sync_en; | |
| 2360 | dr_sync_en__gclk void; | |
| 2361 | gclk clkgen_l2d6_cmp_gclk_if.gclk; | |
| 2362 | io2x_sync_en__gclk void; | |
| 2363 | l2clk__gclk clkgen_l2d6_cmp_gclk_if.l2clk; | |
| 2364 | pce_ov__gclk clkgen_l2d6_cmp_gclk_if.pce_ov; | |
| 2365 | por___gclk clkgen_l2d6_cmp_gclk_if.por_; | |
| 2366 | rst_por___gclk clkgen_l2d6_cmp_gclk_if.rst_por_; | |
| 2367 | rst_wmr___gclk clkgen_l2d6_cmp_gclk_if.rst_wmr_; | |
| 2368 | rst_wmr_protect__gclk clkgen_l2d6_cmp_gclk_if.rst_wmr_protect; | |
| 2369 | scan_en__gclk clkgen_l2d6_cmp_gclk_if.scan_en; | |
| 2370 | scan_in__gclk clkgen_l2d6_cmp_gclk_if.scan_in; | |
| 2371 | scan_out__gclk clkgen_l2d6_cmp_gclk_if.scan_out; | |
| 2372 | slow_cmp_sync_en__gclk clkgen_l2d6_cmp_gclk_if.slow_cmp_sync_en; | |
| 2373 | tcu_aclk__gclk clkgen_l2d6_cmp_gclk_if.tcu_aclk; | |
| 2374 | tcu_atpg_mode__gclk clkgen_l2d6_cmp_gclk_if.tcu_atpg_mode; | |
| 2375 | tcu_bclk__gclk clkgen_l2d6_cmp_gclk_if.tcu_bclk; | |
| 2376 | tcu_clk_stop__gclk clkgen_l2d6_cmp_gclk_if.tcu_clk_stop; | |
| 2377 | tcu_div_bypass__gclk clkgen_l2d6_cmp_gclk_if.tcu_div_bypass; | |
| 2378 | tcu_pce_ov__gclk clkgen_l2d6_cmp_gclk_if.tcu_pce_ov; | |
| 2379 | tcu_wr_inhibit__gclk clkgen_l2d6_cmp_gclk_if.tcu_wr_inhibit; | |
| 2380 | wmr___gclk clkgen_l2d6_cmp_gclk_if.wmr_; | |
| 2381 | wmr_protect__gclk clkgen_l2d6_cmp_gclk_if.wmr_protect; | |
| 2382 | pc_clk__gclk void; | |
| 2383 | pc_clk_sel__gclk void; | |
| 2384 | test_clk__gclk void; | |
| 2385 | test_clk_sel__gclk void; | |
| 2386 | ||
| 2387 | //---l2clk is Vera interface CLOCK--- | |
| 2388 | aclk__l2clk clkgen_l2d6_cmp_l2clk_if.aclk; | |
| 2389 | aclk_wmr__l2clk clkgen_l2d6_cmp_l2clk_if.aclk_wmr; | |
| 2390 | array_wr_inhibit__l2clk clkgen_l2d6_cmp_l2clk_if.array_wr_inhibit; | |
| 2391 | bclk__l2clk clkgen_l2d6_cmp_l2clk_if.bclk; | |
| 2392 | cmp_slow_sync_en__l2clk clkgen_l2d6_cmp_l2clk_if.cmp_slow_sync_en; | |
| 2393 | dr_sync_en__l2clk void; | |
| 2394 | io2x_sync_en__l2clk void; | |
| 2395 | l2clk clkgen_l2d6_cmp_l2clk_if.l2clk; | |
| 2396 | pce_ov__l2clk clkgen_l2d6_cmp_l2clk_if.pce_ov; | |
| 2397 | por___l2clk clkgen_l2d6_cmp_l2clk_if.por_; | |
| 2398 | scan_out__l2clk clkgen_l2d6_cmp_l2clk_if.scan_out; | |
| 2399 | slow_cmp_sync_en__l2clk clkgen_l2d6_cmp_l2clk_if.slow_cmp_sync_en; | |
| 2400 | wmr___l2clk clkgen_l2d6_cmp_l2clk_if.wmr_; | |
| 2401 | wmr_protect__l2clk clkgen_l2d6_cmp_l2clk_if.wmr_protect; | |
| 2402 | } | |
| 2403 | ||
| 2404 | //----- port binding for clkgen_l2d7_cmp ----- | |
| 2405 | ||
| 2406 | bind CLKGEN_port clkgen_l2d7_cmp_bind { | |
| 2407 | //---gclk is Vera interface CLOCK--- | |
| 2408 | aclk__gclk clkgen_l2d7_cmp_gclk_if.aclk; | |
| 2409 | aclk_wmr__gclk clkgen_l2d7_cmp_gclk_if.aclk_wmr; | |
| 2410 | array_wr_inhibit__gclk clkgen_l2d7_cmp_gclk_if.array_wr_inhibit; | |
| 2411 | bclk__gclk clkgen_l2d7_cmp_gclk_if.bclk; | |
| 2412 | ccu_cmp_slow_sync_en__gclk clkgen_l2d7_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 2413 | ccu_div_ph__gclk clkgen_l2d7_cmp_gclk_if.ccu_div_ph; | |
| 2414 | ccu_dr_sync_en__gclk void; | |
| 2415 | ccu_io2x_sync_en__gclk void; | |
| 2416 | ccu_serdes_dtm__gclk void; | |
| 2417 | ccu_slow_cmp_sync_en__gclk clkgen_l2d7_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 2418 | clk_ext__gclk void; | |
| 2419 | cluster_arst_l__gclk clkgen_l2d7_cmp_gclk_if.cluster_arst_l; | |
| 2420 | cluster_div_en__gclk clkgen_l2d7_cmp_gclk_if.cluster_div_en; | |
| 2421 | cmp_slow_sync_en__gclk clkgen_l2d7_cmp_gclk_if.cmp_slow_sync_en; | |
| 2422 | dr_sync_en__gclk void; | |
| 2423 | gclk clkgen_l2d7_cmp_gclk_if.gclk; | |
| 2424 | io2x_sync_en__gclk void; | |
| 2425 | l2clk__gclk clkgen_l2d7_cmp_gclk_if.l2clk; | |
| 2426 | pce_ov__gclk clkgen_l2d7_cmp_gclk_if.pce_ov; | |
| 2427 | por___gclk clkgen_l2d7_cmp_gclk_if.por_; | |
| 2428 | rst_por___gclk clkgen_l2d7_cmp_gclk_if.rst_por_; | |
| 2429 | rst_wmr___gclk clkgen_l2d7_cmp_gclk_if.rst_wmr_; | |
| 2430 | rst_wmr_protect__gclk clkgen_l2d7_cmp_gclk_if.rst_wmr_protect; | |
| 2431 | scan_en__gclk clkgen_l2d7_cmp_gclk_if.scan_en; | |
| 2432 | scan_in__gclk clkgen_l2d7_cmp_gclk_if.scan_in; | |
| 2433 | scan_out__gclk clkgen_l2d7_cmp_gclk_if.scan_out; | |
| 2434 | slow_cmp_sync_en__gclk clkgen_l2d7_cmp_gclk_if.slow_cmp_sync_en; | |
| 2435 | tcu_aclk__gclk clkgen_l2d7_cmp_gclk_if.tcu_aclk; | |
| 2436 | tcu_atpg_mode__gclk clkgen_l2d7_cmp_gclk_if.tcu_atpg_mode; | |
| 2437 | tcu_bclk__gclk clkgen_l2d7_cmp_gclk_if.tcu_bclk; | |
| 2438 | tcu_clk_stop__gclk clkgen_l2d7_cmp_gclk_if.tcu_clk_stop; | |
| 2439 | tcu_div_bypass__gclk clkgen_l2d7_cmp_gclk_if.tcu_div_bypass; | |
| 2440 | tcu_pce_ov__gclk clkgen_l2d7_cmp_gclk_if.tcu_pce_ov; | |
| 2441 | tcu_wr_inhibit__gclk clkgen_l2d7_cmp_gclk_if.tcu_wr_inhibit; | |
| 2442 | wmr___gclk clkgen_l2d7_cmp_gclk_if.wmr_; | |
| 2443 | wmr_protect__gclk clkgen_l2d7_cmp_gclk_if.wmr_protect; | |
| 2444 | pc_clk__gclk void; | |
| 2445 | pc_clk_sel__gclk void; | |
| 2446 | test_clk__gclk void; | |
| 2447 | test_clk_sel__gclk void; | |
| 2448 | ||
| 2449 | //---l2clk is Vera interface CLOCK--- | |
| 2450 | aclk__l2clk clkgen_l2d7_cmp_l2clk_if.aclk; | |
| 2451 | aclk_wmr__l2clk clkgen_l2d7_cmp_l2clk_if.aclk_wmr; | |
| 2452 | array_wr_inhibit__l2clk clkgen_l2d7_cmp_l2clk_if.array_wr_inhibit; | |
| 2453 | bclk__l2clk clkgen_l2d7_cmp_l2clk_if.bclk; | |
| 2454 | cmp_slow_sync_en__l2clk clkgen_l2d7_cmp_l2clk_if.cmp_slow_sync_en; | |
| 2455 | dr_sync_en__l2clk void; | |
| 2456 | io2x_sync_en__l2clk void; | |
| 2457 | l2clk clkgen_l2d7_cmp_l2clk_if.l2clk; | |
| 2458 | pce_ov__l2clk clkgen_l2d7_cmp_l2clk_if.pce_ov; | |
| 2459 | por___l2clk clkgen_l2d7_cmp_l2clk_if.por_; | |
| 2460 | scan_out__l2clk clkgen_l2d7_cmp_l2clk_if.scan_out; | |
| 2461 | slow_cmp_sync_en__l2clk clkgen_l2d7_cmp_l2clk_if.slow_cmp_sync_en; | |
| 2462 | wmr___l2clk clkgen_l2d7_cmp_l2clk_if.wmr_; | |
| 2463 | wmr_protect__l2clk clkgen_l2d7_cmp_l2clk_if.wmr_protect; | |
| 2464 | } | |
| 2465 | ||
| 2466 | //----- port binding for clkgen_l2t0_cmp ----- | |
| 2467 | ||
| 2468 | bind CLKGEN_port clkgen_l2t0_cmp_bind { | |
| 2469 | //---gclk is Vera interface CLOCK--- | |
| 2470 | aclk__gclk clkgen_l2t0_cmp_gclk_if.aclk; | |
| 2471 | aclk_wmr__gclk clkgen_l2t0_cmp_gclk_if.aclk_wmr; | |
| 2472 | array_wr_inhibit__gclk clkgen_l2t0_cmp_gclk_if.array_wr_inhibit; | |
| 2473 | bclk__gclk clkgen_l2t0_cmp_gclk_if.bclk; | |
| 2474 | ccu_cmp_slow_sync_en__gclk clkgen_l2t0_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 2475 | ccu_div_ph__gclk clkgen_l2t0_cmp_gclk_if.ccu_div_ph; | |
| 2476 | ccu_dr_sync_en__gclk void; | |
| 2477 | ccu_io2x_sync_en__gclk void; | |
| 2478 | ccu_serdes_dtm__gclk clkgen_l2t0_cmp_gclk_if.ccu_serdes_dtm; | |
| 2479 | ccu_slow_cmp_sync_en__gclk clkgen_l2t0_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 2480 | clk_ext__gclk clkgen_l2t0_cmp_gclk_if.clk_ext; | |
| 2481 | cluster_arst_l__gclk clkgen_l2t0_cmp_gclk_if.cluster_arst_l; | |
| 2482 | cluster_div_en__gclk clkgen_l2t0_cmp_gclk_if.cluster_div_en; | |
| 2483 | cmp_slow_sync_en__gclk clkgen_l2t0_cmp_gclk_if.cmp_slow_sync_en; | |
| 2484 | dr_sync_en__gclk void; | |
| 2485 | gclk clkgen_l2t0_cmp_gclk_if.gclk; | |
| 2486 | io2x_sync_en__gclk void; | |
| 2487 | l2clk__gclk clkgen_l2t0_cmp_gclk_if.l2clk; | |
| 2488 | pce_ov__gclk clkgen_l2t0_cmp_gclk_if.pce_ov; | |
| 2489 | por___gclk clkgen_l2t0_cmp_gclk_if.por_; | |
| 2490 | rst_por___gclk clkgen_l2t0_cmp_gclk_if.rst_por_; | |
| 2491 | rst_wmr___gclk clkgen_l2t0_cmp_gclk_if.rst_wmr_; | |
| 2492 | rst_wmr_protect__gclk clkgen_l2t0_cmp_gclk_if.rst_wmr_protect; | |
| 2493 | scan_en__gclk clkgen_l2t0_cmp_gclk_if.scan_en; | |
| 2494 | scan_in__gclk clkgen_l2t0_cmp_gclk_if.scan_in; | |
| 2495 | scan_out__gclk clkgen_l2t0_cmp_gclk_if.scan_out; | |
| 2496 | slow_cmp_sync_en__gclk clkgen_l2t0_cmp_gclk_if.slow_cmp_sync_en; | |
| 2497 | tcu_aclk__gclk clkgen_l2t0_cmp_gclk_if.tcu_aclk; | |
| 2498 | tcu_atpg_mode__gclk clkgen_l2t0_cmp_gclk_if.tcu_atpg_mode; | |
| 2499 | tcu_bclk__gclk clkgen_l2t0_cmp_gclk_if.tcu_bclk; | |
| 2500 | tcu_clk_stop__gclk clkgen_l2t0_cmp_gclk_if.tcu_clk_stop; | |
| 2501 | tcu_div_bypass__gclk clkgen_l2t0_cmp_gclk_if.tcu_div_bypass; | |
| 2502 | tcu_pce_ov__gclk clkgen_l2t0_cmp_gclk_if.tcu_pce_ov; | |
| 2503 | tcu_wr_inhibit__gclk clkgen_l2t0_cmp_gclk_if.tcu_wr_inhibit; | |
| 2504 | wmr___gclk clkgen_l2t0_cmp_gclk_if.wmr_; | |
| 2505 | wmr_protect__gclk clkgen_l2t0_cmp_gclk_if.wmr_protect; | |
| 2506 | pc_clk__gclk void; | |
| 2507 | pc_clk_sel__gclk void; | |
| 2508 | test_clk__gclk void; | |
| 2509 | test_clk_sel__gclk void; | |
| 2510 | ||
| 2511 | //---l2clk is Vera interface CLOCK--- | |
| 2512 | aclk__l2clk clkgen_l2t0_cmp_l2clk_if.aclk; | |
| 2513 | aclk_wmr__l2clk clkgen_l2t0_cmp_l2clk_if.aclk_wmr; | |
| 2514 | array_wr_inhibit__l2clk clkgen_l2t0_cmp_l2clk_if.array_wr_inhibit; | |
| 2515 | bclk__l2clk clkgen_l2t0_cmp_l2clk_if.bclk; | |
| 2516 | cmp_slow_sync_en__l2clk clkgen_l2t0_cmp_l2clk_if.cmp_slow_sync_en; | |
| 2517 | dr_sync_en__l2clk void; | |
| 2518 | io2x_sync_en__l2clk void; | |
| 2519 | l2clk clkgen_l2t0_cmp_l2clk_if.l2clk; | |
| 2520 | pce_ov__l2clk clkgen_l2t0_cmp_l2clk_if.pce_ov; | |
| 2521 | por___l2clk clkgen_l2t0_cmp_l2clk_if.por_; | |
| 2522 | scan_out__l2clk clkgen_l2t0_cmp_l2clk_if.scan_out; | |
| 2523 | slow_cmp_sync_en__l2clk clkgen_l2t0_cmp_l2clk_if.slow_cmp_sync_en; | |
| 2524 | wmr___l2clk clkgen_l2t0_cmp_l2clk_if.wmr_; | |
| 2525 | wmr_protect__l2clk clkgen_l2t0_cmp_l2clk_if.wmr_protect; | |
| 2526 | } | |
| 2527 | ||
| 2528 | //----- port binding for clkgen_l2t1_cmp ----- | |
| 2529 | ||
| 2530 | bind CLKGEN_port clkgen_l2t1_cmp_bind { | |
| 2531 | //---gclk is Vera interface CLOCK--- | |
| 2532 | aclk__gclk clkgen_l2t1_cmp_gclk_if.aclk; | |
| 2533 | aclk_wmr__gclk clkgen_l2t1_cmp_gclk_if.aclk_wmr; | |
| 2534 | array_wr_inhibit__gclk clkgen_l2t1_cmp_gclk_if.array_wr_inhibit; | |
| 2535 | bclk__gclk clkgen_l2t1_cmp_gclk_if.bclk; | |
| 2536 | ccu_cmp_slow_sync_en__gclk clkgen_l2t1_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 2537 | ccu_div_ph__gclk clkgen_l2t1_cmp_gclk_if.ccu_div_ph; | |
| 2538 | ccu_dr_sync_en__gclk void; | |
| 2539 | ccu_io2x_sync_en__gclk void; | |
| 2540 | ccu_serdes_dtm__gclk clkgen_l2t1_cmp_gclk_if.ccu_serdes_dtm; | |
| 2541 | ccu_slow_cmp_sync_en__gclk clkgen_l2t1_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 2542 | clk_ext__gclk clkgen_l2t1_cmp_gclk_if.clk_ext; | |
| 2543 | cluster_arst_l__gclk clkgen_l2t1_cmp_gclk_if.cluster_arst_l; | |
| 2544 | cluster_div_en__gclk clkgen_l2t1_cmp_gclk_if.cluster_div_en; | |
| 2545 | cmp_slow_sync_en__gclk clkgen_l2t1_cmp_gclk_if.cmp_slow_sync_en; | |
| 2546 | dr_sync_en__gclk void; | |
| 2547 | gclk clkgen_l2t1_cmp_gclk_if.gclk; | |
| 2548 | io2x_sync_en__gclk void; | |
| 2549 | l2clk__gclk clkgen_l2t1_cmp_gclk_if.l2clk; | |
| 2550 | pce_ov__gclk clkgen_l2t1_cmp_gclk_if.pce_ov; | |
| 2551 | por___gclk clkgen_l2t1_cmp_gclk_if.por_; | |
| 2552 | rst_por___gclk clkgen_l2t1_cmp_gclk_if.rst_por_; | |
| 2553 | rst_wmr___gclk clkgen_l2t1_cmp_gclk_if.rst_wmr_; | |
| 2554 | rst_wmr_protect__gclk clkgen_l2t1_cmp_gclk_if.rst_wmr_protect; | |
| 2555 | scan_en__gclk clkgen_l2t1_cmp_gclk_if.scan_en; | |
| 2556 | scan_in__gclk clkgen_l2t1_cmp_gclk_if.scan_in; | |
| 2557 | scan_out__gclk clkgen_l2t1_cmp_gclk_if.scan_out; | |
| 2558 | slow_cmp_sync_en__gclk clkgen_l2t1_cmp_gclk_if.slow_cmp_sync_en; | |
| 2559 | tcu_aclk__gclk clkgen_l2t1_cmp_gclk_if.tcu_aclk; | |
| 2560 | tcu_atpg_mode__gclk clkgen_l2t1_cmp_gclk_if.tcu_atpg_mode; | |
| 2561 | tcu_bclk__gclk clkgen_l2t1_cmp_gclk_if.tcu_bclk; | |
| 2562 | tcu_clk_stop__gclk clkgen_l2t1_cmp_gclk_if.tcu_clk_stop; | |
| 2563 | tcu_div_bypass__gclk clkgen_l2t1_cmp_gclk_if.tcu_div_bypass; | |
| 2564 | tcu_pce_ov__gclk clkgen_l2t1_cmp_gclk_if.tcu_pce_ov; | |
| 2565 | tcu_wr_inhibit__gclk clkgen_l2t1_cmp_gclk_if.tcu_wr_inhibit; | |
| 2566 | wmr___gclk clkgen_l2t1_cmp_gclk_if.wmr_; | |
| 2567 | wmr_protect__gclk clkgen_l2t1_cmp_gclk_if.wmr_protect; | |
| 2568 | pc_clk__gclk void; | |
| 2569 | pc_clk_sel__gclk void; | |
| 2570 | test_clk__gclk void; | |
| 2571 | test_clk_sel__gclk void; | |
| 2572 | ||
| 2573 | //---l2clk is Vera interface CLOCK--- | |
| 2574 | aclk__l2clk clkgen_l2t1_cmp_l2clk_if.aclk; | |
| 2575 | aclk_wmr__l2clk clkgen_l2t1_cmp_l2clk_if.aclk_wmr; | |
| 2576 | array_wr_inhibit__l2clk clkgen_l2t1_cmp_l2clk_if.array_wr_inhibit; | |
| 2577 | bclk__l2clk clkgen_l2t1_cmp_l2clk_if.bclk; | |
| 2578 | cmp_slow_sync_en__l2clk clkgen_l2t1_cmp_l2clk_if.cmp_slow_sync_en; | |
| 2579 | dr_sync_en__l2clk void; | |
| 2580 | io2x_sync_en__l2clk void; | |
| 2581 | l2clk clkgen_l2t1_cmp_l2clk_if.l2clk; | |
| 2582 | pce_ov__l2clk clkgen_l2t1_cmp_l2clk_if.pce_ov; | |
| 2583 | por___l2clk clkgen_l2t1_cmp_l2clk_if.por_; | |
| 2584 | scan_out__l2clk clkgen_l2t1_cmp_l2clk_if.scan_out; | |
| 2585 | slow_cmp_sync_en__l2clk clkgen_l2t1_cmp_l2clk_if.slow_cmp_sync_en; | |
| 2586 | wmr___l2clk clkgen_l2t1_cmp_l2clk_if.wmr_; | |
| 2587 | wmr_protect__l2clk clkgen_l2t1_cmp_l2clk_if.wmr_protect; | |
| 2588 | } | |
| 2589 | ||
| 2590 | //----- port binding for clkgen_l2t2_cmp ----- | |
| 2591 | ||
| 2592 | bind CLKGEN_port clkgen_l2t2_cmp_bind { | |
| 2593 | //---gclk is Vera interface CLOCK--- | |
| 2594 | aclk__gclk clkgen_l2t2_cmp_gclk_if.aclk; | |
| 2595 | aclk_wmr__gclk clkgen_l2t2_cmp_gclk_if.aclk_wmr; | |
| 2596 | array_wr_inhibit__gclk clkgen_l2t2_cmp_gclk_if.array_wr_inhibit; | |
| 2597 | bclk__gclk clkgen_l2t2_cmp_gclk_if.bclk; | |
| 2598 | ccu_cmp_slow_sync_en__gclk clkgen_l2t2_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 2599 | ccu_div_ph__gclk clkgen_l2t2_cmp_gclk_if.ccu_div_ph; | |
| 2600 | ccu_dr_sync_en__gclk void; | |
| 2601 | ccu_io2x_sync_en__gclk void; | |
| 2602 | ccu_serdes_dtm__gclk clkgen_l2t2_cmp_gclk_if.ccu_serdes_dtm; | |
| 2603 | ccu_slow_cmp_sync_en__gclk clkgen_l2t2_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 2604 | clk_ext__gclk clkgen_l2t2_cmp_gclk_if.clk_ext; | |
| 2605 | cluster_arst_l__gclk clkgen_l2t2_cmp_gclk_if.cluster_arst_l; | |
| 2606 | cluster_div_en__gclk clkgen_l2t2_cmp_gclk_if.cluster_div_en; | |
| 2607 | cmp_slow_sync_en__gclk clkgen_l2t2_cmp_gclk_if.cmp_slow_sync_en; | |
| 2608 | dr_sync_en__gclk void; | |
| 2609 | gclk clkgen_l2t2_cmp_gclk_if.gclk; | |
| 2610 | io2x_sync_en__gclk void; | |
| 2611 | l2clk__gclk clkgen_l2t2_cmp_gclk_if.l2clk; | |
| 2612 | pce_ov__gclk clkgen_l2t2_cmp_gclk_if.pce_ov; | |
| 2613 | por___gclk clkgen_l2t2_cmp_gclk_if.por_; | |
| 2614 | rst_por___gclk clkgen_l2t2_cmp_gclk_if.rst_por_; | |
| 2615 | rst_wmr___gclk clkgen_l2t2_cmp_gclk_if.rst_wmr_; | |
| 2616 | rst_wmr_protect__gclk clkgen_l2t2_cmp_gclk_if.rst_wmr_protect; | |
| 2617 | scan_en__gclk clkgen_l2t2_cmp_gclk_if.scan_en; | |
| 2618 | scan_in__gclk clkgen_l2t2_cmp_gclk_if.scan_in; | |
| 2619 | scan_out__gclk clkgen_l2t2_cmp_gclk_if.scan_out; | |
| 2620 | slow_cmp_sync_en__gclk clkgen_l2t2_cmp_gclk_if.slow_cmp_sync_en; | |
| 2621 | tcu_aclk__gclk clkgen_l2t2_cmp_gclk_if.tcu_aclk; | |
| 2622 | tcu_atpg_mode__gclk clkgen_l2t2_cmp_gclk_if.tcu_atpg_mode; | |
| 2623 | tcu_bclk__gclk clkgen_l2t2_cmp_gclk_if.tcu_bclk; | |
| 2624 | tcu_clk_stop__gclk clkgen_l2t2_cmp_gclk_if.tcu_clk_stop; | |
| 2625 | tcu_div_bypass__gclk clkgen_l2t2_cmp_gclk_if.tcu_div_bypass; | |
| 2626 | tcu_pce_ov__gclk clkgen_l2t2_cmp_gclk_if.tcu_pce_ov; | |
| 2627 | tcu_wr_inhibit__gclk clkgen_l2t2_cmp_gclk_if.tcu_wr_inhibit; | |
| 2628 | wmr___gclk clkgen_l2t2_cmp_gclk_if.wmr_; | |
| 2629 | wmr_protect__gclk clkgen_l2t2_cmp_gclk_if.wmr_protect; | |
| 2630 | pc_clk__gclk void; | |
| 2631 | pc_clk_sel__gclk void; | |
| 2632 | test_clk__gclk void; | |
| 2633 | test_clk_sel__gclk void; | |
| 2634 | ||
| 2635 | //---l2clk is Vera interface CLOCK--- | |
| 2636 | aclk__l2clk clkgen_l2t2_cmp_l2clk_if.aclk; | |
| 2637 | aclk_wmr__l2clk clkgen_l2t2_cmp_l2clk_if.aclk_wmr; | |
| 2638 | array_wr_inhibit__l2clk clkgen_l2t2_cmp_l2clk_if.array_wr_inhibit; | |
| 2639 | bclk__l2clk clkgen_l2t2_cmp_l2clk_if.bclk; | |
| 2640 | cmp_slow_sync_en__l2clk clkgen_l2t2_cmp_l2clk_if.cmp_slow_sync_en; | |
| 2641 | dr_sync_en__l2clk void; | |
| 2642 | io2x_sync_en__l2clk void; | |
| 2643 | l2clk clkgen_l2t2_cmp_l2clk_if.l2clk; | |
| 2644 | pce_ov__l2clk clkgen_l2t2_cmp_l2clk_if.pce_ov; | |
| 2645 | por___l2clk clkgen_l2t2_cmp_l2clk_if.por_; | |
| 2646 | scan_out__l2clk clkgen_l2t2_cmp_l2clk_if.scan_out; | |
| 2647 | slow_cmp_sync_en__l2clk clkgen_l2t2_cmp_l2clk_if.slow_cmp_sync_en; | |
| 2648 | wmr___l2clk clkgen_l2t2_cmp_l2clk_if.wmr_; | |
| 2649 | wmr_protect__l2clk clkgen_l2t2_cmp_l2clk_if.wmr_protect; | |
| 2650 | } | |
| 2651 | ||
| 2652 | //----- port binding for clkgen_l2t3_cmp ----- | |
| 2653 | ||
| 2654 | bind CLKGEN_port clkgen_l2t3_cmp_bind { | |
| 2655 | //---gclk is Vera interface CLOCK--- | |
| 2656 | aclk__gclk clkgen_l2t3_cmp_gclk_if.aclk; | |
| 2657 | aclk_wmr__gclk clkgen_l2t3_cmp_gclk_if.aclk_wmr; | |
| 2658 | array_wr_inhibit__gclk clkgen_l2t3_cmp_gclk_if.array_wr_inhibit; | |
| 2659 | bclk__gclk clkgen_l2t3_cmp_gclk_if.bclk; | |
| 2660 | ccu_cmp_slow_sync_en__gclk clkgen_l2t3_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 2661 | ccu_div_ph__gclk clkgen_l2t3_cmp_gclk_if.ccu_div_ph; | |
| 2662 | ccu_dr_sync_en__gclk void; | |
| 2663 | ccu_io2x_sync_en__gclk void; | |
| 2664 | ccu_serdes_dtm__gclk clkgen_l2t3_cmp_gclk_if.ccu_serdes_dtm; | |
| 2665 | ccu_slow_cmp_sync_en__gclk clkgen_l2t3_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 2666 | clk_ext__gclk clkgen_l2t3_cmp_gclk_if.clk_ext; | |
| 2667 | cluster_arst_l__gclk clkgen_l2t3_cmp_gclk_if.cluster_arst_l; | |
| 2668 | cluster_div_en__gclk clkgen_l2t3_cmp_gclk_if.cluster_div_en; | |
| 2669 | cmp_slow_sync_en__gclk clkgen_l2t3_cmp_gclk_if.cmp_slow_sync_en; | |
| 2670 | dr_sync_en__gclk void; | |
| 2671 | gclk clkgen_l2t3_cmp_gclk_if.gclk; | |
| 2672 | io2x_sync_en__gclk void; | |
| 2673 | l2clk__gclk clkgen_l2t3_cmp_gclk_if.l2clk; | |
| 2674 | pce_ov__gclk clkgen_l2t3_cmp_gclk_if.pce_ov; | |
| 2675 | por___gclk clkgen_l2t3_cmp_gclk_if.por_; | |
| 2676 | rst_por___gclk clkgen_l2t3_cmp_gclk_if.rst_por_; | |
| 2677 | rst_wmr___gclk clkgen_l2t3_cmp_gclk_if.rst_wmr_; | |
| 2678 | rst_wmr_protect__gclk clkgen_l2t3_cmp_gclk_if.rst_wmr_protect; | |
| 2679 | scan_en__gclk clkgen_l2t3_cmp_gclk_if.scan_en; | |
| 2680 | scan_in__gclk clkgen_l2t3_cmp_gclk_if.scan_in; | |
| 2681 | scan_out__gclk clkgen_l2t3_cmp_gclk_if.scan_out; | |
| 2682 | slow_cmp_sync_en__gclk clkgen_l2t3_cmp_gclk_if.slow_cmp_sync_en; | |
| 2683 | tcu_aclk__gclk clkgen_l2t3_cmp_gclk_if.tcu_aclk; | |
| 2684 | tcu_atpg_mode__gclk clkgen_l2t3_cmp_gclk_if.tcu_atpg_mode; | |
| 2685 | tcu_bclk__gclk clkgen_l2t3_cmp_gclk_if.tcu_bclk; | |
| 2686 | tcu_clk_stop__gclk clkgen_l2t3_cmp_gclk_if.tcu_clk_stop; | |
| 2687 | tcu_div_bypass__gclk clkgen_l2t3_cmp_gclk_if.tcu_div_bypass; | |
| 2688 | tcu_pce_ov__gclk clkgen_l2t3_cmp_gclk_if.tcu_pce_ov; | |
| 2689 | tcu_wr_inhibit__gclk clkgen_l2t3_cmp_gclk_if.tcu_wr_inhibit; | |
| 2690 | wmr___gclk clkgen_l2t3_cmp_gclk_if.wmr_; | |
| 2691 | wmr_protect__gclk clkgen_l2t3_cmp_gclk_if.wmr_protect; | |
| 2692 | pc_clk__gclk void; | |
| 2693 | pc_clk_sel__gclk void; | |
| 2694 | test_clk__gclk void; | |
| 2695 | test_clk_sel__gclk void; | |
| 2696 | ||
| 2697 | //---l2clk is Vera interface CLOCK--- | |
| 2698 | aclk__l2clk clkgen_l2t3_cmp_l2clk_if.aclk; | |
| 2699 | aclk_wmr__l2clk clkgen_l2t3_cmp_l2clk_if.aclk_wmr; | |
| 2700 | array_wr_inhibit__l2clk clkgen_l2t3_cmp_l2clk_if.array_wr_inhibit; | |
| 2701 | bclk__l2clk clkgen_l2t3_cmp_l2clk_if.bclk; | |
| 2702 | cmp_slow_sync_en__l2clk clkgen_l2t3_cmp_l2clk_if.cmp_slow_sync_en; | |
| 2703 | dr_sync_en__l2clk void; | |
| 2704 | io2x_sync_en__l2clk void; | |
| 2705 | l2clk clkgen_l2t3_cmp_l2clk_if.l2clk; | |
| 2706 | pce_ov__l2clk clkgen_l2t3_cmp_l2clk_if.pce_ov; | |
| 2707 | por___l2clk clkgen_l2t3_cmp_l2clk_if.por_; | |
| 2708 | scan_out__l2clk clkgen_l2t3_cmp_l2clk_if.scan_out; | |
| 2709 | slow_cmp_sync_en__l2clk clkgen_l2t3_cmp_l2clk_if.slow_cmp_sync_en; | |
| 2710 | wmr___l2clk clkgen_l2t3_cmp_l2clk_if.wmr_; | |
| 2711 | wmr_protect__l2clk clkgen_l2t3_cmp_l2clk_if.wmr_protect; | |
| 2712 | } | |
| 2713 | ||
| 2714 | //----- port binding for clkgen_l2t4_cmp ----- | |
| 2715 | ||
| 2716 | bind CLKGEN_port clkgen_l2t4_cmp_bind { | |
| 2717 | //---gclk is Vera interface CLOCK--- | |
| 2718 | aclk__gclk clkgen_l2t4_cmp_gclk_if.aclk; | |
| 2719 | aclk_wmr__gclk clkgen_l2t4_cmp_gclk_if.aclk_wmr; | |
| 2720 | array_wr_inhibit__gclk clkgen_l2t4_cmp_gclk_if.array_wr_inhibit; | |
| 2721 | bclk__gclk clkgen_l2t4_cmp_gclk_if.bclk; | |
| 2722 | ccu_cmp_slow_sync_en__gclk clkgen_l2t4_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 2723 | ccu_div_ph__gclk clkgen_l2t4_cmp_gclk_if.ccu_div_ph; | |
| 2724 | ccu_dr_sync_en__gclk void; | |
| 2725 | ccu_io2x_sync_en__gclk void; | |
| 2726 | ccu_serdes_dtm__gclk clkgen_l2t4_cmp_gclk_if.ccu_serdes_dtm; | |
| 2727 | ccu_slow_cmp_sync_en__gclk clkgen_l2t4_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 2728 | clk_ext__gclk clkgen_l2t4_cmp_gclk_if.clk_ext; | |
| 2729 | cluster_arst_l__gclk clkgen_l2t4_cmp_gclk_if.cluster_arst_l; | |
| 2730 | cluster_div_en__gclk clkgen_l2t4_cmp_gclk_if.cluster_div_en; | |
| 2731 | cmp_slow_sync_en__gclk clkgen_l2t4_cmp_gclk_if.cmp_slow_sync_en; | |
| 2732 | dr_sync_en__gclk void; | |
| 2733 | gclk clkgen_l2t4_cmp_gclk_if.gclk; | |
| 2734 | io2x_sync_en__gclk void; | |
| 2735 | l2clk__gclk clkgen_l2t4_cmp_gclk_if.l2clk; | |
| 2736 | pce_ov__gclk clkgen_l2t4_cmp_gclk_if.pce_ov; | |
| 2737 | por___gclk clkgen_l2t4_cmp_gclk_if.por_; | |
| 2738 | rst_por___gclk clkgen_l2t4_cmp_gclk_if.rst_por_; | |
| 2739 | rst_wmr___gclk clkgen_l2t4_cmp_gclk_if.rst_wmr_; | |
| 2740 | rst_wmr_protect__gclk clkgen_l2t4_cmp_gclk_if.rst_wmr_protect; | |
| 2741 | scan_en__gclk clkgen_l2t4_cmp_gclk_if.scan_en; | |
| 2742 | scan_in__gclk clkgen_l2t4_cmp_gclk_if.scan_in; | |
| 2743 | scan_out__gclk clkgen_l2t4_cmp_gclk_if.scan_out; | |
| 2744 | slow_cmp_sync_en__gclk clkgen_l2t4_cmp_gclk_if.slow_cmp_sync_en; | |
| 2745 | tcu_aclk__gclk clkgen_l2t4_cmp_gclk_if.tcu_aclk; | |
| 2746 | tcu_atpg_mode__gclk clkgen_l2t4_cmp_gclk_if.tcu_atpg_mode; | |
| 2747 | tcu_bclk__gclk clkgen_l2t4_cmp_gclk_if.tcu_bclk; | |
| 2748 | tcu_clk_stop__gclk clkgen_l2t4_cmp_gclk_if.tcu_clk_stop; | |
| 2749 | tcu_div_bypass__gclk clkgen_l2t4_cmp_gclk_if.tcu_div_bypass; | |
| 2750 | tcu_pce_ov__gclk clkgen_l2t4_cmp_gclk_if.tcu_pce_ov; | |
| 2751 | tcu_wr_inhibit__gclk clkgen_l2t4_cmp_gclk_if.tcu_wr_inhibit; | |
| 2752 | wmr___gclk clkgen_l2t4_cmp_gclk_if.wmr_; | |
| 2753 | wmr_protect__gclk clkgen_l2t4_cmp_gclk_if.wmr_protect; | |
| 2754 | pc_clk__gclk void; | |
| 2755 | pc_clk_sel__gclk void; | |
| 2756 | test_clk__gclk void; | |
| 2757 | test_clk_sel__gclk void; | |
| 2758 | ||
| 2759 | //---l2clk is Vera interface CLOCK--- | |
| 2760 | aclk__l2clk clkgen_l2t4_cmp_l2clk_if.aclk; | |
| 2761 | aclk_wmr__l2clk clkgen_l2t4_cmp_l2clk_if.aclk_wmr; | |
| 2762 | array_wr_inhibit__l2clk clkgen_l2t4_cmp_l2clk_if.array_wr_inhibit; | |
| 2763 | bclk__l2clk clkgen_l2t4_cmp_l2clk_if.bclk; | |
| 2764 | cmp_slow_sync_en__l2clk clkgen_l2t4_cmp_l2clk_if.cmp_slow_sync_en; | |
| 2765 | dr_sync_en__l2clk void; | |
| 2766 | io2x_sync_en__l2clk void; | |
| 2767 | l2clk clkgen_l2t4_cmp_l2clk_if.l2clk; | |
| 2768 | pce_ov__l2clk clkgen_l2t4_cmp_l2clk_if.pce_ov; | |
| 2769 | por___l2clk clkgen_l2t4_cmp_l2clk_if.por_; | |
| 2770 | scan_out__l2clk clkgen_l2t4_cmp_l2clk_if.scan_out; | |
| 2771 | slow_cmp_sync_en__l2clk clkgen_l2t4_cmp_l2clk_if.slow_cmp_sync_en; | |
| 2772 | wmr___l2clk clkgen_l2t4_cmp_l2clk_if.wmr_; | |
| 2773 | wmr_protect__l2clk clkgen_l2t4_cmp_l2clk_if.wmr_protect; | |
| 2774 | } | |
| 2775 | ||
| 2776 | //----- port binding for clkgen_l2t5_cmp ----- | |
| 2777 | ||
| 2778 | bind CLKGEN_port clkgen_l2t5_cmp_bind { | |
| 2779 | //---gclk is Vera interface CLOCK--- | |
| 2780 | aclk__gclk clkgen_l2t5_cmp_gclk_if.aclk; | |
| 2781 | aclk_wmr__gclk clkgen_l2t5_cmp_gclk_if.aclk_wmr; | |
| 2782 | array_wr_inhibit__gclk clkgen_l2t5_cmp_gclk_if.array_wr_inhibit; | |
| 2783 | bclk__gclk clkgen_l2t5_cmp_gclk_if.bclk; | |
| 2784 | ccu_cmp_slow_sync_en__gclk clkgen_l2t5_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 2785 | ccu_div_ph__gclk clkgen_l2t5_cmp_gclk_if.ccu_div_ph; | |
| 2786 | ccu_dr_sync_en__gclk void; | |
| 2787 | ccu_io2x_sync_en__gclk void; | |
| 2788 | ccu_serdes_dtm__gclk clkgen_l2t5_cmp_gclk_if.ccu_serdes_dtm; | |
| 2789 | ccu_slow_cmp_sync_en__gclk clkgen_l2t5_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 2790 | clk_ext__gclk clkgen_l2t5_cmp_gclk_if.clk_ext; | |
| 2791 | cluster_arst_l__gclk clkgen_l2t5_cmp_gclk_if.cluster_arst_l; | |
| 2792 | cluster_div_en__gclk clkgen_l2t5_cmp_gclk_if.cluster_div_en; | |
| 2793 | cmp_slow_sync_en__gclk clkgen_l2t5_cmp_gclk_if.cmp_slow_sync_en; | |
| 2794 | dr_sync_en__gclk void; | |
| 2795 | gclk clkgen_l2t5_cmp_gclk_if.gclk; | |
| 2796 | io2x_sync_en__gclk void; | |
| 2797 | l2clk__gclk clkgen_l2t5_cmp_gclk_if.l2clk; | |
| 2798 | pce_ov__gclk clkgen_l2t5_cmp_gclk_if.pce_ov; | |
| 2799 | por___gclk clkgen_l2t5_cmp_gclk_if.por_; | |
| 2800 | rst_por___gclk clkgen_l2t5_cmp_gclk_if.rst_por_; | |
| 2801 | rst_wmr___gclk clkgen_l2t5_cmp_gclk_if.rst_wmr_; | |
| 2802 | rst_wmr_protect__gclk clkgen_l2t5_cmp_gclk_if.rst_wmr_protect; | |
| 2803 | scan_en__gclk clkgen_l2t5_cmp_gclk_if.scan_en; | |
| 2804 | scan_in__gclk clkgen_l2t5_cmp_gclk_if.scan_in; | |
| 2805 | scan_out__gclk clkgen_l2t5_cmp_gclk_if.scan_out; | |
| 2806 | slow_cmp_sync_en__gclk clkgen_l2t5_cmp_gclk_if.slow_cmp_sync_en; | |
| 2807 | tcu_aclk__gclk clkgen_l2t5_cmp_gclk_if.tcu_aclk; | |
| 2808 | tcu_atpg_mode__gclk clkgen_l2t5_cmp_gclk_if.tcu_atpg_mode; | |
| 2809 | tcu_bclk__gclk clkgen_l2t5_cmp_gclk_if.tcu_bclk; | |
| 2810 | tcu_clk_stop__gclk clkgen_l2t5_cmp_gclk_if.tcu_clk_stop; | |
| 2811 | tcu_div_bypass__gclk clkgen_l2t5_cmp_gclk_if.tcu_div_bypass; | |
| 2812 | tcu_pce_ov__gclk clkgen_l2t5_cmp_gclk_if.tcu_pce_ov; | |
| 2813 | tcu_wr_inhibit__gclk clkgen_l2t5_cmp_gclk_if.tcu_wr_inhibit; | |
| 2814 | wmr___gclk clkgen_l2t5_cmp_gclk_if.wmr_; | |
| 2815 | wmr_protect__gclk clkgen_l2t5_cmp_gclk_if.wmr_protect; | |
| 2816 | pc_clk__gclk void; | |
| 2817 | pc_clk_sel__gclk void; | |
| 2818 | test_clk__gclk void; | |
| 2819 | test_clk_sel__gclk void; | |
| 2820 | ||
| 2821 | //---l2clk is Vera interface CLOCK--- | |
| 2822 | aclk__l2clk clkgen_l2t5_cmp_l2clk_if.aclk; | |
| 2823 | aclk_wmr__l2clk clkgen_l2t5_cmp_l2clk_if.aclk_wmr; | |
| 2824 | array_wr_inhibit__l2clk clkgen_l2t5_cmp_l2clk_if.array_wr_inhibit; | |
| 2825 | bclk__l2clk clkgen_l2t5_cmp_l2clk_if.bclk; | |
| 2826 | cmp_slow_sync_en__l2clk clkgen_l2t5_cmp_l2clk_if.cmp_slow_sync_en; | |
| 2827 | dr_sync_en__l2clk void; | |
| 2828 | io2x_sync_en__l2clk void; | |
| 2829 | l2clk clkgen_l2t5_cmp_l2clk_if.l2clk; | |
| 2830 | pce_ov__l2clk clkgen_l2t5_cmp_l2clk_if.pce_ov; | |
| 2831 | por___l2clk clkgen_l2t5_cmp_l2clk_if.por_; | |
| 2832 | scan_out__l2clk clkgen_l2t5_cmp_l2clk_if.scan_out; | |
| 2833 | slow_cmp_sync_en__l2clk clkgen_l2t5_cmp_l2clk_if.slow_cmp_sync_en; | |
| 2834 | wmr___l2clk clkgen_l2t5_cmp_l2clk_if.wmr_; | |
| 2835 | wmr_protect__l2clk clkgen_l2t5_cmp_l2clk_if.wmr_protect; | |
| 2836 | } | |
| 2837 | ||
| 2838 | //----- port binding for clkgen_l2t6_cmp ----- | |
| 2839 | ||
| 2840 | bind CLKGEN_port clkgen_l2t6_cmp_bind { | |
| 2841 | //---gclk is Vera interface CLOCK--- | |
| 2842 | aclk__gclk clkgen_l2t6_cmp_gclk_if.aclk; | |
| 2843 | aclk_wmr__gclk clkgen_l2t6_cmp_gclk_if.aclk_wmr; | |
| 2844 | array_wr_inhibit__gclk clkgen_l2t6_cmp_gclk_if.array_wr_inhibit; | |
| 2845 | bclk__gclk clkgen_l2t6_cmp_gclk_if.bclk; | |
| 2846 | ccu_cmp_slow_sync_en__gclk clkgen_l2t6_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 2847 | ccu_div_ph__gclk clkgen_l2t6_cmp_gclk_if.ccu_div_ph; | |
| 2848 | ccu_dr_sync_en__gclk void; | |
| 2849 | ccu_io2x_sync_en__gclk void; | |
| 2850 | ccu_serdes_dtm__gclk clkgen_l2t6_cmp_gclk_if.ccu_serdes_dtm; | |
| 2851 | ccu_slow_cmp_sync_en__gclk clkgen_l2t6_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 2852 | clk_ext__gclk clkgen_l2t6_cmp_gclk_if.clk_ext; | |
| 2853 | cluster_arst_l__gclk clkgen_l2t6_cmp_gclk_if.cluster_arst_l; | |
| 2854 | cluster_div_en__gclk clkgen_l2t6_cmp_gclk_if.cluster_div_en; | |
| 2855 | cmp_slow_sync_en__gclk clkgen_l2t6_cmp_gclk_if.cmp_slow_sync_en; | |
| 2856 | dr_sync_en__gclk void; | |
| 2857 | gclk clkgen_l2t6_cmp_gclk_if.gclk; | |
| 2858 | io2x_sync_en__gclk void; | |
| 2859 | l2clk__gclk clkgen_l2t6_cmp_gclk_if.l2clk; | |
| 2860 | pce_ov__gclk clkgen_l2t6_cmp_gclk_if.pce_ov; | |
| 2861 | por___gclk clkgen_l2t6_cmp_gclk_if.por_; | |
| 2862 | rst_por___gclk clkgen_l2t6_cmp_gclk_if.rst_por_; | |
| 2863 | rst_wmr___gclk clkgen_l2t6_cmp_gclk_if.rst_wmr_; | |
| 2864 | rst_wmr_protect__gclk clkgen_l2t6_cmp_gclk_if.rst_wmr_protect; | |
| 2865 | scan_en__gclk clkgen_l2t6_cmp_gclk_if.scan_en; | |
| 2866 | scan_in__gclk clkgen_l2t6_cmp_gclk_if.scan_in; | |
| 2867 | scan_out__gclk clkgen_l2t6_cmp_gclk_if.scan_out; | |
| 2868 | slow_cmp_sync_en__gclk clkgen_l2t6_cmp_gclk_if.slow_cmp_sync_en; | |
| 2869 | tcu_aclk__gclk clkgen_l2t6_cmp_gclk_if.tcu_aclk; | |
| 2870 | tcu_atpg_mode__gclk clkgen_l2t6_cmp_gclk_if.tcu_atpg_mode; | |
| 2871 | tcu_bclk__gclk clkgen_l2t6_cmp_gclk_if.tcu_bclk; | |
| 2872 | tcu_clk_stop__gclk clkgen_l2t6_cmp_gclk_if.tcu_clk_stop; | |
| 2873 | tcu_div_bypass__gclk clkgen_l2t6_cmp_gclk_if.tcu_div_bypass; | |
| 2874 | tcu_pce_ov__gclk clkgen_l2t6_cmp_gclk_if.tcu_pce_ov; | |
| 2875 | tcu_wr_inhibit__gclk clkgen_l2t6_cmp_gclk_if.tcu_wr_inhibit; | |
| 2876 | wmr___gclk clkgen_l2t6_cmp_gclk_if.wmr_; | |
| 2877 | wmr_protect__gclk clkgen_l2t6_cmp_gclk_if.wmr_protect; | |
| 2878 | pc_clk__gclk void; | |
| 2879 | pc_clk_sel__gclk void; | |
| 2880 | test_clk__gclk void; | |
| 2881 | test_clk_sel__gclk void; | |
| 2882 | ||
| 2883 | //---l2clk is Vera interface CLOCK--- | |
| 2884 | aclk__l2clk clkgen_l2t6_cmp_l2clk_if.aclk; | |
| 2885 | aclk_wmr__l2clk clkgen_l2t6_cmp_l2clk_if.aclk_wmr; | |
| 2886 | array_wr_inhibit__l2clk clkgen_l2t6_cmp_l2clk_if.array_wr_inhibit; | |
| 2887 | bclk__l2clk clkgen_l2t6_cmp_l2clk_if.bclk; | |
| 2888 | cmp_slow_sync_en__l2clk clkgen_l2t6_cmp_l2clk_if.cmp_slow_sync_en; | |
| 2889 | dr_sync_en__l2clk void; | |
| 2890 | io2x_sync_en__l2clk void; | |
| 2891 | l2clk clkgen_l2t6_cmp_l2clk_if.l2clk; | |
| 2892 | pce_ov__l2clk clkgen_l2t6_cmp_l2clk_if.pce_ov; | |
| 2893 | por___l2clk clkgen_l2t6_cmp_l2clk_if.por_; | |
| 2894 | scan_out__l2clk clkgen_l2t6_cmp_l2clk_if.scan_out; | |
| 2895 | slow_cmp_sync_en__l2clk clkgen_l2t6_cmp_l2clk_if.slow_cmp_sync_en; | |
| 2896 | wmr___l2clk clkgen_l2t6_cmp_l2clk_if.wmr_; | |
| 2897 | wmr_protect__l2clk clkgen_l2t6_cmp_l2clk_if.wmr_protect; | |
| 2898 | } | |
| 2899 | ||
| 2900 | //----- port binding for clkgen_l2t7_cmp ----- | |
| 2901 | ||
| 2902 | bind CLKGEN_port clkgen_l2t7_cmp_bind { | |
| 2903 | //---gclk is Vera interface CLOCK--- | |
| 2904 | aclk__gclk clkgen_l2t7_cmp_gclk_if.aclk; | |
| 2905 | aclk_wmr__gclk clkgen_l2t7_cmp_gclk_if.aclk_wmr; | |
| 2906 | array_wr_inhibit__gclk clkgen_l2t7_cmp_gclk_if.array_wr_inhibit; | |
| 2907 | bclk__gclk clkgen_l2t7_cmp_gclk_if.bclk; | |
| 2908 | ccu_cmp_slow_sync_en__gclk clkgen_l2t7_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 2909 | ccu_div_ph__gclk clkgen_l2t7_cmp_gclk_if.ccu_div_ph; | |
| 2910 | ccu_dr_sync_en__gclk void; | |
| 2911 | ccu_io2x_sync_en__gclk void; | |
| 2912 | ccu_serdes_dtm__gclk clkgen_l2t7_cmp_gclk_if.ccu_serdes_dtm; | |
| 2913 | ccu_slow_cmp_sync_en__gclk clkgen_l2t7_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 2914 | clk_ext__gclk clkgen_l2t7_cmp_gclk_if.clk_ext; | |
| 2915 | cluster_arst_l__gclk clkgen_l2t7_cmp_gclk_if.cluster_arst_l; | |
| 2916 | cluster_div_en__gclk clkgen_l2t7_cmp_gclk_if.cluster_div_en; | |
| 2917 | cmp_slow_sync_en__gclk clkgen_l2t7_cmp_gclk_if.cmp_slow_sync_en; | |
| 2918 | dr_sync_en__gclk void; | |
| 2919 | gclk clkgen_l2t7_cmp_gclk_if.gclk; | |
| 2920 | io2x_sync_en__gclk void; | |
| 2921 | l2clk__gclk clkgen_l2t7_cmp_gclk_if.l2clk; | |
| 2922 | pce_ov__gclk clkgen_l2t7_cmp_gclk_if.pce_ov; | |
| 2923 | por___gclk clkgen_l2t7_cmp_gclk_if.por_; | |
| 2924 | rst_por___gclk clkgen_l2t7_cmp_gclk_if.rst_por_; | |
| 2925 | rst_wmr___gclk clkgen_l2t7_cmp_gclk_if.rst_wmr_; | |
| 2926 | rst_wmr_protect__gclk clkgen_l2t7_cmp_gclk_if.rst_wmr_protect; | |
| 2927 | scan_en__gclk clkgen_l2t7_cmp_gclk_if.scan_en; | |
| 2928 | scan_in__gclk clkgen_l2t7_cmp_gclk_if.scan_in; | |
| 2929 | scan_out__gclk clkgen_l2t7_cmp_gclk_if.scan_out; | |
| 2930 | slow_cmp_sync_en__gclk clkgen_l2t7_cmp_gclk_if.slow_cmp_sync_en; | |
| 2931 | tcu_aclk__gclk clkgen_l2t7_cmp_gclk_if.tcu_aclk; | |
| 2932 | tcu_atpg_mode__gclk clkgen_l2t7_cmp_gclk_if.tcu_atpg_mode; | |
| 2933 | tcu_bclk__gclk clkgen_l2t7_cmp_gclk_if.tcu_bclk; | |
| 2934 | tcu_clk_stop__gclk clkgen_l2t7_cmp_gclk_if.tcu_clk_stop; | |
| 2935 | tcu_div_bypass__gclk clkgen_l2t7_cmp_gclk_if.tcu_div_bypass; | |
| 2936 | tcu_pce_ov__gclk clkgen_l2t7_cmp_gclk_if.tcu_pce_ov; | |
| 2937 | tcu_wr_inhibit__gclk clkgen_l2t7_cmp_gclk_if.tcu_wr_inhibit; | |
| 2938 | wmr___gclk clkgen_l2t7_cmp_gclk_if.wmr_; | |
| 2939 | wmr_protect__gclk clkgen_l2t7_cmp_gclk_if.wmr_protect; | |
| 2940 | pc_clk__gclk void; | |
| 2941 | pc_clk_sel__gclk void; | |
| 2942 | test_clk__gclk void; | |
| 2943 | test_clk_sel__gclk void; | |
| 2944 | ||
| 2945 | //---l2clk is Vera interface CLOCK--- | |
| 2946 | aclk__l2clk clkgen_l2t7_cmp_l2clk_if.aclk; | |
| 2947 | aclk_wmr__l2clk clkgen_l2t7_cmp_l2clk_if.aclk_wmr; | |
| 2948 | array_wr_inhibit__l2clk clkgen_l2t7_cmp_l2clk_if.array_wr_inhibit; | |
| 2949 | bclk__l2clk clkgen_l2t7_cmp_l2clk_if.bclk; | |
| 2950 | cmp_slow_sync_en__l2clk clkgen_l2t7_cmp_l2clk_if.cmp_slow_sync_en; | |
| 2951 | dr_sync_en__l2clk void; | |
| 2952 | io2x_sync_en__l2clk void; | |
| 2953 | l2clk clkgen_l2t7_cmp_l2clk_if.l2clk; | |
| 2954 | pce_ov__l2clk clkgen_l2t7_cmp_l2clk_if.pce_ov; | |
| 2955 | por___l2clk clkgen_l2t7_cmp_l2clk_if.por_; | |
| 2956 | scan_out__l2clk clkgen_l2t7_cmp_l2clk_if.scan_out; | |
| 2957 | slow_cmp_sync_en__l2clk clkgen_l2t7_cmp_l2clk_if.slow_cmp_sync_en; | |
| 2958 | wmr___l2clk clkgen_l2t7_cmp_l2clk_if.wmr_; | |
| 2959 | wmr_protect__l2clk clkgen_l2t7_cmp_l2clk_if.wmr_protect; | |
| 2960 | } | |
| 2961 | ||
| 2962 | #ifndef FC_NO_NIU_T2 | |
| 2963 | #ifndef NIU_SYSTEMC_T2 | |
| 2964 | //----- port binding for clkgen_mac_io ----- | |
| 2965 | ||
| 2966 | bind CLKGEN_port clkgen_mac_io_bind { | |
| 2967 | //---gclk is Vera interface CLOCK--- | |
| 2968 | aclk__gclk clkgen_mac_io_gclk_if.aclk; | |
| 2969 | aclk_wmr__gclk clkgen_mac_io_gclk_if.aclk_wmr; | |
| 2970 | array_wr_inhibit__gclk clkgen_mac_io_gclk_if.array_wr_inhibit; | |
| 2971 | bclk__gclk clkgen_mac_io_gclk_if.bclk; | |
| 2972 | ccu_cmp_slow_sync_en__gclk clkgen_mac_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 2973 | ccu_div_ph__gclk clkgen_mac_io_gclk_if.ccu_div_ph; | |
| 2974 | ccu_dr_sync_en__gclk void; | |
| 2975 | ccu_io2x_sync_en__gclk void; | |
| 2976 | ccu_serdes_dtm__gclk clkgen_mac_io_gclk_if.ccu_serdes_dtm; | |
| 2977 | ccu_slow_cmp_sync_en__gclk clkgen_mac_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 2978 | clk_ext__gclk clkgen_mac_io_gclk_if.clk_ext; | |
| 2979 | cluster_arst_l__gclk clkgen_mac_io_gclk_if.cluster_arst_l; | |
| 2980 | cluster_div_en__gclk clkgen_mac_io_gclk_if.cluster_div_en; | |
| 2981 | cmp_slow_sync_en__gclk clkgen_mac_io_gclk_if.cmp_slow_sync_en; | |
| 2982 | dr_sync_en__gclk void; | |
| 2983 | gclk clkgen_mac_io_gclk_if.gclk; | |
| 2984 | io2x_sync_en__gclk void; | |
| 2985 | l2clk__gclk clkgen_mac_io_gclk_if.l2clk; | |
| 2986 | pce_ov__gclk clkgen_mac_io_gclk_if.pce_ov; | |
| 2987 | por___gclk clkgen_mac_io_gclk_if.por_; | |
| 2988 | rst_por___gclk clkgen_mac_io_gclk_if.rst_por_; | |
| 2989 | rst_wmr___gclk clkgen_mac_io_gclk_if.rst_wmr_; | |
| 2990 | rst_wmr_protect__gclk clkgen_mac_io_gclk_if.rst_wmr_protect; | |
| 2991 | scan_en__gclk clkgen_mac_io_gclk_if.scan_en; | |
| 2992 | scan_in__gclk clkgen_mac_io_gclk_if.scan_in; | |
| 2993 | scan_out__gclk clkgen_mac_io_gclk_if.scan_out; | |
| 2994 | slow_cmp_sync_en__gclk clkgen_mac_io_gclk_if.slow_cmp_sync_en; | |
| 2995 | tcu_aclk__gclk clkgen_mac_io_gclk_if.tcu_aclk; | |
| 2996 | tcu_atpg_mode__gclk clkgen_mac_io_gclk_if.tcu_atpg_mode; | |
| 2997 | tcu_bclk__gclk clkgen_mac_io_gclk_if.tcu_bclk; | |
| 2998 | tcu_clk_stop__gclk clkgen_mac_io_gclk_if.tcu_clk_stop; | |
| 2999 | tcu_div_bypass__gclk clkgen_mac_io_gclk_if.tcu_div_bypass; | |
| 3000 | tcu_pce_ov__gclk clkgen_mac_io_gclk_if.tcu_pce_ov; | |
| 3001 | tcu_wr_inhibit__gclk clkgen_mac_io_gclk_if.tcu_wr_inhibit; | |
| 3002 | wmr___gclk clkgen_mac_io_gclk_if.wmr_; | |
| 3003 | wmr_protect__gclk clkgen_mac_io_gclk_if.wmr_protect; | |
| 3004 | pc_clk__gclk void; | |
| 3005 | pc_clk_sel__gclk void; | |
| 3006 | test_clk__gclk void; | |
| 3007 | test_clk_sel__gclk void; | |
| 3008 | ||
| 3009 | //---l2clk is Vera interface CLOCK--- | |
| 3010 | aclk__l2clk clkgen_mac_io_l2clk_if.aclk; | |
| 3011 | aclk_wmr__l2clk clkgen_mac_io_l2clk_if.aclk_wmr; | |
| 3012 | array_wr_inhibit__l2clk clkgen_mac_io_l2clk_if.array_wr_inhibit; | |
| 3013 | bclk__l2clk clkgen_mac_io_l2clk_if.bclk; | |
| 3014 | cmp_slow_sync_en__l2clk clkgen_mac_io_l2clk_if.cmp_slow_sync_en; | |
| 3015 | dr_sync_en__l2clk void; | |
| 3016 | io2x_sync_en__l2clk void; | |
| 3017 | l2clk clkgen_mac_io_l2clk_if.l2clk; | |
| 3018 | pce_ov__l2clk clkgen_mac_io_l2clk_if.pce_ov; | |
| 3019 | por___l2clk clkgen_mac_io_l2clk_if.por_; | |
| 3020 | scan_out__l2clk clkgen_mac_io_l2clk_if.scan_out; | |
| 3021 | slow_cmp_sync_en__l2clk clkgen_mac_io_l2clk_if.slow_cmp_sync_en; | |
| 3022 | wmr___l2clk clkgen_mac_io_l2clk_if.wmr_; | |
| 3023 | wmr_protect__l2clk clkgen_mac_io_l2clk_if.wmr_protect; | |
| 3024 | } | |
| 3025 | #endif | |
| 3026 | #endif | |
| 3027 | ||
| 3028 | //----- port binding for clkgen_mcu0_cmp ----- | |
| 3029 | ||
| 3030 | bind CLKGEN_port clkgen_mcu0_cmp_bind { | |
| 3031 | //---gclk is Vera interface CLOCK--- | |
| 3032 | aclk__gclk clkgen_mcu0_cmp_gclk_if.aclk; | |
| 3033 | aclk_wmr__gclk clkgen_mcu0_cmp_gclk_if.aclk_wmr; | |
| 3034 | array_wr_inhibit__gclk clkgen_mcu0_cmp_gclk_if.array_wr_inhibit; | |
| 3035 | bclk__gclk clkgen_mcu0_cmp_gclk_if.bclk; | |
| 3036 | ccu_cmp_slow_sync_en__gclk clkgen_mcu0_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 3037 | ccu_div_ph__gclk clkgen_mcu0_cmp_gclk_if.ccu_div_ph; | |
| 3038 | ccu_dr_sync_en__gclk clkgen_mcu0_cmp_gclk_if.ccu_dr_sync_en; | |
| 3039 | ccu_io2x_sync_en__gclk clkgen_mcu0_cmp_gclk_if.ccu_io2x_sync_en; | |
| 3040 | ccu_serdes_dtm__gclk clkgen_mcu0_cmp_gclk_if.ccu_serdes_dtm; | |
| 3041 | ccu_slow_cmp_sync_en__gclk clkgen_mcu0_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 3042 | clk_ext__gclk clkgen_mcu0_cmp_gclk_if.clk_ext; | |
| 3043 | cluster_arst_l__gclk clkgen_mcu0_cmp_gclk_if.cluster_arst_l; | |
| 3044 | cluster_div_en__gclk clkgen_mcu0_cmp_gclk_if.cluster_div_en; | |
| 3045 | cmp_slow_sync_en__gclk clkgen_mcu0_cmp_gclk_if.cmp_slow_sync_en; | |
| 3046 | dr_sync_en__gclk clkgen_mcu0_cmp_gclk_if.dr_sync_en; | |
| 3047 | gclk clkgen_mcu0_cmp_gclk_if.gclk; | |
| 3048 | io2x_sync_en__gclk clkgen_mcu0_cmp_gclk_if.io2x_sync_en; | |
| 3049 | l2clk__gclk clkgen_mcu0_cmp_gclk_if.l2clk; | |
| 3050 | pce_ov__gclk clkgen_mcu0_cmp_gclk_if.pce_ov; | |
| 3051 | por___gclk clkgen_mcu0_cmp_gclk_if.por_; | |
| 3052 | rst_por___gclk clkgen_mcu0_cmp_gclk_if.rst_por_; | |
| 3053 | rst_wmr___gclk clkgen_mcu0_cmp_gclk_if.rst_wmr_; | |
| 3054 | rst_wmr_protect__gclk clkgen_mcu0_cmp_gclk_if.rst_wmr_protect; | |
| 3055 | scan_en__gclk clkgen_mcu0_cmp_gclk_if.scan_en; | |
| 3056 | scan_in__gclk clkgen_mcu0_cmp_gclk_if.scan_in; | |
| 3057 | scan_out__gclk clkgen_mcu0_cmp_gclk_if.scan_out; | |
| 3058 | slow_cmp_sync_en__gclk clkgen_mcu0_cmp_gclk_if.slow_cmp_sync_en; | |
| 3059 | tcu_aclk__gclk clkgen_mcu0_cmp_gclk_if.tcu_aclk; | |
| 3060 | tcu_atpg_mode__gclk clkgen_mcu0_cmp_gclk_if.tcu_atpg_mode; | |
| 3061 | tcu_bclk__gclk clkgen_mcu0_cmp_gclk_if.tcu_bclk; | |
| 3062 | tcu_clk_stop__gclk clkgen_mcu0_cmp_gclk_if.tcu_clk_stop; | |
| 3063 | tcu_div_bypass__gclk clkgen_mcu0_cmp_gclk_if.tcu_div_bypass; | |
| 3064 | tcu_pce_ov__gclk clkgen_mcu0_cmp_gclk_if.tcu_pce_ov; | |
| 3065 | tcu_wr_inhibit__gclk clkgen_mcu0_cmp_gclk_if.tcu_wr_inhibit; | |
| 3066 | wmr___gclk clkgen_mcu0_cmp_gclk_if.wmr_; | |
| 3067 | wmr_protect__gclk clkgen_mcu0_cmp_gclk_if.wmr_protect; | |
| 3068 | pc_clk__gclk void; | |
| 3069 | pc_clk_sel__gclk void; | |
| 3070 | test_clk__gclk void; | |
| 3071 | test_clk_sel__gclk void; | |
| 3072 | ||
| 3073 | //---l2clk is Vera interface CLOCK--- | |
| 3074 | aclk__l2clk clkgen_mcu0_cmp_l2clk_if.aclk; | |
| 3075 | aclk_wmr__l2clk clkgen_mcu0_cmp_l2clk_if.aclk_wmr; | |
| 3076 | array_wr_inhibit__l2clk clkgen_mcu0_cmp_l2clk_if.array_wr_inhibit; | |
| 3077 | bclk__l2clk clkgen_mcu0_cmp_l2clk_if.bclk; | |
| 3078 | cmp_slow_sync_en__l2clk clkgen_mcu0_cmp_l2clk_if.cmp_slow_sync_en; | |
| 3079 | dr_sync_en__l2clk clkgen_mcu0_cmp_l2clk_if.dr_sync_en; | |
| 3080 | io2x_sync_en__l2clk clkgen_mcu0_cmp_l2clk_if.io2x_sync_en; | |
| 3081 | l2clk clkgen_mcu0_cmp_l2clk_if.l2clk; | |
| 3082 | pce_ov__l2clk clkgen_mcu0_cmp_l2clk_if.pce_ov; | |
| 3083 | por___l2clk clkgen_mcu0_cmp_l2clk_if.por_; | |
| 3084 | scan_out__l2clk clkgen_mcu0_cmp_l2clk_if.scan_out; | |
| 3085 | slow_cmp_sync_en__l2clk clkgen_mcu0_cmp_l2clk_if.slow_cmp_sync_en; | |
| 3086 | wmr___l2clk clkgen_mcu0_cmp_l2clk_if.wmr_; | |
| 3087 | wmr_protect__l2clk clkgen_mcu0_cmp_l2clk_if.wmr_protect; | |
| 3088 | } | |
| 3089 | ||
| 3090 | //----- port binding for clkgen_mcu0_dr ----- | |
| 3091 | ||
| 3092 | bind CLKGEN_port clkgen_mcu0_dr_bind { | |
| 3093 | //---gclk is Vera interface CLOCK--- | |
| 3094 | aclk__gclk clkgen_mcu0_dr_gclk_if.aclk; | |
| 3095 | aclk_wmr__gclk clkgen_mcu0_dr_gclk_if.aclk_wmr; | |
| 3096 | array_wr_inhibit__gclk clkgen_mcu0_dr_gclk_if.array_wr_inhibit; | |
| 3097 | bclk__gclk clkgen_mcu0_dr_gclk_if.bclk; | |
| 3098 | ccu_cmp_slow_sync_en__gclk clkgen_mcu0_dr_gclk_if.ccu_cmp_slow_sync_en; | |
| 3099 | ccu_div_ph__gclk clkgen_mcu0_dr_gclk_if.ccu_div_ph; | |
| 3100 | ccu_dr_sync_en__gclk void; | |
| 3101 | ccu_io2x_sync_en__gclk void; | |
| 3102 | ccu_serdes_dtm__gclk clkgen_mcu0_dr_gclk_if.ccu_serdes_dtm; | |
| 3103 | ccu_slow_cmp_sync_en__gclk clkgen_mcu0_dr_gclk_if.ccu_slow_cmp_sync_en; | |
| 3104 | clk_ext__gclk clkgen_mcu0_dr_gclk_if.clk_ext; | |
| 3105 | cluster_arst_l__gclk clkgen_mcu0_dr_gclk_if.cluster_arst_l; | |
| 3106 | cluster_div_en__gclk clkgen_mcu0_dr_gclk_if.cluster_div_en; | |
| 3107 | cmp_slow_sync_en__gclk clkgen_mcu0_dr_gclk_if.cmp_slow_sync_en; | |
| 3108 | dr_sync_en__gclk void; | |
| 3109 | gclk clkgen_mcu0_dr_gclk_if.gclk; | |
| 3110 | io2x_sync_en__gclk void; | |
| 3111 | l2clk__gclk clkgen_mcu0_dr_gclk_if.l2clk; | |
| 3112 | pce_ov__gclk clkgen_mcu0_dr_gclk_if.pce_ov; | |
| 3113 | por___gclk clkgen_mcu0_dr_gclk_if.por_; | |
| 3114 | rst_por___gclk clkgen_mcu0_dr_gclk_if.rst_por_; | |
| 3115 | rst_wmr___gclk clkgen_mcu0_dr_gclk_if.rst_wmr_; | |
| 3116 | rst_wmr_protect__gclk clkgen_mcu0_dr_gclk_if.rst_wmr_protect; | |
| 3117 | scan_en__gclk clkgen_mcu0_dr_gclk_if.scan_en; | |
| 3118 | scan_in__gclk clkgen_mcu0_dr_gclk_if.scan_in; | |
| 3119 | scan_out__gclk clkgen_mcu0_dr_gclk_if.scan_out; | |
| 3120 | slow_cmp_sync_en__gclk clkgen_mcu0_dr_gclk_if.slow_cmp_sync_en; | |
| 3121 | tcu_aclk__gclk clkgen_mcu0_dr_gclk_if.tcu_aclk; | |
| 3122 | tcu_atpg_mode__gclk clkgen_mcu0_dr_gclk_if.tcu_atpg_mode; | |
| 3123 | tcu_bclk__gclk clkgen_mcu0_dr_gclk_if.tcu_bclk; | |
| 3124 | tcu_clk_stop__gclk clkgen_mcu0_dr_gclk_if.tcu_clk_stop; | |
| 3125 | tcu_div_bypass__gclk clkgen_mcu0_dr_gclk_if.tcu_div_bypass; | |
| 3126 | tcu_pce_ov__gclk clkgen_mcu0_dr_gclk_if.tcu_pce_ov; | |
| 3127 | tcu_wr_inhibit__gclk clkgen_mcu0_dr_gclk_if.tcu_wr_inhibit; | |
| 3128 | wmr___gclk clkgen_mcu0_dr_gclk_if.wmr_; | |
| 3129 | wmr_protect__gclk clkgen_mcu0_dr_gclk_if.wmr_protect; | |
| 3130 | pc_clk__gclk void; | |
| 3131 | pc_clk_sel__gclk void; | |
| 3132 | test_clk__gclk void; | |
| 3133 | test_clk_sel__gclk void; | |
| 3134 | ||
| 3135 | //---l2clk is Vera interface CLOCK--- | |
| 3136 | aclk__l2clk clkgen_mcu0_dr_l2clk_if.aclk; | |
| 3137 | aclk_wmr__l2clk clkgen_mcu0_dr_l2clk_if.aclk_wmr; | |
| 3138 | array_wr_inhibit__l2clk clkgen_mcu0_dr_l2clk_if.array_wr_inhibit; | |
| 3139 | bclk__l2clk clkgen_mcu0_dr_l2clk_if.bclk; | |
| 3140 | cmp_slow_sync_en__l2clk clkgen_mcu0_dr_l2clk_if.cmp_slow_sync_en; | |
| 3141 | dr_sync_en__l2clk void; | |
| 3142 | io2x_sync_en__l2clk void; | |
| 3143 | l2clk clkgen_mcu0_dr_l2clk_if.l2clk; | |
| 3144 | pce_ov__l2clk clkgen_mcu0_dr_l2clk_if.pce_ov; | |
| 3145 | por___l2clk clkgen_mcu0_dr_l2clk_if.por_; | |
| 3146 | scan_out__l2clk clkgen_mcu0_dr_l2clk_if.scan_out; | |
| 3147 | slow_cmp_sync_en__l2clk clkgen_mcu0_dr_l2clk_if.slow_cmp_sync_en; | |
| 3148 | wmr___l2clk clkgen_mcu0_dr_l2clk_if.wmr_; | |
| 3149 | wmr_protect__l2clk clkgen_mcu0_dr_l2clk_if.wmr_protect; | |
| 3150 | } | |
| 3151 | ||
| 3152 | //----- port binding for clkgen_mcu0_io ----- | |
| 3153 | ||
| 3154 | bind CLKGEN_port clkgen_mcu0_io_bind { | |
| 3155 | //---gclk is Vera interface CLOCK--- | |
| 3156 | aclk__gclk clkgen_mcu0_io_gclk_if.aclk; | |
| 3157 | aclk_wmr__gclk clkgen_mcu0_io_gclk_if.aclk_wmr; | |
| 3158 | array_wr_inhibit__gclk clkgen_mcu0_io_gclk_if.array_wr_inhibit; | |
| 3159 | bclk__gclk clkgen_mcu0_io_gclk_if.bclk; | |
| 3160 | ccu_cmp_slow_sync_en__gclk clkgen_mcu0_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 3161 | ccu_div_ph__gclk clkgen_mcu0_io_gclk_if.ccu_div_ph; | |
| 3162 | ccu_dr_sync_en__gclk void; | |
| 3163 | ccu_io2x_sync_en__gclk void; | |
| 3164 | ccu_serdes_dtm__gclk clkgen_mcu0_io_gclk_if.ccu_serdes_dtm; | |
| 3165 | ccu_slow_cmp_sync_en__gclk clkgen_mcu0_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 3166 | clk_ext__gclk clkgen_mcu0_io_gclk_if.clk_ext; | |
| 3167 | cluster_arst_l__gclk clkgen_mcu0_io_gclk_if.cluster_arst_l; | |
| 3168 | cluster_div_en__gclk clkgen_mcu0_io_gclk_if.cluster_div_en; | |
| 3169 | cmp_slow_sync_en__gclk clkgen_mcu0_io_gclk_if.cmp_slow_sync_en; | |
| 3170 | dr_sync_en__gclk void; | |
| 3171 | gclk clkgen_mcu0_io_gclk_if.gclk; | |
| 3172 | io2x_sync_en__gclk void; | |
| 3173 | l2clk__gclk clkgen_mcu0_io_gclk_if.l2clk; | |
| 3174 | pce_ov__gclk clkgen_mcu0_io_gclk_if.pce_ov; | |
| 3175 | por___gclk clkgen_mcu0_io_gclk_if.por_; | |
| 3176 | rst_por___gclk clkgen_mcu0_io_gclk_if.rst_por_; | |
| 3177 | rst_wmr___gclk clkgen_mcu0_io_gclk_if.rst_wmr_; | |
| 3178 | rst_wmr_protect__gclk clkgen_mcu0_io_gclk_if.rst_wmr_protect; | |
| 3179 | scan_en__gclk clkgen_mcu0_io_gclk_if.scan_en; | |
| 3180 | scan_in__gclk clkgen_mcu0_io_gclk_if.scan_in; | |
| 3181 | scan_out__gclk clkgen_mcu0_io_gclk_if.scan_out; | |
| 3182 | slow_cmp_sync_en__gclk clkgen_mcu0_io_gclk_if.slow_cmp_sync_en; | |
| 3183 | tcu_aclk__gclk clkgen_mcu0_io_gclk_if.tcu_aclk; | |
| 3184 | tcu_atpg_mode__gclk clkgen_mcu0_io_gclk_if.tcu_atpg_mode; | |
| 3185 | tcu_bclk__gclk clkgen_mcu0_io_gclk_if.tcu_bclk; | |
| 3186 | tcu_clk_stop__gclk clkgen_mcu0_io_gclk_if.tcu_clk_stop; | |
| 3187 | tcu_div_bypass__gclk clkgen_mcu0_io_gclk_if.tcu_div_bypass; | |
| 3188 | tcu_pce_ov__gclk clkgen_mcu0_io_gclk_if.tcu_pce_ov; | |
| 3189 | tcu_wr_inhibit__gclk clkgen_mcu0_io_gclk_if.tcu_wr_inhibit; | |
| 3190 | wmr___gclk clkgen_mcu0_io_gclk_if.wmr_; | |
| 3191 | wmr_protect__gclk clkgen_mcu0_io_gclk_if.wmr_protect; | |
| 3192 | pc_clk__gclk void; | |
| 3193 | pc_clk_sel__gclk void; | |
| 3194 | test_clk__gclk void; | |
| 3195 | test_clk_sel__gclk void; | |
| 3196 | ||
| 3197 | //---l2clk is Vera interface CLOCK--- | |
| 3198 | aclk__l2clk clkgen_mcu0_io_l2clk_if.aclk; | |
| 3199 | aclk_wmr__l2clk clkgen_mcu0_io_l2clk_if.aclk_wmr; | |
| 3200 | array_wr_inhibit__l2clk clkgen_mcu0_io_l2clk_if.array_wr_inhibit; | |
| 3201 | bclk__l2clk clkgen_mcu0_io_l2clk_if.bclk; | |
| 3202 | cmp_slow_sync_en__l2clk clkgen_mcu0_io_l2clk_if.cmp_slow_sync_en; | |
| 3203 | dr_sync_en__l2clk void; | |
| 3204 | io2x_sync_en__l2clk void; | |
| 3205 | l2clk clkgen_mcu0_io_l2clk_if.l2clk; | |
| 3206 | pce_ov__l2clk clkgen_mcu0_io_l2clk_if.pce_ov; | |
| 3207 | por___l2clk clkgen_mcu0_io_l2clk_if.por_; | |
| 3208 | scan_out__l2clk clkgen_mcu0_io_l2clk_if.scan_out; | |
| 3209 | slow_cmp_sync_en__l2clk clkgen_mcu0_io_l2clk_if.slow_cmp_sync_en; | |
| 3210 | wmr___l2clk clkgen_mcu0_io_l2clk_if.wmr_; | |
| 3211 | wmr_protect__l2clk clkgen_mcu0_io_l2clk_if.wmr_protect; | |
| 3212 | } | |
| 3213 | ||
| 3214 | //----- port binding for clkgen_mcu1_cmp ----- | |
| 3215 | ||
| 3216 | bind CLKGEN_port clkgen_mcu1_cmp_bind { | |
| 3217 | //---gclk is Vera interface CLOCK--- | |
| 3218 | aclk__gclk clkgen_mcu1_cmp_gclk_if.aclk; | |
| 3219 | aclk_wmr__gclk clkgen_mcu1_cmp_gclk_if.aclk_wmr; | |
| 3220 | array_wr_inhibit__gclk clkgen_mcu1_cmp_gclk_if.array_wr_inhibit; | |
| 3221 | bclk__gclk clkgen_mcu1_cmp_gclk_if.bclk; | |
| 3222 | ccu_cmp_slow_sync_en__gclk clkgen_mcu1_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 3223 | ccu_div_ph__gclk clkgen_mcu1_cmp_gclk_if.ccu_div_ph; | |
| 3224 | ccu_dr_sync_en__gclk clkgen_mcu1_cmp_gclk_if.ccu_dr_sync_en; | |
| 3225 | ccu_io2x_sync_en__gclk clkgen_mcu1_cmp_gclk_if.ccu_io2x_sync_en; | |
| 3226 | ccu_serdes_dtm__gclk clkgen_mcu1_cmp_gclk_if.ccu_serdes_dtm; | |
| 3227 | ccu_slow_cmp_sync_en__gclk clkgen_mcu1_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 3228 | clk_ext__gclk clkgen_mcu1_cmp_gclk_if.clk_ext; | |
| 3229 | cluster_arst_l__gclk clkgen_mcu1_cmp_gclk_if.cluster_arst_l; | |
| 3230 | cluster_div_en__gclk clkgen_mcu1_cmp_gclk_if.cluster_div_en; | |
| 3231 | cmp_slow_sync_en__gclk clkgen_mcu1_cmp_gclk_if.cmp_slow_sync_en; | |
| 3232 | dr_sync_en__gclk clkgen_mcu1_cmp_gclk_if.dr_sync_en; | |
| 3233 | gclk clkgen_mcu1_cmp_gclk_if.gclk; | |
| 3234 | io2x_sync_en__gclk clkgen_mcu1_cmp_gclk_if.io2x_sync_en; | |
| 3235 | l2clk__gclk clkgen_mcu1_cmp_gclk_if.l2clk; | |
| 3236 | pce_ov__gclk clkgen_mcu1_cmp_gclk_if.pce_ov; | |
| 3237 | por___gclk clkgen_mcu1_cmp_gclk_if.por_; | |
| 3238 | rst_por___gclk clkgen_mcu1_cmp_gclk_if.rst_por_; | |
| 3239 | rst_wmr___gclk clkgen_mcu1_cmp_gclk_if.rst_wmr_; | |
| 3240 | rst_wmr_protect__gclk clkgen_mcu1_cmp_gclk_if.rst_wmr_protect; | |
| 3241 | scan_en__gclk clkgen_mcu1_cmp_gclk_if.scan_en; | |
| 3242 | scan_in__gclk clkgen_mcu1_cmp_gclk_if.scan_in; | |
| 3243 | scan_out__gclk clkgen_mcu1_cmp_gclk_if.scan_out; | |
| 3244 | slow_cmp_sync_en__gclk clkgen_mcu1_cmp_gclk_if.slow_cmp_sync_en; | |
| 3245 | tcu_aclk__gclk clkgen_mcu1_cmp_gclk_if.tcu_aclk; | |
| 3246 | tcu_atpg_mode__gclk clkgen_mcu1_cmp_gclk_if.tcu_atpg_mode; | |
| 3247 | tcu_bclk__gclk clkgen_mcu1_cmp_gclk_if.tcu_bclk; | |
| 3248 | tcu_clk_stop__gclk clkgen_mcu1_cmp_gclk_if.tcu_clk_stop; | |
| 3249 | tcu_div_bypass__gclk clkgen_mcu1_cmp_gclk_if.tcu_div_bypass; | |
| 3250 | tcu_pce_ov__gclk clkgen_mcu1_cmp_gclk_if.tcu_pce_ov; | |
| 3251 | tcu_wr_inhibit__gclk clkgen_mcu1_cmp_gclk_if.tcu_wr_inhibit; | |
| 3252 | wmr___gclk clkgen_mcu1_cmp_gclk_if.wmr_; | |
| 3253 | wmr_protect__gclk clkgen_mcu1_cmp_gclk_if.wmr_protect; | |
| 3254 | pc_clk__gclk void; | |
| 3255 | pc_clk_sel__gclk void; | |
| 3256 | test_clk__gclk void; | |
| 3257 | test_clk_sel__gclk void; | |
| 3258 | ||
| 3259 | //---l2clk is Vera interface CLOCK--- | |
| 3260 | aclk__l2clk clkgen_mcu1_cmp_l2clk_if.aclk; | |
| 3261 | aclk_wmr__l2clk clkgen_mcu1_cmp_l2clk_if.aclk_wmr; | |
| 3262 | array_wr_inhibit__l2clk clkgen_mcu1_cmp_l2clk_if.array_wr_inhibit; | |
| 3263 | bclk__l2clk clkgen_mcu1_cmp_l2clk_if.bclk; | |
| 3264 | cmp_slow_sync_en__l2clk clkgen_mcu1_cmp_l2clk_if.cmp_slow_sync_en; | |
| 3265 | dr_sync_en__l2clk clkgen_mcu1_cmp_l2clk_if.dr_sync_en; | |
| 3266 | io2x_sync_en__l2clk clkgen_mcu1_cmp_l2clk_if.io2x_sync_en; | |
| 3267 | l2clk clkgen_mcu1_cmp_l2clk_if.l2clk; | |
| 3268 | pce_ov__l2clk clkgen_mcu1_cmp_l2clk_if.pce_ov; | |
| 3269 | por___l2clk clkgen_mcu1_cmp_l2clk_if.por_; | |
| 3270 | scan_out__l2clk clkgen_mcu1_cmp_l2clk_if.scan_out; | |
| 3271 | slow_cmp_sync_en__l2clk clkgen_mcu1_cmp_l2clk_if.slow_cmp_sync_en; | |
| 3272 | wmr___l2clk clkgen_mcu1_cmp_l2clk_if.wmr_; | |
| 3273 | wmr_protect__l2clk clkgen_mcu1_cmp_l2clk_if.wmr_protect; | |
| 3274 | } | |
| 3275 | ||
| 3276 | //----- port binding for clkgen_mcu1_dr ----- | |
| 3277 | ||
| 3278 | bind CLKGEN_port clkgen_mcu1_dr_bind { | |
| 3279 | //---gclk is Vera interface CLOCK--- | |
| 3280 | aclk__gclk clkgen_mcu1_dr_gclk_if.aclk; | |
| 3281 | aclk_wmr__gclk clkgen_mcu1_dr_gclk_if.aclk_wmr; | |
| 3282 | array_wr_inhibit__gclk clkgen_mcu1_dr_gclk_if.array_wr_inhibit; | |
| 3283 | bclk__gclk clkgen_mcu1_dr_gclk_if.bclk; | |
| 3284 | ccu_cmp_slow_sync_en__gclk clkgen_mcu1_dr_gclk_if.ccu_cmp_slow_sync_en; | |
| 3285 | ccu_div_ph__gclk clkgen_mcu1_dr_gclk_if.ccu_div_ph; | |
| 3286 | ccu_dr_sync_en__gclk void; | |
| 3287 | ccu_io2x_sync_en__gclk void; | |
| 3288 | ccu_serdes_dtm__gclk clkgen_mcu1_dr_gclk_if.ccu_serdes_dtm; | |
| 3289 | ccu_slow_cmp_sync_en__gclk clkgen_mcu1_dr_gclk_if.ccu_slow_cmp_sync_en; | |
| 3290 | clk_ext__gclk clkgen_mcu1_dr_gclk_if.clk_ext; | |
| 3291 | cluster_arst_l__gclk clkgen_mcu1_dr_gclk_if.cluster_arst_l; | |
| 3292 | cluster_div_en__gclk clkgen_mcu1_dr_gclk_if.cluster_div_en; | |
| 3293 | cmp_slow_sync_en__gclk clkgen_mcu1_dr_gclk_if.cmp_slow_sync_en; | |
| 3294 | dr_sync_en__gclk void; | |
| 3295 | gclk clkgen_mcu1_dr_gclk_if.gclk; | |
| 3296 | io2x_sync_en__gclk void; | |
| 3297 | l2clk__gclk clkgen_mcu1_dr_gclk_if.l2clk; | |
| 3298 | pce_ov__gclk clkgen_mcu1_dr_gclk_if.pce_ov; | |
| 3299 | por___gclk clkgen_mcu1_dr_gclk_if.por_; | |
| 3300 | rst_por___gclk clkgen_mcu1_dr_gclk_if.rst_por_; | |
| 3301 | rst_wmr___gclk clkgen_mcu1_dr_gclk_if.rst_wmr_; | |
| 3302 | rst_wmr_protect__gclk clkgen_mcu1_dr_gclk_if.rst_wmr_protect; | |
| 3303 | scan_en__gclk clkgen_mcu1_dr_gclk_if.scan_en; | |
| 3304 | scan_in__gclk clkgen_mcu1_dr_gclk_if.scan_in; | |
| 3305 | scan_out__gclk clkgen_mcu1_dr_gclk_if.scan_out; | |
| 3306 | slow_cmp_sync_en__gclk clkgen_mcu1_dr_gclk_if.slow_cmp_sync_en; | |
| 3307 | tcu_aclk__gclk clkgen_mcu1_dr_gclk_if.tcu_aclk; | |
| 3308 | tcu_atpg_mode__gclk clkgen_mcu1_dr_gclk_if.tcu_atpg_mode; | |
| 3309 | tcu_bclk__gclk clkgen_mcu1_dr_gclk_if.tcu_bclk; | |
| 3310 | tcu_clk_stop__gclk clkgen_mcu1_dr_gclk_if.tcu_clk_stop; | |
| 3311 | tcu_div_bypass__gclk clkgen_mcu1_dr_gclk_if.tcu_div_bypass; | |
| 3312 | tcu_pce_ov__gclk clkgen_mcu1_dr_gclk_if.tcu_pce_ov; | |
| 3313 | tcu_wr_inhibit__gclk clkgen_mcu1_dr_gclk_if.tcu_wr_inhibit; | |
| 3314 | wmr___gclk clkgen_mcu1_dr_gclk_if.wmr_; | |
| 3315 | wmr_protect__gclk clkgen_mcu1_dr_gclk_if.wmr_protect; | |
| 3316 | pc_clk__gclk void; | |
| 3317 | pc_clk_sel__gclk void; | |
| 3318 | test_clk__gclk void; | |
| 3319 | test_clk_sel__gclk void; | |
| 3320 | ||
| 3321 | //---l2clk is Vera interface CLOCK--- | |
| 3322 | aclk__l2clk clkgen_mcu1_dr_l2clk_if.aclk; | |
| 3323 | aclk_wmr__l2clk clkgen_mcu1_dr_l2clk_if.aclk_wmr; | |
| 3324 | array_wr_inhibit__l2clk clkgen_mcu1_dr_l2clk_if.array_wr_inhibit; | |
| 3325 | bclk__l2clk clkgen_mcu1_dr_l2clk_if.bclk; | |
| 3326 | cmp_slow_sync_en__l2clk clkgen_mcu1_dr_l2clk_if.cmp_slow_sync_en; | |
| 3327 | dr_sync_en__l2clk void; | |
| 3328 | io2x_sync_en__l2clk void; | |
| 3329 | l2clk clkgen_mcu1_dr_l2clk_if.l2clk; | |
| 3330 | pce_ov__l2clk clkgen_mcu1_dr_l2clk_if.pce_ov; | |
| 3331 | por___l2clk clkgen_mcu1_dr_l2clk_if.por_; | |
| 3332 | scan_out__l2clk clkgen_mcu1_dr_l2clk_if.scan_out; | |
| 3333 | slow_cmp_sync_en__l2clk clkgen_mcu1_dr_l2clk_if.slow_cmp_sync_en; | |
| 3334 | wmr___l2clk clkgen_mcu1_dr_l2clk_if.wmr_; | |
| 3335 | wmr_protect__l2clk clkgen_mcu1_dr_l2clk_if.wmr_protect; | |
| 3336 | } | |
| 3337 | ||
| 3338 | //----- port binding for clkgen_mcu1_io ----- | |
| 3339 | ||
| 3340 | bind CLKGEN_port clkgen_mcu1_io_bind { | |
| 3341 | //---gclk is Vera interface CLOCK--- | |
| 3342 | aclk__gclk clkgen_mcu1_io_gclk_if.aclk; | |
| 3343 | aclk_wmr__gclk clkgen_mcu1_io_gclk_if.aclk_wmr; | |
| 3344 | array_wr_inhibit__gclk clkgen_mcu1_io_gclk_if.array_wr_inhibit; | |
| 3345 | bclk__gclk clkgen_mcu1_io_gclk_if.bclk; | |
| 3346 | ccu_cmp_slow_sync_en__gclk clkgen_mcu1_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 3347 | ccu_div_ph__gclk clkgen_mcu1_io_gclk_if.ccu_div_ph; | |
| 3348 | ccu_dr_sync_en__gclk void; | |
| 3349 | ccu_io2x_sync_en__gclk void; | |
| 3350 | ccu_serdes_dtm__gclk clkgen_mcu1_io_gclk_if.ccu_serdes_dtm; | |
| 3351 | ccu_slow_cmp_sync_en__gclk clkgen_mcu1_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 3352 | clk_ext__gclk clkgen_mcu1_io_gclk_if.clk_ext; | |
| 3353 | cluster_arst_l__gclk clkgen_mcu1_io_gclk_if.cluster_arst_l; | |
| 3354 | cluster_div_en__gclk clkgen_mcu1_io_gclk_if.cluster_div_en; | |
| 3355 | cmp_slow_sync_en__gclk clkgen_mcu1_io_gclk_if.cmp_slow_sync_en; | |
| 3356 | dr_sync_en__gclk void; | |
| 3357 | gclk clkgen_mcu1_io_gclk_if.gclk; | |
| 3358 | io2x_sync_en__gclk void; | |
| 3359 | l2clk__gclk clkgen_mcu1_io_gclk_if.l2clk; | |
| 3360 | pce_ov__gclk clkgen_mcu1_io_gclk_if.pce_ov; | |
| 3361 | por___gclk clkgen_mcu1_io_gclk_if.por_; | |
| 3362 | rst_por___gclk clkgen_mcu1_io_gclk_if.rst_por_; | |
| 3363 | rst_wmr___gclk clkgen_mcu1_io_gclk_if.rst_wmr_; | |
| 3364 | rst_wmr_protect__gclk clkgen_mcu1_io_gclk_if.rst_wmr_protect; | |
| 3365 | scan_en__gclk clkgen_mcu1_io_gclk_if.scan_en; | |
| 3366 | scan_in__gclk clkgen_mcu1_io_gclk_if.scan_in; | |
| 3367 | scan_out__gclk clkgen_mcu1_io_gclk_if.scan_out; | |
| 3368 | slow_cmp_sync_en__gclk clkgen_mcu1_io_gclk_if.slow_cmp_sync_en; | |
| 3369 | tcu_aclk__gclk clkgen_mcu1_io_gclk_if.tcu_aclk; | |
| 3370 | tcu_atpg_mode__gclk clkgen_mcu1_io_gclk_if.tcu_atpg_mode; | |
| 3371 | tcu_bclk__gclk clkgen_mcu1_io_gclk_if.tcu_bclk; | |
| 3372 | tcu_clk_stop__gclk clkgen_mcu1_io_gclk_if.tcu_clk_stop; | |
| 3373 | tcu_div_bypass__gclk clkgen_mcu1_io_gclk_if.tcu_div_bypass; | |
| 3374 | tcu_pce_ov__gclk clkgen_mcu1_io_gclk_if.tcu_pce_ov; | |
| 3375 | tcu_wr_inhibit__gclk clkgen_mcu1_io_gclk_if.tcu_wr_inhibit; | |
| 3376 | wmr___gclk clkgen_mcu1_io_gclk_if.wmr_; | |
| 3377 | wmr_protect__gclk clkgen_mcu1_io_gclk_if.wmr_protect; | |
| 3378 | pc_clk__gclk void; | |
| 3379 | pc_clk_sel__gclk void; | |
| 3380 | test_clk__gclk void; | |
| 3381 | test_clk_sel__gclk void; | |
| 3382 | ||
| 3383 | //---l2clk is Vera interface CLOCK--- | |
| 3384 | aclk__l2clk clkgen_mcu1_io_l2clk_if.aclk; | |
| 3385 | aclk_wmr__l2clk clkgen_mcu1_io_l2clk_if.aclk_wmr; | |
| 3386 | array_wr_inhibit__l2clk clkgen_mcu1_io_l2clk_if.array_wr_inhibit; | |
| 3387 | bclk__l2clk clkgen_mcu1_io_l2clk_if.bclk; | |
| 3388 | cmp_slow_sync_en__l2clk clkgen_mcu1_io_l2clk_if.cmp_slow_sync_en; | |
| 3389 | dr_sync_en__l2clk void; | |
| 3390 | io2x_sync_en__l2clk void; | |
| 3391 | l2clk clkgen_mcu1_io_l2clk_if.l2clk; | |
| 3392 | pce_ov__l2clk clkgen_mcu1_io_l2clk_if.pce_ov; | |
| 3393 | por___l2clk clkgen_mcu1_io_l2clk_if.por_; | |
| 3394 | scan_out__l2clk clkgen_mcu1_io_l2clk_if.scan_out; | |
| 3395 | slow_cmp_sync_en__l2clk clkgen_mcu1_io_l2clk_if.slow_cmp_sync_en; | |
| 3396 | wmr___l2clk clkgen_mcu1_io_l2clk_if.wmr_; | |
| 3397 | wmr_protect__l2clk clkgen_mcu1_io_l2clk_if.wmr_protect; | |
| 3398 | } | |
| 3399 | ||
| 3400 | //----- port binding for clkgen_mcu2_cmp ----- | |
| 3401 | ||
| 3402 | bind CLKGEN_port clkgen_mcu2_cmp_bind { | |
| 3403 | //---gclk is Vera interface CLOCK--- | |
| 3404 | aclk__gclk clkgen_mcu2_cmp_gclk_if.aclk; | |
| 3405 | aclk_wmr__gclk clkgen_mcu2_cmp_gclk_if.aclk_wmr; | |
| 3406 | array_wr_inhibit__gclk clkgen_mcu2_cmp_gclk_if.array_wr_inhibit; | |
| 3407 | bclk__gclk clkgen_mcu2_cmp_gclk_if.bclk; | |
| 3408 | ccu_cmp_slow_sync_en__gclk clkgen_mcu2_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 3409 | ccu_div_ph__gclk clkgen_mcu2_cmp_gclk_if.ccu_div_ph; | |
| 3410 | ccu_dr_sync_en__gclk clkgen_mcu2_cmp_gclk_if.ccu_dr_sync_en; | |
| 3411 | ccu_io2x_sync_en__gclk clkgen_mcu2_cmp_gclk_if.ccu_io2x_sync_en; | |
| 3412 | ccu_serdes_dtm__gclk clkgen_mcu2_cmp_gclk_if.ccu_serdes_dtm; | |
| 3413 | ccu_slow_cmp_sync_en__gclk clkgen_mcu2_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 3414 | clk_ext__gclk clkgen_mcu2_cmp_gclk_if.clk_ext; | |
| 3415 | cluster_arst_l__gclk clkgen_mcu2_cmp_gclk_if.cluster_arst_l; | |
| 3416 | cluster_div_en__gclk clkgen_mcu2_cmp_gclk_if.cluster_div_en; | |
| 3417 | cmp_slow_sync_en__gclk clkgen_mcu2_cmp_gclk_if.cmp_slow_sync_en; | |
| 3418 | dr_sync_en__gclk clkgen_mcu2_cmp_gclk_if.dr_sync_en; | |
| 3419 | gclk clkgen_mcu2_cmp_gclk_if.gclk; | |
| 3420 | io2x_sync_en__gclk clkgen_mcu2_cmp_gclk_if.io2x_sync_en; | |
| 3421 | l2clk__gclk clkgen_mcu2_cmp_gclk_if.l2clk; | |
| 3422 | pce_ov__gclk clkgen_mcu2_cmp_gclk_if.pce_ov; | |
| 3423 | por___gclk clkgen_mcu2_cmp_gclk_if.por_; | |
| 3424 | rst_por___gclk clkgen_mcu2_cmp_gclk_if.rst_por_; | |
| 3425 | rst_wmr___gclk clkgen_mcu2_cmp_gclk_if.rst_wmr_; | |
| 3426 | rst_wmr_protect__gclk clkgen_mcu2_cmp_gclk_if.rst_wmr_protect; | |
| 3427 | scan_en__gclk clkgen_mcu2_cmp_gclk_if.scan_en; | |
| 3428 | scan_in__gclk clkgen_mcu2_cmp_gclk_if.scan_in; | |
| 3429 | scan_out__gclk clkgen_mcu2_cmp_gclk_if.scan_out; | |
| 3430 | slow_cmp_sync_en__gclk clkgen_mcu2_cmp_gclk_if.slow_cmp_sync_en; | |
| 3431 | tcu_aclk__gclk clkgen_mcu2_cmp_gclk_if.tcu_aclk; | |
| 3432 | tcu_atpg_mode__gclk clkgen_mcu2_cmp_gclk_if.tcu_atpg_mode; | |
| 3433 | tcu_bclk__gclk clkgen_mcu2_cmp_gclk_if.tcu_bclk; | |
| 3434 | tcu_clk_stop__gclk clkgen_mcu2_cmp_gclk_if.tcu_clk_stop; | |
| 3435 | tcu_div_bypass__gclk clkgen_mcu2_cmp_gclk_if.tcu_div_bypass; | |
| 3436 | tcu_pce_ov__gclk clkgen_mcu2_cmp_gclk_if.tcu_pce_ov; | |
| 3437 | tcu_wr_inhibit__gclk clkgen_mcu2_cmp_gclk_if.tcu_wr_inhibit; | |
| 3438 | wmr___gclk clkgen_mcu2_cmp_gclk_if.wmr_; | |
| 3439 | wmr_protect__gclk clkgen_mcu2_cmp_gclk_if.wmr_protect; | |
| 3440 | pc_clk__gclk void; | |
| 3441 | pc_clk_sel__gclk void; | |
| 3442 | test_clk__gclk void; | |
| 3443 | test_clk_sel__gclk void; | |
| 3444 | ||
| 3445 | //---l2clk is Vera interface CLOCK--- | |
| 3446 | aclk__l2clk clkgen_mcu2_cmp_l2clk_if.aclk; | |
| 3447 | aclk_wmr__l2clk clkgen_mcu2_cmp_l2clk_if.aclk_wmr; | |
| 3448 | array_wr_inhibit__l2clk clkgen_mcu2_cmp_l2clk_if.array_wr_inhibit; | |
| 3449 | bclk__l2clk clkgen_mcu2_cmp_l2clk_if.bclk; | |
| 3450 | cmp_slow_sync_en__l2clk clkgen_mcu2_cmp_l2clk_if.cmp_slow_sync_en; | |
| 3451 | dr_sync_en__l2clk clkgen_mcu2_cmp_l2clk_if.dr_sync_en; | |
| 3452 | io2x_sync_en__l2clk clkgen_mcu2_cmp_l2clk_if.io2x_sync_en; | |
| 3453 | l2clk clkgen_mcu2_cmp_l2clk_if.l2clk; | |
| 3454 | pce_ov__l2clk clkgen_mcu2_cmp_l2clk_if.pce_ov; | |
| 3455 | por___l2clk clkgen_mcu2_cmp_l2clk_if.por_; | |
| 3456 | scan_out__l2clk clkgen_mcu2_cmp_l2clk_if.scan_out; | |
| 3457 | slow_cmp_sync_en__l2clk clkgen_mcu2_cmp_l2clk_if.slow_cmp_sync_en; | |
| 3458 | wmr___l2clk clkgen_mcu2_cmp_l2clk_if.wmr_; | |
| 3459 | wmr_protect__l2clk clkgen_mcu2_cmp_l2clk_if.wmr_protect; | |
| 3460 | } | |
| 3461 | ||
| 3462 | //----- port binding for clkgen_mcu2_dr ----- | |
| 3463 | ||
| 3464 | bind CLKGEN_port clkgen_mcu2_dr_bind { | |
| 3465 | //---gclk is Vera interface CLOCK--- | |
| 3466 | aclk__gclk clkgen_mcu2_dr_gclk_if.aclk; | |
| 3467 | aclk_wmr__gclk clkgen_mcu2_dr_gclk_if.aclk_wmr; | |
| 3468 | array_wr_inhibit__gclk clkgen_mcu2_dr_gclk_if.array_wr_inhibit; | |
| 3469 | bclk__gclk clkgen_mcu2_dr_gclk_if.bclk; | |
| 3470 | ccu_cmp_slow_sync_en__gclk clkgen_mcu2_dr_gclk_if.ccu_cmp_slow_sync_en; | |
| 3471 | ccu_div_ph__gclk clkgen_mcu2_dr_gclk_if.ccu_div_ph; | |
| 3472 | ccu_dr_sync_en__gclk void; | |
| 3473 | ccu_io2x_sync_en__gclk void; | |
| 3474 | ccu_serdes_dtm__gclk clkgen_mcu2_dr_gclk_if.ccu_serdes_dtm; | |
| 3475 | ccu_slow_cmp_sync_en__gclk clkgen_mcu2_dr_gclk_if.ccu_slow_cmp_sync_en; | |
| 3476 | clk_ext__gclk clkgen_mcu2_dr_gclk_if.clk_ext; | |
| 3477 | cluster_arst_l__gclk clkgen_mcu2_dr_gclk_if.cluster_arst_l; | |
| 3478 | cluster_div_en__gclk clkgen_mcu2_dr_gclk_if.cluster_div_en; | |
| 3479 | cmp_slow_sync_en__gclk clkgen_mcu2_dr_gclk_if.cmp_slow_sync_en; | |
| 3480 | dr_sync_en__gclk void; | |
| 3481 | gclk clkgen_mcu2_dr_gclk_if.gclk; | |
| 3482 | io2x_sync_en__gclk void; | |
| 3483 | l2clk__gclk clkgen_mcu2_dr_gclk_if.l2clk; | |
| 3484 | pce_ov__gclk clkgen_mcu2_dr_gclk_if.pce_ov; | |
| 3485 | por___gclk clkgen_mcu2_dr_gclk_if.por_; | |
| 3486 | rst_por___gclk clkgen_mcu2_dr_gclk_if.rst_por_; | |
| 3487 | rst_wmr___gclk clkgen_mcu2_dr_gclk_if.rst_wmr_; | |
| 3488 | rst_wmr_protect__gclk clkgen_mcu2_dr_gclk_if.rst_wmr_protect; | |
| 3489 | scan_en__gclk clkgen_mcu2_dr_gclk_if.scan_en; | |
| 3490 | scan_in__gclk clkgen_mcu2_dr_gclk_if.scan_in; | |
| 3491 | scan_out__gclk clkgen_mcu2_dr_gclk_if.scan_out; | |
| 3492 | slow_cmp_sync_en__gclk clkgen_mcu2_dr_gclk_if.slow_cmp_sync_en; | |
| 3493 | tcu_aclk__gclk clkgen_mcu2_dr_gclk_if.tcu_aclk; | |
| 3494 | tcu_atpg_mode__gclk clkgen_mcu2_dr_gclk_if.tcu_atpg_mode; | |
| 3495 | tcu_bclk__gclk clkgen_mcu2_dr_gclk_if.tcu_bclk; | |
| 3496 | tcu_clk_stop__gclk clkgen_mcu2_dr_gclk_if.tcu_clk_stop; | |
| 3497 | tcu_div_bypass__gclk clkgen_mcu2_dr_gclk_if.tcu_div_bypass; | |
| 3498 | tcu_pce_ov__gclk clkgen_mcu2_dr_gclk_if.tcu_pce_ov; | |
| 3499 | tcu_wr_inhibit__gclk clkgen_mcu2_dr_gclk_if.tcu_wr_inhibit; | |
| 3500 | wmr___gclk clkgen_mcu2_dr_gclk_if.wmr_; | |
| 3501 | wmr_protect__gclk clkgen_mcu2_dr_gclk_if.wmr_protect; | |
| 3502 | pc_clk__gclk void; | |
| 3503 | pc_clk_sel__gclk void; | |
| 3504 | test_clk__gclk void; | |
| 3505 | test_clk_sel__gclk void; | |
| 3506 | ||
| 3507 | //---l2clk is Vera interface CLOCK--- | |
| 3508 | aclk__l2clk clkgen_mcu2_dr_l2clk_if.aclk; | |
| 3509 | aclk_wmr__l2clk clkgen_mcu2_dr_l2clk_if.aclk_wmr; | |
| 3510 | array_wr_inhibit__l2clk clkgen_mcu2_dr_l2clk_if.array_wr_inhibit; | |
| 3511 | bclk__l2clk clkgen_mcu2_dr_l2clk_if.bclk; | |
| 3512 | cmp_slow_sync_en__l2clk clkgen_mcu2_dr_l2clk_if.cmp_slow_sync_en; | |
| 3513 | dr_sync_en__l2clk void; | |
| 3514 | io2x_sync_en__l2clk void; | |
| 3515 | l2clk clkgen_mcu2_dr_l2clk_if.l2clk; | |
| 3516 | pce_ov__l2clk clkgen_mcu2_dr_l2clk_if.pce_ov; | |
| 3517 | por___l2clk clkgen_mcu2_dr_l2clk_if.por_; | |
| 3518 | scan_out__l2clk clkgen_mcu2_dr_l2clk_if.scan_out; | |
| 3519 | slow_cmp_sync_en__l2clk clkgen_mcu2_dr_l2clk_if.slow_cmp_sync_en; | |
| 3520 | wmr___l2clk clkgen_mcu2_dr_l2clk_if.wmr_; | |
| 3521 | wmr_protect__l2clk clkgen_mcu2_dr_l2clk_if.wmr_protect; | |
| 3522 | } | |
| 3523 | ||
| 3524 | //----- port binding for clkgen_mcu2_io ----- | |
| 3525 | ||
| 3526 | bind CLKGEN_port clkgen_mcu2_io_bind { | |
| 3527 | //---gclk is Vera interface CLOCK--- | |
| 3528 | aclk__gclk clkgen_mcu2_io_gclk_if.aclk; | |
| 3529 | aclk_wmr__gclk clkgen_mcu2_io_gclk_if.aclk_wmr; | |
| 3530 | array_wr_inhibit__gclk clkgen_mcu2_io_gclk_if.array_wr_inhibit; | |
| 3531 | bclk__gclk clkgen_mcu2_io_gclk_if.bclk; | |
| 3532 | ccu_cmp_slow_sync_en__gclk clkgen_mcu2_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 3533 | ccu_div_ph__gclk clkgen_mcu2_io_gclk_if.ccu_div_ph; | |
| 3534 | ccu_dr_sync_en__gclk void; | |
| 3535 | ccu_io2x_sync_en__gclk void; | |
| 3536 | ccu_serdes_dtm__gclk clkgen_mcu2_io_gclk_if.ccu_serdes_dtm; | |
| 3537 | ccu_slow_cmp_sync_en__gclk clkgen_mcu2_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 3538 | clk_ext__gclk clkgen_mcu2_io_gclk_if.clk_ext; | |
| 3539 | cluster_arst_l__gclk clkgen_mcu2_io_gclk_if.cluster_arst_l; | |
| 3540 | cluster_div_en__gclk clkgen_mcu2_io_gclk_if.cluster_div_en; | |
| 3541 | cmp_slow_sync_en__gclk clkgen_mcu2_io_gclk_if.cmp_slow_sync_en; | |
| 3542 | dr_sync_en__gclk void; | |
| 3543 | gclk clkgen_mcu2_io_gclk_if.gclk; | |
| 3544 | io2x_sync_en__gclk void; | |
| 3545 | l2clk__gclk clkgen_mcu2_io_gclk_if.l2clk; | |
| 3546 | pce_ov__gclk clkgen_mcu2_io_gclk_if.pce_ov; | |
| 3547 | por___gclk clkgen_mcu2_io_gclk_if.por_; | |
| 3548 | rst_por___gclk clkgen_mcu2_io_gclk_if.rst_por_; | |
| 3549 | rst_wmr___gclk clkgen_mcu2_io_gclk_if.rst_wmr_; | |
| 3550 | rst_wmr_protect__gclk clkgen_mcu2_io_gclk_if.rst_wmr_protect; | |
| 3551 | scan_en__gclk clkgen_mcu2_io_gclk_if.scan_en; | |
| 3552 | scan_in__gclk clkgen_mcu2_io_gclk_if.scan_in; | |
| 3553 | scan_out__gclk clkgen_mcu2_io_gclk_if.scan_out; | |
| 3554 | slow_cmp_sync_en__gclk clkgen_mcu2_io_gclk_if.slow_cmp_sync_en; | |
| 3555 | tcu_aclk__gclk clkgen_mcu2_io_gclk_if.tcu_aclk; | |
| 3556 | tcu_atpg_mode__gclk clkgen_mcu2_io_gclk_if.tcu_atpg_mode; | |
| 3557 | tcu_bclk__gclk clkgen_mcu2_io_gclk_if.tcu_bclk; | |
| 3558 | tcu_clk_stop__gclk clkgen_mcu2_io_gclk_if.tcu_clk_stop; | |
| 3559 | tcu_div_bypass__gclk clkgen_mcu2_io_gclk_if.tcu_div_bypass; | |
| 3560 | tcu_pce_ov__gclk clkgen_mcu2_io_gclk_if.tcu_pce_ov; | |
| 3561 | tcu_wr_inhibit__gclk clkgen_mcu2_io_gclk_if.tcu_wr_inhibit; | |
| 3562 | wmr___gclk clkgen_mcu2_io_gclk_if.wmr_; | |
| 3563 | wmr_protect__gclk clkgen_mcu2_io_gclk_if.wmr_protect; | |
| 3564 | pc_clk__gclk void; | |
| 3565 | pc_clk_sel__gclk void; | |
| 3566 | test_clk__gclk void; | |
| 3567 | test_clk_sel__gclk void; | |
| 3568 | ||
| 3569 | //---l2clk is Vera interface CLOCK--- | |
| 3570 | aclk__l2clk clkgen_mcu2_io_l2clk_if.aclk; | |
| 3571 | aclk_wmr__l2clk clkgen_mcu2_io_l2clk_if.aclk_wmr; | |
| 3572 | array_wr_inhibit__l2clk clkgen_mcu2_io_l2clk_if.array_wr_inhibit; | |
| 3573 | bclk__l2clk clkgen_mcu2_io_l2clk_if.bclk; | |
| 3574 | cmp_slow_sync_en__l2clk clkgen_mcu2_io_l2clk_if.cmp_slow_sync_en; | |
| 3575 | dr_sync_en__l2clk void; | |
| 3576 | io2x_sync_en__l2clk void; | |
| 3577 | l2clk clkgen_mcu2_io_l2clk_if.l2clk; | |
| 3578 | pce_ov__l2clk clkgen_mcu2_io_l2clk_if.pce_ov; | |
| 3579 | por___l2clk clkgen_mcu2_io_l2clk_if.por_; | |
| 3580 | scan_out__l2clk clkgen_mcu2_io_l2clk_if.scan_out; | |
| 3581 | slow_cmp_sync_en__l2clk clkgen_mcu2_io_l2clk_if.slow_cmp_sync_en; | |
| 3582 | wmr___l2clk clkgen_mcu2_io_l2clk_if.wmr_; | |
| 3583 | wmr_protect__l2clk clkgen_mcu2_io_l2clk_if.wmr_protect; | |
| 3584 | } | |
| 3585 | ||
| 3586 | //----- port binding for clkgen_mcu3_cmp ----- | |
| 3587 | ||
| 3588 | bind CLKGEN_port clkgen_mcu3_cmp_bind { | |
| 3589 | //---gclk is Vera interface CLOCK--- | |
| 3590 | aclk__gclk clkgen_mcu3_cmp_gclk_if.aclk; | |
| 3591 | aclk_wmr__gclk clkgen_mcu3_cmp_gclk_if.aclk_wmr; | |
| 3592 | array_wr_inhibit__gclk clkgen_mcu3_cmp_gclk_if.array_wr_inhibit; | |
| 3593 | bclk__gclk clkgen_mcu3_cmp_gclk_if.bclk; | |
| 3594 | ccu_cmp_slow_sync_en__gclk clkgen_mcu3_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 3595 | ccu_div_ph__gclk clkgen_mcu3_cmp_gclk_if.ccu_div_ph; | |
| 3596 | ccu_dr_sync_en__gclk clkgen_mcu3_cmp_gclk_if.ccu_dr_sync_en; | |
| 3597 | ccu_io2x_sync_en__gclk clkgen_mcu3_cmp_gclk_if.ccu_io2x_sync_en; | |
| 3598 | ccu_serdes_dtm__gclk clkgen_mcu3_cmp_gclk_if.ccu_serdes_dtm; | |
| 3599 | ccu_slow_cmp_sync_en__gclk clkgen_mcu3_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 3600 | clk_ext__gclk clkgen_mcu3_cmp_gclk_if.clk_ext; | |
| 3601 | cluster_arst_l__gclk clkgen_mcu3_cmp_gclk_if.cluster_arst_l; | |
| 3602 | cluster_div_en__gclk clkgen_mcu3_cmp_gclk_if.cluster_div_en; | |
| 3603 | cmp_slow_sync_en__gclk clkgen_mcu3_cmp_gclk_if.cmp_slow_sync_en; | |
| 3604 | dr_sync_en__gclk clkgen_mcu3_cmp_gclk_if.dr_sync_en; | |
| 3605 | gclk clkgen_mcu3_cmp_gclk_if.gclk; | |
| 3606 | io2x_sync_en__gclk clkgen_mcu3_cmp_gclk_if.io2x_sync_en; | |
| 3607 | l2clk__gclk clkgen_mcu3_cmp_gclk_if.l2clk; | |
| 3608 | pce_ov__gclk clkgen_mcu3_cmp_gclk_if.pce_ov; | |
| 3609 | por___gclk clkgen_mcu3_cmp_gclk_if.por_; | |
| 3610 | rst_por___gclk clkgen_mcu3_cmp_gclk_if.rst_por_; | |
| 3611 | rst_wmr___gclk clkgen_mcu3_cmp_gclk_if.rst_wmr_; | |
| 3612 | rst_wmr_protect__gclk clkgen_mcu3_cmp_gclk_if.rst_wmr_protect; | |
| 3613 | scan_en__gclk clkgen_mcu3_cmp_gclk_if.scan_en; | |
| 3614 | scan_in__gclk clkgen_mcu3_cmp_gclk_if.scan_in; | |
| 3615 | scan_out__gclk clkgen_mcu3_cmp_gclk_if.scan_out; | |
| 3616 | slow_cmp_sync_en__gclk clkgen_mcu3_cmp_gclk_if.slow_cmp_sync_en; | |
| 3617 | tcu_aclk__gclk clkgen_mcu3_cmp_gclk_if.tcu_aclk; | |
| 3618 | tcu_atpg_mode__gclk clkgen_mcu3_cmp_gclk_if.tcu_atpg_mode; | |
| 3619 | tcu_bclk__gclk clkgen_mcu3_cmp_gclk_if.tcu_bclk; | |
| 3620 | tcu_clk_stop__gclk clkgen_mcu3_cmp_gclk_if.tcu_clk_stop; | |
| 3621 | tcu_div_bypass__gclk clkgen_mcu3_cmp_gclk_if.tcu_div_bypass; | |
| 3622 | tcu_pce_ov__gclk clkgen_mcu3_cmp_gclk_if.tcu_pce_ov; | |
| 3623 | tcu_wr_inhibit__gclk clkgen_mcu3_cmp_gclk_if.tcu_wr_inhibit; | |
| 3624 | wmr___gclk clkgen_mcu3_cmp_gclk_if.wmr_; | |
| 3625 | wmr_protect__gclk clkgen_mcu3_cmp_gclk_if.wmr_protect; | |
| 3626 | pc_clk__gclk void; | |
| 3627 | pc_clk_sel__gclk void; | |
| 3628 | test_clk__gclk void; | |
| 3629 | test_clk_sel__gclk void; | |
| 3630 | ||
| 3631 | //---l2clk is Vera interface CLOCK--- | |
| 3632 | aclk__l2clk clkgen_mcu3_cmp_l2clk_if.aclk; | |
| 3633 | aclk_wmr__l2clk clkgen_mcu3_cmp_l2clk_if.aclk_wmr; | |
| 3634 | array_wr_inhibit__l2clk clkgen_mcu3_cmp_l2clk_if.array_wr_inhibit; | |
| 3635 | bclk__l2clk clkgen_mcu3_cmp_l2clk_if.bclk; | |
| 3636 | cmp_slow_sync_en__l2clk clkgen_mcu3_cmp_l2clk_if.cmp_slow_sync_en; | |
| 3637 | dr_sync_en__l2clk clkgen_mcu3_cmp_l2clk_if.dr_sync_en; | |
| 3638 | io2x_sync_en__l2clk clkgen_mcu3_cmp_l2clk_if.io2x_sync_en; | |
| 3639 | l2clk clkgen_mcu3_cmp_l2clk_if.l2clk; | |
| 3640 | pce_ov__l2clk clkgen_mcu3_cmp_l2clk_if.pce_ov; | |
| 3641 | por___l2clk clkgen_mcu3_cmp_l2clk_if.por_; | |
| 3642 | scan_out__l2clk clkgen_mcu3_cmp_l2clk_if.scan_out; | |
| 3643 | slow_cmp_sync_en__l2clk clkgen_mcu3_cmp_l2clk_if.slow_cmp_sync_en; | |
| 3644 | wmr___l2clk clkgen_mcu3_cmp_l2clk_if.wmr_; | |
| 3645 | wmr_protect__l2clk clkgen_mcu3_cmp_l2clk_if.wmr_protect; | |
| 3646 | } | |
| 3647 | ||
| 3648 | //----- port binding for clkgen_mcu3_dr ----- | |
| 3649 | ||
| 3650 | bind CLKGEN_port clkgen_mcu3_dr_bind { | |
| 3651 | //---gclk is Vera interface CLOCK--- | |
| 3652 | aclk__gclk clkgen_mcu3_dr_gclk_if.aclk; | |
| 3653 | aclk_wmr__gclk clkgen_mcu3_dr_gclk_if.aclk_wmr; | |
| 3654 | array_wr_inhibit__gclk clkgen_mcu3_dr_gclk_if.array_wr_inhibit; | |
| 3655 | bclk__gclk clkgen_mcu3_dr_gclk_if.bclk; | |
| 3656 | ccu_cmp_slow_sync_en__gclk clkgen_mcu3_dr_gclk_if.ccu_cmp_slow_sync_en; | |
| 3657 | ccu_div_ph__gclk clkgen_mcu3_dr_gclk_if.ccu_div_ph; | |
| 3658 | ccu_dr_sync_en__gclk void; | |
| 3659 | ccu_io2x_sync_en__gclk void; | |
| 3660 | ccu_serdes_dtm__gclk clkgen_mcu3_dr_gclk_if.ccu_serdes_dtm; | |
| 3661 | ccu_slow_cmp_sync_en__gclk clkgen_mcu3_dr_gclk_if.ccu_slow_cmp_sync_en; | |
| 3662 | clk_ext__gclk clkgen_mcu3_dr_gclk_if.clk_ext; | |
| 3663 | cluster_arst_l__gclk clkgen_mcu3_dr_gclk_if.cluster_arst_l; | |
| 3664 | cluster_div_en__gclk clkgen_mcu3_dr_gclk_if.cluster_div_en; | |
| 3665 | cmp_slow_sync_en__gclk clkgen_mcu3_dr_gclk_if.cmp_slow_sync_en; | |
| 3666 | dr_sync_en__gclk void; | |
| 3667 | gclk clkgen_mcu3_dr_gclk_if.gclk; | |
| 3668 | io2x_sync_en__gclk void; | |
| 3669 | l2clk__gclk clkgen_mcu3_dr_gclk_if.l2clk; | |
| 3670 | pce_ov__gclk clkgen_mcu3_dr_gclk_if.pce_ov; | |
| 3671 | por___gclk clkgen_mcu3_dr_gclk_if.por_; | |
| 3672 | rst_por___gclk clkgen_mcu3_dr_gclk_if.rst_por_; | |
| 3673 | rst_wmr___gclk clkgen_mcu3_dr_gclk_if.rst_wmr_; | |
| 3674 | rst_wmr_protect__gclk clkgen_mcu3_dr_gclk_if.rst_wmr_protect; | |
| 3675 | scan_en__gclk clkgen_mcu3_dr_gclk_if.scan_en; | |
| 3676 | scan_in__gclk clkgen_mcu3_dr_gclk_if.scan_in; | |
| 3677 | scan_out__gclk clkgen_mcu3_dr_gclk_if.scan_out; | |
| 3678 | slow_cmp_sync_en__gclk clkgen_mcu3_dr_gclk_if.slow_cmp_sync_en; | |
| 3679 | tcu_aclk__gclk clkgen_mcu3_dr_gclk_if.tcu_aclk; | |
| 3680 | tcu_atpg_mode__gclk clkgen_mcu3_dr_gclk_if.tcu_atpg_mode; | |
| 3681 | tcu_bclk__gclk clkgen_mcu3_dr_gclk_if.tcu_bclk; | |
| 3682 | tcu_clk_stop__gclk clkgen_mcu3_dr_gclk_if.tcu_clk_stop; | |
| 3683 | tcu_div_bypass__gclk clkgen_mcu3_dr_gclk_if.tcu_div_bypass; | |
| 3684 | tcu_pce_ov__gclk clkgen_mcu3_dr_gclk_if.tcu_pce_ov; | |
| 3685 | tcu_wr_inhibit__gclk clkgen_mcu3_dr_gclk_if.tcu_wr_inhibit; | |
| 3686 | wmr___gclk clkgen_mcu3_dr_gclk_if.wmr_; | |
| 3687 | wmr_protect__gclk clkgen_mcu3_dr_gclk_if.wmr_protect; | |
| 3688 | pc_clk__gclk void; | |
| 3689 | pc_clk_sel__gclk void; | |
| 3690 | test_clk__gclk void; | |
| 3691 | test_clk_sel__gclk void; | |
| 3692 | ||
| 3693 | //---l2clk is Vera interface CLOCK--- | |
| 3694 | aclk__l2clk clkgen_mcu3_dr_l2clk_if.aclk; | |
| 3695 | aclk_wmr__l2clk clkgen_mcu3_dr_l2clk_if.aclk_wmr; | |
| 3696 | array_wr_inhibit__l2clk clkgen_mcu3_dr_l2clk_if.array_wr_inhibit; | |
| 3697 | bclk__l2clk clkgen_mcu3_dr_l2clk_if.bclk; | |
| 3698 | cmp_slow_sync_en__l2clk clkgen_mcu3_dr_l2clk_if.cmp_slow_sync_en; | |
| 3699 | dr_sync_en__l2clk void; | |
| 3700 | io2x_sync_en__l2clk void; | |
| 3701 | l2clk clkgen_mcu3_dr_l2clk_if.l2clk; | |
| 3702 | pce_ov__l2clk clkgen_mcu3_dr_l2clk_if.pce_ov; | |
| 3703 | por___l2clk clkgen_mcu3_dr_l2clk_if.por_; | |
| 3704 | scan_out__l2clk clkgen_mcu3_dr_l2clk_if.scan_out; | |
| 3705 | slow_cmp_sync_en__l2clk clkgen_mcu3_dr_l2clk_if.slow_cmp_sync_en; | |
| 3706 | wmr___l2clk clkgen_mcu3_dr_l2clk_if.wmr_; | |
| 3707 | wmr_protect__l2clk clkgen_mcu3_dr_l2clk_if.wmr_protect; | |
| 3708 | } | |
| 3709 | ||
| 3710 | //----- port binding for clkgen_mcu3_io ----- | |
| 3711 | ||
| 3712 | bind CLKGEN_port clkgen_mcu3_io_bind { | |
| 3713 | //---gclk is Vera interface CLOCK--- | |
| 3714 | aclk__gclk clkgen_mcu3_io_gclk_if.aclk; | |
| 3715 | aclk_wmr__gclk clkgen_mcu3_io_gclk_if.aclk_wmr; | |
| 3716 | array_wr_inhibit__gclk clkgen_mcu3_io_gclk_if.array_wr_inhibit; | |
| 3717 | bclk__gclk clkgen_mcu3_io_gclk_if.bclk; | |
| 3718 | ccu_cmp_slow_sync_en__gclk clkgen_mcu3_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 3719 | ccu_div_ph__gclk clkgen_mcu3_io_gclk_if.ccu_div_ph; | |
| 3720 | ccu_dr_sync_en__gclk void; | |
| 3721 | ccu_io2x_sync_en__gclk void; | |
| 3722 | ccu_serdes_dtm__gclk clkgen_mcu3_io_gclk_if.ccu_serdes_dtm; | |
| 3723 | ccu_slow_cmp_sync_en__gclk clkgen_mcu3_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 3724 | clk_ext__gclk clkgen_mcu3_io_gclk_if.clk_ext; | |
| 3725 | cluster_arst_l__gclk clkgen_mcu3_io_gclk_if.cluster_arst_l; | |
| 3726 | cluster_div_en__gclk clkgen_mcu3_io_gclk_if.cluster_div_en; | |
| 3727 | cmp_slow_sync_en__gclk clkgen_mcu3_io_gclk_if.cmp_slow_sync_en; | |
| 3728 | dr_sync_en__gclk void; | |
| 3729 | gclk clkgen_mcu3_io_gclk_if.gclk; | |
| 3730 | io2x_sync_en__gclk void; | |
| 3731 | l2clk__gclk clkgen_mcu3_io_gclk_if.l2clk; | |
| 3732 | pce_ov__gclk clkgen_mcu3_io_gclk_if.pce_ov; | |
| 3733 | por___gclk clkgen_mcu3_io_gclk_if.por_; | |
| 3734 | rst_por___gclk clkgen_mcu3_io_gclk_if.rst_por_; | |
| 3735 | rst_wmr___gclk clkgen_mcu3_io_gclk_if.rst_wmr_; | |
| 3736 | rst_wmr_protect__gclk clkgen_mcu3_io_gclk_if.rst_wmr_protect; | |
| 3737 | scan_en__gclk clkgen_mcu3_io_gclk_if.scan_en; | |
| 3738 | scan_in__gclk clkgen_mcu3_io_gclk_if.scan_in; | |
| 3739 | scan_out__gclk clkgen_mcu3_io_gclk_if.scan_out; | |
| 3740 | slow_cmp_sync_en__gclk clkgen_mcu3_io_gclk_if.slow_cmp_sync_en; | |
| 3741 | tcu_aclk__gclk clkgen_mcu3_io_gclk_if.tcu_aclk; | |
| 3742 | tcu_atpg_mode__gclk clkgen_mcu3_io_gclk_if.tcu_atpg_mode; | |
| 3743 | tcu_bclk__gclk clkgen_mcu3_io_gclk_if.tcu_bclk; | |
| 3744 | tcu_clk_stop__gclk clkgen_mcu3_io_gclk_if.tcu_clk_stop; | |
| 3745 | tcu_div_bypass__gclk clkgen_mcu3_io_gclk_if.tcu_div_bypass; | |
| 3746 | tcu_pce_ov__gclk clkgen_mcu3_io_gclk_if.tcu_pce_ov; | |
| 3747 | tcu_wr_inhibit__gclk clkgen_mcu3_io_gclk_if.tcu_wr_inhibit; | |
| 3748 | wmr___gclk clkgen_mcu3_io_gclk_if.wmr_; | |
| 3749 | wmr_protect__gclk clkgen_mcu3_io_gclk_if.wmr_protect; | |
| 3750 | pc_clk__gclk void; | |
| 3751 | pc_clk_sel__gclk void; | |
| 3752 | test_clk__gclk void; | |
| 3753 | test_clk_sel__gclk void; | |
| 3754 | ||
| 3755 | //---l2clk is Vera interface CLOCK--- | |
| 3756 | aclk__l2clk clkgen_mcu3_io_l2clk_if.aclk; | |
| 3757 | aclk_wmr__l2clk clkgen_mcu3_io_l2clk_if.aclk_wmr; | |
| 3758 | array_wr_inhibit__l2clk clkgen_mcu3_io_l2clk_if.array_wr_inhibit; | |
| 3759 | bclk__l2clk clkgen_mcu3_io_l2clk_if.bclk; | |
| 3760 | cmp_slow_sync_en__l2clk clkgen_mcu3_io_l2clk_if.cmp_slow_sync_en; | |
| 3761 | dr_sync_en__l2clk void; | |
| 3762 | io2x_sync_en__l2clk void; | |
| 3763 | l2clk clkgen_mcu3_io_l2clk_if.l2clk; | |
| 3764 | pce_ov__l2clk clkgen_mcu3_io_l2clk_if.pce_ov; | |
| 3765 | por___l2clk clkgen_mcu3_io_l2clk_if.por_; | |
| 3766 | scan_out__l2clk clkgen_mcu3_io_l2clk_if.scan_out; | |
| 3767 | slow_cmp_sync_en__l2clk clkgen_mcu3_io_l2clk_if.slow_cmp_sync_en; | |
| 3768 | wmr___l2clk clkgen_mcu3_io_l2clk_if.wmr_; | |
| 3769 | wmr_protect__l2clk clkgen_mcu3_io_l2clk_if.wmr_protect; | |
| 3770 | } | |
| 3771 | ||
| 3772 | // added this: | |
| 3773 | #ifndef FC_NO_PEU_VERA | |
| 3774 | #ifndef PEU_SYSTEMC_T2 | |
| 3775 | //----- port binding for clkgen_peu_io ----- | |
| 3776 | ||
| 3777 | bind CLKGEN_port clkgen_peu_io_bind { | |
| 3778 | //---gclk is Vera interface CLOCK--- | |
| 3779 | aclk__gclk clkgen_peu_io_gclk_if.aclk; | |
| 3780 | aclk_wmr__gclk clkgen_peu_io_gclk_if.aclk_wmr; | |
| 3781 | array_wr_inhibit__gclk clkgen_peu_io_gclk_if.array_wr_inhibit; | |
| 3782 | bclk__gclk clkgen_peu_io_gclk_if.bclk; | |
| 3783 | ccu_cmp_slow_sync_en__gclk clkgen_peu_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 3784 | ccu_div_ph__gclk clkgen_peu_io_gclk_if.ccu_div_ph; | |
| 3785 | ccu_dr_sync_en__gclk void; | |
| 3786 | ccu_io2x_sync_en__gclk void; | |
| 3787 | ccu_serdes_dtm__gclk clkgen_peu_io_gclk_if.ccu_serdes_dtm; | |
| 3788 | ccu_slow_cmp_sync_en__gclk clkgen_peu_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 3789 | clk_ext__gclk clkgen_peu_io_gclk_if.clk_ext; | |
| 3790 | cluster_arst_l__gclk clkgen_peu_io_gclk_if.cluster_arst_l; | |
| 3791 | cluster_div_en__gclk clkgen_peu_io_gclk_if.cluster_div_en; | |
| 3792 | cmp_slow_sync_en__gclk clkgen_peu_io_gclk_if.cmp_slow_sync_en; | |
| 3793 | dr_sync_en__gclk void; | |
| 3794 | gclk clkgen_peu_io_gclk_if.gclk; | |
| 3795 | io2x_sync_en__gclk void; | |
| 3796 | l2clk__gclk clkgen_peu_io_gclk_if.l2clk; | |
| 3797 | pce_ov__gclk clkgen_peu_io_gclk_if.pce_ov; | |
| 3798 | por___gclk clkgen_peu_io_gclk_if.por_; | |
| 3799 | rst_por___gclk clkgen_peu_io_gclk_if.rst_por_; | |
| 3800 | rst_wmr___gclk clkgen_peu_io_gclk_if.rst_wmr_; | |
| 3801 | rst_wmr_protect__gclk clkgen_peu_io_gclk_if.rst_wmr_protect; | |
| 3802 | scan_en__gclk clkgen_peu_io_gclk_if.scan_en; | |
| 3803 | scan_in__gclk clkgen_peu_io_gclk_if.scan_in; | |
| 3804 | scan_out__gclk clkgen_peu_io_gclk_if.scan_out; | |
| 3805 | slow_cmp_sync_en__gclk clkgen_peu_io_gclk_if.slow_cmp_sync_en; | |
| 3806 | tcu_aclk__gclk clkgen_peu_io_gclk_if.tcu_aclk; | |
| 3807 | tcu_atpg_mode__gclk clkgen_peu_io_gclk_if.tcu_atpg_mode; | |
| 3808 | tcu_bclk__gclk clkgen_peu_io_gclk_if.tcu_bclk; | |
| 3809 | tcu_clk_stop__gclk clkgen_peu_io_gclk_if.tcu_clk_stop; | |
| 3810 | tcu_div_bypass__gclk clkgen_peu_io_gclk_if.tcu_div_bypass; | |
| 3811 | tcu_pce_ov__gclk clkgen_peu_io_gclk_if.tcu_pce_ov; | |
| 3812 | tcu_wr_inhibit__gclk clkgen_peu_io_gclk_if.tcu_wr_inhibit; | |
| 3813 | wmr___gclk clkgen_peu_io_gclk_if.wmr_; | |
| 3814 | wmr_protect__gclk clkgen_peu_io_gclk_if.wmr_protect; | |
| 3815 | pc_clk__gclk void; | |
| 3816 | pc_clk_sel__gclk void; | |
| 3817 | test_clk__gclk void; | |
| 3818 | test_clk_sel__gclk void; | |
| 3819 | ||
| 3820 | //---l2clk is Vera interface CLOCK--- | |
| 3821 | aclk__l2clk clkgen_peu_io_l2clk_if.aclk; | |
| 3822 | aclk_wmr__l2clk clkgen_peu_io_l2clk_if.aclk_wmr; | |
| 3823 | array_wr_inhibit__l2clk clkgen_peu_io_l2clk_if.array_wr_inhibit; | |
| 3824 | bclk__l2clk clkgen_peu_io_l2clk_if.bclk; | |
| 3825 | cmp_slow_sync_en__l2clk clkgen_peu_io_l2clk_if.cmp_slow_sync_en; | |
| 3826 | dr_sync_en__l2clk void; | |
| 3827 | io2x_sync_en__l2clk void; | |
| 3828 | l2clk clkgen_peu_io_l2clk_if.l2clk; | |
| 3829 | pce_ov__l2clk clkgen_peu_io_l2clk_if.pce_ov; | |
| 3830 | por___l2clk clkgen_peu_io_l2clk_if.por_; | |
| 3831 | scan_out__l2clk clkgen_peu_io_l2clk_if.scan_out; | |
| 3832 | slow_cmp_sync_en__l2clk clkgen_peu_io_l2clk_if.slow_cmp_sync_en; | |
| 3833 | wmr___l2clk clkgen_peu_io_l2clk_if.wmr_; | |
| 3834 | wmr_protect__l2clk clkgen_peu_io_l2clk_if.wmr_protect; | |
| 3835 | } | |
| 3836 | ||
| 3837 | //----- port binding for clkgen_peu_pc ----- | |
| 3838 | ||
| 3839 | bind CLKGEN_port clkgen_peu_pc_bind { | |
| 3840 | //---gclk is Vera interface CLOCK--- | |
| 3841 | aclk__gclk clkgen_peu_pc_gclk_if.aclk; | |
| 3842 | aclk_wmr__gclk clkgen_peu_pc_gclk_if.aclk_wmr; | |
| 3843 | array_wr_inhibit__gclk clkgen_peu_pc_gclk_if.array_wr_inhibit; | |
| 3844 | bclk__gclk clkgen_peu_pc_gclk_if.bclk; | |
| 3845 | ccu_cmp_slow_sync_en__gclk void; | |
| 3846 | ccu_div_ph__gclk clkgen_peu_pc_gclk_if.ccu_div_ph; | |
| 3847 | ccu_dr_sync_en__gclk void; | |
| 3848 | ccu_io2x_sync_en__gclk void; | |
| 3849 | ccu_serdes_dtm__gclk void; | |
| 3850 | ccu_slow_cmp_sync_en__gclk void; | |
| 3851 | clk_ext__gclk void; | |
| 3852 | cluster_arst_l__gclk clkgen_peu_pc_gclk_if.cluster_arst_l; | |
| 3853 | cluster_div_en__gclk clkgen_peu_pc_gclk_if.cluster_div_en; | |
| 3854 | cmp_slow_sync_en__gclk void; | |
| 3855 | dr_sync_en__gclk void; | |
| 3856 | gclk clkgen_peu_pc_gclk_if.gclk; | |
| 3857 | io2x_sync_en__gclk void; | |
| 3858 | l2clk__gclk clkgen_peu_pc_gclk_if.l2clk; | |
| 3859 | pce_ov__gclk clkgen_peu_pc_gclk_if.pce_ov; | |
| 3860 | por___gclk clkgen_peu_pc_gclk_if.por_; | |
| 3861 | rst_por___gclk clkgen_peu_pc_gclk_if.rst_por_; | |
| 3862 | rst_wmr___gclk clkgen_peu_pc_gclk_if.rst_wmr_; | |
| 3863 | rst_wmr_protect__gclk clkgen_peu_pc_gclk_if.rst_wmr_protect; | |
| 3864 | scan_en__gclk clkgen_peu_pc_gclk_if.scan_en; | |
| 3865 | scan_in__gclk clkgen_peu_pc_gclk_if.scan_in; | |
| 3866 | scan_out__gclk clkgen_peu_pc_gclk_if.scan_out; | |
| 3867 | slow_cmp_sync_en__gclk void; | |
| 3868 | tcu_aclk__gclk clkgen_peu_pc_gclk_if.tcu_aclk; | |
| 3869 | tcu_atpg_mode__gclk clkgen_peu_pc_gclk_if.tcu_atpg_mode; | |
| 3870 | tcu_bclk__gclk clkgen_peu_pc_gclk_if.tcu_bclk; | |
| 3871 | tcu_clk_stop__gclk clkgen_peu_pc_gclk_if.tcu_clk_stop; | |
| 3872 | tcu_div_bypass__gclk void; | |
| 3873 | tcu_pce_ov__gclk clkgen_peu_pc_gclk_if.tcu_pce_ov; | |
| 3874 | tcu_wr_inhibit__gclk clkgen_peu_pc_gclk_if.tcu_wr_inhibit; | |
| 3875 | wmr___gclk clkgen_peu_pc_gclk_if.wmr_; | |
| 3876 | wmr_protect__gclk clkgen_peu_pc_gclk_if.wmr_protect; | |
| 3877 | pc_clk__gclk clkgen_peu_pc_gclk_if.pc_clk; | |
| 3878 | pc_clk_sel__gclk clkgen_peu_pc_gclk_if.pc_clk_sel; | |
| 3879 | test_clk__gclk clkgen_peu_pc_gclk_if.test_clk; | |
| 3880 | test_clk_sel__gclk clkgen_peu_pc_gclk_if.test_clk_sel; | |
| 3881 | ||
| 3882 | //---l2clk is Vera interface CLOCK--- | |
| 3883 | aclk__l2clk clkgen_peu_pc_l2clk_if.aclk; | |
| 3884 | aclk_wmr__l2clk clkgen_peu_pc_l2clk_if.aclk_wmr; | |
| 3885 | array_wr_inhibit__l2clk clkgen_peu_pc_l2clk_if.array_wr_inhibit; | |
| 3886 | bclk__l2clk clkgen_peu_pc_l2clk_if.bclk; | |
| 3887 | cmp_slow_sync_en__l2clk void; | |
| 3888 | dr_sync_en__l2clk void; | |
| 3889 | io2x_sync_en__l2clk void; | |
| 3890 | l2clk clkgen_peu_pc_l2clk_if.l2clk; | |
| 3891 | pce_ov__l2clk clkgen_peu_pc_l2clk_if.pce_ov; | |
| 3892 | por___l2clk clkgen_peu_pc_l2clk_if.por_; | |
| 3893 | scan_out__l2clk clkgen_peu_pc_l2clk_if.scan_out; | |
| 3894 | slow_cmp_sync_en__l2clk void; | |
| 3895 | wmr___l2clk clkgen_peu_pc_l2clk_if.wmr_; | |
| 3896 | wmr_protect__l2clk clkgen_peu_pc_l2clk_if.wmr_protect; | |
| 3897 | } | |
| 3898 | #endif | |
| 3899 | #endif | |
| 3900 | #ifndef FC_NO_NIU_T2 | |
| 3901 | #ifndef NIU_SYSTEMC_T2 | |
| 3902 | //----- port binding for clkgen_rdp_io ----- | |
| 3903 | ||
| 3904 | bind CLKGEN_port clkgen_rdp_io_bind { | |
| 3905 | //---gclk is Vera interface CLOCK--- | |
| 3906 | aclk__gclk clkgen_rdp_io_gclk_if.aclk; | |
| 3907 | aclk_wmr__gclk clkgen_rdp_io_gclk_if.aclk_wmr; | |
| 3908 | array_wr_inhibit__gclk clkgen_rdp_io_gclk_if.array_wr_inhibit; | |
| 3909 | bclk__gclk clkgen_rdp_io_gclk_if.bclk; | |
| 3910 | ccu_cmp_slow_sync_en__gclk clkgen_rdp_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 3911 | ccu_div_ph__gclk clkgen_rdp_io_gclk_if.ccu_div_ph; | |
| 3912 | ccu_dr_sync_en__gclk void; | |
| 3913 | ccu_io2x_sync_en__gclk void; | |
| 3914 | ccu_serdes_dtm__gclk clkgen_rdp_io_gclk_if.ccu_serdes_dtm; | |
| 3915 | ccu_slow_cmp_sync_en__gclk clkgen_rdp_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 3916 | clk_ext__gclk clkgen_rdp_io_gclk_if.clk_ext; | |
| 3917 | cluster_arst_l__gclk clkgen_rdp_io_gclk_if.cluster_arst_l; | |
| 3918 | cluster_div_en__gclk clkgen_rdp_io_gclk_if.cluster_div_en; | |
| 3919 | cmp_slow_sync_en__gclk clkgen_rdp_io_gclk_if.cmp_slow_sync_en; | |
| 3920 | dr_sync_en__gclk void; | |
| 3921 | gclk clkgen_rdp_io_gclk_if.gclk; | |
| 3922 | io2x_sync_en__gclk void; | |
| 3923 | l2clk__gclk clkgen_rdp_io_gclk_if.l2clk; | |
| 3924 | pce_ov__gclk clkgen_rdp_io_gclk_if.pce_ov; | |
| 3925 | por___gclk clkgen_rdp_io_gclk_if.por_; | |
| 3926 | rst_por___gclk clkgen_rdp_io_gclk_if.rst_por_; | |
| 3927 | rst_wmr___gclk clkgen_rdp_io_gclk_if.rst_wmr_; | |
| 3928 | rst_wmr_protect__gclk clkgen_rdp_io_gclk_if.rst_wmr_protect; | |
| 3929 | scan_en__gclk clkgen_rdp_io_gclk_if.scan_en; | |
| 3930 | scan_in__gclk clkgen_rdp_io_gclk_if.scan_in; | |
| 3931 | scan_out__gclk clkgen_rdp_io_gclk_if.scan_out; | |
| 3932 | slow_cmp_sync_en__gclk clkgen_rdp_io_gclk_if.slow_cmp_sync_en; | |
| 3933 | tcu_aclk__gclk clkgen_rdp_io_gclk_if.tcu_aclk; | |
| 3934 | tcu_atpg_mode__gclk clkgen_rdp_io_gclk_if.tcu_atpg_mode; | |
| 3935 | tcu_bclk__gclk clkgen_rdp_io_gclk_if.tcu_bclk; | |
| 3936 | tcu_clk_stop__gclk clkgen_rdp_io_gclk_if.tcu_clk_stop; | |
| 3937 | tcu_div_bypass__gclk clkgen_rdp_io_gclk_if.tcu_div_bypass; | |
| 3938 | tcu_pce_ov__gclk clkgen_rdp_io_gclk_if.tcu_pce_ov; | |
| 3939 | tcu_wr_inhibit__gclk clkgen_rdp_io_gclk_if.tcu_wr_inhibit; | |
| 3940 | wmr___gclk clkgen_rdp_io_gclk_if.wmr_; | |
| 3941 | wmr_protect__gclk clkgen_rdp_io_gclk_if.wmr_protect; | |
| 3942 | pc_clk__gclk void; | |
| 3943 | pc_clk_sel__gclk void; | |
| 3944 | test_clk__gclk void; | |
| 3945 | test_clk_sel__gclk void; | |
| 3946 | ||
| 3947 | //---l2clk is Vera interface CLOCK--- | |
| 3948 | aclk__l2clk clkgen_rdp_io_l2clk_if.aclk; | |
| 3949 | aclk_wmr__l2clk clkgen_rdp_io_l2clk_if.aclk_wmr; | |
| 3950 | array_wr_inhibit__l2clk clkgen_rdp_io_l2clk_if.array_wr_inhibit; | |
| 3951 | bclk__l2clk clkgen_rdp_io_l2clk_if.bclk; | |
| 3952 | cmp_slow_sync_en__l2clk clkgen_rdp_io_l2clk_if.cmp_slow_sync_en; | |
| 3953 | dr_sync_en__l2clk void; | |
| 3954 | io2x_sync_en__l2clk void; | |
| 3955 | l2clk clkgen_rdp_io_l2clk_if.l2clk; | |
| 3956 | pce_ov__l2clk clkgen_rdp_io_l2clk_if.pce_ov; | |
| 3957 | por___l2clk clkgen_rdp_io_l2clk_if.por_; | |
| 3958 | scan_out__l2clk clkgen_rdp_io_l2clk_if.scan_out; | |
| 3959 | slow_cmp_sync_en__l2clk clkgen_rdp_io_l2clk_if.slow_cmp_sync_en; | |
| 3960 | wmr___l2clk clkgen_rdp_io_l2clk_if.wmr_; | |
| 3961 | wmr_protect__l2clk clkgen_rdp_io_l2clk_if.wmr_protect; | |
| 3962 | } | |
| 3963 | ||
| 3964 | //----- port binding for clkgen_rdp_io2x ----- | |
| 3965 | ||
| 3966 | bind CLKGEN_port clkgen_rdp_io2x_bind { | |
| 3967 | //---gclk is Vera interface CLOCK--- | |
| 3968 | aclk__gclk clkgen_rdp_io2x_gclk_if.aclk; | |
| 3969 | aclk_wmr__gclk clkgen_rdp_io2x_gclk_if.aclk_wmr; | |
| 3970 | array_wr_inhibit__gclk clkgen_rdp_io2x_gclk_if.array_wr_inhibit; | |
| 3971 | bclk__gclk clkgen_rdp_io2x_gclk_if.bclk; | |
| 3972 | ccu_cmp_slow_sync_en__gclk clkgen_rdp_io2x_gclk_if.ccu_cmp_slow_sync_en; | |
| 3973 | ccu_div_ph__gclk clkgen_rdp_io2x_gclk_if.ccu_div_ph; | |
| 3974 | ccu_dr_sync_en__gclk void; | |
| 3975 | ccu_io2x_sync_en__gclk void; | |
| 3976 | ccu_serdes_dtm__gclk clkgen_rdp_io2x_gclk_if.ccu_serdes_dtm; | |
| 3977 | ccu_slow_cmp_sync_en__gclk clkgen_rdp_io2x_gclk_if.ccu_slow_cmp_sync_en; | |
| 3978 | clk_ext__gclk clkgen_rdp_io2x_gclk_if.clk_ext; | |
| 3979 | cluster_arst_l__gclk clkgen_rdp_io2x_gclk_if.cluster_arst_l; | |
| 3980 | cluster_div_en__gclk clkgen_rdp_io2x_gclk_if.cluster_div_en; | |
| 3981 | cmp_slow_sync_en__gclk clkgen_rdp_io2x_gclk_if.cmp_slow_sync_en; | |
| 3982 | dr_sync_en__gclk void; | |
| 3983 | gclk clkgen_rdp_io2x_gclk_if.gclk; | |
| 3984 | io2x_sync_en__gclk void; | |
| 3985 | l2clk__gclk clkgen_rdp_io2x_gclk_if.l2clk; | |
| 3986 | pce_ov__gclk clkgen_rdp_io2x_gclk_if.pce_ov; | |
| 3987 | por___gclk clkgen_rdp_io2x_gclk_if.por_; | |
| 3988 | rst_por___gclk clkgen_rdp_io2x_gclk_if.rst_por_; | |
| 3989 | rst_wmr___gclk clkgen_rdp_io2x_gclk_if.rst_wmr_; | |
| 3990 | rst_wmr_protect__gclk clkgen_rdp_io2x_gclk_if.rst_wmr_protect; | |
| 3991 | scan_en__gclk clkgen_rdp_io2x_gclk_if.scan_en; | |
| 3992 | scan_in__gclk clkgen_rdp_io2x_gclk_if.scan_in; | |
| 3993 | scan_out__gclk clkgen_rdp_io2x_gclk_if.scan_out; | |
| 3994 | slow_cmp_sync_en__gclk clkgen_rdp_io2x_gclk_if.slow_cmp_sync_en; | |
| 3995 | tcu_aclk__gclk clkgen_rdp_io2x_gclk_if.tcu_aclk; | |
| 3996 | tcu_atpg_mode__gclk clkgen_rdp_io2x_gclk_if.tcu_atpg_mode; | |
| 3997 | tcu_bclk__gclk clkgen_rdp_io2x_gclk_if.tcu_bclk; | |
| 3998 | tcu_clk_stop__gclk clkgen_rdp_io2x_gclk_if.tcu_clk_stop; | |
| 3999 | tcu_div_bypass__gclk clkgen_rdp_io2x_gclk_if.tcu_div_bypass; | |
| 4000 | tcu_pce_ov__gclk clkgen_rdp_io2x_gclk_if.tcu_pce_ov; | |
| 4001 | tcu_wr_inhibit__gclk clkgen_rdp_io2x_gclk_if.tcu_wr_inhibit; | |
| 4002 | wmr___gclk clkgen_rdp_io2x_gclk_if.wmr_; | |
| 4003 | wmr_protect__gclk clkgen_rdp_io2x_gclk_if.wmr_protect; | |
| 4004 | pc_clk__gclk void; | |
| 4005 | pc_clk_sel__gclk void; | |
| 4006 | test_clk__gclk void; | |
| 4007 | test_clk_sel__gclk void; | |
| 4008 | ||
| 4009 | //---l2clk is Vera interface CLOCK--- | |
| 4010 | aclk__l2clk clkgen_rdp_io2x_l2clk_if.aclk; | |
| 4011 | aclk_wmr__l2clk clkgen_rdp_io2x_l2clk_if.aclk_wmr; | |
| 4012 | array_wr_inhibit__l2clk clkgen_rdp_io2x_l2clk_if.array_wr_inhibit; | |
| 4013 | bclk__l2clk clkgen_rdp_io2x_l2clk_if.bclk; | |
| 4014 | cmp_slow_sync_en__l2clk clkgen_rdp_io2x_l2clk_if.cmp_slow_sync_en; | |
| 4015 | dr_sync_en__l2clk void; | |
| 4016 | io2x_sync_en__l2clk void; | |
| 4017 | l2clk clkgen_rdp_io2x_l2clk_if.l2clk; | |
| 4018 | pce_ov__l2clk clkgen_rdp_io2x_l2clk_if.pce_ov; | |
| 4019 | por___l2clk clkgen_rdp_io2x_l2clk_if.por_; | |
| 4020 | scan_out__l2clk clkgen_rdp_io2x_l2clk_if.scan_out; | |
| 4021 | slow_cmp_sync_en__l2clk clkgen_rdp_io2x_l2clk_if.slow_cmp_sync_en; | |
| 4022 | wmr___l2clk clkgen_rdp_io2x_l2clk_if.wmr_; | |
| 4023 | wmr_protect__l2clk clkgen_rdp_io2x_l2clk_if.wmr_protect; | |
| 4024 | } | |
| 4025 | ||
| 4026 | //----- port binding for clkgen_rtx_io ----- | |
| 4027 | ||
| 4028 | bind CLKGEN_port clkgen_rtx_io_bind { | |
| 4029 | //---gclk is Vera interface CLOCK--- | |
| 4030 | aclk__gclk clkgen_rtx_io_gclk_if.aclk; | |
| 4031 | aclk_wmr__gclk clkgen_rtx_io_gclk_if.aclk_wmr; | |
| 4032 | array_wr_inhibit__gclk clkgen_rtx_io_gclk_if.array_wr_inhibit; | |
| 4033 | bclk__gclk clkgen_rtx_io_gclk_if.bclk; | |
| 4034 | ccu_cmp_slow_sync_en__gclk clkgen_rtx_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 4035 | ccu_div_ph__gclk clkgen_rtx_io_gclk_if.ccu_div_ph; | |
| 4036 | ccu_dr_sync_en__gclk void; | |
| 4037 | ccu_io2x_sync_en__gclk void; | |
| 4038 | ccu_serdes_dtm__gclk clkgen_rtx_io_gclk_if.ccu_serdes_dtm; | |
| 4039 | ccu_slow_cmp_sync_en__gclk clkgen_rtx_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 4040 | clk_ext__gclk clkgen_rtx_io_gclk_if.clk_ext; | |
| 4041 | cluster_arst_l__gclk clkgen_rtx_io_gclk_if.cluster_arst_l; | |
| 4042 | cluster_div_en__gclk clkgen_rtx_io_gclk_if.cluster_div_en; | |
| 4043 | cmp_slow_sync_en__gclk clkgen_rtx_io_gclk_if.cmp_slow_sync_en; | |
| 4044 | dr_sync_en__gclk void; | |
| 4045 | gclk clkgen_rtx_io_gclk_if.gclk; | |
| 4046 | io2x_sync_en__gclk void; | |
| 4047 | l2clk__gclk clkgen_rtx_io_gclk_if.l2clk; | |
| 4048 | pce_ov__gclk clkgen_rtx_io_gclk_if.pce_ov; | |
| 4049 | por___gclk clkgen_rtx_io_gclk_if.por_; | |
| 4050 | rst_por___gclk clkgen_rtx_io_gclk_if.rst_por_; | |
| 4051 | rst_wmr___gclk clkgen_rtx_io_gclk_if.rst_wmr_; | |
| 4052 | rst_wmr_protect__gclk clkgen_rtx_io_gclk_if.rst_wmr_protect; | |
| 4053 | scan_en__gclk clkgen_rtx_io_gclk_if.scan_en; | |
| 4054 | scan_in__gclk clkgen_rtx_io_gclk_if.scan_in; | |
| 4055 | scan_out__gclk clkgen_rtx_io_gclk_if.scan_out; | |
| 4056 | slow_cmp_sync_en__gclk clkgen_rtx_io_gclk_if.slow_cmp_sync_en; | |
| 4057 | tcu_aclk__gclk clkgen_rtx_io_gclk_if.tcu_aclk; | |
| 4058 | tcu_atpg_mode__gclk clkgen_rtx_io_gclk_if.tcu_atpg_mode; | |
| 4059 | tcu_bclk__gclk clkgen_rtx_io_gclk_if.tcu_bclk; | |
| 4060 | tcu_clk_stop__gclk clkgen_rtx_io_gclk_if.tcu_clk_stop; | |
| 4061 | tcu_div_bypass__gclk clkgen_rtx_io_gclk_if.tcu_div_bypass; | |
| 4062 | tcu_pce_ov__gclk clkgen_rtx_io_gclk_if.tcu_pce_ov; | |
| 4063 | tcu_wr_inhibit__gclk clkgen_rtx_io_gclk_if.tcu_wr_inhibit; | |
| 4064 | wmr___gclk clkgen_rtx_io_gclk_if.wmr_; | |
| 4065 | wmr_protect__gclk clkgen_rtx_io_gclk_if.wmr_protect; | |
| 4066 | pc_clk__gclk void; | |
| 4067 | pc_clk_sel__gclk void; | |
| 4068 | test_clk__gclk void; | |
| 4069 | test_clk_sel__gclk void; | |
| 4070 | ||
| 4071 | //---l2clk is Vera interface CLOCK--- | |
| 4072 | aclk__l2clk clkgen_rtx_io_l2clk_if.aclk; | |
| 4073 | aclk_wmr__l2clk clkgen_rtx_io_l2clk_if.aclk_wmr; | |
| 4074 | array_wr_inhibit__l2clk clkgen_rtx_io_l2clk_if.array_wr_inhibit; | |
| 4075 | bclk__l2clk clkgen_rtx_io_l2clk_if.bclk; | |
| 4076 | cmp_slow_sync_en__l2clk clkgen_rtx_io_l2clk_if.cmp_slow_sync_en; | |
| 4077 | dr_sync_en__l2clk void; | |
| 4078 | io2x_sync_en__l2clk void; | |
| 4079 | l2clk clkgen_rtx_io_l2clk_if.l2clk; | |
| 4080 | pce_ov__l2clk clkgen_rtx_io_l2clk_if.pce_ov; | |
| 4081 | por___l2clk clkgen_rtx_io_l2clk_if.por_; | |
| 4082 | scan_out__l2clk clkgen_rtx_io_l2clk_if.scan_out; | |
| 4083 | slow_cmp_sync_en__l2clk clkgen_rtx_io_l2clk_if.slow_cmp_sync_en; | |
| 4084 | wmr___l2clk clkgen_rtx_io_l2clk_if.wmr_; | |
| 4085 | wmr_protect__l2clk clkgen_rtx_io_l2clk_if.wmr_protect; | |
| 4086 | } | |
| 4087 | ||
| 4088 | //----- port binding for clkgen_rtx_io2x ----- | |
| 4089 | ||
| 4090 | bind CLKGEN_port clkgen_rtx_io2x_bind { | |
| 4091 | //---gclk is Vera interface CLOCK--- | |
| 4092 | aclk__gclk clkgen_rtx_io2x_gclk_if.aclk; | |
| 4093 | aclk_wmr__gclk clkgen_rtx_io2x_gclk_if.aclk_wmr; | |
| 4094 | array_wr_inhibit__gclk clkgen_rtx_io2x_gclk_if.array_wr_inhibit; | |
| 4095 | bclk__gclk clkgen_rtx_io2x_gclk_if.bclk; | |
| 4096 | ccu_cmp_slow_sync_en__gclk clkgen_rtx_io2x_gclk_if.ccu_cmp_slow_sync_en; | |
| 4097 | ccu_div_ph__gclk clkgen_rtx_io2x_gclk_if.ccu_div_ph; | |
| 4098 | ccu_dr_sync_en__gclk void; | |
| 4099 | ccu_io2x_sync_en__gclk void; | |
| 4100 | ccu_serdes_dtm__gclk clkgen_rtx_io2x_gclk_if.ccu_serdes_dtm; | |
| 4101 | ccu_slow_cmp_sync_en__gclk clkgen_rtx_io2x_gclk_if.ccu_slow_cmp_sync_en; | |
| 4102 | clk_ext__gclk clkgen_rtx_io2x_gclk_if.clk_ext; | |
| 4103 | cluster_arst_l__gclk clkgen_rtx_io2x_gclk_if.cluster_arst_l; | |
| 4104 | cluster_div_en__gclk clkgen_rtx_io2x_gclk_if.cluster_div_en; | |
| 4105 | cmp_slow_sync_en__gclk clkgen_rtx_io2x_gclk_if.cmp_slow_sync_en; | |
| 4106 | dr_sync_en__gclk void; | |
| 4107 | gclk clkgen_rtx_io2x_gclk_if.gclk; | |
| 4108 | io2x_sync_en__gclk void; | |
| 4109 | l2clk__gclk clkgen_rtx_io2x_gclk_if.l2clk; | |
| 4110 | pce_ov__gclk clkgen_rtx_io2x_gclk_if.pce_ov; | |
| 4111 | por___gclk clkgen_rtx_io2x_gclk_if.por_; | |
| 4112 | rst_por___gclk clkgen_rtx_io2x_gclk_if.rst_por_; | |
| 4113 | rst_wmr___gclk clkgen_rtx_io2x_gclk_if.rst_wmr_; | |
| 4114 | rst_wmr_protect__gclk clkgen_rtx_io2x_gclk_if.rst_wmr_protect; | |
| 4115 | scan_en__gclk clkgen_rtx_io2x_gclk_if.scan_en; | |
| 4116 | scan_in__gclk clkgen_rtx_io2x_gclk_if.scan_in; | |
| 4117 | scan_out__gclk clkgen_rtx_io2x_gclk_if.scan_out; | |
| 4118 | slow_cmp_sync_en__gclk clkgen_rtx_io2x_gclk_if.slow_cmp_sync_en; | |
| 4119 | tcu_aclk__gclk clkgen_rtx_io2x_gclk_if.tcu_aclk; | |
| 4120 | tcu_atpg_mode__gclk clkgen_rtx_io2x_gclk_if.tcu_atpg_mode; | |
| 4121 | tcu_bclk__gclk clkgen_rtx_io2x_gclk_if.tcu_bclk; | |
| 4122 | tcu_clk_stop__gclk clkgen_rtx_io2x_gclk_if.tcu_clk_stop; | |
| 4123 | tcu_div_bypass__gclk clkgen_rtx_io2x_gclk_if.tcu_div_bypass; | |
| 4124 | tcu_pce_ov__gclk clkgen_rtx_io2x_gclk_if.tcu_pce_ov; | |
| 4125 | tcu_wr_inhibit__gclk clkgen_rtx_io2x_gclk_if.tcu_wr_inhibit; | |
| 4126 | wmr___gclk clkgen_rtx_io2x_gclk_if.wmr_; | |
| 4127 | wmr_protect__gclk clkgen_rtx_io2x_gclk_if.wmr_protect; | |
| 4128 | pc_clk__gclk void; | |
| 4129 | pc_clk_sel__gclk void; | |
| 4130 | test_clk__gclk void; | |
| 4131 | test_clk_sel__gclk void; | |
| 4132 | ||
| 4133 | //---l2clk is Vera interface CLOCK--- | |
| 4134 | aclk__l2clk clkgen_rtx_io2x_l2clk_if.aclk; | |
| 4135 | aclk_wmr__l2clk clkgen_rtx_io2x_l2clk_if.aclk_wmr; | |
| 4136 | array_wr_inhibit__l2clk clkgen_rtx_io2x_l2clk_if.array_wr_inhibit; | |
| 4137 | bclk__l2clk clkgen_rtx_io2x_l2clk_if.bclk; | |
| 4138 | cmp_slow_sync_en__l2clk clkgen_rtx_io2x_l2clk_if.cmp_slow_sync_en; | |
| 4139 | dr_sync_en__l2clk void; | |
| 4140 | io2x_sync_en__l2clk void; | |
| 4141 | l2clk clkgen_rtx_io2x_l2clk_if.l2clk; | |
| 4142 | pce_ov__l2clk clkgen_rtx_io2x_l2clk_if.pce_ov; | |
| 4143 | por___l2clk clkgen_rtx_io2x_l2clk_if.por_; | |
| 4144 | scan_out__l2clk clkgen_rtx_io2x_l2clk_if.scan_out; | |
| 4145 | slow_cmp_sync_en__l2clk clkgen_rtx_io2x_l2clk_if.slow_cmp_sync_en; | |
| 4146 | wmr___l2clk clkgen_rtx_io2x_l2clk_if.wmr_; | |
| 4147 | wmr_protect__l2clk clkgen_rtx_io2x_l2clk_if.wmr_protect; | |
| 4148 | } | |
| 4149 | #endif | |
| 4150 | #endif | |
| 4151 | ||
| 4152 | //----- port binding for clkgen_sii_cmp ----- | |
| 4153 | ||
| 4154 | bind CLKGEN_port clkgen_sii_cmp_bind { | |
| 4155 | //---gclk is Vera interface CLOCK--- | |
| 4156 | aclk__gclk clkgen_sii_cmp_gclk_if.aclk; | |
| 4157 | aclk_wmr__gclk clkgen_sii_cmp_gclk_if.aclk_wmr; | |
| 4158 | array_wr_inhibit__gclk clkgen_sii_cmp_gclk_if.array_wr_inhibit; | |
| 4159 | bclk__gclk clkgen_sii_cmp_gclk_if.bclk; | |
| 4160 | ccu_cmp_slow_sync_en__gclk clkgen_sii_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 4161 | ccu_div_ph__gclk clkgen_sii_cmp_gclk_if.ccu_div_ph; | |
| 4162 | ccu_dr_sync_en__gclk void; | |
| 4163 | ccu_io2x_sync_en__gclk void; | |
| 4164 | ccu_serdes_dtm__gclk clkgen_sii_cmp_gclk_if.ccu_serdes_dtm; | |
| 4165 | ccu_slow_cmp_sync_en__gclk clkgen_sii_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 4166 | clk_ext__gclk clkgen_sii_cmp_gclk_if.clk_ext; | |
| 4167 | cluster_arst_l__gclk clkgen_sii_cmp_gclk_if.cluster_arst_l; | |
| 4168 | cluster_div_en__gclk clkgen_sii_cmp_gclk_if.cluster_div_en; | |
| 4169 | cmp_slow_sync_en__gclk clkgen_sii_cmp_gclk_if.cmp_slow_sync_en; | |
| 4170 | dr_sync_en__gclk void; | |
| 4171 | gclk clkgen_sii_cmp_gclk_if.gclk; | |
| 4172 | io2x_sync_en__gclk void; | |
| 4173 | l2clk__gclk clkgen_sii_cmp_gclk_if.l2clk; | |
| 4174 | pce_ov__gclk clkgen_sii_cmp_gclk_if.pce_ov; | |
| 4175 | por___gclk clkgen_sii_cmp_gclk_if.por_; | |
| 4176 | rst_por___gclk clkgen_sii_cmp_gclk_if.rst_por_; | |
| 4177 | rst_wmr___gclk clkgen_sii_cmp_gclk_if.rst_wmr_; | |
| 4178 | rst_wmr_protect__gclk clkgen_sii_cmp_gclk_if.rst_wmr_protect; | |
| 4179 | scan_en__gclk clkgen_sii_cmp_gclk_if.scan_en; | |
| 4180 | scan_in__gclk clkgen_sii_cmp_gclk_if.scan_in; | |
| 4181 | scan_out__gclk clkgen_sii_cmp_gclk_if.scan_out; | |
| 4182 | slow_cmp_sync_en__gclk clkgen_sii_cmp_gclk_if.slow_cmp_sync_en; | |
| 4183 | tcu_aclk__gclk clkgen_sii_cmp_gclk_if.tcu_aclk; | |
| 4184 | tcu_atpg_mode__gclk clkgen_sii_cmp_gclk_if.tcu_atpg_mode; | |
| 4185 | tcu_bclk__gclk clkgen_sii_cmp_gclk_if.tcu_bclk; | |
| 4186 | tcu_clk_stop__gclk clkgen_sii_cmp_gclk_if.tcu_clk_stop; | |
| 4187 | tcu_div_bypass__gclk clkgen_sii_cmp_gclk_if.tcu_div_bypass; | |
| 4188 | tcu_pce_ov__gclk clkgen_sii_cmp_gclk_if.tcu_pce_ov; | |
| 4189 | tcu_wr_inhibit__gclk clkgen_sii_cmp_gclk_if.tcu_wr_inhibit; | |
| 4190 | wmr___gclk clkgen_sii_cmp_gclk_if.wmr_; | |
| 4191 | wmr_protect__gclk clkgen_sii_cmp_gclk_if.wmr_protect; | |
| 4192 | pc_clk__gclk void; | |
| 4193 | pc_clk_sel__gclk void; | |
| 4194 | test_clk__gclk void; | |
| 4195 | test_clk_sel__gclk void; | |
| 4196 | ||
| 4197 | //---l2clk is Vera interface CLOCK--- | |
| 4198 | aclk__l2clk clkgen_sii_cmp_l2clk_if.aclk; | |
| 4199 | aclk_wmr__l2clk clkgen_sii_cmp_l2clk_if.aclk_wmr; | |
| 4200 | array_wr_inhibit__l2clk clkgen_sii_cmp_l2clk_if.array_wr_inhibit; | |
| 4201 | bclk__l2clk clkgen_sii_cmp_l2clk_if.bclk; | |
| 4202 | cmp_slow_sync_en__l2clk clkgen_sii_cmp_l2clk_if.cmp_slow_sync_en; | |
| 4203 | dr_sync_en__l2clk void; | |
| 4204 | io2x_sync_en__l2clk void; | |
| 4205 | l2clk clkgen_sii_cmp_l2clk_if.l2clk; | |
| 4206 | pce_ov__l2clk clkgen_sii_cmp_l2clk_if.pce_ov; | |
| 4207 | por___l2clk clkgen_sii_cmp_l2clk_if.por_; | |
| 4208 | scan_out__l2clk clkgen_sii_cmp_l2clk_if.scan_out; | |
| 4209 | slow_cmp_sync_en__l2clk clkgen_sii_cmp_l2clk_if.slow_cmp_sync_en; | |
| 4210 | wmr___l2clk clkgen_sii_cmp_l2clk_if.wmr_; | |
| 4211 | wmr_protect__l2clk clkgen_sii_cmp_l2clk_if.wmr_protect; | |
| 4212 | } | |
| 4213 | ||
| 4214 | //----- port binding for clkgen_sii_io ----- | |
| 4215 | ||
| 4216 | bind CLKGEN_port clkgen_sii_io_bind { | |
| 4217 | //---gclk is Vera interface CLOCK--- | |
| 4218 | aclk__gclk clkgen_sii_io_gclk_if.aclk; | |
| 4219 | aclk_wmr__gclk clkgen_sii_io_gclk_if.aclk_wmr; | |
| 4220 | array_wr_inhibit__gclk clkgen_sii_io_gclk_if.array_wr_inhibit; | |
| 4221 | bclk__gclk clkgen_sii_io_gclk_if.bclk; | |
| 4222 | ccu_cmp_slow_sync_en__gclk clkgen_sii_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 4223 | ccu_div_ph__gclk clkgen_sii_io_gclk_if.ccu_div_ph; | |
| 4224 | ccu_dr_sync_en__gclk void; | |
| 4225 | ccu_io2x_sync_en__gclk void; | |
| 4226 | ccu_serdes_dtm__gclk clkgen_sii_io_gclk_if.ccu_serdes_dtm; | |
| 4227 | ccu_slow_cmp_sync_en__gclk clkgen_sii_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 4228 | clk_ext__gclk clkgen_sii_io_gclk_if.clk_ext; | |
| 4229 | cluster_arst_l__gclk clkgen_sii_io_gclk_if.cluster_arst_l; | |
| 4230 | cluster_div_en__gclk clkgen_sii_io_gclk_if.cluster_div_en; | |
| 4231 | cmp_slow_sync_en__gclk clkgen_sii_io_gclk_if.cmp_slow_sync_en; | |
| 4232 | dr_sync_en__gclk void; | |
| 4233 | gclk clkgen_sii_io_gclk_if.gclk; | |
| 4234 | io2x_sync_en__gclk void; | |
| 4235 | l2clk__gclk clkgen_sii_io_gclk_if.l2clk; | |
| 4236 | pce_ov__gclk clkgen_sii_io_gclk_if.pce_ov; | |
| 4237 | por___gclk clkgen_sii_io_gclk_if.por_; | |
| 4238 | rst_por___gclk clkgen_sii_io_gclk_if.rst_por_; | |
| 4239 | rst_wmr___gclk clkgen_sii_io_gclk_if.rst_wmr_; | |
| 4240 | rst_wmr_protect__gclk clkgen_sii_io_gclk_if.rst_wmr_protect; | |
| 4241 | scan_en__gclk clkgen_sii_io_gclk_if.scan_en; | |
| 4242 | scan_in__gclk clkgen_sii_io_gclk_if.scan_in; | |
| 4243 | scan_out__gclk clkgen_sii_io_gclk_if.scan_out; | |
| 4244 | slow_cmp_sync_en__gclk clkgen_sii_io_gclk_if.slow_cmp_sync_en; | |
| 4245 | tcu_aclk__gclk clkgen_sii_io_gclk_if.tcu_aclk; | |
| 4246 | tcu_atpg_mode__gclk clkgen_sii_io_gclk_if.tcu_atpg_mode; | |
| 4247 | tcu_bclk__gclk clkgen_sii_io_gclk_if.tcu_bclk; | |
| 4248 | tcu_clk_stop__gclk clkgen_sii_io_gclk_if.tcu_clk_stop; | |
| 4249 | tcu_div_bypass__gclk clkgen_sii_io_gclk_if.tcu_div_bypass; | |
| 4250 | tcu_pce_ov__gclk clkgen_sii_io_gclk_if.tcu_pce_ov; | |
| 4251 | tcu_wr_inhibit__gclk clkgen_sii_io_gclk_if.tcu_wr_inhibit; | |
| 4252 | wmr___gclk clkgen_sii_io_gclk_if.wmr_; | |
| 4253 | wmr_protect__gclk clkgen_sii_io_gclk_if.wmr_protect; | |
| 4254 | pc_clk__gclk void; | |
| 4255 | pc_clk_sel__gclk void; | |
| 4256 | test_clk__gclk void; | |
| 4257 | test_clk_sel__gclk void; | |
| 4258 | ||
| 4259 | //---l2clk is Vera interface CLOCK--- | |
| 4260 | aclk__l2clk clkgen_sii_io_l2clk_if.aclk; | |
| 4261 | aclk_wmr__l2clk clkgen_sii_io_l2clk_if.aclk_wmr; | |
| 4262 | array_wr_inhibit__l2clk clkgen_sii_io_l2clk_if.array_wr_inhibit; | |
| 4263 | bclk__l2clk clkgen_sii_io_l2clk_if.bclk; | |
| 4264 | cmp_slow_sync_en__l2clk clkgen_sii_io_l2clk_if.cmp_slow_sync_en; | |
| 4265 | dr_sync_en__l2clk void; | |
| 4266 | io2x_sync_en__l2clk void; | |
| 4267 | l2clk clkgen_sii_io_l2clk_if.l2clk; | |
| 4268 | pce_ov__l2clk clkgen_sii_io_l2clk_if.pce_ov; | |
| 4269 | por___l2clk clkgen_sii_io_l2clk_if.por_; | |
| 4270 | scan_out__l2clk clkgen_sii_io_l2clk_if.scan_out; | |
| 4271 | slow_cmp_sync_en__l2clk clkgen_sii_io_l2clk_if.slow_cmp_sync_en; | |
| 4272 | wmr___l2clk clkgen_sii_io_l2clk_if.wmr_; | |
| 4273 | wmr_protect__l2clk clkgen_sii_io_l2clk_if.wmr_protect; | |
| 4274 | } | |
| 4275 | ||
| 4276 | //----- port binding for clkgen_sio_cmp ----- | |
| 4277 | ||
| 4278 | bind CLKGEN_port clkgen_sio_cmp_bind { | |
| 4279 | //---gclk is Vera interface CLOCK--- | |
| 4280 | aclk__gclk clkgen_sio_cmp_gclk_if.aclk; | |
| 4281 | aclk_wmr__gclk clkgen_sio_cmp_gclk_if.aclk_wmr; | |
| 4282 | array_wr_inhibit__gclk clkgen_sio_cmp_gclk_if.array_wr_inhibit; | |
| 4283 | bclk__gclk clkgen_sio_cmp_gclk_if.bclk; | |
| 4284 | ccu_cmp_slow_sync_en__gclk clkgen_sio_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 4285 | ccu_div_ph__gclk clkgen_sio_cmp_gclk_if.ccu_div_ph; | |
| 4286 | ccu_dr_sync_en__gclk void; | |
| 4287 | ccu_io2x_sync_en__gclk void; | |
| 4288 | ccu_serdes_dtm__gclk clkgen_sio_cmp_gclk_if.ccu_serdes_dtm; | |
| 4289 | ccu_slow_cmp_sync_en__gclk clkgen_sio_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 4290 | clk_ext__gclk clkgen_sio_cmp_gclk_if.clk_ext; | |
| 4291 | cluster_arst_l__gclk clkgen_sio_cmp_gclk_if.cluster_arst_l; | |
| 4292 | cluster_div_en__gclk clkgen_sio_cmp_gclk_if.cluster_div_en; | |
| 4293 | cmp_slow_sync_en__gclk clkgen_sio_cmp_gclk_if.cmp_slow_sync_en; | |
| 4294 | dr_sync_en__gclk void; | |
| 4295 | gclk clkgen_sio_cmp_gclk_if.gclk; | |
| 4296 | io2x_sync_en__gclk void; | |
| 4297 | l2clk__gclk clkgen_sio_cmp_gclk_if.l2clk; | |
| 4298 | pce_ov__gclk clkgen_sio_cmp_gclk_if.pce_ov; | |
| 4299 | por___gclk clkgen_sio_cmp_gclk_if.por_; | |
| 4300 | rst_por___gclk clkgen_sio_cmp_gclk_if.rst_por_; | |
| 4301 | rst_wmr___gclk clkgen_sio_cmp_gclk_if.rst_wmr_; | |
| 4302 | rst_wmr_protect__gclk clkgen_sio_cmp_gclk_if.rst_wmr_protect; | |
| 4303 | scan_en__gclk clkgen_sio_cmp_gclk_if.scan_en; | |
| 4304 | scan_in__gclk clkgen_sio_cmp_gclk_if.scan_in; | |
| 4305 | scan_out__gclk clkgen_sio_cmp_gclk_if.scan_out; | |
| 4306 | slow_cmp_sync_en__gclk clkgen_sio_cmp_gclk_if.slow_cmp_sync_en; | |
| 4307 | tcu_aclk__gclk clkgen_sio_cmp_gclk_if.tcu_aclk; | |
| 4308 | tcu_atpg_mode__gclk clkgen_sio_cmp_gclk_if.tcu_atpg_mode; | |
| 4309 | tcu_bclk__gclk clkgen_sio_cmp_gclk_if.tcu_bclk; | |
| 4310 | tcu_clk_stop__gclk clkgen_sio_cmp_gclk_if.tcu_clk_stop; | |
| 4311 | tcu_div_bypass__gclk clkgen_sio_cmp_gclk_if.tcu_div_bypass; | |
| 4312 | tcu_pce_ov__gclk clkgen_sio_cmp_gclk_if.tcu_pce_ov; | |
| 4313 | tcu_wr_inhibit__gclk clkgen_sio_cmp_gclk_if.tcu_wr_inhibit; | |
| 4314 | wmr___gclk clkgen_sio_cmp_gclk_if.wmr_; | |
| 4315 | wmr_protect__gclk clkgen_sio_cmp_gclk_if.wmr_protect; | |
| 4316 | pc_clk__gclk void; | |
| 4317 | pc_clk_sel__gclk void; | |
| 4318 | test_clk__gclk void; | |
| 4319 | test_clk_sel__gclk void; | |
| 4320 | ||
| 4321 | //---l2clk is Vera interface CLOCK--- | |
| 4322 | aclk__l2clk clkgen_sio_cmp_l2clk_if.aclk; | |
| 4323 | aclk_wmr__l2clk clkgen_sio_cmp_l2clk_if.aclk_wmr; | |
| 4324 | array_wr_inhibit__l2clk clkgen_sio_cmp_l2clk_if.array_wr_inhibit; | |
| 4325 | bclk__l2clk clkgen_sio_cmp_l2clk_if.bclk; | |
| 4326 | cmp_slow_sync_en__l2clk clkgen_sio_cmp_l2clk_if.cmp_slow_sync_en; | |
| 4327 | dr_sync_en__l2clk void; | |
| 4328 | io2x_sync_en__l2clk void; | |
| 4329 | l2clk clkgen_sio_cmp_l2clk_if.l2clk; | |
| 4330 | pce_ov__l2clk clkgen_sio_cmp_l2clk_if.pce_ov; | |
| 4331 | por___l2clk clkgen_sio_cmp_l2clk_if.por_; | |
| 4332 | scan_out__l2clk clkgen_sio_cmp_l2clk_if.scan_out; | |
| 4333 | slow_cmp_sync_en__l2clk clkgen_sio_cmp_l2clk_if.slow_cmp_sync_en; | |
| 4334 | wmr___l2clk clkgen_sio_cmp_l2clk_if.wmr_; | |
| 4335 | wmr_protect__l2clk clkgen_sio_cmp_l2clk_if.wmr_protect; | |
| 4336 | } | |
| 4337 | ||
| 4338 | //----- port binding for clkgen_sio_io ----- | |
| 4339 | ||
| 4340 | bind CLKGEN_port clkgen_sio_io_bind { | |
| 4341 | //---gclk is Vera interface CLOCK--- | |
| 4342 | aclk__gclk clkgen_sio_io_gclk_if.aclk; | |
| 4343 | aclk_wmr__gclk clkgen_sio_io_gclk_if.aclk_wmr; | |
| 4344 | array_wr_inhibit__gclk clkgen_sio_io_gclk_if.array_wr_inhibit; | |
| 4345 | bclk__gclk clkgen_sio_io_gclk_if.bclk; | |
| 4346 | ccu_cmp_slow_sync_en__gclk clkgen_sio_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 4347 | ccu_div_ph__gclk clkgen_sio_io_gclk_if.ccu_div_ph; | |
| 4348 | ccu_dr_sync_en__gclk void; | |
| 4349 | ccu_io2x_sync_en__gclk void; | |
| 4350 | ccu_serdes_dtm__gclk clkgen_sio_io_gclk_if.ccu_serdes_dtm; | |
| 4351 | ccu_slow_cmp_sync_en__gclk clkgen_sio_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 4352 | clk_ext__gclk clkgen_sio_io_gclk_if.clk_ext; | |
| 4353 | cluster_arst_l__gclk clkgen_sio_io_gclk_if.cluster_arst_l; | |
| 4354 | cluster_div_en__gclk clkgen_sio_io_gclk_if.cluster_div_en; | |
| 4355 | cmp_slow_sync_en__gclk clkgen_sio_io_gclk_if.cmp_slow_sync_en; | |
| 4356 | dr_sync_en__gclk void; | |
| 4357 | gclk clkgen_sio_io_gclk_if.gclk; | |
| 4358 | io2x_sync_en__gclk void; | |
| 4359 | l2clk__gclk clkgen_sio_io_gclk_if.l2clk; | |
| 4360 | pce_ov__gclk clkgen_sio_io_gclk_if.pce_ov; | |
| 4361 | por___gclk clkgen_sio_io_gclk_if.por_; | |
| 4362 | rst_por___gclk clkgen_sio_io_gclk_if.rst_por_; | |
| 4363 | rst_wmr___gclk clkgen_sio_io_gclk_if.rst_wmr_; | |
| 4364 | rst_wmr_protect__gclk clkgen_sio_io_gclk_if.rst_wmr_protect; | |
| 4365 | scan_en__gclk clkgen_sio_io_gclk_if.scan_en; | |
| 4366 | scan_in__gclk clkgen_sio_io_gclk_if.scan_in; | |
| 4367 | scan_out__gclk clkgen_sio_io_gclk_if.scan_out; | |
| 4368 | slow_cmp_sync_en__gclk clkgen_sio_io_gclk_if.slow_cmp_sync_en; | |
| 4369 | tcu_aclk__gclk clkgen_sio_io_gclk_if.tcu_aclk; | |
| 4370 | tcu_atpg_mode__gclk clkgen_sio_io_gclk_if.tcu_atpg_mode; | |
| 4371 | tcu_bclk__gclk clkgen_sio_io_gclk_if.tcu_bclk; | |
| 4372 | tcu_clk_stop__gclk clkgen_sio_io_gclk_if.tcu_clk_stop; | |
| 4373 | tcu_div_bypass__gclk clkgen_sio_io_gclk_if.tcu_div_bypass; | |
| 4374 | tcu_pce_ov__gclk clkgen_sio_io_gclk_if.tcu_pce_ov; | |
| 4375 | tcu_wr_inhibit__gclk clkgen_sio_io_gclk_if.tcu_wr_inhibit; | |
| 4376 | wmr___gclk clkgen_sio_io_gclk_if.wmr_; | |
| 4377 | wmr_protect__gclk clkgen_sio_io_gclk_if.wmr_protect; | |
| 4378 | pc_clk__gclk void; | |
| 4379 | pc_clk_sel__gclk void; | |
| 4380 | test_clk__gclk void; | |
| 4381 | test_clk_sel__gclk void; | |
| 4382 | ||
| 4383 | //---l2clk is Vera interface CLOCK--- | |
| 4384 | aclk__l2clk clkgen_sio_io_l2clk_if.aclk; | |
| 4385 | aclk_wmr__l2clk clkgen_sio_io_l2clk_if.aclk_wmr; | |
| 4386 | array_wr_inhibit__l2clk clkgen_sio_io_l2clk_if.array_wr_inhibit; | |
| 4387 | bclk__l2clk clkgen_sio_io_l2clk_if.bclk; | |
| 4388 | cmp_slow_sync_en__l2clk clkgen_sio_io_l2clk_if.cmp_slow_sync_en; | |
| 4389 | dr_sync_en__l2clk void; | |
| 4390 | io2x_sync_en__l2clk void; | |
| 4391 | l2clk clkgen_sio_io_l2clk_if.l2clk; | |
| 4392 | pce_ov__l2clk clkgen_sio_io_l2clk_if.pce_ov; | |
| 4393 | por___l2clk clkgen_sio_io_l2clk_if.por_; | |
| 4394 | scan_out__l2clk clkgen_sio_io_l2clk_if.scan_out; | |
| 4395 | slow_cmp_sync_en__l2clk clkgen_sio_io_l2clk_if.slow_cmp_sync_en; | |
| 4396 | wmr___l2clk clkgen_sio_io_l2clk_if.wmr_; | |
| 4397 | wmr_protect__l2clk clkgen_sio_io_l2clk_if.wmr_protect; | |
| 4398 | } | |
| 4399 | ||
| 4400 | //----- port binding for clkgen_spc0_cmp ----- | |
| 4401 | ||
| 4402 | #ifndef RTL_NO_SPC0 | |
| 4403 | ||
| 4404 | bind CLKGEN_port clkgen_spc0_cmp_bind { | |
| 4405 | //---gclk is Vera interface CLOCK--- | |
| 4406 | aclk__gclk clkgen_spc0_cmp_gclk_if.aclk; | |
| 4407 | aclk_wmr__gclk clkgen_spc0_cmp_gclk_if.aclk_wmr; | |
| 4408 | array_wr_inhibit__gclk clkgen_spc0_cmp_gclk_if.array_wr_inhibit; | |
| 4409 | bclk__gclk clkgen_spc0_cmp_gclk_if.bclk; | |
| 4410 | ccu_cmp_slow_sync_en__gclk clkgen_spc0_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 4411 | ccu_div_ph__gclk clkgen_spc0_cmp_gclk_if.ccu_div_ph; | |
| 4412 | ccu_dr_sync_en__gclk void; | |
| 4413 | ccu_io2x_sync_en__gclk void; | |
| 4414 | ccu_serdes_dtm__gclk clkgen_spc0_cmp_gclk_if.ccu_serdes_dtm; | |
| 4415 | ccu_slow_cmp_sync_en__gclk clkgen_spc0_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 4416 | clk_ext__gclk clkgen_spc0_cmp_gclk_if.clk_ext; | |
| 4417 | cluster_arst_l__gclk clkgen_spc0_cmp_gclk_if.cluster_arst_l; | |
| 4418 | cluster_div_en__gclk clkgen_spc0_cmp_gclk_if.cluster_div_en; | |
| 4419 | cmp_slow_sync_en__gclk clkgen_spc0_cmp_gclk_if.cmp_slow_sync_en; | |
| 4420 | dr_sync_en__gclk void; | |
| 4421 | gclk clkgen_spc0_cmp_gclk_if.gclk; | |
| 4422 | io2x_sync_en__gclk void; | |
| 4423 | l2clk__gclk clkgen_spc0_cmp_gclk_if.l2clk; | |
| 4424 | pce_ov__gclk clkgen_spc0_cmp_gclk_if.pce_ov; | |
| 4425 | por___gclk clkgen_spc0_cmp_gclk_if.por_; | |
| 4426 | rst_por___gclk clkgen_spc0_cmp_gclk_if.rst_por_; | |
| 4427 | rst_wmr___gclk clkgen_spc0_cmp_gclk_if.rst_wmr_; | |
| 4428 | rst_wmr_protect__gclk clkgen_spc0_cmp_gclk_if.rst_wmr_protect; | |
| 4429 | scan_en__gclk clkgen_spc0_cmp_gclk_if.scan_en; | |
| 4430 | scan_in__gclk clkgen_spc0_cmp_gclk_if.scan_in; | |
| 4431 | scan_out__gclk clkgen_spc0_cmp_gclk_if.scan_out; | |
| 4432 | slow_cmp_sync_en__gclk clkgen_spc0_cmp_gclk_if.slow_cmp_sync_en; | |
| 4433 | tcu_aclk__gclk clkgen_spc0_cmp_gclk_if.tcu_aclk; | |
| 4434 | tcu_atpg_mode__gclk clkgen_spc0_cmp_gclk_if.tcu_atpg_mode; | |
| 4435 | tcu_bclk__gclk clkgen_spc0_cmp_gclk_if.tcu_bclk; | |
| 4436 | tcu_clk_stop__gclk clkgen_spc0_cmp_gclk_if.tcu_clk_stop; | |
| 4437 | tcu_div_bypass__gclk clkgen_spc0_cmp_gclk_if.tcu_div_bypass; | |
| 4438 | tcu_pce_ov__gclk clkgen_spc0_cmp_gclk_if.tcu_pce_ov; | |
| 4439 | tcu_wr_inhibit__gclk clkgen_spc0_cmp_gclk_if.tcu_wr_inhibit; | |
| 4440 | wmr___gclk clkgen_spc0_cmp_gclk_if.wmr_; | |
| 4441 | wmr_protect__gclk clkgen_spc0_cmp_gclk_if.wmr_protect; | |
| 4442 | pc_clk__gclk void; | |
| 4443 | pc_clk_sel__gclk void; | |
| 4444 | test_clk__gclk void; | |
| 4445 | test_clk_sel__gclk void; | |
| 4446 | ||
| 4447 | //---l2clk is Vera interface CLOCK--- | |
| 4448 | aclk__l2clk clkgen_spc0_cmp_l2clk_if.aclk; | |
| 4449 | aclk_wmr__l2clk clkgen_spc0_cmp_l2clk_if.aclk_wmr; | |
| 4450 | array_wr_inhibit__l2clk clkgen_spc0_cmp_l2clk_if.array_wr_inhibit; | |
| 4451 | bclk__l2clk clkgen_spc0_cmp_l2clk_if.bclk; | |
| 4452 | cmp_slow_sync_en__l2clk clkgen_spc0_cmp_l2clk_if.cmp_slow_sync_en; | |
| 4453 | dr_sync_en__l2clk void; | |
| 4454 | io2x_sync_en__l2clk void; | |
| 4455 | l2clk clkgen_spc0_cmp_l2clk_if.l2clk; | |
| 4456 | pce_ov__l2clk clkgen_spc0_cmp_l2clk_if.pce_ov; | |
| 4457 | por___l2clk clkgen_spc0_cmp_l2clk_if.por_; | |
| 4458 | scan_out__l2clk clkgen_spc0_cmp_l2clk_if.scan_out; | |
| 4459 | slow_cmp_sync_en__l2clk clkgen_spc0_cmp_l2clk_if.slow_cmp_sync_en; | |
| 4460 | wmr___l2clk clkgen_spc0_cmp_l2clk_if.wmr_; | |
| 4461 | wmr_protect__l2clk clkgen_spc0_cmp_l2clk_if.wmr_protect; | |
| 4462 | } | |
| 4463 | ||
| 4464 | #endif | |
| 4465 | ||
| 4466 | //----- port binding for clkgen_spc1_cmp ----- | |
| 4467 | ||
| 4468 | #ifndef RTL_NO_SPC1 | |
| 4469 | ||
| 4470 | bind CLKGEN_port clkgen_spc1_cmp_bind { | |
| 4471 | //---gclk is Vera interface CLOCK--- | |
| 4472 | aclk__gclk clkgen_spc1_cmp_gclk_if.aclk; | |
| 4473 | aclk_wmr__gclk clkgen_spc1_cmp_gclk_if.aclk_wmr; | |
| 4474 | array_wr_inhibit__gclk clkgen_spc1_cmp_gclk_if.array_wr_inhibit; | |
| 4475 | bclk__gclk clkgen_spc1_cmp_gclk_if.bclk; | |
| 4476 | ccu_cmp_slow_sync_en__gclk clkgen_spc1_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 4477 | ccu_div_ph__gclk clkgen_spc1_cmp_gclk_if.ccu_div_ph; | |
| 4478 | ccu_dr_sync_en__gclk void; | |
| 4479 | ccu_io2x_sync_en__gclk void; | |
| 4480 | ccu_serdes_dtm__gclk clkgen_spc1_cmp_gclk_if.ccu_serdes_dtm; | |
| 4481 | ccu_slow_cmp_sync_en__gclk clkgen_spc1_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 4482 | clk_ext__gclk clkgen_spc1_cmp_gclk_if.clk_ext; | |
| 4483 | cluster_arst_l__gclk clkgen_spc1_cmp_gclk_if.cluster_arst_l; | |
| 4484 | cluster_div_en__gclk clkgen_spc1_cmp_gclk_if.cluster_div_en; | |
| 4485 | cmp_slow_sync_en__gclk clkgen_spc1_cmp_gclk_if.cmp_slow_sync_en; | |
| 4486 | dr_sync_en__gclk void; | |
| 4487 | gclk clkgen_spc1_cmp_gclk_if.gclk; | |
| 4488 | io2x_sync_en__gclk void; | |
| 4489 | l2clk__gclk clkgen_spc1_cmp_gclk_if.l2clk; | |
| 4490 | pce_ov__gclk clkgen_spc1_cmp_gclk_if.pce_ov; | |
| 4491 | por___gclk clkgen_spc1_cmp_gclk_if.por_; | |
| 4492 | rst_por___gclk clkgen_spc1_cmp_gclk_if.rst_por_; | |
| 4493 | rst_wmr___gclk clkgen_spc1_cmp_gclk_if.rst_wmr_; | |
| 4494 | rst_wmr_protect__gclk clkgen_spc1_cmp_gclk_if.rst_wmr_protect; | |
| 4495 | scan_en__gclk clkgen_spc1_cmp_gclk_if.scan_en; | |
| 4496 | scan_in__gclk clkgen_spc1_cmp_gclk_if.scan_in; | |
| 4497 | scan_out__gclk clkgen_spc1_cmp_gclk_if.scan_out; | |
| 4498 | slow_cmp_sync_en__gclk clkgen_spc1_cmp_gclk_if.slow_cmp_sync_en; | |
| 4499 | tcu_aclk__gclk clkgen_spc1_cmp_gclk_if.tcu_aclk; | |
| 4500 | tcu_atpg_mode__gclk clkgen_spc1_cmp_gclk_if.tcu_atpg_mode; | |
| 4501 | tcu_bclk__gclk clkgen_spc1_cmp_gclk_if.tcu_bclk; | |
| 4502 | tcu_clk_stop__gclk clkgen_spc1_cmp_gclk_if.tcu_clk_stop; | |
| 4503 | tcu_div_bypass__gclk clkgen_spc1_cmp_gclk_if.tcu_div_bypass; | |
| 4504 | tcu_pce_ov__gclk clkgen_spc1_cmp_gclk_if.tcu_pce_ov; | |
| 4505 | tcu_wr_inhibit__gclk clkgen_spc1_cmp_gclk_if.tcu_wr_inhibit; | |
| 4506 | wmr___gclk clkgen_spc1_cmp_gclk_if.wmr_; | |
| 4507 | wmr_protect__gclk clkgen_spc1_cmp_gclk_if.wmr_protect; | |
| 4508 | pc_clk__gclk void; | |
| 4509 | pc_clk_sel__gclk void; | |
| 4510 | test_clk__gclk void; | |
| 4511 | test_clk_sel__gclk void; | |
| 4512 | ||
| 4513 | //---l2clk is Vera interface CLOCK--- | |
| 4514 | aclk__l2clk clkgen_spc1_cmp_l2clk_if.aclk; | |
| 4515 | aclk_wmr__l2clk clkgen_spc1_cmp_l2clk_if.aclk_wmr; | |
| 4516 | array_wr_inhibit__l2clk clkgen_spc1_cmp_l2clk_if.array_wr_inhibit; | |
| 4517 | bclk__l2clk clkgen_spc1_cmp_l2clk_if.bclk; | |
| 4518 | cmp_slow_sync_en__l2clk clkgen_spc1_cmp_l2clk_if.cmp_slow_sync_en; | |
| 4519 | dr_sync_en__l2clk void; | |
| 4520 | io2x_sync_en__l2clk void; | |
| 4521 | l2clk clkgen_spc1_cmp_l2clk_if.l2clk; | |
| 4522 | pce_ov__l2clk clkgen_spc1_cmp_l2clk_if.pce_ov; | |
| 4523 | por___l2clk clkgen_spc1_cmp_l2clk_if.por_; | |
| 4524 | scan_out__l2clk clkgen_spc1_cmp_l2clk_if.scan_out; | |
| 4525 | slow_cmp_sync_en__l2clk clkgen_spc1_cmp_l2clk_if.slow_cmp_sync_en; | |
| 4526 | wmr___l2clk clkgen_spc1_cmp_l2clk_if.wmr_; | |
| 4527 | wmr_protect__l2clk clkgen_spc1_cmp_l2clk_if.wmr_protect; | |
| 4528 | } | |
| 4529 | ||
| 4530 | #endif | |
| 4531 | ||
| 4532 | //----- port binding for clkgen_spc2_cmp ----- | |
| 4533 | ||
| 4534 | #ifndef RTL_NO_SPC2 | |
| 4535 | ||
| 4536 | bind CLKGEN_port clkgen_spc2_cmp_bind { | |
| 4537 | //---gclk is Vera interface CLOCK--- | |
| 4538 | aclk__gclk clkgen_spc2_cmp_gclk_if.aclk; | |
| 4539 | aclk_wmr__gclk clkgen_spc2_cmp_gclk_if.aclk_wmr; | |
| 4540 | array_wr_inhibit__gclk clkgen_spc2_cmp_gclk_if.array_wr_inhibit; | |
| 4541 | bclk__gclk clkgen_spc2_cmp_gclk_if.bclk; | |
| 4542 | ccu_cmp_slow_sync_en__gclk clkgen_spc2_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 4543 | ccu_div_ph__gclk clkgen_spc2_cmp_gclk_if.ccu_div_ph; | |
| 4544 | ccu_dr_sync_en__gclk void; | |
| 4545 | ccu_io2x_sync_en__gclk void; | |
| 4546 | ccu_serdes_dtm__gclk clkgen_spc2_cmp_gclk_if.ccu_serdes_dtm; | |
| 4547 | ccu_slow_cmp_sync_en__gclk clkgen_spc2_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 4548 | clk_ext__gclk clkgen_spc2_cmp_gclk_if.clk_ext; | |
| 4549 | cluster_arst_l__gclk clkgen_spc2_cmp_gclk_if.cluster_arst_l; | |
| 4550 | cluster_div_en__gclk clkgen_spc2_cmp_gclk_if.cluster_div_en; | |
| 4551 | cmp_slow_sync_en__gclk clkgen_spc2_cmp_gclk_if.cmp_slow_sync_en; | |
| 4552 | dr_sync_en__gclk void; | |
| 4553 | gclk clkgen_spc2_cmp_gclk_if.gclk; | |
| 4554 | io2x_sync_en__gclk void; | |
| 4555 | l2clk__gclk clkgen_spc2_cmp_gclk_if.l2clk; | |
| 4556 | pce_ov__gclk clkgen_spc2_cmp_gclk_if.pce_ov; | |
| 4557 | por___gclk clkgen_spc2_cmp_gclk_if.por_; | |
| 4558 | rst_por___gclk clkgen_spc2_cmp_gclk_if.rst_por_; | |
| 4559 | rst_wmr___gclk clkgen_spc2_cmp_gclk_if.rst_wmr_; | |
| 4560 | rst_wmr_protect__gclk clkgen_spc2_cmp_gclk_if.rst_wmr_protect; | |
| 4561 | scan_en__gclk clkgen_spc2_cmp_gclk_if.scan_en; | |
| 4562 | scan_in__gclk clkgen_spc2_cmp_gclk_if.scan_in; | |
| 4563 | scan_out__gclk clkgen_spc2_cmp_gclk_if.scan_out; | |
| 4564 | slow_cmp_sync_en__gclk clkgen_spc2_cmp_gclk_if.slow_cmp_sync_en; | |
| 4565 | tcu_aclk__gclk clkgen_spc2_cmp_gclk_if.tcu_aclk; | |
| 4566 | tcu_atpg_mode__gclk clkgen_spc2_cmp_gclk_if.tcu_atpg_mode; | |
| 4567 | tcu_bclk__gclk clkgen_spc2_cmp_gclk_if.tcu_bclk; | |
| 4568 | tcu_clk_stop__gclk clkgen_spc2_cmp_gclk_if.tcu_clk_stop; | |
| 4569 | tcu_div_bypass__gclk clkgen_spc2_cmp_gclk_if.tcu_div_bypass; | |
| 4570 | tcu_pce_ov__gclk clkgen_spc2_cmp_gclk_if.tcu_pce_ov; | |
| 4571 | tcu_wr_inhibit__gclk clkgen_spc2_cmp_gclk_if.tcu_wr_inhibit; | |
| 4572 | wmr___gclk clkgen_spc2_cmp_gclk_if.wmr_; | |
| 4573 | wmr_protect__gclk clkgen_spc2_cmp_gclk_if.wmr_protect; | |
| 4574 | pc_clk__gclk void; | |
| 4575 | pc_clk_sel__gclk void; | |
| 4576 | test_clk__gclk void; | |
| 4577 | test_clk_sel__gclk void; | |
| 4578 | ||
| 4579 | //---l2clk is Vera interface CLOCK--- | |
| 4580 | aclk__l2clk clkgen_spc2_cmp_l2clk_if.aclk; | |
| 4581 | aclk_wmr__l2clk clkgen_spc2_cmp_l2clk_if.aclk_wmr; | |
| 4582 | array_wr_inhibit__l2clk clkgen_spc2_cmp_l2clk_if.array_wr_inhibit; | |
| 4583 | bclk__l2clk clkgen_spc2_cmp_l2clk_if.bclk; | |
| 4584 | cmp_slow_sync_en__l2clk clkgen_spc2_cmp_l2clk_if.cmp_slow_sync_en; | |
| 4585 | dr_sync_en__l2clk void; | |
| 4586 | io2x_sync_en__l2clk void; | |
| 4587 | l2clk clkgen_spc2_cmp_l2clk_if.l2clk; | |
| 4588 | pce_ov__l2clk clkgen_spc2_cmp_l2clk_if.pce_ov; | |
| 4589 | por___l2clk clkgen_spc2_cmp_l2clk_if.por_; | |
| 4590 | scan_out__l2clk clkgen_spc2_cmp_l2clk_if.scan_out; | |
| 4591 | slow_cmp_sync_en__l2clk clkgen_spc2_cmp_l2clk_if.slow_cmp_sync_en; | |
| 4592 | wmr___l2clk clkgen_spc2_cmp_l2clk_if.wmr_; | |
| 4593 | wmr_protect__l2clk clkgen_spc2_cmp_l2clk_if.wmr_protect; | |
| 4594 | } | |
| 4595 | ||
| 4596 | #endif | |
| 4597 | ||
| 4598 | //----- port binding for clkgen_spc3_cmp ----- | |
| 4599 | ||
| 4600 | #ifndef RTL_NO_SPC3 | |
| 4601 | ||
| 4602 | bind CLKGEN_port clkgen_spc3_cmp_bind { | |
| 4603 | //---gclk is Vera interface CLOCK--- | |
| 4604 | aclk__gclk clkgen_spc3_cmp_gclk_if.aclk; | |
| 4605 | aclk_wmr__gclk clkgen_spc3_cmp_gclk_if.aclk_wmr; | |
| 4606 | array_wr_inhibit__gclk clkgen_spc3_cmp_gclk_if.array_wr_inhibit; | |
| 4607 | bclk__gclk clkgen_spc3_cmp_gclk_if.bclk; | |
| 4608 | ccu_cmp_slow_sync_en__gclk clkgen_spc3_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 4609 | ccu_div_ph__gclk clkgen_spc3_cmp_gclk_if.ccu_div_ph; | |
| 4610 | ccu_dr_sync_en__gclk void; | |
| 4611 | ccu_io2x_sync_en__gclk void; | |
| 4612 | ccu_serdes_dtm__gclk clkgen_spc3_cmp_gclk_if.ccu_serdes_dtm; | |
| 4613 | ccu_slow_cmp_sync_en__gclk clkgen_spc3_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 4614 | clk_ext__gclk clkgen_spc3_cmp_gclk_if.clk_ext; | |
| 4615 | cluster_arst_l__gclk clkgen_spc3_cmp_gclk_if.cluster_arst_l; | |
| 4616 | cluster_div_en__gclk clkgen_spc3_cmp_gclk_if.cluster_div_en; | |
| 4617 | cmp_slow_sync_en__gclk clkgen_spc3_cmp_gclk_if.cmp_slow_sync_en; | |
| 4618 | dr_sync_en__gclk void; | |
| 4619 | gclk clkgen_spc3_cmp_gclk_if.gclk; | |
| 4620 | io2x_sync_en__gclk void; | |
| 4621 | l2clk__gclk clkgen_spc3_cmp_gclk_if.l2clk; | |
| 4622 | pce_ov__gclk clkgen_spc3_cmp_gclk_if.pce_ov; | |
| 4623 | por___gclk clkgen_spc3_cmp_gclk_if.por_; | |
| 4624 | rst_por___gclk clkgen_spc3_cmp_gclk_if.rst_por_; | |
| 4625 | rst_wmr___gclk clkgen_spc3_cmp_gclk_if.rst_wmr_; | |
| 4626 | rst_wmr_protect__gclk clkgen_spc3_cmp_gclk_if.rst_wmr_protect; | |
| 4627 | scan_en__gclk clkgen_spc3_cmp_gclk_if.scan_en; | |
| 4628 | scan_in__gclk clkgen_spc3_cmp_gclk_if.scan_in; | |
| 4629 | scan_out__gclk clkgen_spc3_cmp_gclk_if.scan_out; | |
| 4630 | slow_cmp_sync_en__gclk clkgen_spc3_cmp_gclk_if.slow_cmp_sync_en; | |
| 4631 | tcu_aclk__gclk clkgen_spc3_cmp_gclk_if.tcu_aclk; | |
| 4632 | tcu_atpg_mode__gclk clkgen_spc3_cmp_gclk_if.tcu_atpg_mode; | |
| 4633 | tcu_bclk__gclk clkgen_spc3_cmp_gclk_if.tcu_bclk; | |
| 4634 | tcu_clk_stop__gclk clkgen_spc3_cmp_gclk_if.tcu_clk_stop; | |
| 4635 | tcu_div_bypass__gclk clkgen_spc3_cmp_gclk_if.tcu_div_bypass; | |
| 4636 | tcu_pce_ov__gclk clkgen_spc3_cmp_gclk_if.tcu_pce_ov; | |
| 4637 | tcu_wr_inhibit__gclk clkgen_spc3_cmp_gclk_if.tcu_wr_inhibit; | |
| 4638 | wmr___gclk clkgen_spc3_cmp_gclk_if.wmr_; | |
| 4639 | wmr_protect__gclk clkgen_spc3_cmp_gclk_if.wmr_protect; | |
| 4640 | pc_clk__gclk void; | |
| 4641 | pc_clk_sel__gclk void; | |
| 4642 | test_clk__gclk void; | |
| 4643 | test_clk_sel__gclk void; | |
| 4644 | ||
| 4645 | //---l2clk is Vera interface CLOCK--- | |
| 4646 | aclk__l2clk clkgen_spc3_cmp_l2clk_if.aclk; | |
| 4647 | aclk_wmr__l2clk clkgen_spc3_cmp_l2clk_if.aclk_wmr; | |
| 4648 | array_wr_inhibit__l2clk clkgen_spc3_cmp_l2clk_if.array_wr_inhibit; | |
| 4649 | bclk__l2clk clkgen_spc3_cmp_l2clk_if.bclk; | |
| 4650 | cmp_slow_sync_en__l2clk clkgen_spc3_cmp_l2clk_if.cmp_slow_sync_en; | |
| 4651 | dr_sync_en__l2clk void; | |
| 4652 | io2x_sync_en__l2clk void; | |
| 4653 | l2clk clkgen_spc3_cmp_l2clk_if.l2clk; | |
| 4654 | pce_ov__l2clk clkgen_spc3_cmp_l2clk_if.pce_ov; | |
| 4655 | por___l2clk clkgen_spc3_cmp_l2clk_if.por_; | |
| 4656 | scan_out__l2clk clkgen_spc3_cmp_l2clk_if.scan_out; | |
| 4657 | slow_cmp_sync_en__l2clk clkgen_spc3_cmp_l2clk_if.slow_cmp_sync_en; | |
| 4658 | wmr___l2clk clkgen_spc3_cmp_l2clk_if.wmr_; | |
| 4659 | wmr_protect__l2clk clkgen_spc3_cmp_l2clk_if.wmr_protect; | |
| 4660 | } | |
| 4661 | ||
| 4662 | #endif | |
| 4663 | ||
| 4664 | //----- port binding for clkgen_spc4_cmp ----- | |
| 4665 | ||
| 4666 | #ifndef RTL_NO_SPC4 | |
| 4667 | ||
| 4668 | bind CLKGEN_port clkgen_spc4_cmp_bind { | |
| 4669 | //---gclk is Vera interface CLOCK--- | |
| 4670 | aclk__gclk clkgen_spc4_cmp_gclk_if.aclk; | |
| 4671 | aclk_wmr__gclk clkgen_spc4_cmp_gclk_if.aclk_wmr; | |
| 4672 | array_wr_inhibit__gclk clkgen_spc4_cmp_gclk_if.array_wr_inhibit; | |
| 4673 | bclk__gclk clkgen_spc4_cmp_gclk_if.bclk; | |
| 4674 | ccu_cmp_slow_sync_en__gclk clkgen_spc4_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 4675 | ccu_div_ph__gclk clkgen_spc4_cmp_gclk_if.ccu_div_ph; | |
| 4676 | ccu_dr_sync_en__gclk void; | |
| 4677 | ccu_io2x_sync_en__gclk void; | |
| 4678 | ccu_serdes_dtm__gclk clkgen_spc4_cmp_gclk_if.ccu_serdes_dtm; | |
| 4679 | ccu_slow_cmp_sync_en__gclk clkgen_spc4_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 4680 | clk_ext__gclk clkgen_spc4_cmp_gclk_if.clk_ext; | |
| 4681 | cluster_arst_l__gclk clkgen_spc4_cmp_gclk_if.cluster_arst_l; | |
| 4682 | cluster_div_en__gclk clkgen_spc4_cmp_gclk_if.cluster_div_en; | |
| 4683 | cmp_slow_sync_en__gclk clkgen_spc4_cmp_gclk_if.cmp_slow_sync_en; | |
| 4684 | dr_sync_en__gclk void; | |
| 4685 | gclk clkgen_spc4_cmp_gclk_if.gclk; | |
| 4686 | io2x_sync_en__gclk void; | |
| 4687 | l2clk__gclk clkgen_spc4_cmp_gclk_if.l2clk; | |
| 4688 | pce_ov__gclk clkgen_spc4_cmp_gclk_if.pce_ov; | |
| 4689 | por___gclk clkgen_spc4_cmp_gclk_if.por_; | |
| 4690 | rst_por___gclk clkgen_spc4_cmp_gclk_if.rst_por_; | |
| 4691 | rst_wmr___gclk clkgen_spc4_cmp_gclk_if.rst_wmr_; | |
| 4692 | rst_wmr_protect__gclk clkgen_spc4_cmp_gclk_if.rst_wmr_protect; | |
| 4693 | scan_en__gclk clkgen_spc4_cmp_gclk_if.scan_en; | |
| 4694 | scan_in__gclk clkgen_spc4_cmp_gclk_if.scan_in; | |
| 4695 | scan_out__gclk clkgen_spc4_cmp_gclk_if.scan_out; | |
| 4696 | slow_cmp_sync_en__gclk clkgen_spc4_cmp_gclk_if.slow_cmp_sync_en; | |
| 4697 | tcu_aclk__gclk clkgen_spc4_cmp_gclk_if.tcu_aclk; | |
| 4698 | tcu_atpg_mode__gclk clkgen_spc4_cmp_gclk_if.tcu_atpg_mode; | |
| 4699 | tcu_bclk__gclk clkgen_spc4_cmp_gclk_if.tcu_bclk; | |
| 4700 | tcu_clk_stop__gclk clkgen_spc4_cmp_gclk_if.tcu_clk_stop; | |
| 4701 | tcu_div_bypass__gclk clkgen_spc4_cmp_gclk_if.tcu_div_bypass; | |
| 4702 | tcu_pce_ov__gclk clkgen_spc4_cmp_gclk_if.tcu_pce_ov; | |
| 4703 | tcu_wr_inhibit__gclk clkgen_spc4_cmp_gclk_if.tcu_wr_inhibit; | |
| 4704 | wmr___gclk clkgen_spc4_cmp_gclk_if.wmr_; | |
| 4705 | wmr_protect__gclk clkgen_spc4_cmp_gclk_if.wmr_protect; | |
| 4706 | pc_clk__gclk void; | |
| 4707 | pc_clk_sel__gclk void; | |
| 4708 | test_clk__gclk void; | |
| 4709 | test_clk_sel__gclk void; | |
| 4710 | ||
| 4711 | //---l2clk is Vera interface CLOCK--- | |
| 4712 | aclk__l2clk clkgen_spc4_cmp_l2clk_if.aclk; | |
| 4713 | aclk_wmr__l2clk clkgen_spc4_cmp_l2clk_if.aclk_wmr; | |
| 4714 | array_wr_inhibit__l2clk clkgen_spc4_cmp_l2clk_if.array_wr_inhibit; | |
| 4715 | bclk__l2clk clkgen_spc4_cmp_l2clk_if.bclk; | |
| 4716 | cmp_slow_sync_en__l2clk clkgen_spc4_cmp_l2clk_if.cmp_slow_sync_en; | |
| 4717 | dr_sync_en__l2clk void; | |
| 4718 | io2x_sync_en__l2clk void; | |
| 4719 | l2clk clkgen_spc4_cmp_l2clk_if.l2clk; | |
| 4720 | pce_ov__l2clk clkgen_spc4_cmp_l2clk_if.pce_ov; | |
| 4721 | por___l2clk clkgen_spc4_cmp_l2clk_if.por_; | |
| 4722 | scan_out__l2clk clkgen_spc4_cmp_l2clk_if.scan_out; | |
| 4723 | slow_cmp_sync_en__l2clk clkgen_spc4_cmp_l2clk_if.slow_cmp_sync_en; | |
| 4724 | wmr___l2clk clkgen_spc4_cmp_l2clk_if.wmr_; | |
| 4725 | wmr_protect__l2clk clkgen_spc4_cmp_l2clk_if.wmr_protect; | |
| 4726 | } | |
| 4727 | ||
| 4728 | #endif | |
| 4729 | ||
| 4730 | //----- port binding for clkgen_spc5_cmp ----- | |
| 4731 | ||
| 4732 | #ifndef RTL_NO_SPC5 | |
| 4733 | ||
| 4734 | bind CLKGEN_port clkgen_spc5_cmp_bind { | |
| 4735 | //---gclk is Vera interface CLOCK--- | |
| 4736 | aclk__gclk clkgen_spc5_cmp_gclk_if.aclk; | |
| 4737 | aclk_wmr__gclk clkgen_spc5_cmp_gclk_if.aclk_wmr; | |
| 4738 | array_wr_inhibit__gclk clkgen_spc5_cmp_gclk_if.array_wr_inhibit; | |
| 4739 | bclk__gclk clkgen_spc5_cmp_gclk_if.bclk; | |
| 4740 | ccu_cmp_slow_sync_en__gclk clkgen_spc5_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 4741 | ccu_div_ph__gclk clkgen_spc5_cmp_gclk_if.ccu_div_ph; | |
| 4742 | ccu_dr_sync_en__gclk void; | |
| 4743 | ccu_io2x_sync_en__gclk void; | |
| 4744 | ccu_serdes_dtm__gclk clkgen_spc5_cmp_gclk_if.ccu_serdes_dtm; | |
| 4745 | ccu_slow_cmp_sync_en__gclk clkgen_spc5_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 4746 | clk_ext__gclk clkgen_spc5_cmp_gclk_if.clk_ext; | |
| 4747 | cluster_arst_l__gclk clkgen_spc5_cmp_gclk_if.cluster_arst_l; | |
| 4748 | cluster_div_en__gclk clkgen_spc5_cmp_gclk_if.cluster_div_en; | |
| 4749 | cmp_slow_sync_en__gclk clkgen_spc5_cmp_gclk_if.cmp_slow_sync_en; | |
| 4750 | dr_sync_en__gclk void; | |
| 4751 | gclk clkgen_spc5_cmp_gclk_if.gclk; | |
| 4752 | io2x_sync_en__gclk void; | |
| 4753 | l2clk__gclk clkgen_spc5_cmp_gclk_if.l2clk; | |
| 4754 | pce_ov__gclk clkgen_spc5_cmp_gclk_if.pce_ov; | |
| 4755 | por___gclk clkgen_spc5_cmp_gclk_if.por_; | |
| 4756 | rst_por___gclk clkgen_spc5_cmp_gclk_if.rst_por_; | |
| 4757 | rst_wmr___gclk clkgen_spc5_cmp_gclk_if.rst_wmr_; | |
| 4758 | rst_wmr_protect__gclk clkgen_spc5_cmp_gclk_if.rst_wmr_protect; | |
| 4759 | scan_en__gclk clkgen_spc5_cmp_gclk_if.scan_en; | |
| 4760 | scan_in__gclk clkgen_spc5_cmp_gclk_if.scan_in; | |
| 4761 | scan_out__gclk clkgen_spc5_cmp_gclk_if.scan_out; | |
| 4762 | slow_cmp_sync_en__gclk clkgen_spc5_cmp_gclk_if.slow_cmp_sync_en; | |
| 4763 | tcu_aclk__gclk clkgen_spc5_cmp_gclk_if.tcu_aclk; | |
| 4764 | tcu_atpg_mode__gclk clkgen_spc5_cmp_gclk_if.tcu_atpg_mode; | |
| 4765 | tcu_bclk__gclk clkgen_spc5_cmp_gclk_if.tcu_bclk; | |
| 4766 | tcu_clk_stop__gclk clkgen_spc5_cmp_gclk_if.tcu_clk_stop; | |
| 4767 | tcu_div_bypass__gclk clkgen_spc5_cmp_gclk_if.tcu_div_bypass; | |
| 4768 | tcu_pce_ov__gclk clkgen_spc5_cmp_gclk_if.tcu_pce_ov; | |
| 4769 | tcu_wr_inhibit__gclk clkgen_spc5_cmp_gclk_if.tcu_wr_inhibit; | |
| 4770 | wmr___gclk clkgen_spc5_cmp_gclk_if.wmr_; | |
| 4771 | wmr_protect__gclk clkgen_spc5_cmp_gclk_if.wmr_protect; | |
| 4772 | pc_clk__gclk void; | |
| 4773 | pc_clk_sel__gclk void; | |
| 4774 | test_clk__gclk void; | |
| 4775 | test_clk_sel__gclk void; | |
| 4776 | ||
| 4777 | //---l2clk is Vera interface CLOCK--- | |
| 4778 | aclk__l2clk clkgen_spc5_cmp_l2clk_if.aclk; | |
| 4779 | aclk_wmr__l2clk clkgen_spc5_cmp_l2clk_if.aclk_wmr; | |
| 4780 | array_wr_inhibit__l2clk clkgen_spc5_cmp_l2clk_if.array_wr_inhibit; | |
| 4781 | bclk__l2clk clkgen_spc5_cmp_l2clk_if.bclk; | |
| 4782 | cmp_slow_sync_en__l2clk clkgen_spc5_cmp_l2clk_if.cmp_slow_sync_en; | |
| 4783 | dr_sync_en__l2clk void; | |
| 4784 | io2x_sync_en__l2clk void; | |
| 4785 | l2clk clkgen_spc5_cmp_l2clk_if.l2clk; | |
| 4786 | pce_ov__l2clk clkgen_spc5_cmp_l2clk_if.pce_ov; | |
| 4787 | por___l2clk clkgen_spc5_cmp_l2clk_if.por_; | |
| 4788 | scan_out__l2clk clkgen_spc5_cmp_l2clk_if.scan_out; | |
| 4789 | slow_cmp_sync_en__l2clk clkgen_spc5_cmp_l2clk_if.slow_cmp_sync_en; | |
| 4790 | wmr___l2clk clkgen_spc5_cmp_l2clk_if.wmr_; | |
| 4791 | wmr_protect__l2clk clkgen_spc5_cmp_l2clk_if.wmr_protect; | |
| 4792 | } | |
| 4793 | ||
| 4794 | #endif | |
| 4795 | ||
| 4796 | //----- port binding for clkgen_spc6_cmp ----- | |
| 4797 | ||
| 4798 | #ifndef RTL_NO_SPC6 | |
| 4799 | ||
| 4800 | bind CLKGEN_port clkgen_spc6_cmp_bind { | |
| 4801 | //---gclk is Vera interface CLOCK--- | |
| 4802 | aclk__gclk clkgen_spc6_cmp_gclk_if.aclk; | |
| 4803 | aclk_wmr__gclk clkgen_spc6_cmp_gclk_if.aclk_wmr; | |
| 4804 | array_wr_inhibit__gclk clkgen_spc6_cmp_gclk_if.array_wr_inhibit; | |
| 4805 | bclk__gclk clkgen_spc6_cmp_gclk_if.bclk; | |
| 4806 | ccu_cmp_slow_sync_en__gclk clkgen_spc6_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 4807 | ccu_div_ph__gclk clkgen_spc6_cmp_gclk_if.ccu_div_ph; | |
| 4808 | ccu_dr_sync_en__gclk void; | |
| 4809 | ccu_io2x_sync_en__gclk void; | |
| 4810 | ccu_serdes_dtm__gclk clkgen_spc6_cmp_gclk_if.ccu_serdes_dtm; | |
| 4811 | ccu_slow_cmp_sync_en__gclk clkgen_spc6_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 4812 | clk_ext__gclk clkgen_spc6_cmp_gclk_if.clk_ext; | |
| 4813 | cluster_arst_l__gclk clkgen_spc6_cmp_gclk_if.cluster_arst_l; | |
| 4814 | cluster_div_en__gclk clkgen_spc6_cmp_gclk_if.cluster_div_en; | |
| 4815 | cmp_slow_sync_en__gclk clkgen_spc6_cmp_gclk_if.cmp_slow_sync_en; | |
| 4816 | dr_sync_en__gclk void; | |
| 4817 | gclk clkgen_spc6_cmp_gclk_if.gclk; | |
| 4818 | io2x_sync_en__gclk void; | |
| 4819 | l2clk__gclk clkgen_spc6_cmp_gclk_if.l2clk; | |
| 4820 | pce_ov__gclk clkgen_spc6_cmp_gclk_if.pce_ov; | |
| 4821 | por___gclk clkgen_spc6_cmp_gclk_if.por_; | |
| 4822 | rst_por___gclk clkgen_spc6_cmp_gclk_if.rst_por_; | |
| 4823 | rst_wmr___gclk clkgen_spc6_cmp_gclk_if.rst_wmr_; | |
| 4824 | rst_wmr_protect__gclk clkgen_spc6_cmp_gclk_if.rst_wmr_protect; | |
| 4825 | scan_en__gclk clkgen_spc6_cmp_gclk_if.scan_en; | |
| 4826 | scan_in__gclk clkgen_spc6_cmp_gclk_if.scan_in; | |
| 4827 | scan_out__gclk clkgen_spc6_cmp_gclk_if.scan_out; | |
| 4828 | slow_cmp_sync_en__gclk clkgen_spc6_cmp_gclk_if.slow_cmp_sync_en; | |
| 4829 | tcu_aclk__gclk clkgen_spc6_cmp_gclk_if.tcu_aclk; | |
| 4830 | tcu_atpg_mode__gclk clkgen_spc6_cmp_gclk_if.tcu_atpg_mode; | |
| 4831 | tcu_bclk__gclk clkgen_spc6_cmp_gclk_if.tcu_bclk; | |
| 4832 | tcu_clk_stop__gclk clkgen_spc6_cmp_gclk_if.tcu_clk_stop; | |
| 4833 | tcu_div_bypass__gclk clkgen_spc6_cmp_gclk_if.tcu_div_bypass; | |
| 4834 | tcu_pce_ov__gclk clkgen_spc6_cmp_gclk_if.tcu_pce_ov; | |
| 4835 | tcu_wr_inhibit__gclk clkgen_spc6_cmp_gclk_if.tcu_wr_inhibit; | |
| 4836 | wmr___gclk clkgen_spc6_cmp_gclk_if.wmr_; | |
| 4837 | wmr_protect__gclk clkgen_spc6_cmp_gclk_if.wmr_protect; | |
| 4838 | pc_clk__gclk void; | |
| 4839 | pc_clk_sel__gclk void; | |
| 4840 | test_clk__gclk void; | |
| 4841 | test_clk_sel__gclk void; | |
| 4842 | ||
| 4843 | //---l2clk is Vera interface CLOCK--- | |
| 4844 | aclk__l2clk clkgen_spc6_cmp_l2clk_if.aclk; | |
| 4845 | aclk_wmr__l2clk clkgen_spc6_cmp_l2clk_if.aclk_wmr; | |
| 4846 | array_wr_inhibit__l2clk clkgen_spc6_cmp_l2clk_if.array_wr_inhibit; | |
| 4847 | bclk__l2clk clkgen_spc6_cmp_l2clk_if.bclk; | |
| 4848 | cmp_slow_sync_en__l2clk clkgen_spc6_cmp_l2clk_if.cmp_slow_sync_en; | |
| 4849 | dr_sync_en__l2clk void; | |
| 4850 | io2x_sync_en__l2clk void; | |
| 4851 | l2clk clkgen_spc6_cmp_l2clk_if.l2clk; | |
| 4852 | pce_ov__l2clk clkgen_spc6_cmp_l2clk_if.pce_ov; | |
| 4853 | por___l2clk clkgen_spc6_cmp_l2clk_if.por_; | |
| 4854 | scan_out__l2clk clkgen_spc6_cmp_l2clk_if.scan_out; | |
| 4855 | slow_cmp_sync_en__l2clk clkgen_spc6_cmp_l2clk_if.slow_cmp_sync_en; | |
| 4856 | wmr___l2clk clkgen_spc6_cmp_l2clk_if.wmr_; | |
| 4857 | wmr_protect__l2clk clkgen_spc6_cmp_l2clk_if.wmr_protect; | |
| 4858 | } | |
| 4859 | ||
| 4860 | #endif | |
| 4861 | ||
| 4862 | //----- port binding for clkgen_spc7_cmp ----- | |
| 4863 | ||
| 4864 | #ifndef RTL_NO_SPC7 | |
| 4865 | ||
| 4866 | bind CLKGEN_port clkgen_spc7_cmp_bind { | |
| 4867 | //---gclk is Vera interface CLOCK--- | |
| 4868 | aclk__gclk clkgen_spc7_cmp_gclk_if.aclk; | |
| 4869 | aclk_wmr__gclk clkgen_spc7_cmp_gclk_if.aclk_wmr; | |
| 4870 | array_wr_inhibit__gclk clkgen_spc7_cmp_gclk_if.array_wr_inhibit; | |
| 4871 | bclk__gclk clkgen_spc7_cmp_gclk_if.bclk; | |
| 4872 | ccu_cmp_slow_sync_en__gclk clkgen_spc7_cmp_gclk_if.ccu_cmp_slow_sync_en; | |
| 4873 | ccu_div_ph__gclk clkgen_spc7_cmp_gclk_if.ccu_div_ph; | |
| 4874 | ccu_dr_sync_en__gclk void; | |
| 4875 | ccu_io2x_sync_en__gclk void; | |
| 4876 | ccu_serdes_dtm__gclk clkgen_spc7_cmp_gclk_if.ccu_serdes_dtm; | |
| 4877 | ccu_slow_cmp_sync_en__gclk clkgen_spc7_cmp_gclk_if.ccu_slow_cmp_sync_en; | |
| 4878 | clk_ext__gclk clkgen_spc7_cmp_gclk_if.clk_ext; | |
| 4879 | cluster_arst_l__gclk clkgen_spc7_cmp_gclk_if.cluster_arst_l; | |
| 4880 | cluster_div_en__gclk clkgen_spc7_cmp_gclk_if.cluster_div_en; | |
| 4881 | cmp_slow_sync_en__gclk clkgen_spc7_cmp_gclk_if.cmp_slow_sync_en; | |
| 4882 | dr_sync_en__gclk void; | |
| 4883 | gclk clkgen_spc7_cmp_gclk_if.gclk; | |
| 4884 | io2x_sync_en__gclk void; | |
| 4885 | l2clk__gclk clkgen_spc7_cmp_gclk_if.l2clk; | |
| 4886 | pce_ov__gclk clkgen_spc7_cmp_gclk_if.pce_ov; | |
| 4887 | por___gclk clkgen_spc7_cmp_gclk_if.por_; | |
| 4888 | rst_por___gclk clkgen_spc7_cmp_gclk_if.rst_por_; | |
| 4889 | rst_wmr___gclk clkgen_spc7_cmp_gclk_if.rst_wmr_; | |
| 4890 | rst_wmr_protect__gclk clkgen_spc7_cmp_gclk_if.rst_wmr_protect; | |
| 4891 | scan_en__gclk clkgen_spc7_cmp_gclk_if.scan_en; | |
| 4892 | scan_in__gclk clkgen_spc7_cmp_gclk_if.scan_in; | |
| 4893 | scan_out__gclk clkgen_spc7_cmp_gclk_if.scan_out; | |
| 4894 | slow_cmp_sync_en__gclk clkgen_spc7_cmp_gclk_if.slow_cmp_sync_en; | |
| 4895 | tcu_aclk__gclk clkgen_spc7_cmp_gclk_if.tcu_aclk; | |
| 4896 | tcu_atpg_mode__gclk clkgen_spc7_cmp_gclk_if.tcu_atpg_mode; | |
| 4897 | tcu_bclk__gclk clkgen_spc7_cmp_gclk_if.tcu_bclk; | |
| 4898 | tcu_clk_stop__gclk clkgen_spc7_cmp_gclk_if.tcu_clk_stop; | |
| 4899 | tcu_div_bypass__gclk clkgen_spc7_cmp_gclk_if.tcu_div_bypass; | |
| 4900 | tcu_pce_ov__gclk clkgen_spc7_cmp_gclk_if.tcu_pce_ov; | |
| 4901 | tcu_wr_inhibit__gclk clkgen_spc7_cmp_gclk_if.tcu_wr_inhibit; | |
| 4902 | wmr___gclk clkgen_spc7_cmp_gclk_if.wmr_; | |
| 4903 | wmr_protect__gclk clkgen_spc7_cmp_gclk_if.wmr_protect; | |
| 4904 | pc_clk__gclk void; | |
| 4905 | pc_clk_sel__gclk void; | |
| 4906 | test_clk__gclk void; | |
| 4907 | test_clk_sel__gclk void; | |
| 4908 | ||
| 4909 | //---l2clk is Vera interface CLOCK--- | |
| 4910 | aclk__l2clk clkgen_spc7_cmp_l2clk_if.aclk; | |
| 4911 | aclk_wmr__l2clk clkgen_spc7_cmp_l2clk_if.aclk_wmr; | |
| 4912 | array_wr_inhibit__l2clk clkgen_spc7_cmp_l2clk_if.array_wr_inhibit; | |
| 4913 | bclk__l2clk clkgen_spc7_cmp_l2clk_if.bclk; | |
| 4914 | cmp_slow_sync_en__l2clk clkgen_spc7_cmp_l2clk_if.cmp_slow_sync_en; | |
| 4915 | dr_sync_en__l2clk void; | |
| 4916 | io2x_sync_en__l2clk void; | |
| 4917 | l2clk clkgen_spc7_cmp_l2clk_if.l2clk; | |
| 4918 | pce_ov__l2clk clkgen_spc7_cmp_l2clk_if.pce_ov; | |
| 4919 | por___l2clk clkgen_spc7_cmp_l2clk_if.por_; | |
| 4920 | scan_out__l2clk clkgen_spc7_cmp_l2clk_if.scan_out; | |
| 4921 | slow_cmp_sync_en__l2clk clkgen_spc7_cmp_l2clk_if.slow_cmp_sync_en; | |
| 4922 | wmr___l2clk clkgen_spc7_cmp_l2clk_if.wmr_; | |
| 4923 | wmr_protect__l2clk clkgen_spc7_cmp_l2clk_if.wmr_protect; | |
| 4924 | } | |
| 4925 | ||
| 4926 | #endif | |
| 4927 | ||
| 4928 | #ifndef FC_NO_NIU_T2 | |
| 4929 | #ifndef NIU_SYSTEMC_T2 | |
| 4930 | //----- port binding for clkgen_tds_io ----- | |
| 4931 | ||
| 4932 | bind CLKGEN_port clkgen_tds_io_bind { | |
| 4933 | //---gclk is Vera interface CLOCK--- | |
| 4934 | aclk__gclk clkgen_tds_io_gclk_if.aclk; | |
| 4935 | aclk_wmr__gclk clkgen_tds_io_gclk_if.aclk_wmr; | |
| 4936 | array_wr_inhibit__gclk clkgen_tds_io_gclk_if.array_wr_inhibit; | |
| 4937 | bclk__gclk clkgen_tds_io_gclk_if.bclk; | |
| 4938 | ccu_cmp_slow_sync_en__gclk clkgen_tds_io_gclk_if.ccu_cmp_slow_sync_en; | |
| 4939 | ccu_div_ph__gclk clkgen_tds_io_gclk_if.ccu_div_ph; | |
| 4940 | ccu_dr_sync_en__gclk void; | |
| 4941 | ccu_io2x_sync_en__gclk void; | |
| 4942 | ccu_serdes_dtm__gclk clkgen_tds_io_gclk_if.ccu_serdes_dtm; | |
| 4943 | ccu_slow_cmp_sync_en__gclk clkgen_tds_io_gclk_if.ccu_slow_cmp_sync_en; | |
| 4944 | clk_ext__gclk clkgen_tds_io_gclk_if.clk_ext; | |
| 4945 | cluster_arst_l__gclk clkgen_tds_io_gclk_if.cluster_arst_l; | |
| 4946 | cluster_div_en__gclk clkgen_tds_io_gclk_if.cluster_div_en; | |
| 4947 | cmp_slow_sync_en__gclk clkgen_tds_io_gclk_if.cmp_slow_sync_en; | |
| 4948 | dr_sync_en__gclk void; | |
| 4949 | gclk clkgen_tds_io_gclk_if.gclk; | |
| 4950 | io2x_sync_en__gclk void; | |
| 4951 | l2clk__gclk clkgen_tds_io_gclk_if.l2clk; | |
| 4952 | pce_ov__gclk clkgen_tds_io_gclk_if.pce_ov; | |
| 4953 | por___gclk clkgen_tds_io_gclk_if.por_; | |
| 4954 | rst_por___gclk clkgen_tds_io_gclk_if.rst_por_; | |
| 4955 | rst_wmr___gclk clkgen_tds_io_gclk_if.rst_wmr_; | |
| 4956 | rst_wmr_protect__gclk clkgen_tds_io_gclk_if.rst_wmr_protect; | |
| 4957 | scan_en__gclk clkgen_tds_io_gclk_if.scan_en; | |
| 4958 | scan_in__gclk clkgen_tds_io_gclk_if.scan_in; | |
| 4959 | scan_out__gclk clkgen_tds_io_gclk_if.scan_out; | |
| 4960 | slow_cmp_sync_en__gclk clkgen_tds_io_gclk_if.slow_cmp_sync_en; | |
| 4961 | tcu_aclk__gclk clkgen_tds_io_gclk_if.tcu_aclk; | |
| 4962 | tcu_atpg_mode__gclk clkgen_tds_io_gclk_if.tcu_atpg_mode; | |
| 4963 | tcu_bclk__gclk clkgen_tds_io_gclk_if.tcu_bclk; | |
| 4964 | tcu_clk_stop__gclk clkgen_tds_io_gclk_if.tcu_clk_stop; | |
| 4965 | tcu_div_bypass__gclk clkgen_tds_io_gclk_if.tcu_div_bypass; | |
| 4966 | tcu_pce_ov__gclk clkgen_tds_io_gclk_if.tcu_pce_ov; | |
| 4967 | tcu_wr_inhibit__gclk clkgen_tds_io_gclk_if.tcu_wr_inhibit; | |
| 4968 | wmr___gclk clkgen_tds_io_gclk_if.wmr_; | |
| 4969 | wmr_protect__gclk clkgen_tds_io_gclk_if.wmr_protect; | |
| 4970 | pc_clk__gclk void; | |
| 4971 | pc_clk_sel__gclk void; | |
| 4972 | test_clk__gclk void; | |
| 4973 | test_clk_sel__gclk void; | |
| 4974 | ||
| 4975 | //---l2clk is Vera interface CLOCK--- | |
| 4976 | aclk__l2clk clkgen_tds_io_l2clk_if.aclk; | |
| 4977 | aclk_wmr__l2clk clkgen_tds_io_l2clk_if.aclk_wmr; | |
| 4978 | array_wr_inhibit__l2clk clkgen_tds_io_l2clk_if.array_wr_inhibit; | |
| 4979 | bclk__l2clk clkgen_tds_io_l2clk_if.bclk; | |
| 4980 | cmp_slow_sync_en__l2clk clkgen_tds_io_l2clk_if.cmp_slow_sync_en; | |
| 4981 | dr_sync_en__l2clk void; | |
| 4982 | io2x_sync_en__l2clk void; | |
| 4983 | l2clk clkgen_tds_io_l2clk_if.l2clk; | |
| 4984 | pce_ov__l2clk clkgen_tds_io_l2clk_if.pce_ov; | |
| 4985 | por___l2clk clkgen_tds_io_l2clk_if.por_; | |
| 4986 | scan_out__l2clk clkgen_tds_io_l2clk_if.scan_out; | |
| 4987 | slow_cmp_sync_en__l2clk clkgen_tds_io_l2clk_if.slow_cmp_sync_en; | |
| 4988 | wmr___l2clk clkgen_tds_io_l2clk_if.wmr_; | |
| 4989 | wmr_protect__l2clk clkgen_tds_io_l2clk_if.wmr_protect; | |
| 4990 | } | |
| 4991 | ||
| 4992 | //----- port binding for clkgen_tds_io2x ----- | |
| 4993 | ||
| 4994 | bind CLKGEN_port clkgen_tds_io2x_bind { | |
| 4995 | //---gclk is Vera interface CLOCK--- | |
| 4996 | aclk__gclk clkgen_tds_io2x_gclk_if.aclk; | |
| 4997 | aclk_wmr__gclk clkgen_tds_io2x_gclk_if.aclk_wmr; | |
| 4998 | array_wr_inhibit__gclk clkgen_tds_io2x_gclk_if.array_wr_inhibit; | |
| 4999 | bclk__gclk clkgen_tds_io2x_gclk_if.bclk; | |
| 5000 | ccu_cmp_slow_sync_en__gclk clkgen_tds_io2x_gclk_if.ccu_cmp_slow_sync_en; | |
| 5001 | ccu_div_ph__gclk clkgen_tds_io2x_gclk_if.ccu_div_ph; | |
| 5002 | ccu_dr_sync_en__gclk void; | |
| 5003 | ccu_io2x_sync_en__gclk void; | |
| 5004 | ccu_serdes_dtm__gclk clkgen_tds_io2x_gclk_if.ccu_serdes_dtm; | |
| 5005 | ccu_slow_cmp_sync_en__gclk clkgen_tds_io2x_gclk_if.ccu_slow_cmp_sync_en; | |
| 5006 | clk_ext__gclk clkgen_tds_io2x_gclk_if.clk_ext; | |
| 5007 | cluster_arst_l__gclk clkgen_tds_io2x_gclk_if.cluster_arst_l; | |
| 5008 | cluster_div_en__gclk clkgen_tds_io2x_gclk_if.cluster_div_en; | |
| 5009 | cmp_slow_sync_en__gclk clkgen_tds_io2x_gclk_if.cmp_slow_sync_en; | |
| 5010 | dr_sync_en__gclk void; | |
| 5011 | gclk clkgen_tds_io2x_gclk_if.gclk; | |
| 5012 | io2x_sync_en__gclk void; | |
| 5013 | l2clk__gclk clkgen_tds_io2x_gclk_if.l2clk; | |
| 5014 | pce_ov__gclk clkgen_tds_io2x_gclk_if.pce_ov; | |
| 5015 | por___gclk clkgen_tds_io2x_gclk_if.por_; | |
| 5016 | rst_por___gclk clkgen_tds_io2x_gclk_if.rst_por_; | |
| 5017 | rst_wmr___gclk clkgen_tds_io2x_gclk_if.rst_wmr_; | |
| 5018 | rst_wmr_protect__gclk clkgen_tds_io2x_gclk_if.rst_wmr_protect; | |
| 5019 | scan_en__gclk clkgen_tds_io2x_gclk_if.scan_en; | |
| 5020 | scan_in__gclk clkgen_tds_io2x_gclk_if.scan_in; | |
| 5021 | scan_out__gclk clkgen_tds_io2x_gclk_if.scan_out; | |
| 5022 | slow_cmp_sync_en__gclk clkgen_tds_io2x_gclk_if.slow_cmp_sync_en; | |
| 5023 | tcu_aclk__gclk clkgen_tds_io2x_gclk_if.tcu_aclk; | |
| 5024 | tcu_atpg_mode__gclk clkgen_tds_io2x_gclk_if.tcu_atpg_mode; | |
| 5025 | tcu_bclk__gclk clkgen_tds_io2x_gclk_if.tcu_bclk; | |
| 5026 | tcu_clk_stop__gclk clkgen_tds_io2x_gclk_if.tcu_clk_stop; | |
| 5027 | tcu_div_bypass__gclk clkgen_tds_io2x_gclk_if.tcu_div_bypass; | |
| 5028 | tcu_pce_ov__gclk clkgen_tds_io2x_gclk_if.tcu_pce_ov; | |
| 5029 | tcu_wr_inhibit__gclk clkgen_tds_io2x_gclk_if.tcu_wr_inhibit; | |
| 5030 | wmr___gclk clkgen_tds_io2x_gclk_if.wmr_; | |
| 5031 | wmr_protect__gclk clkgen_tds_io2x_gclk_if.wmr_protect; | |
| 5032 | pc_clk__gclk void; | |
| 5033 | pc_clk_sel__gclk void; | |
| 5034 | test_clk__gclk void; | |
| 5035 | test_clk_sel__gclk void; | |
| 5036 | ||
| 5037 | //---l2clk is Vera interface CLOCK--- | |
| 5038 | aclk__l2clk clkgen_tds_io2x_l2clk_if.aclk; | |
| 5039 | aclk_wmr__l2clk clkgen_tds_io2x_l2clk_if.aclk_wmr; | |
| 5040 | array_wr_inhibit__l2clk clkgen_tds_io2x_l2clk_if.array_wr_inhibit; | |
| 5041 | bclk__l2clk clkgen_tds_io2x_l2clk_if.bclk; | |
| 5042 | cmp_slow_sync_en__l2clk clkgen_tds_io2x_l2clk_if.cmp_slow_sync_en; | |
| 5043 | dr_sync_en__l2clk void; | |
| 5044 | io2x_sync_en__l2clk void; | |
| 5045 | l2clk clkgen_tds_io2x_l2clk_if.l2clk; | |
| 5046 | pce_ov__l2clk clkgen_tds_io2x_l2clk_if.pce_ov; | |
| 5047 | por___l2clk clkgen_tds_io2x_l2clk_if.por_; | |
| 5048 | scan_out__l2clk clkgen_tds_io2x_l2clk_if.scan_out; | |
| 5049 | slow_cmp_sync_en__l2clk clkgen_tds_io2x_l2clk_if.slow_cmp_sync_en; | |
| 5050 | wmr___l2clk clkgen_tds_io2x_l2clk_if.wmr_; | |
| 5051 | wmr_protect__l2clk clkgen_tds_io2x_l2clk_if.wmr_protect; | |
| 5052 | } | |
| 5053 | #endif | |
| 5054 | #endif | |
| 5055 | ||
| 5056 | #endif // #ifdef FC_BENCH | |
| 5057 | #endif // #ifndef INC_CLUSTER_HDR_BIND_VRI |