Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / tcu / vera / include / cluster_hdr.port.vri
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: cluster_hdr.port.vri
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
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8//
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10// it under the terms of the GNU General Public License as published by
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14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
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21//
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34// ========== Copyright Header End ============================================
35#ifndef INC_CLUSTER_HDR_PORT_VRI
36#define INC_CLUSTER_HDR_PORT_VRI
37
38//===============================================================
39// WHAT: port declaration for clkgen modules (aka cluster headers)
40//
41// NAMING CONVENTION:
42// -Signals without "tag" is a Vera CLOCK.
43// -SignalNameInRtl__VeraInterfaceClock. Eg. dr_sync_en__gclk.
44//
45// WARNING: this file is generated by gen_cluster_hdr.pl. Do not modify.
46//===============================================================
47
48port CLKGEN_port {
49 //---All signals (listed in alphabetical order). gclk is Vera CLOCK---
50 //---NOTE: gclk is an always-running clock---
51 aclk__gclk;
52 aclk_wmr__gclk;
53 array_wr_inhibit__gclk;
54 bclk__gclk;
55 ccu_cmp_slow_sync_en__gclk;
56 ccu_div_ph__gclk;
57 ccu_dr_sync_en__gclk;
58 ccu_io2x_sync_en__gclk;
59 ccu_serdes_dtm__gclk;
60 ccu_slow_cmp_sync_en__gclk;
61 clk_ext__gclk;
62 cluster_arst_l__gclk;
63 cluster_div_en__gclk;
64 cmp_slow_sync_en__gclk;
65 dr_sync_en__gclk;
66 gclk;
67 io2x_sync_en__gclk;
68 l2clk__gclk;
69 pce_ov__gclk;
70 por___gclk;
71 rst_por___gclk;
72 rst_wmr___gclk;
73 rst_wmr_protect__gclk;
74 scan_en__gclk;
75 scan_in__gclk;
76 scan_out__gclk;
77 slow_cmp_sync_en__gclk;
78 tcu_aclk__gclk;
79 tcu_atpg_mode__gclk;
80 tcu_bclk__gclk;
81 tcu_clk_stop__gclk;
82 tcu_div_bypass__gclk;
83 tcu_pce_ov__gclk;
84 tcu_wr_inhibit__gclk;
85 wmr___gclk;
86 wmr_protect__gclk;
87 pc_clk__gclk;
88 pc_clk_sel__gclk;
89 test_clk__gclk;
90 test_clk_sel__gclk;
91
92 //---output signals (listed in alphabetical order). l2clk is Vera CLOCK---
93 aclk__l2clk;
94 aclk_wmr__l2clk;
95 array_wr_inhibit__l2clk;
96 bclk__l2clk;
97 cmp_slow_sync_en__l2clk;
98 dr_sync_en__l2clk;
99 io2x_sync_en__l2clk;
100 l2clk;
101 pce_ov__l2clk;
102 por___l2clk;
103 scan_out__l2clk;
104 slow_cmp_sync_en__l2clk;
105 wmr___l2clk;
106 wmr_protect__l2clk;
107}
108
109#endif