Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / tcu / vera / include / pkg.if.vri

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// OpenSPARC T2 Processor File: pkg.if.vri
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#ifndef INC_PKG_IF_VRI
#define INC_PKG_IF_VRI

#include "fc_top_defines.vri"
#include "dbg_dq_pins_defines.vri"

interface pkg_if {
  input   clk              CLOCK     verilog_node "`CPU.PLL_CMP_CLK_P";  // review: need to use an always running IO2X clk

  //---- N2 input pins (listed in alphabetical order) ----
  output  DIVIDER_BYPASS   NHOLD  verilog_node "`CPU.DIVIDER_BYPASS";
  output  PLL_CMP_BYPASS   NHOLD  verilog_node "`CPU.PLL_CMP_BYPASS";
  output  PLL_TESTMODE     NHOLD  verilog_node "`CPU.PLL_TESTMODE";
  output  TRIGIN           NHOLD  verilog_node "`CPU.TRIGIN";
  output  VDD_PLL_CMP_REG  NHOLD  verilog_node "`CPU.VDD_PLL_CMP_REG";
  output  VDD_RNG_HV       NHOLD  verilog_node "`CPU.VDD_RNG_HV";
  output  VREG_SELBG_L     NHOLD  verilog_node "`CPU.VREG_SELBG_L";

  //---- N2 output pins  (listed in alphabetical order)----
  input  [1:0] PLL_CHAR_OUT       PSAMPLE #-1  verilog_node "`CPU.PLL_CHAR_OUT";
  input        RNG_ANLG_CHAR_OUT  PSAMPLE #-1  verilog_node "`CPU.RNG_ANLG_CHAR_OUT";
  input        TRIGOUT            PSAMPLE #-1  verilog_node "`CPU.TRIGOUT";

  //--- N2 bidirectional pins  (listed in alphabetical order)---
  input  [165:0] DBG_DQ_in  PSAMPLE #-1  verilog_node "`CPU.DBG_DQ";
  output [165:0] DBG_DQ_out NHOLD        verilog_node "`CPU.DBG_DQ";
}

#endif