Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / tcu / vera / include / reg.if.vri

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: reg.if.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
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// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#ifndef INC_REG_IF_VRI
#define INC_REG_IF_VRI

#include "tcu_top_defines.vri"

//----------------- Reset status register ---------------------
interface reg_rst_if {
  input        clk           	CLOCK                 verilog_node "`CPU.PLL_CMP_CLK_P";
  input        zero          	INPUT_EDGE INPUT_SKEW verilog_node "`TOP.zero";
  input        one           	INPUT_EDGE INPUT_SKEW verilog_node "`TOP.one";
#ifdef GATESIM
  input [15:0]  reset_src       INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.rst.rst_fsm_ctl__reset_source_q_15_,`CPU.rst.rst_fsm_ctl__reset_source_q_14_,`CPU.rst.rst_fsm_ctl__reset_source_q_13_,`CPU.rst.rst_fsm_ctl__reset_source_q_12_,`CPU.rst.rst_fsm_ctl__reset_source_q_11_,`CPU.rst.rst_fsm_ctl__reset_source_q_10_,`CPU.rst.rst_fsm_ctl__reset_source_q_9_,`CPU.rst.rst_fsm_ctl__reset_source_q_8_,`CPU.rst.rst_fsm_ctl__reset_source_q_7_,`CPU.rst.rst_fsm_ctl__reset_source_q_6_,`CPU.rst.rst_fsm_ctl__reset_source_q_5_,`CPU.rst.rst_fsm_ctl__reset_source_pwron_q_,`CPU.rst.rst_fsm_ctl__reset_source_q_3_,1'b0,`CPU.rst.rst_fsm_ctl__reset_source_q_1_,`CPU.rst.rst_fsm_ctl__reset_source_q_0_}";
  input [4:0]  reset_gen        INPUT_EDGE INPUT_SKEW verilog_node "{1'b0,`CPU.rst.reset_gen_dbr_gen_q,1'b0,`CPU.rst.rst_fsm_ctl__reset_gen_q_1_,`CPU.rst.rst_fsm_ctl__reset_gen_q_0_}";
  input [1:0]  ssys_reset       INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.rst.rst_fsm_ctl__ssys_reset_q_1_,`CPU.rst.rst_fsm_ctl__ssys_reset_q_0_}";
  input [2:0]  status_shdw      INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.rst.rst_fsm_ctl__rset_stat_shadow_q_2_,`CPU.rst.rst_fsm_ctl__rset_stat_shadow_q_1_,`CPU.rst.rst_fsm_ctl__rset_stat_shadow_q_0_}";
  input [2:0]  status           INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.rst.rst_fsm_ctl__rset_stat_q_3_,`CPU.rst.rst_fsm_ctl__rset_stat_por_q_phy_,`CPU.rst.rst_fsm_ctl__rset_stat_q_1_}";
  input        mcu_selfrsh      INPUT_EDGE INPUT_SKEW verilog_node "`CPU.rst.rst_mcu_selfrsh_sys2";
  input [15:0] lock_count       INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.rst.rst_fsm_ctl__lock_time_q_phy_15_,`CPU.rst.rst_fsm_ctl__lock_time_q_phy_14_,`CPU.rst.rst_fsm_ctl__lock_time_q_phy_13_,`CPU.rst.rst_fsm_ctl__lock_time_q_phy_12_,`CPU.rst.rst_fsm_ctl__lock_time_q_phy_11_,`CPU.rst.rst_fsm_ctl__lock_time_q_phy_10_,`CPU.rst.rst_fsm_ctl__lock_time_q_phy_9_,`CPU.rst.rst_fsm_ctl__lock_time_q_phy_8_,`CPU.rst.rst_fsm_ctl__lock_time_q_phy_7_,`CPU.rst.rst_fsm_ctl__lock_time_q_phy_6_,`CPU.rst.rst_fsm_ctl__lock_time_q_phy_5_,`CPU.rst.rst_fsm_ctl__lock_time_q_phy_4_,`CPU.rst.rst_fsm_ctl__lock_time_q_phy_3_,`CPU.rst.rst_fsm_ctl__lock_time_q_phy_2_,`CPU.rst.rst_fsm_ctl__lock_time_q_phy_1_,`CPU.rst.rst_fsm_ctl__lock_time_q_phy_0_}";
  input [15:0] niu_count        INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.rst.rst_fsm_ctl__niu_time_q_phy_15_,`CPU.rst.rst_fsm_ctl__niu_time_q_phy_14_,`CPU.rst.rst_fsm_ctl__niu_time_q_phy_13_,`CPU.rst.rst_fsm_ctl__niu_time_q_phy_12_,`CPU.rst.rst_fsm_ctl__niu_time_q_phy_11_,`CPU.rst.rst_fsm_ctl__niu_time_q_phy_10_,`CPU.rst.rst_fsm_ctl__niu_time_q_phy_9_,`CPU.rst.rst_fsm_ctl__niu_time_q_phy_8_,`CPU.rst.rst_fsm_ctl__niu_time_q_phy_7_,`CPU.rst.rst_fsm_ctl__niu_time_q_phy_6_,`CPU.rst.rst_fsm_ctl__niu_time_q_phy_5_,`CPU.rst.rst_fsm_ctl__niu_time_q_phy_4_,`CPU.rst.rst_fsm_ctl__niu_time_q_phy_3_,`CPU.rst.rst_fsm_ctl__niu_time_q_phy_2_,`CPU.rst.rst_fsm_ctl__niu_time_q_phy_1_,`CPU.rst.rst_fsm_ctl__niu_time_q_phy_0_}";
  input [15:0] prop_count       INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.rst.rst_fsm_ctl__prop_time_q_phy_15_,`CPU.rst.rst_fsm_ctl__prop_time_q_phy_14_,`CPU.rst.rst_fsm_ctl__prop_time_q_phy_13_,`CPU.rst.rst_fsm_ctl__prop_time_q_phy_12_,`CPU.rst.rst_fsm_ctl__prop_time_q_phy_11_,`CPU.rst.rst_fsm_ctl__prop_time_q_phy_10_,`CPU.rst.rst_fsm_ctl__prop_time_q_phy_9_,`CPU.rst.rst_fsm_ctl__prop_time_q_phy_8_,`CPU.rst.rst_fsm_ctl__prop_time_q_phy_7_,`CPU.rst.rst_fsm_ctl__prop_time_q_phy_6_,`CPU.rst.rst_fsm_ctl__prop_time_q_phy_5_,`CPU.rst.rst_fsm_ctl__prop_time_q_phy_4_,`CPU.rst.rst_fsm_ctl__prop_time_q_phy_3_,`CPU.rst.rst_fsm_ctl__prop_time_q_phy_2_,`CPU.rst.rst_fsm_ctl__prop_time_q_phy_1_,`CPU.rst.rst_fsm_ctl__prop_time_q_phy_0_}";
  input [15:0] ccu_count        INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.rst.rst_fsm_ctl__ccu_time_q_phy_15_,`CPU.rst.rst_fsm_ctl__ccu_time_q_phy_14_,`CPU.rst.rst_fsm_ctl__ccu_time_q_phy_13_,`CPU.rst.rst_fsm_ctl__ccu_time_q_phy_12_,`CPU.rst.rst_fsm_ctl__ccu_time_q_phy_11_,`CPU.rst.rst_fsm_ctl__ccu_time_q_phy_10_,`CPU.rst.rst_fsm_ctl__ccu_time_q_phy_9_,`CPU.rst.rst_fsm_ctl__ccu_time_q_phy_8_,`CPU.rst.rst_fsm_ctl__ccu_time_q_phy_7_,`CPU.rst.rst_fsm_ctl__ccu_time_q_phy_6_,`CPU.rst.rst_fsm_ctl__ccu_time_q_phy_5_,`CPU.rst.rst_fsm_ctl__ccu_time_q_phy_4_,`CPU.rst.rst_fsm_ctl__ccu_time_q_phy_3_,`CPU.rst.rst_fsm_ctl__ccu_time_q_phy_2_,`CPU.rst.rst_fsm_ctl__ccu_time_q_phy_1_,`CPU.rst.rst_fsm_ctl__ccu_time_q_phy_0_}";
  input [7:0]  reset_fee        INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.rst.rst_fsm_ctl__reset_fee_q_7_,`CPU.rst.rst_fsm_ctl__reset_fee_q_6_,`CPU.rst.rst_fsm_ctl__reset_fee_q_5_,`CPU.rst.rst_fsm_ctl__reset_fee_q_4_,`CPU.rst.rst_fsm_ctl__reset_fee_q_3_,`CPU.rst.rst_fsm_ctl__reset_fee_q_2_,`CPU.rst.rst_fsm_ctl__reset_fee_q_1_,`CPU.rst.rst_fsm_ctl__reset_fee_q_0_}";
#else
  input [15:0]  reset_src     	INPUT_EDGE INPUT_SKEW verilog_node "`CPU.rst.rst_fsm_ctl.reset_source_q";
  input [4:0]  reset_gen     	INPUT_EDGE INPUT_SKEW verilog_node "`CPU.rst.rst_fsm_ctl.reset_gen_q";  
  input [1:0]  ssys_reset    	INPUT_EDGE INPUT_SKEW verilog_node "`CPU.rst.rst_fsm_ctl.ssys_reset_q";
  input [2:0]  status_shdw   	INPUT_EDGE INPUT_SKEW verilog_node "`CPU.rst.rst_fsm_ctl.rset_stat_q[11:9]";
  input [2:0]  status        	INPUT_EDGE INPUT_SKEW verilog_node "`CPU.rst.rst_fsm_ctl.rset_stat_q[3:1]";
  input        mcu_selfrsh 	INPUT_EDGE INPUT_SKEW verilog_node "`CPU.rst.rst_fsm_ctl.ssys_reset_mcu_q";
  input [15:0] lock_count       INPUT_EDGE INPUT_SKEW verilog_node "`CPU.rst.rst_fsm_ctl.lock_time_q";
  input [15:0] niu_count        INPUT_EDGE INPUT_SKEW verilog_node "`CPU.rst.rst_fsm_ctl.niu_time_q";
  input [15:0] prop_count       INPUT_EDGE INPUT_SKEW verilog_node "`CPU.rst.rst_fsm_ctl.prop_time_q";
  input [15:0] ccu_count        INPUT_EDGE INPUT_SKEW verilog_node "`CPU.rst.rst_fsm_ctl.ccu_time_q";
  input [7:0]  reset_fee        INPUT_EDGE INPUT_SKEW verilog_node "`CPU.rst.rst_fsm_ctl.reset_fee_q";
#endif
}

#endif