[OpenSPARC-T2-DV] / verif / env / tcu / vera / include / rst.if.vri

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: rst.if.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#ifndef INC_RST_IF_VRI
#define INC_RST_IF_VRI

#include "tcu_top_defines.vri"

interface sc {
  input  clk                   CLOCK                          verilog_node "`CPU.PLL_CMP_CLK_P";
  input  POR_L_IN              INPUT_EDGE  INPUT_SKEW         verilog_node "`CPU.PWRON_RST_L";
  output POR_L                 OUTPUT_EDGE_N         verilog_node "`CPU.PWRON_RST_L";
  output PB_XIR_L              OUTPUT_EDGE_N         verilog_node "`CPU.BUTTON_XIR_L";
  output PB_RST_L              OUTPUT_EDGE_N         verilog_node "`CPU.PB_RST_L";
}

interface rst {
  input  clk                         CLOCK                          verilog_node "`CPU.PLL_CMP_CLK_P";
  input  tb_clk_stop_all             INPUT_EDGE INPUT_SKEW          verilog_node "`MONTCU.tb_clk_stop_all";
  input  tb_clk_stop_one             INPUT_EDGE INPUT_SKEW          verilog_node "`MONTCU.tb_clk_stop_one";
}

interface rst_l2clk {
  input  clk_l2clk                   CLOCK                          verilog_node "`RST.l2clk";
  input  rst_niu_wmr_                INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_niu_wmr_";
  input  ccu_rst_change              INPUT_EDGE INPUT_SKEW          verilog_node "`RST.ccu_rst_change"; 
  input  tcu_bisx_done               INPUT_EDGE INPUT_SKEW          verilog_node "`RST.tcu_bisx_done"; 
  input  tcu_rst_efu_done            INPUT_EDGE INPUT_SKEW          verilog_node "`RST.tcu_rst_efu_done"; 
  input  tcu_pce_ov                  INPUT_EDGE INPUT_SKEW          verilog_node "`RST.tcu_pce_ov";
  input  tcu_rst_io_clk_stop         INPUT_EDGE INPUT_SKEW          verilog_node "`RST.tcu_rst_io_clk_stop";
  input  tcu_rst_flush_init_ack      INPUT_EDGE INPUT_SKEW          verilog_node "`RST.tcu_rst_flush_init_ack";
  input  tcu_rst_flush_stop_ack      INPUT_EDGE INPUT_SKEW          verilog_node "`RST.tcu_rst_flush_stop_ack";
  input  rst_tcu_flush_init_req      INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_tcu_flush_init_req";
  input  rst_tcu_flush_stop_req      INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_tcu_flush_stop_req";
  input  rst_tcu_asicflush_stop_req  INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_tcu_asicflush_stop_req";
  input  tcu_rst_asicflush_stop_ack  INPUT_EDGE INPUT_SKEW          verilog_node "`RST.tcu_rst_asicflush_stop_ack";
  input  rst_l2_por_                 INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_l2_por_";
  input  rst_l2_wmr_                 INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_l2_wmr_";
  input  rst_wmr_protect             INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_wmr_protect";
  input  rst_dmu_peu_por_            INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_dmu_peu_por_";
  input  rst_dmu_peu_wmr_            INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_dmu_peu_wmr_";
  input  ccu_rst_sync_stable         INPUT_EDGE INPUT_SKEW          verilog_node "`RST.ccu_rst_sync_stable";
  input  tcu_rst_scan_mode           INPUT_EDGE INPUT_SKEW          verilog_node "`RST.tcu_rst_scan_mode";
}

interface rst_iol2clk {
  input  clk_iol2clk                 CLOCK                          verilog_node "`RST.iol2clk";
  input  rst_ncu_unpark_thread       INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_ncu_unpark_thread";
  input  rst_ncu_xir_                INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_ncu_xir_";
  input  ncu_rst_xir_done            INPUT_EDGE INPUT_SKEW          verilog_node "`RST.ncu_rst_xir_done";
  input  rst_mcu_selfrsh             INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_mcu_selfrsh";
#ifdef TCU_SAT
  output ncu_rst_fatal_error         OUTPUT_EDGE_N         verilog_node "`TOP.ncu_rst_fatal_error_vera"; // Forced in tcu_top.vh to enable driving the signal through vera
#else
  output ncu_rst_fatal_error         OUTPUT_EDGE_N         verilog_node "`NCU.ncu_rst_fatal_error";
#endif

  output l2t0_rst_fatal_error        OUTPUT_EDGE_N         verilog_node "`RST.l2t0_rst_fatal_error";
  output l2t1_rst_fatal_error        OUTPUT_EDGE_N         verilog_node "`RST.l2t1_rst_fatal_error";
  output l2t2_rst_fatal_error        OUTPUT_EDGE_N         verilog_node "`RST.l2t2_rst_fatal_error";
  output l2t3_rst_fatal_error        OUTPUT_EDGE_N         verilog_node "`RST.l2t3_rst_fatal_error";
  output l2t4_rst_fatal_error        OUTPUT_EDGE_N         verilog_node "`RST.l2t4_rst_fatal_error";
  output l2t5_rst_fatal_error        OUTPUT_EDGE_N         verilog_node "`RST.l2t5_rst_fatal_error";
  output l2t6_rst_fatal_error        OUTPUT_EDGE_N         verilog_node "`RST.l2t6_rst_fatal_error";
  output l2t7_rst_fatal_error        OUTPUT_EDGE_N         verilog_node "`RST.l2t7_rst_fatal_error";
}


#endif
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: rst.if.vri
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	#ifndef INC_RST_IF_VRI
	36	#define INC_RST_IF_VRI
	37
	38	#include "tcu_top_defines.vri"
	39
	40	interface sc {
	41	input clk CLOCK verilog_node "`CPU.PLL_CMP_CLK_P";
	42	input POR_L_IN INPUT_EDGE INPUT_SKEW verilog_node "`CPU.PWRON_RST_L";
	43	output POR_L OUTPUT_EDGE_N verilog_node "`CPU.PWRON_RST_L";
	44	output PB_XIR_L OUTPUT_EDGE_N verilog_node "`CPU.BUTTON_XIR_L";
	45	output PB_RST_L OUTPUT_EDGE_N verilog_node "`CPU.PB_RST_L";
	46	}
	47
	48	interface rst {
	49	input clk CLOCK verilog_node "`CPU.PLL_CMP_CLK_P";
	50	input tb_clk_stop_all INPUT_EDGE INPUT_SKEW verilog_node "`MONTCU.tb_clk_stop_all";
	51	input tb_clk_stop_one INPUT_EDGE INPUT_SKEW verilog_node "`MONTCU.tb_clk_stop_one";
	52	}
	53
	54	interface rst_l2clk {
	55	input clk_l2clk CLOCK verilog_node "`RST.l2clk";
	56	input rst_niu_wmr_ INPUT_EDGE INPUT_SKEW verilog_node "`RST.rst_niu_wmr_";
	57	input ccu_rst_change INPUT_EDGE INPUT_SKEW verilog_node "`RST.ccu_rst_change";
	58	input tcu_bisx_done INPUT_EDGE INPUT_SKEW verilog_node "`RST.tcu_bisx_done";
	59	input tcu_rst_efu_done INPUT_EDGE INPUT_SKEW verilog_node "`RST.tcu_rst_efu_done";
	60	input tcu_pce_ov INPUT_EDGE INPUT_SKEW verilog_node "`RST.tcu_pce_ov";
	61	input tcu_rst_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`RST.tcu_rst_io_clk_stop";
	62	input tcu_rst_flush_init_ack INPUT_EDGE INPUT_SKEW verilog_node "`RST.tcu_rst_flush_init_ack";
	63	input tcu_rst_flush_stop_ack INPUT_EDGE INPUT_SKEW verilog_node "`RST.tcu_rst_flush_stop_ack";
	64	input rst_tcu_flush_init_req INPUT_EDGE INPUT_SKEW verilog_node "`RST.rst_tcu_flush_init_req";
65	input rst_tcu_flush_stop_req INPUT_EDGE INPUT_SKEW verilog_node "`RST.rst_tcu_flush_stop_req";
66	input rst_tcu_asicflush_stop_req INPUT_EDGE INPUT_SKEW verilog_node "`RST.rst_tcu_asicflush_stop_req";
67	input tcu_rst_asicflush_stop_ack INPUT_EDGE INPUT_SKEW verilog_node "`RST.tcu_rst_asicflush_stop_ack";
68	input rst_l2_por_ INPUT_EDGE INPUT_SKEW verilog_node "`RST.rst_l2_por_";
69	input rst_l2_wmr_ INPUT_EDGE INPUT_SKEW verilog_node "`RST.rst_l2_wmr_";
70	input rst_wmr_protect INPUT_EDGE INPUT_SKEW verilog_node "`RST.rst_wmr_protect";
71	input rst_dmu_peu_por_ INPUT_EDGE INPUT_SKEW verilog_node "`RST.rst_dmu_peu_por_";
72	input rst_dmu_peu_wmr_ INPUT_EDGE INPUT_SKEW verilog_node "`RST.rst_dmu_peu_wmr_";
73	input ccu_rst_sync_stable INPUT_EDGE INPUT_SKEW verilog_node "`RST.ccu_rst_sync_stable";
74	input tcu_rst_scan_mode INPUT_EDGE INPUT_SKEW verilog_node "`RST.tcu_rst_scan_mode";
75	}
76
77	interface rst_iol2clk {
78	input clk_iol2clk CLOCK verilog_node "`RST.iol2clk";
79	input rst_ncu_unpark_thread INPUT_EDGE INPUT_SKEW verilog_node "`RST.rst_ncu_unpark_thread";
80	input rst_ncu_xir_ INPUT_EDGE INPUT_SKEW verilog_node "`RST.rst_ncu_xir_";
81	input ncu_rst_xir_done INPUT_EDGE INPUT_SKEW verilog_node "`RST.ncu_rst_xir_done";
82	input rst_mcu_selfrsh INPUT_EDGE INPUT_SKEW verilog_node "`RST.rst_mcu_selfrsh";
83	#ifdef TCU_SAT
84	output ncu_rst_fatal_error OUTPUT_EDGE_N verilog_node "`TOP.ncu_rst_fatal_error_vera"; // Forced in tcu_top.vh to enable driving the signal through vera
85	#else
86	output ncu_rst_fatal_error OUTPUT_EDGE_N verilog_node "`NCU.ncu_rst_fatal_error";
87	#endif
88
89	output l2t0_rst_fatal_error OUTPUT_EDGE_N verilog_node "`RST.l2t0_rst_fatal_error";
90	output l2t1_rst_fatal_error OUTPUT_EDGE_N verilog_node "`RST.l2t1_rst_fatal_error";
91	output l2t2_rst_fatal_error OUTPUT_EDGE_N verilog_node "`RST.l2t2_rst_fatal_error";
92	output l2t3_rst_fatal_error OUTPUT_EDGE_N verilog_node "`RST.l2t3_rst_fatal_error";
93	output l2t4_rst_fatal_error OUTPUT_EDGE_N verilog_node "`RST.l2t4_rst_fatal_error";
94	output l2t5_rst_fatal_error OUTPUT_EDGE_N verilog_node "`RST.l2t5_rst_fatal_error";
95	output l2t6_rst_fatal_error OUTPUT_EDGE_N verilog_node "`RST.l2t6_rst_fatal_error";
96	output l2t7_rst_fatal_error OUTPUT_EDGE_N verilog_node "`RST.l2t7_rst_fatal_error";
97	}
98
99
100	#endif