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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / tcu / vera / include / tcu.bind.vri
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: tcu.bind.vri
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#ifndef INC_TCU_BIND_VRI
36#define INC_TCU_BIND_VRI
37
38#include <tcu_top_defines.vri>
39
40bind TCU_clk_port tcu_clk_bind {
41 l2clk tcu_l2clk_if.l2clk;
42 iol2clk tcu_iol2clk_if.l2clk;
43 gclk tcu_gclk_if.gclk;
44}
45
46// now in common
47// bind tap__port tap_bind {
48// tck jtag.TCK;
49// trst_n jtag.TRST_L;
50// test_mode jtag.TEST_MODE;
51// tms jtag.TMS;
52// tdi jtag.TDI;
53// tdo jtag.TDO;
54// }
55
56bind bscan__port bscan_bind {
57 tck bscan.TCK;
58 scan_en bscan.bs_scan_en;
59 clk bscan.bs_clk;
60 aclk bscan.bs_aclk;
61 bclk bscan.bs_bclk;
62 uclk bscan.bs_uclk;
63}
64
65bind mbist__port mbist_bind {
66 clk mbist.TCK;
67 mbist_user mbist.mbist_user;
68 mbist_start
69 {
70 mbist.tcu_rdp_rdmc_mbist_start,
71 mbist.tcu_rtx_rxc_ipp0_mbist_start,
72 mbist.tcu_rtx_rxc_ipp1_mbist_start,
73 mbist.tcu_rtx_rxc_mb5_mbist_start,
74 mbist.tcu_rtx_rxc_mb6_mbist_start,
75 mbist.tcu_rtx_rxc_zcp0_mbist_start,
76 mbist.tcu_rtx_rxc_zcp1_mbist_start,
77 mbist.tcu_rtx_txc_txe0_mbist_start,
78 mbist.tcu_rtx_txc_txe1_mbist_start,
79 mbist.tcu_tds_smx_mbist_start,
80 mbist.tcu_tds_tdmc_mbist_start,
81 mbist.tcu_peu_mbist_start,
82 mbist.tcu_dmu_mbist_start,
83 mbist.tcu_l2t7_mbist_start,
84 mbist.tcu_l2t6_mbist_start,
85 mbist.tcu_l2t5_mbist_start,
86 mbist.tcu_l2t4_mbist_start,
87 mbist.tcu_l2t3_mbist_start,
88 mbist.tcu_l2t2_mbist_start,
89 mbist.tcu_l2t1_mbist_start,
90 mbist.tcu_l2t0_mbist_start,
91 mbist.tcu_l2b7_mbist_start,
92 mbist.tcu_l2b6_mbist_start,
93 mbist.tcu_l2b5_mbist_start,
94 mbist.tcu_l2b4_mbist_start,
95 mbist.tcu_l2b3_mbist_start,
96 mbist.tcu_l2b2_mbist_start,
97 mbist.tcu_l2b1_mbist_start,
98 mbist.tcu_l2b0_mbist_start,
99 mbist.tcu_mcu3_mbist_start,
100 mbist.tcu_mcu2_mbist_start,
101 mbist.tcu_mcu1_mbist_start,
102 mbist.tcu_mcu0_mbist_start,
103 mbist.tcu_ncu_mbist_start,
104 mbist.tcu_sio_mbist_start,
105 mbist.tcu_sii_mbist_start,
106 mbist.tcu_spc_mbist_start
107 };
108 mbist_done
109 {
110 mbist.rdp_rdmc_tcu_mbist_done
111 , mbist.rtx_rxc_ipp0_tcu_mbist_done
112 , mbist.rtx_rxc_ipp1_tcu_mbist_done
113 , mbist.rtx_rxc_mb5_tcu_mbist_done
114 , mbist.rtx_rxc_mb6_tcu_mbist_done
115 , mbist.rtx_rxc_zcp0_tcu_mbist_done
116 , mbist.rtx_rxc_zcp1_tcu_mbist_done
117 , mbist.rtx_txc_txe0_tcu_mbist_done
118 , mbist.rtx_txc_txe1_tcu_mbist_done
119 , mbist.tds_smx_tcu_mbist_done
120 , mbist.tds_tdmc_tcu_mbist_done
121 , mbist.peu_tcu_mbist_done
122 , mbist.dmu_tcu_mbist_done
123 , mbist.l2t7_tcu_mbist_done
124 , mbist.l2t6_tcu_mbist_done
125 , mbist.l2t5_tcu_mbist_done
126 , mbist.l2t4_tcu_mbist_done
127 , mbist.l2t3_tcu_mbist_done
128 , mbist.l2t2_tcu_mbist_done
129 , mbist.l2t1_tcu_mbist_done
130 , mbist.l2t0_tcu_mbist_done
131 , mbist.l2b7_tcu_mbist_done
132 , mbist.l2b6_tcu_mbist_done
133 , mbist.l2b5_tcu_mbist_done
134 , mbist.l2b4_tcu_mbist_done
135 , mbist.l2b3_tcu_mbist_done
136 , mbist.l2b2_tcu_mbist_done
137 , mbist.l2b1_tcu_mbist_done
138 , mbist.l2b0_tcu_mbist_done
139 , mbist.mcu3_tcu_mbist_done
140 , mbist.mcu2_tcu_mbist_done
141 , mbist.mcu1_tcu_mbist_done
142 , mbist.mcu0_tcu_mbist_done
143 , mbist.ncu_tcu_mbist_done
144 , mbist.sio_tcu_mbist_done
145 , mbist.sii_tcu_mbist_done
146 , mbist.spc7_tcu_mbist_done
147 , mbist.spc6_tcu_mbist_done
148 , mbist.spc5_tcu_mbist_done
149 , mbist.spc4_tcu_mbist_done
150 , mbist.spc3_tcu_mbist_done
151 , mbist.spc2_tcu_mbist_done
152 , mbist.spc1_tcu_mbist_done
153 , mbist.spc0_tcu_mbist_done
154 };
155 mbist_fail
156 {
157 mbist.rdp_rdmc_tcu_mbist_fail
158 , mbist.rtx_rxc_ipp0_tcu_mbist_fail
159 , mbist.rtx_rxc_ipp1_tcu_mbist_fail
160 , mbist.rtx_rxc_mb5_tcu_mbist_fail
161 , mbist.rtx_rxc_mb6_tcu_mbist_fail
162 , mbist.rtx_rxc_zcp0_tcu_mbist_fail
163 , mbist.rtx_rxc_zcp1_tcu_mbist_fail
164 , mbist.rtx_txc_txe0_tcu_mbist_fail
165 , mbist.rtx_txc_txe1_tcu_mbist_fail
166 , mbist.tds_smx_tcu_mbist_fail
167 , mbist.tds_tdmc_tcu_mbist_fail
168 , mbist.peu_tcu_mbist_fail
169 , mbist.dmu_tcu_mbist_fail
170 , mbist.l2t7_tcu_mbist_fail
171 , mbist.l2t6_tcu_mbist_fail
172 , mbist.l2t5_tcu_mbist_fail
173 , mbist.l2t4_tcu_mbist_fail
174 , mbist.l2t3_tcu_mbist_fail
175 , mbist.l2t2_tcu_mbist_fail
176 , mbist.l2t1_tcu_mbist_fail
177 , mbist.l2t0_tcu_mbist_fail
178 , mbist.l2b7_tcu_mbist_fail
179 , mbist.l2b6_tcu_mbist_fail
180 , mbist.l2b5_tcu_mbist_fail
181 , mbist.l2b4_tcu_mbist_fail
182 , mbist.l2b3_tcu_mbist_fail
183 , mbist.l2b2_tcu_mbist_fail
184 , mbist.l2b1_tcu_mbist_fail
185 , mbist.l2b0_tcu_mbist_fail
186 , mbist.mcu3_tcu_mbist_fail
187 , mbist.mcu2_tcu_mbist_fail
188 , mbist.mcu1_tcu_mbist_fail
189 , mbist.mcu0_tcu_mbist_fail
190 , mbist.ncu_tcu_mbist_fail
191 , mbist.sio_tcu_mbist_fail
192 , mbist.sii_tcu_mbist_fail
193 , mbist.spc7_tcu_mbist_fail
194 , mbist.spc6_tcu_mbist_fail
195 , mbist.spc5_tcu_mbist_fail
196 , mbist.spc4_tcu_mbist_fail
197 , mbist.spc3_tcu_mbist_fail
198 , mbist.spc2_tcu_mbist_fail
199 , mbist.spc1_tcu_mbist_fail
200 , mbist.spc0_tcu_mbist_fail
201 };
202 mb_scan_en
203 {
204 mbist.tcu_spc7_scan_en
205 , mbist.tcu_spc6_scan_en
206 , mbist.tcu_spc5_scan_en
207 , mbist.tcu_spc4_scan_en
208 , mbist.tcu_spc3_scan_en
209 , mbist.tcu_spc2_scan_en
210 , mbist.tcu_spc1_scan_en
211 , mbist.tcu_spc0_scan_en
212 };
213 tcu_aclk
214 {
215 mbist.tcu_spc7_aclk
216 , mbist.tcu_spc6_aclk
217 , mbist.tcu_spc5_aclk
218 , mbist.tcu_spc4_aclk
219 , mbist.tcu_spc3_aclk
220 , mbist.tcu_spc2_aclk
221 , mbist.tcu_spc1_aclk
222 , mbist.tcu_spc0_aclk
223 };
224 tcu_bclk
225 {
226 mbist.tcu_spc7_bclk
227 , mbist.tcu_spc6_bclk
228 , mbist.tcu_spc5_bclk
229 , mbist.tcu_spc4_bclk
230 , mbist.tcu_spc3_bclk
231 , mbist.tcu_spc2_bclk
232 , mbist.tcu_spc1_bclk
233 , mbist.tcu_spc0_bclk
234 };
235 tcu_clk_stop
236 {
237 mbist.tcu_spc7_clk_stop
238 , mbist.tcu_spc6_clk_stop
239 , mbist.tcu_spc5_clk_stop
240 , mbist.tcu_spc4_clk_stop
241 , mbist.tcu_spc3_clk_stop
242 , mbist.tcu_spc2_clk_stop
243 , mbist.tcu_spc1_clk_stop
244 , mbist.tcu_spc0_clk_stop
245 };
246 tcu_scan_in
247 {
248 mbist.spc7_tcu_mbist_scan_in
249 , mbist.spc6_tcu_mbist_scan_in
250 , mbist.spc5_tcu_mbist_scan_in
251 , mbist.spc4_tcu_mbist_scan_in
252 , mbist.spc3_tcu_mbist_scan_in
253 , mbist.spc2_tcu_mbist_scan_in
254 , mbist.spc1_tcu_mbist_scan_in
255 , mbist.spc0_tcu_mbist_scan_in
256 };
257 tcu_scan_out
258 {
259 mbist.tcu_spc7_mbist_scan_out
260 , mbist.tcu_spc6_mbist_scan_out
261 , mbist.tcu_spc5_mbist_scan_out
262 , mbist.tcu_spc4_mbist_scan_out
263 , mbist.tcu_spc3_mbist_scan_out
264 , mbist.tcu_spc2_mbist_scan_out
265 , mbist.tcu_spc1_mbist_scan_out
266 , mbist.tcu_spc0_mbist_scan_out
267 };
268 tcu_soc_scan_in
269 {
270 mbist.rdp_rdmc_mbist_scan_out
271 , mbist.rtx_mbist_scan_out
272 , mbist.tds_mbist_scan_out
273 , mbist.peu_tcu_mbist_scan_out
274 , mbist.dmu_tcu_mbist_scan_out
275 , mbist.l2t7_tcu_mbist_scan_out
276 , mbist.l2t6_tcu_mbist_scan_out
277 , mbist.l2t5_tcu_mbist_scan_out
278 , mbist.l2t4_tcu_mbist_scan_out
279 , mbist.l2t3_tcu_mbist_scan_out
280 , mbist.l2t2_tcu_mbist_scan_out
281 , mbist.l2t1_tcu_mbist_scan_out
282 , mbist.l2t0_tcu_mbist_scan_out
283 , mbist.l2b7_tcu_mbist_scan_out
284 , mbist.l2b6_tcu_mbist_scan_out
285 , mbist.l2b5_tcu_mbist_scan_out
286 , mbist.l2b4_tcu_mbist_scan_out
287 , mbist.l2b3_tcu_mbist_scan_out
288 , mbist.l2b2_tcu_mbist_scan_out
289 , mbist.l2b1_tcu_mbist_scan_out
290 , mbist.l2b0_tcu_mbist_scan_out
291 , mbist.mcu3_tcu_mbist_scan_out
292 , mbist.mcu2_tcu_mbist_scan_out
293 , mbist.mcu1_tcu_mbist_scan_out
294 , mbist.mcu0_tcu_mbist_scan_out
295 , mbist.ncu_tcu_mbist_scan_out
296 , mbist.sio_tcu_mbist_scan_out
297 , mbist.sii_tcu_mbist_scan_out
298 };
299 tcu_soc_scan_out
300 {
301 mbist.rdp_rdmc_mbist_scan_in
302 , mbist.rtx_mbist_scan_in
303 , mbist.tds_mbist_scan_in
304 , mbist.tcu_peu_mbist_scan_in
305 , mbist.tcu_dmu_mbist_scan_in
306 , mbist.tcu_l2t7_mbist_scan_in
307 , mbist.tcu_l2t6_mbist_scan_in
308 , mbist.tcu_l2t5_mbist_scan_in
309 , mbist.tcu_l2t4_mbist_scan_in
310 , mbist.tcu_l2t3_mbist_scan_in
311 , mbist.tcu_l2t2_mbist_scan_in
312 , mbist.tcu_l2t1_mbist_scan_in
313 , mbist.tcu_l2t0_mbist_scan_in
314 , mbist.tcu_l2b7_mbist_scan_in
315 , mbist.tcu_l2b6_mbist_scan_in
316 , mbist.tcu_l2b5_mbist_scan_in
317 , mbist.tcu_l2b4_mbist_scan_in
318 , mbist.tcu_l2b3_mbist_scan_in
319 , mbist.tcu_l2b2_mbist_scan_in
320 , mbist.tcu_l2b1_mbist_scan_in
321 , mbist.tcu_l2b0_mbist_scan_in
322 , mbist.tcu_mcu3_mbist_scan_in
323 , mbist.tcu_mcu2_mbist_scan_in
324 , mbist.tcu_mcu1_mbist_scan_in
325 , mbist.tcu_mcu0_mbist_scan_in
326 , mbist.tcu_ncu_mbist_scan_in
327 , mbist.tcu_sio_mbist_scan_in
328 , mbist.tcu_sii_mbist_scan_in
329 };
330 tcu_niu_clk_stop
331 {
332 mbist.tcu_rdp_io_clk_stop
333 , mbist.tcu_rtx_io_clk_stop
334 , mbist.tcu_tds_io_clk_stop
335 };
336 tcu_dmu_io_clk_stop mbist.tcu_dmu_io_clk_stop;
337 tcu_peu_io_clk_stop mbist.tcu_peu_io_clk_stop;
338 tcu_l2t7_clk_stop mbist.tcu_l2t7_clk_stop;
339 tcu_l2t6_clk_stop mbist.tcu_l2t6_clk_stop;
340 tcu_l2t5_clk_stop mbist.tcu_l2t5_clk_stop;
341 tcu_l2t4_clk_stop mbist.tcu_l2t4_clk_stop;
342 tcu_l2t3_clk_stop mbist.tcu_l2t3_clk_stop;
343 tcu_l2t2_clk_stop mbist.tcu_l2t2_clk_stop;
344 tcu_l2t1_clk_stop mbist.tcu_l2t1_clk_stop;
345 tcu_l2t0_clk_stop mbist.tcu_l2t0_clk_stop;
346 tcu_l2b7_clk_stop mbist.tcu_l2b7_clk_stop;
347 tcu_l2b6_clk_stop mbist.tcu_l2b6_clk_stop;
348 tcu_l2b5_clk_stop mbist.tcu_l2b5_clk_stop;
349 tcu_l2b4_clk_stop mbist.tcu_l2b4_clk_stop;
350 tcu_l2b3_clk_stop mbist.tcu_l2b3_clk_stop;
351 tcu_l2b2_clk_stop mbist.tcu_l2b2_clk_stop;
352 tcu_l2b1_clk_stop mbist.tcu_l2b1_clk_stop;
353 tcu_l2b0_clk_stop mbist.tcu_l2b0_clk_stop;
354 tcu_mcu3_clk_stop mbist.tcu_mcu3_clk_stop;
355 tcu_mcu2_clk_stop mbist.tcu_mcu2_clk_stop;
356 tcu_mcu1_clk_stop mbist.tcu_mcu1_clk_stop;
357 tcu_mcu0_clk_stop mbist.tcu_mcu0_clk_stop;
358 tcu_soc_clk_stop
359 {
360 mbist.tcu_ncu_clk_stop
361 , mbist.tcu_sio_clk_stop
362 , mbist.tcu_sii_clk_stop
363 };
364
365 tcu_peu_pc_clk_stop mbist.tcu_peu_pc_clk_stop;
366 tcu_mcu0_dr_clk_stop mbist.tcu_mcu0_dr_clk_stop;
367 tcu_mcu0_io_clk_stop mbist.tcu_mcu0_io_clk_stop;
368 tcu_mcu0_fbd_clk_stop mbist.tcu_mcu0_fbd_clk_stop;
369 tcu_mcu1_dr_clk_stop mbist.tcu_mcu1_dr_clk_stop;
370 tcu_mcu1_io_clk_stop mbist.tcu_mcu1_io_clk_stop;
371 tcu_mcu1_fbd_clk_stop mbist.tcu_mcu1_fbd_clk_stop;
372 tcu_mcu2_dr_clk_stop mbist.tcu_mcu2_dr_clk_stop;
373 tcu_mcu2_io_clk_stop mbist.tcu_mcu2_io_clk_stop;
374 tcu_mcu2_fbd_clk_stop mbist.tcu_mcu2_fbd_clk_stop;
375 tcu_mcu3_dr_clk_stop mbist.tcu_mcu3_dr_clk_stop;
376 tcu_mcu3_io_clk_stop mbist.tcu_mcu3_io_clk_stop;
377 tcu_mcu3_fbd_clk_stop mbist.tcu_mcu3_fbd_clk_stop;
378
379 tcu_ncu_io_clk_stop mbist.tcu_ncu_io_clk_stop;
380 tcu_sio_io_clk_stop mbist.tcu_sio_io_clk_stop;
381 tcu_sii_io_clk_stop mbist.tcu_sii_io_clk_stop;
382
383 tcu_soc_aclk mbist.tcu_aclk;
384 tcu_soc_bclk mbist.tcu_bclk;
385 tcu_soc_scan_en mbist.tcu_scan_en;
386 tcu_spc_mbist_start mbist.tcu_spc_mbist_start;
387 tcu_mbist_bisi_en mbist.tcu_mbist_bisi_en;
388
389 tcu_mio_mbist_fail mbist.tcu_mio_mbist_fail;
390 tcu_mio_mbist_done mbist.tcu_mio_mbist_done;
391 pin_mbist_fail mbist.DBG_DQ[0];
392 pin_mbist_done mbist.DBG_DQ[1];
393#ifdef FC_SCAN_BENCH
394 mbist_l2tag_read_l2t0 mbist.mbist_l2tag_read_l2t0;
395#endif //FC_SCAN_BENCH
396 bisx_counter mbist.bisx_counter;
397}
398
399bind lbist__port lbist_bind {
400 clk lbist.clk;
401 lbist_start lbist.lbist_start;
402 lbist_scan_in lbist.lbist_scan_in;
403 lbist_pgm lbist.lbist_pgm;
404 test_mode lbist.test_mode;
405 lbist_done
406 {
407 lbist.spc7_tcu_lbist_done
408 , lbist.spc6_tcu_lbist_done
409 , lbist.spc5_tcu_lbist_done
410 , lbist.spc4_tcu_lbist_done
411 , lbist.spc3_tcu_lbist_done
412 , lbist.spc2_tcu_lbist_done
413 , lbist.spc1_tcu_lbist_done
414 , lbist.spc0_tcu_lbist_done
415 };
416 lbist_scan_out
417 {
418 lbist.spc7_tcu_lbist_scan_out
419 , lbist.spc6_tcu_lbist_scan_out
420 , lbist.spc5_tcu_lbist_scan_out
421 , lbist.spc4_tcu_lbist_scan_out
422 , lbist.spc3_tcu_lbist_scan_out
423 , lbist.spc2_tcu_lbist_scan_out
424 , lbist.spc1_tcu_lbist_scan_out
425 , lbist.spc0_tcu_lbist_scan_out
426 };
427}
428
429bind scan__port scan_bind {
430 tck scan.TCK;
431 ac_test_mode void; // scan.AC_TEST_MODE; // moved it to pkg.*.vri
432 //srdes_scancfg scan.SRDES_SCANCFG;
433 //tcu_srdes_scancfg scan.tcu_srdes_scancfg;
434 //tcu_pllbypass scan.tcu_pllbypass;
435 scan_en void; // scan.SCAN_EN; // moved it to pkg.*.vri
436 tcu_scan_en scan.tcu_scan_en;
437 tcu_se_scancollar_in scan.tcu_se_scancollar_in;
438 tcu_se_scancollar_out scan.tcu_se_scancollar_out;
439 tcu_array_wr_inhibit scan.tcu_array_wr_inhibit;
440 tcu_array_bypass scan.tcu_array_bypass;
441 tcu_dectest scan.tcu_dectest;
442 tcu_muxtest scan.tcu_muxtest;
443 tcu_aclk scan.tcu_aclk;
444 tcu_bclk scan.tcu_bclk;
445 pscan_si void; // scan.SCAN_IN; // moved it to pkg.*.vri
446 pscan_so
447 {
448 scan.SCAN_OUT31
449 , scan.SCAN_OUT30_0
450 };
451 jtag_si
452 {
453 //scan.srdes_tcu_scan_in
454 scan.soc6_tcu_scan_in
455 , scan.soc5_tcu_scan_in
456 , scan.soc4_tcu_scan_in
457 , scan.soc3_tcu_scan_in
458 , scan.soc2_tcu_scan_in
459 , scan.soc1_tcu_scan_in
460 , scan.soc0_tcu_scan_in
461 , scan.soch_tcu_scan_in
462 , scan.socg_tcu_scan_in
463 , scan.socf_tcu_scan_in
464 , scan.soce_tcu_scan_in
465 , scan.socd_tcu_scan_in
466 , scan.socc_tcu_scan_in
467 , scan.socb_tcu_scan_in
468 , scan.soca_tcu_scan_in
469 , scan.spc7_tcu_scan_in[1]
470 , scan.spc7_tcu_scan_in[0]
471 , scan.spc6_tcu_scan_in[1]
472 , scan.spc6_tcu_scan_in[0]
473 , scan.spc5_tcu_scan_in[1]
474 , scan.spc5_tcu_scan_in[0]
475 , scan.spc4_tcu_scan_in[1]
476 , scan.spc4_tcu_scan_in[0]
477 , scan.spc3_tcu_scan_in[1]
478 , scan.spc3_tcu_scan_in[0]
479 , scan.spc2_tcu_scan_in[1]
480 , scan.spc2_tcu_scan_in[0]
481 , scan.spc1_tcu_scan_in[1]
482 , scan.spc1_tcu_scan_in[0]
483 , scan.spc0_tcu_scan_in[1]
484 , scan.spc0_tcu_scan_in[0]
485 };
486 jtag_so
487 {
488 //scan.tcu_srdes_scan_out
489 scan.tcu_soc6_scan_out
490 ,scan.tcu_soc5_scan_out
491 ,scan.tcu_soc4_scan_out
492 ,scan.tcu_soc3_scan_out
493 ,scan.tcu_soc2_scan_out
494 ,scan.tcu_soc1_scan_out
495 ,scan.tcu_soc0_scan_out
496 ,scan.tcu_soch_scan_out
497 ,scan.tcu_socg_scan_out
498 ,scan.tcu_socf_scan_out
499 ,scan.tcu_soce_scan_out
500 ,scan.tcu_socd_scan_out
501 ,scan.tcu_socc_scan_out
502 ,scan.tcu_socb_scan_out
503 ,scan.tcu_soca_scan_out
504 ,scan.tcu_spc7_scan_out[1]
505 ,scan.tcu_spc7_scan_out[0]
506 ,scan.tcu_spc6_scan_out[1]
507 ,scan.tcu_spc6_scan_out[0]
508 ,scan.tcu_spc5_scan_out[1]
509 ,scan.tcu_spc5_scan_out[0]
510 ,scan.tcu_spc4_scan_out[1]
511 ,scan.tcu_spc4_scan_out[0]
512 ,scan.tcu_spc3_scan_out[1]
513 ,scan.tcu_spc3_scan_out[0]
514 ,scan.tcu_spc2_scan_out[1]
515 ,scan.tcu_spc2_scan_out[0]
516 ,scan.tcu_spc1_scan_out[1]
517 ,scan.tcu_spc1_scan_out[0]
518 ,scan.tcu_spc0_scan_out[1]
519 ,scan.tcu_spc0_scan_out[1]
520 };
521}
522
523bind efuse__port efuse_bind {
524 tck efuse.TCK;
525 efuse_rowaddr efuse.tcu_efu_rowaddr;
526 efuse_coladdr efuse.tcu_efu_coladdr;
527 efuse_read_en efuse.tcu_efu_read_en;
528 efuse_read_mode efuse.tcu_efu_read_mode;
529 efuse_read_start efuse.tcu_efu_read_start;
530 efuse_fuse_bypass efuse.tcu_efu_fuse_bypass;
531 efuse_dest_sample efuse.tcu_efu_dest_sample;
532 efuse_updatedr efuse.tcu_efu_updatedr;
533 efuse_shiftdr efuse.tcu_efu_shiftdr;
534 efuse_capturedr efuse.tcu_efu_capturedr;
535 efuse_sbc_efa_bit_addr efuse.sbc_efa_bit_addr;
536 efuse_sbc_efa_word_addr efuse.sbc_efa_word_addr;
537 efuse_sbc_efa_margin0_rd efuse.sbc_efa_margin0_rd;
538 efuse_sbc_efa_margin1_rd efuse.sbc_efa_margin1_rd;
539 efuse_sbc_efa_power_down efuse.sbc_efa_power_down;
540 efuse_pwr_ok efuse.pwr_ok;
541 efuse_por_l efuse.por_l;
542 efuse_pi_efa_prog_en efuse.pi_efa_prog_en;
543 efuse_vpp efuse.vpp;
544 efuse_efuse_row efuse.efuse_row;
545 efuse_por_n efuse.por_n;
546 efuse_sbc_efa_read_en efuse.sbc_efa_read_en;
547 efuse_efa_read_data efuse.efa_read_data;
548 efuse_efa_out_data efuse.efa_out_data;
549 efuse_read_data_ff efuse.read_data_ff;
550 efuse_tck_shft_data_ff efuse.tck_shft_data_ff;
551 efuse_io_vpp efuse.io_vpp;
552 efuse_io_pgrm_en efuse.io_pgrm_en;
553 efu_ncu_coreavl_xfer_en efuse.efu_ncu_coreavl_xfer_en;
554 efu_ncu_bankavl_xfer_en efuse.efu_ncu_bankavl_xfer_en;
555 efu_l2b1_fuse_xfer_en efuse.efu_l2b1_fuse_xfer_en;
556 efu_l2t1_fuse_xfer_en efuse.efu_l2t1_fuse_xfer_en;
557 efu_ncu_srlnum1_xfer_en efuse.efu_ncu_srlnum1_xfer_en;
558 efu_niu_4k_xfer_en efuse.efu_niu_4k_xfer_en;
559 efu_spc1_fuse_dxfer_en efuse.efu_spc1_fuse_dxfer_en;
560 efu_spc1_fuse_ixfer_en efuse.efu_spc1_fuse_ixfer_en;
561 efu_dmu_xfer_en efuse.efu_dmu_xfer_en;
562 efuse_xfer_en
563 {
564 efuse.efu_dmu_xfer_en
565 , efuse.efu_niu_ram_xfer_en
566 , efuse.efu_niu_4k_xfer_en
567 , efuse.efu_niu_ram1_xfer_en
568 , efuse.efu_niu_ram0_xfer_en
569 , efuse.efu_niu_cfifo1_xfer_en
570 , efuse.efu_niu_cfifo0_xfer_en
571 , efuse.efu_niu_ipp1_xfer_en
572 , efuse.efu_niu_ipp0_xfer_en
573 , efuse.efu_niu_mac0_ro_xfer_en
574 , efuse.efu_niu_mac0_sf_xfer_en
575 , efuse.efu_niu_mac1_ro_xfer_en
576 , efuse.efu_niu_mac1_sf_xfer_en
577 , efuse.efu_ncu_srlnum2_xfer_en
578 , efuse.efu_ncu_srlnum1_xfer_en
579 , efuse.efu_ncu_srlnum0_xfer_en
580 , efuse.efu_ncu_bankavl_xfer_en
581 , efuse.efu_ncu_coreavl_xfer_en
582 , efuse.efu_l2d7_fuse_xfer_en
583 , efuse.efu_l2d6_fuse_xfer_en
584 , efuse.efu_l2d5_fuse_xfer_en
585 , efuse.efu_l2d4_fuse_xfer_en
586 , efuse.efu_l2d3_fuse_xfer_en
587 , efuse.efu_l2d2_fuse_xfer_en
588 , efuse.efu_l2d1_fuse_xfer_en
589 , efuse.efu_l2d0_fuse_xfer_en
590 , efuse.efu_l2t7_fuse_xfer_en
591 , efuse.efu_l2t6_fuse_xfer_en
592 , efuse.efu_l2t5_fuse_xfer_en
593 , efuse.efu_l2t4_fuse_xfer_en
594 , efuse.efu_l2t3_fuse_xfer_en
595 , efuse.efu_l2t2_fuse_xfer_en
596 , efuse.efu_l2t1_fuse_xfer_en
597 , efuse.efu_l2t0_fuse_xfer_en
598 , efuse.efu_spc7_fuse_dxfer_en
599 , efuse.efu_spc7_fuse_ixfer_en
600 , efuse.efu_spc6_fuse_dxfer_en
601 , efuse.efu_spc6_fuse_ixfer_en
602 , efuse.efu_spc5_fuse_dxfer_en
603 , efuse.efu_spc5_fuse_ixfer_en
604 , efuse.efu_spc4_fuse_dxfer_en
605 , efuse.efu_spc4_fuse_ixfer_en
606 , efuse.efu_spc3_fuse_dxfer_en
607 , efuse.efu_spc3_fuse_ixfer_en
608 , efuse.efu_spc2_fuse_dxfer_en
609 , efuse.efu_spc2_fuse_ixfer_en
610 , efuse.efu_spc1_fuse_dxfer_en
611 , efuse.efu_spc1_fuse_ixfer_en
612 , efuse.efu_spc0_fuse_dxfer_en
613 , efuse.efu_spc0_fuse_ixfer_en
614 };
615 dest_efu_xfer_en
616 {
617 efuse.dmu_efu_xfer_en
618 , efuse.niu_efu_ram_xfer_en
619 , efuse.niu_efu_4k_xfer_en
620 , efuse.niu_efu_ram1_xfer_en
621 , efuse.niu_efu_ram0_xfer_en
622 , efuse.niu_efu_cfifo1_xfer_en
623 , efuse.niu_efu_cfifo0_xfer_en
624 , efuse.niu_efu_ipp1_xfer_en
625 , efuse.niu_efu_ipp0_xfer_en
626 , efuse.niu_efu_mac0_ro_xfer_en
627 , efuse.niu_efu_mac0_sf_xfer_en
628 , efuse.niu_efu_mac1_ro_xfer_en
629 , efuse.niu_efu_mac1_sf_xfer_en
630 , efuse.l2d7_efu_fuse_xfer_en
631 , efuse.l2d6_efu_fuse_xfer_en
632 , efuse.l2d5_efu_fuse_xfer_en
633 , efuse.l2d4_efu_fuse_xfer_en
634 , efuse.l2d3_efu_fuse_xfer_en
635 , efuse.l2d2_efu_fuse_xfer_en
636 , efuse.l2d1_efu_fuse_xfer_en
637 , efuse.l2d0_efu_fuse_xfer_en
638 , efuse.l2t7_efu_fuse_xfer_en
639 , efuse.l2t6_efu_fuse_xfer_en
640 , efuse.l2t5_efu_fuse_xfer_en
641 , efuse.l2t4_efu_fuse_xfer_en
642 , efuse.l2t3_efu_fuse_xfer_en
643 , efuse.l2t2_efu_fuse_xfer_en
644 , efuse.l2t1_efu_fuse_xfer_en
645 , efuse.l2t0_efu_fuse_xfer_en
646 , efuse.spc7_efu_fuse_dxfer_en
647 , efuse.spc7_efu_fuse_ixfer_en
648 , efuse.spc6_efu_fuse_dxfer_en
649 , efuse.spc6_efu_fuse_ixfer_en
650 , efuse.spc5_efu_fuse_dxfer_en
651 , efuse.spc5_efu_fuse_ixfer_en
652 , efuse.spc4_efu_fuse_dxfer_en
653 , efuse.spc4_efu_fuse_ixfer_en
654 , efuse.spc3_efu_fuse_dxfer_en
655 , efuse.spc3_efu_fuse_ixfer_en
656 , efuse.spc2_efu_fuse_dxfer_en
657 , efuse.spc2_efu_fuse_ixfer_en
658 , efuse.spc1_efu_fuse_dxfer_en
659 , efuse.spc1_efu_fuse_ixfer_en
660 , efuse.spc0_efu_fuse_dxfer_en
661 , efuse.spc0_efu_fuse_ixfer_en
662 };
663 efu_rv_clr
664 {
665 efuse_gclk_if.efu_niu_fclrz
666 , efuse_gclk_if.efu_psr_fclrz
667 , efuse_gclk_if.efu_mcu_fclrz
668 , efuse_gclk_if.efu_dmu_clr
669 , efuse_gclk_if.efu_niu_ipp0_clr
670 , efuse_gclk_if.efu_niu_ipp1_clr
671 , efuse_gclk_if.efu_niu_mac0_ro_clr
672 , efuse_gclk_if.efu_niu_mac0_sf_clr
673 , efuse_gclk_if.efu_niu_mac1_ro_clr
674 , efuse_gclk_if.efu_niu_mac1_sf_clr
675 , efuse_gclk_if.efu_niu_cfifo0_clr
676 , efuse_gclk_if.efu_niu_cfifo1_clr
677 , efuse_gclk_if.efu_niu_ram1_clr
678 , efuse_gclk_if.efu_niu_ram0_clr
679 , efuse_gclk_if.efu_niu_ram_clr
680 , efuse_gclk_if.efu_niu_4k_clr
681 , efuse_gclk_if.efu_l2b7_fuse_clr
682 , efuse_gclk_if.efu_l2b6_fuse_clr
683 , efuse_gclk_if.efu_l2b5_fuse_clr
684 , efuse_gclk_if.efu_l2b4_fuse_clr
685 , efuse_gclk_if.efu_l2b3_fuse_clr
686 , efuse_gclk_if.efu_l2b2_fuse_clr
687 , efuse_gclk_if.efu_l2b1_fuse_clr
688 , efuse_gclk_if.efu_l2b0_fuse_clr
689 , efuse_gclk_if.efu_l2t7_fuse_clr
690 , efuse_gclk_if.efu_l2t6_fuse_clr
691 , efuse_gclk_if.efu_l2t5_fuse_clr
692 , efuse_gclk_if.efu_l2t4_fuse_clr
693 , efuse_gclk_if.efu_l2t3_fuse_clr
694 , efuse_gclk_if.efu_l2t2_fuse_clr
695 , efuse_gclk_if.efu_l2t1_fuse_clr
696 , efuse_gclk_if.efu_l2t0_fuse_clr
697 , efuse_gclk_if.efu_spc7_fuse_dclr
698 , efuse_gclk_if.efu_spc7_fuse_iclr
699 , efuse_gclk_if.efu_spc6_fuse_dclr
700 , efuse_gclk_if.efu_spc6_fuse_iclr
701 , efuse_gclk_if.efu_spc5_fuse_dclr
702 , efuse_gclk_if.efu_spc5_fuse_iclr
703 , efuse_gclk_if.efu_spc4_fuse_dclr
704 , efuse_gclk_if.efu_spc4_fuse_iclr
705 , efuse_gclk_if.efu_spc3_fuse_dclr
706 , efuse_gclk_if.efu_spc3_fuse_iclr
707 , efuse_gclk_if.efu_spc2_fuse_dclr
708 , efuse_gclk_if.efu_spc2_fuse_iclr
709 , efuse_gclk_if.efu_spc1_fuse_dclr
710 , efuse_gclk_if.efu_spc1_fuse_iclr
711 , efuse_gclk_if.efu_spc0_fuse_dclr
712 , efuse_gclk_if.efu_spc0_fuse_iclr
713 };
714 VPP efuse.VPP;
715 PGRM_EN efuse.PGRM_EN;
716 coreavail efuse.coreavail;
717 bankavail efuse.bankavail;
718 sernum0 efuse.sernum0;
719 sernum1 efuse.sernum1;
720 sernum2 efuse.sernum2;
721 fusestat efuse.creg_fusestat;
722 efcnt_dout efuse.efcnt_dout;
723 efu_done_int efuse.efu_done_int;
724 }
725
726#ifndef FC_SCAN_BENCH
727bind cmp__port cmp_bind {
728 clk cmp_spc.CLK;
729 tb_fusedata_init cmp_spc.tb_fusedata_init;
730 core_available_array
731 {
732 cmp_spc.core_available_7
733 ,cmp_spc.core_available_6
734 ,cmp_spc.core_available_5
735 ,cmp_spc.core_available_4
736 ,cmp_spc.core_available_3
737 ,cmp_spc.core_available_2
738 ,cmp_spc.core_available_1
739 ,cmp_spc.core_available_0
740 };
741 core_enable_status_array
742 {
743 cmp_spc.core_enable_status_7
744 ,cmp_spc.core_enable_status_6
745 ,cmp_spc.core_enable_status_5
746 ,cmp_spc.core_enable_status_4
747 ,cmp_spc.core_enable_status_3
748 ,cmp_spc.core_enable_status_2
749 ,cmp_spc.core_enable_status_1
750 ,cmp_spc.core_enable_status_0
751 };
752 core_running_array
753 {
754 cmp_spc.core_running_7
755 ,cmp_spc.core_running_6
756 ,cmp_spc.core_running_5
757 ,cmp_spc.core_running_4
758 ,cmp_spc.core_running_3
759 ,cmp_spc.core_running_2
760 ,cmp_spc.core_running_1
761 ,cmp_spc.core_running_0
762 };
763 core_running_status_array
764 {
765 cmp_spc.core_running_status_7
766 ,cmp_spc.core_running_status_6
767 ,cmp_spc.core_running_status_5
768 ,cmp_spc.core_running_status_4
769 ,cmp_spc.core_running_status_3
770 ,cmp_spc.core_running_status_2
771 ,cmp_spc.core_running_status_1
772 ,cmp_spc.core_running_status_0
773 };
774}
775
776bind ncu_sck__port ncu_sck_bind {
777 sck_cnt ncu_sck.sck_cnt;
778}
779
780bind spc_debug__port spc_debug_bind {
781 clk spc_debug.CLK;
782 tcu_ss_mode spc_debug.tcu_ss_mode;
783 tcu_do_mode spc_debug.tcu_do_mode;
784 tcu_ss_request spc_debug.tcu_ss_request;
785 core_running
786 {
787 spc_debug.ncu_spc7_core_running,
788 spc_debug.ncu_spc6_core_running,
789 spc_debug.ncu_spc5_core_running,
790 spc_debug.ncu_spc4_core_running,
791 spc_debug.ncu_spc3_core_running,
792 spc_debug.ncu_spc2_core_running,
793 spc_debug.ncu_spc1_core_running,
794 spc_debug.ncu_spc0_core_running
795 };
796 ss_complete
797 {
798 spc_debug.spc7_ss_complete,
799 spc_debug.spc6_ss_complete,
800 spc_debug.spc5_ss_complete,
801 spc_debug.spc4_ss_complete,
802 spc_debug.spc3_ss_complete,
803 spc_debug.spc2_ss_complete,
804 spc_debug.spc1_ss_complete,
805 spc_debug.spc0_ss_complete
806 };
807 core_running_status
808 {
809 spc_debug.spc7_ncu_core_running_status,
810 spc_debug.spc6_ncu_core_running_status,
811 spc_debug.spc5_ncu_core_running_status,
812 spc_debug.spc4_ncu_core_running_status,
813 spc_debug.spc3_ncu_core_running_status,
814 spc_debug.spc2_ncu_core_running_status,
815 spc_debug.spc1_ncu_core_running_status,
816 spc_debug.spc0_ncu_core_running_status
817 };
818}
819
820bind tcu_siu__port tcu_siu_bind {
821 clk tcu_siu.CLK;
822 tcu_sii_data tcu_siu.tcu_sii_data;
823 tcu_sii_vld tcu_siu.tcu_sii_vld;
824 sio_tcu_data tcu_siu.sio_tcu_data;
825 sio_tcu_vld tcu_siu.sio_tcu_vld;
826 sio_tcu_data__in tcu_siu.sio_tcu_data__in;
827 sio_tcu_vld__in tcu_siu.sio_tcu_vld__in;
828}
829#endif //FC_SCAN_BENCH
830
831bind jt_scan_clk__port jt_scan_clk_bind {
832 jt_scan_aclk jt_sy_clk.jt_scan_aclk;
833 jt_scan_bclk jt_sy_clk.jt_scan_bclk;
834 io_test_mode jt_sy_clk.io_test_mode;
835 mtaccess jt_sy_clk.mtaccess;
836#ifndef TCU_GATE
837 instr_ser_scan jt_sy_clk.instr_ser_scan;
838#endif
839 jt_scan_en jt_sy_clk.jt_scan_en;
840 tcu_asic_array_wr_inhibit jt_sy_clk.tcu_asic_array_wr_inhibit;
841 tcu_spc0_array_wr_inhibit jt_sy_clk.tcu_spc0_array_wr_inhibit;
842 tcu_spc1_array_wr_inhibit jt_sy_clk.tcu_spc1_array_wr_inhibit;
843 tcu_spc2_array_wr_inhibit jt_sy_clk.tcu_spc2_array_wr_inhibit;
844 tcu_spc3_array_wr_inhibit jt_sy_clk.tcu_spc3_array_wr_inhibit;
845 tcu_spc4_array_wr_inhibit jt_sy_clk.tcu_spc4_array_wr_inhibit;
846 tcu_spc5_array_wr_inhibit jt_sy_clk.tcu_spc5_array_wr_inhibit;
847 tcu_spc6_array_wr_inhibit jt_sy_clk.tcu_spc6_array_wr_inhibit;
848 tcu_spc7_array_wr_inhibit jt_sy_clk.tcu_spc7_array_wr_inhibit;
849}
850
851bind shscan__port shscan_bind {
852 tck shscan.TCK;
853 shscan_spc_aclk shscan.tcu_spc_shscan_aclk;
854 shscan_spc_bclk shscan.tcu_spc_shscan_bclk;
855 shscan_spc_se shscan.tcu_spc_shscan_scan_en;
856 shscan_spc_pce_ov shscan.tcu_spc_shscan_pce_ov;
857 shscan_spc_shscanid shscan.tcu_spc_shscanid;
858 shscan_spc_clk_stop
859 {
860 shscan.tcu_spc0_shscan_clk_stop
861 , shscan.tcu_spc1_shscan_clk_stop
862 , shscan.tcu_spc2_shscan_clk_stop
863 , shscan.tcu_spc3_shscan_clk_stop
864 , shscan.tcu_spc4_shscan_clk_stop
865 , shscan.tcu_spc5_shscan_clk_stop
866 , shscan.tcu_spc6_shscan_clk_stop
867 , shscan.tcu_spc7_shscan_clk_stop
868 };
869 shscan_l2t_aclk shscan.tcu_l2t_shscan_aclk;
870 shscan_l2t_bclk shscan.tcu_l2t_shscan_bclk;
871 shscan_l2t_se shscan.tcu_l2t_shscan_scan_en;
872 shscan_l2t_pce_ov shscan.tcu_l2t_shscan_pce_ov;
873 shscan_l2t_clk_stop
874 {
875 shscan.tcu_l2t0_shscan_clk_stop
876 , shscan.tcu_l2t1_shscan_clk_stop
877 , shscan.tcu_l2t2_shscan_clk_stop
878 , shscan.tcu_l2t3_shscan_clk_stop
879 , shscan.tcu_l2t4_shscan_clk_stop
880 , shscan.tcu_l2t5_shscan_clk_stop
881 , shscan.tcu_l2t6_shscan_clk_stop
882 , shscan.tcu_l2t7_shscan_clk_stop
883 };
884 spc_tcu_shscan_scan_in
885 {
886 shscan.spc7_tcu_shscan_scan_in
887 , shscan.spc6_tcu_shscan_scan_in
888 , shscan.spc5_tcu_shscan_scan_in
889 , shscan.spc4_tcu_shscan_scan_in
890 , shscan.spc3_tcu_shscan_scan_in
891 , shscan.spc2_tcu_shscan_scan_in
892 , shscan.spc1_tcu_shscan_scan_in
893 , shscan.spc0_tcu_shscan_scan_in
894 };
895 tcu_spc_shscan_scan_out
896 {
897 shscan.tcu_spc7_shscan_scan_out
898 , shscan.tcu_spc6_shscan_scan_out
899 , shscan.tcu_spc5_shscan_scan_out
900 , shscan.tcu_spc4_shscan_scan_out
901 , shscan.tcu_spc3_shscan_scan_out
902 , shscan.tcu_spc2_shscan_scan_out
903 , shscan.tcu_spc1_shscan_scan_out
904 , shscan.tcu_spc0_shscan_scan_out
905 };
906
907}
908
909bind TCU_rst_port tcu_rst_bind {
910 l2clk tcu_rst_if.l2clk;
911 PWRON_RST_L tcu_rst_if.PWRON_RST_L;
912 tcu_por_reset tcu_rst_if.tcu_por_reset;
913 rst_tcu_asicflush_stop_req tcu_rst_if.rst_tcu_asicflush_stop_req;
914 tcu_rst_asicflush_stop_ack tcu_rst_if.tcu_rst_asicflush_stop_ack;
915 rst_tcu_flush_init_req tcu_rst_if.rst_tcu_flush_init_req;
916 tcu_rst_flush_init_ack tcu_rst_if.tcu_rst_flush_init_ack;
917 rst_tcu_flush_stop_req tcu_rst_if.rst_tcu_flush_stop_req;
918 tcu_rst_flush_stop_ack tcu_rst_if.tcu_rst_flush_stop_ack;
919 tcu_efu_read_start tcu_rst_if.tcu_efu_read_start;
920 tcu_rst_efu_done tcu_rst_if.tcu_rst_efu_done;
921 rst_ncu_unpark_thread tcu_rst_if.rst_ncu_unpark_thread;
922}
923
924bind TCU_corebank_port tcu_corebank_bind {
925 l2clk tcu_corebank_if.l2clk;
926 core_available tcu_corebank_if.core_available;
927 core_enable tcu_corebank_if.core_enable;
928 bank_available tcu_corebank_if.bank_available;
929 bank_enable tcu_corebank_if.bank_enable;
930}
931
932bind TCU_clkstop_port tcu_clkstop_bind {
933 clk tcu_clkstop_if.clk;
934
935 spc_clkstop {
936 tcu_clkstop_if.tcu_spc7_clk_stop,
937 tcu_clkstop_if.tcu_spc6_clk_stop,
938 tcu_clkstop_if.tcu_spc5_clk_stop,
939 tcu_clkstop_if.tcu_spc4_clk_stop,
940 tcu_clkstop_if.tcu_spc3_clk_stop,
941 tcu_clkstop_if.tcu_spc2_clk_stop,
942 tcu_clkstop_if.tcu_spc1_clk_stop,
943 tcu_clkstop_if.tcu_spc0_clk_stop
944 };
945 spc_shscan_clkstop {
946 tcu_clkstop_if.tcu_spc7_shscan_clk_stop,
947 tcu_clkstop_if.tcu_spc6_shscan_clk_stop,
948 tcu_clkstop_if.tcu_spc5_shscan_clk_stop,
949 tcu_clkstop_if.tcu_spc4_shscan_clk_stop,
950 tcu_clkstop_if.tcu_spc3_shscan_clk_stop,
951 tcu_clkstop_if.tcu_spc2_shscan_clk_stop,
952 tcu_clkstop_if.tcu_spc1_shscan_clk_stop,
953 tcu_clkstop_if.tcu_spc0_shscan_clk_stop
954 };
955 l2b_clkstop {
956 tcu_clkstop_if.tcu_l2b7_clk_stop,
957 tcu_clkstop_if.tcu_l2b6_clk_stop,
958 tcu_clkstop_if.tcu_l2b5_clk_stop,
959 tcu_clkstop_if.tcu_l2b4_clk_stop,
960 tcu_clkstop_if.tcu_l2b3_clk_stop,
961 tcu_clkstop_if.tcu_l2b2_clk_stop,
962 tcu_clkstop_if.tcu_l2b1_clk_stop,
963 tcu_clkstop_if.tcu_l2b0_clk_stop
964 };
965 l2d_clkstop {
966 tcu_clkstop_if.tcu_l2d7_clk_stop,
967 tcu_clkstop_if.tcu_l2d6_clk_stop,
968 tcu_clkstop_if.tcu_l2d5_clk_stop,
969 tcu_clkstop_if.tcu_l2d4_clk_stop,
970 tcu_clkstop_if.tcu_l2d3_clk_stop,
971 tcu_clkstop_if.tcu_l2d2_clk_stop,
972 tcu_clkstop_if.tcu_l2d1_clk_stop,
973 tcu_clkstop_if.tcu_l2d0_clk_stop
974 };
975 l2t_clkstop {
976 tcu_clkstop_if.tcu_l2t7_clk_stop,
977 tcu_clkstop_if.tcu_l2t6_clk_stop,
978 tcu_clkstop_if.tcu_l2t5_clk_stop,
979 tcu_clkstop_if.tcu_l2t4_clk_stop,
980 tcu_clkstop_if.tcu_l2t3_clk_stop,
981 tcu_clkstop_if.tcu_l2t2_clk_stop,
982 tcu_clkstop_if.tcu_l2t1_clk_stop,
983 tcu_clkstop_if.tcu_l2t0_clk_stop
984 };
985 l2t_shscan_clkstop {
986 tcu_clkstop_if.tcu_l2t7_shscan_clk_stop,
987 tcu_clkstop_if.tcu_l2t6_shscan_clk_stop,
988 tcu_clkstop_if.tcu_l2t5_shscan_clk_stop,
989 tcu_clkstop_if.tcu_l2t4_shscan_clk_stop,
990 tcu_clkstop_if.tcu_l2t3_shscan_clk_stop,
991 tcu_clkstop_if.tcu_l2t2_shscan_clk_stop,
992 tcu_clkstop_if.tcu_l2t1_shscan_clk_stop,
993 tcu_clkstop_if.tcu_l2t0_shscan_clk_stop
994 };
995 mcu_clkstop {
996 tcu_clkstop_if.tcu_mcu3_clk_stop,
997 tcu_clkstop_if.tcu_mcu2_clk_stop,
998 tcu_clkstop_if.tcu_mcu1_clk_stop,
999 tcu_clkstop_if.tcu_mcu0_clk_stop
1000 };
1001 mcu_dr_clkstop {
1002 tcu_clkstop_if.tcu_mcu3_dr_clk_stop,
1003 tcu_clkstop_if.tcu_mcu2_dr_clk_stop,
1004 tcu_clkstop_if.tcu_mcu1_dr_clk_stop,
1005 tcu_clkstop_if.tcu_mcu0_dr_clk_stop
1006 };
1007 mcu_io_clkstop {
1008 tcu_clkstop_if.tcu_mcu3_io_clk_stop,
1009 tcu_clkstop_if.tcu_mcu2_io_clk_stop,
1010 tcu_clkstop_if.tcu_mcu1_io_clk_stop,
1011 tcu_clkstop_if.tcu_mcu0_io_clk_stop
1012 };
1013 mcu_fbd_clkstop {
1014 tcu_clkstop_if.tcu_mcu3_fbd_clk_stop,
1015 tcu_clkstop_if.tcu_mcu2_fbd_clk_stop,
1016 tcu_clkstop_if.tcu_mcu1_fbd_clk_stop,
1017 tcu_clkstop_if.tcu_mcu0_fbd_clk_stop
1018 };
1019 soc0_clkstop { // warning: order is matter
1020 tcu_clkstop_if.tcu_ccx_clk_stop, // [4]
1021 tcu_clkstop_if.tcu_efu_clk_stop,
1022 tcu_clkstop_if.tcu_ncu_clk_stop,
1023 tcu_clkstop_if.tcu_sii_clk_stop,
1024 tcu_clkstop_if.tcu_sio_clk_stop // [0]
1025 };
1026 soc0_io_clkstop { // warning: order is matter
1027 tcu_clkstop_if.tcu_db0_clk_stop, // [6]
1028 tcu_clkstop_if.tcu_db1_clk_stop,
1029 tcu_clkstop_if.tcu_efu_io_clk_stop,
1030 tcu_clkstop_if.tcu_mio_clk_stop,
1031 tcu_clkstop_if.tcu_ncu_io_clk_stop,
1032 tcu_clkstop_if.tcu_sii_io_clk_stop,
1033 tcu_clkstop_if.tcu_sio_io_clk_stop // [0]
1034 };
1035 soc1_io_clkstop { // warning: order is matter
1036 tcu_clkstop_if.tcu_mac_io_clk_stop, // [3]
1037 tcu_clkstop_if.tcu_rdp_io_clk_stop,
1038 tcu_clkstop_if.tcu_rtx_io_clk_stop,
1039 tcu_clkstop_if.tcu_tds_io_clk_stop // [0]
1040 };
1041 soc2_io_clkstop tcu_clkstop_if.tcu_dmu_io_clk_stop;
1042 soc3_io_clkstop tcu_clkstop_if.tcu_peu_io_clk_stop;
1043 soc3_clkstop tcu_clkstop_if.tcu_peu_pc_clk_stop;
1044
1045 ccu_clkstop tcu_clkstop_if.tcu_ccu_clk_stop;
1046 ccu_io_clkstop tcu_clkstop_if.tcu_ccu_io_clk_stop;
1047
1048 rst_clkstop tcu_clkstop_if.tcu_rst_clk_stop;
1049 rst_io_clkstop tcu_clkstop_if.tcu_rst_io_clk_stop;
1050
1051 all_clk_stop_sigs { // warning: order is matter.
1052 tcu_clkstop_if.tcu_tds_io_clk_stop, // warn: in reverse alphabetical order
1053 tcu_clkstop_if.tcu_spc7_shscan_clk_stop,
1054 tcu_clkstop_if.tcu_spc7_clk_stop,
1055 tcu_clkstop_if.tcu_spc6_shscan_clk_stop,
1056 tcu_clkstop_if.tcu_spc6_clk_stop,
1057 tcu_clkstop_if.tcu_spc5_shscan_clk_stop,
1058 tcu_clkstop_if.tcu_spc5_clk_stop,
1059 tcu_clkstop_if.tcu_spc4_shscan_clk_stop,
1060 tcu_clkstop_if.tcu_spc4_clk_stop,
1061 tcu_clkstop_if.tcu_spc3_shscan_clk_stop,
1062 tcu_clkstop_if.tcu_spc3_clk_stop,
1063 tcu_clkstop_if.tcu_spc2_shscan_clk_stop,
1064 tcu_clkstop_if.tcu_spc2_clk_stop,
1065 tcu_clkstop_if.tcu_spc1_shscan_clk_stop,
1066 tcu_clkstop_if.tcu_spc1_clk_stop,
1067 tcu_clkstop_if.tcu_spc0_shscan_clk_stop,
1068 tcu_clkstop_if.tcu_spc0_clk_stop,
1069 tcu_clkstop_if.tcu_sio_io_clk_stop,
1070 tcu_clkstop_if.tcu_sio_clk_stop,
1071 tcu_clkstop_if.tcu_sii_io_clk_stop,
1072 tcu_clkstop_if.tcu_sii_clk_stop,
1073 tcu_clkstop_if.tcu_rtx_io_clk_stop,
1074 tcu_clkstop_if.tcu_rst_io_clk_stop,
1075 tcu_clkstop_if.tcu_rst_clk_stop,
1076 tcu_clkstop_if.tcu_rdp_io_clk_stop,
1077 tcu_clkstop_if.tcu_peu_pc_clk_stop,
1078 tcu_clkstop_if.tcu_peu_io_clk_stop,
1079 tcu_clkstop_if.tcu_ncu_io_clk_stop,
1080 tcu_clkstop_if.tcu_ncu_clk_stop,
1081 tcu_clkstop_if.tcu_mio_clk_stop,
1082 tcu_clkstop_if.tcu_mcu3_io_clk_stop,
1083 tcu_clkstop_if.tcu_mcu3_fbd_clk_stop,
1084 tcu_clkstop_if.tcu_mcu3_dr_clk_stop,
1085 tcu_clkstop_if.tcu_mcu3_clk_stop,
1086 tcu_clkstop_if.tcu_mcu2_io_clk_stop,
1087 tcu_clkstop_if.tcu_mcu2_fbd_clk_stop,
1088 tcu_clkstop_if.tcu_mcu2_dr_clk_stop,
1089 tcu_clkstop_if.tcu_mcu2_clk_stop,
1090 tcu_clkstop_if.tcu_mcu1_io_clk_stop,
1091 tcu_clkstop_if.tcu_mcu1_fbd_clk_stop,
1092 tcu_clkstop_if.tcu_mcu1_dr_clk_stop,
1093 tcu_clkstop_if.tcu_mcu1_clk_stop,
1094 tcu_clkstop_if.tcu_mcu0_io_clk_stop,
1095 tcu_clkstop_if.tcu_mcu0_fbd_clk_stop,
1096 tcu_clkstop_if.tcu_mcu0_dr_clk_stop,
1097 tcu_clkstop_if.tcu_mcu0_clk_stop,
1098 tcu_clkstop_if.tcu_mac_io_clk_stop,
1099 tcu_clkstop_if.tcu_l2t7_shscan_clk_stop,
1100 tcu_clkstop_if.tcu_l2t7_clk_stop,
1101 tcu_clkstop_if.tcu_l2t6_shscan_clk_stop,
1102 tcu_clkstop_if.tcu_l2t6_clk_stop,
1103 tcu_clkstop_if.tcu_l2t5_shscan_clk_stop,
1104 tcu_clkstop_if.tcu_l2t5_clk_stop,
1105 tcu_clkstop_if.tcu_l2t4_shscan_clk_stop,
1106 tcu_clkstop_if.tcu_l2t4_clk_stop,
1107 tcu_clkstop_if.tcu_l2t3_shscan_clk_stop,
1108 tcu_clkstop_if.tcu_l2t3_clk_stop,
1109 tcu_clkstop_if.tcu_l2t2_shscan_clk_stop,
1110 tcu_clkstop_if.tcu_l2t2_clk_stop,
1111 tcu_clkstop_if.tcu_l2t1_shscan_clk_stop,
1112 tcu_clkstop_if.tcu_l2t1_clk_stop,
1113 tcu_clkstop_if.tcu_l2t0_shscan_clk_stop,
1114 tcu_clkstop_if.tcu_l2t0_clk_stop,
1115 tcu_clkstop_if.tcu_l2d7_clk_stop,
1116 tcu_clkstop_if.tcu_l2d6_clk_stop,
1117 tcu_clkstop_if.tcu_l2d5_clk_stop,
1118 tcu_clkstop_if.tcu_l2d4_clk_stop,
1119 tcu_clkstop_if.tcu_l2d3_clk_stop,
1120 tcu_clkstop_if.tcu_l2d2_clk_stop,
1121 tcu_clkstop_if.tcu_l2d1_clk_stop,
1122 tcu_clkstop_if.tcu_l2d0_clk_stop,
1123 tcu_clkstop_if.tcu_l2b7_clk_stop,
1124 tcu_clkstop_if.tcu_l2b6_clk_stop,
1125 tcu_clkstop_if.tcu_l2b5_clk_stop,
1126 tcu_clkstop_if.tcu_l2b4_clk_stop,
1127 tcu_clkstop_if.tcu_l2b3_clk_stop,
1128 tcu_clkstop_if.tcu_l2b2_clk_stop,
1129 tcu_clkstop_if.tcu_l2b1_clk_stop,
1130 tcu_clkstop_if.tcu_l2b0_clk_stop,
1131 tcu_clkstop_if.tcu_efu_io_clk_stop,
1132 tcu_clkstop_if.tcu_efu_clk_stop,
1133 tcu_clkstop_if.tcu_dmu_io_clk_stop,
1134 tcu_clkstop_if.tcu_db1_clk_stop,
1135 tcu_clkstop_if.tcu_db0_clk_stop,
1136 tcu_clkstop_if.tcu_ccx_clk_stop,
1137 tcu_clkstop_if.tcu_ccu_io_clk_stop,
1138 tcu_clkstop_if.tcu_ccu_clk_stop
1139 };
1140}
1141
1142bind TCU_dbg_event_port tcu_dbg_event_bind {
1143 l2clk tcu_dbg_event_if.l2clk;
1144 hardstop_request
1145 {
1146 tcu_dbg_event_if.spc7_hardstop_request,
1147 tcu_dbg_event_if.spc6_hardstop_request,
1148 tcu_dbg_event_if.spc5_hardstop_request,
1149 tcu_dbg_event_if.spc4_hardstop_request,
1150 tcu_dbg_event_if.spc3_hardstop_request,
1151 tcu_dbg_event_if.spc2_hardstop_request,
1152 tcu_dbg_event_if.spc1_hardstop_request,
1153 tcu_dbg_event_if.spc0_hardstop_request
1154 };
1155 softstop_request
1156 {
1157 tcu_dbg_event_if.spc7_softstop_request,
1158 tcu_dbg_event_if.spc6_softstop_request,
1159 tcu_dbg_event_if.spc5_softstop_request,
1160 tcu_dbg_event_if.spc4_softstop_request,
1161 tcu_dbg_event_if.spc3_softstop_request,
1162 tcu_dbg_event_if.spc2_softstop_request,
1163 tcu_dbg_event_if.spc1_softstop_request,
1164 tcu_dbg_event_if.spc0_softstop_request
1165 };
1166 trigger_pulse
1167 {
1168 tcu_dbg_event_if.spc7_trigger_pulse,
1169 tcu_dbg_event_if.spc6_trigger_pulse,
1170 tcu_dbg_event_if.spc5_trigger_pulse,
1171 tcu_dbg_event_if.spc4_trigger_pulse,
1172 tcu_dbg_event_if.spc3_trigger_pulse,
1173 tcu_dbg_event_if.spc2_trigger_pulse,
1174 tcu_dbg_event_if.spc1_trigger_pulse,
1175 tcu_dbg_event_if.spc0_trigger_pulse
1176 };
1177 soc_hard_stop tcu_dbg_event_if.dbg1_tcu_soc_hard_stop;
1178 soc_trigout tcu_dbg_event_if.dbg1_tcu_soc_asrt_trigout;
1179
1180 tcu_mio_trigout tcu_dbg_event_if.tcu_mio_trigout;
1181 mio_tcu_trigin tcu_dbg_event_if.mio_tcu_trigin;
1182}
1183
1184bind TCU_dbg_event_port tcu_dbg_event_out_bind {
1185 l2clk tcu_dbg_event_out_if.l2clk;
1186 hardstop_request
1187 {
1188 tcu_dbg_event_out_if.spc7_hardstop_request,
1189 tcu_dbg_event_out_if.spc6_hardstop_request,
1190 tcu_dbg_event_out_if.spc5_hardstop_request,
1191 tcu_dbg_event_out_if.spc4_hardstop_request,
1192 tcu_dbg_event_out_if.spc3_hardstop_request,
1193 tcu_dbg_event_out_if.spc2_hardstop_request,
1194 tcu_dbg_event_out_if.spc1_hardstop_request,
1195 tcu_dbg_event_out_if.spc0_hardstop_request
1196 };
1197 softstop_request
1198 {
1199 tcu_dbg_event_out_if.spc7_softstop_request,
1200 tcu_dbg_event_out_if.spc6_softstop_request,
1201 tcu_dbg_event_out_if.spc5_softstop_request,
1202 tcu_dbg_event_out_if.spc4_softstop_request,
1203 tcu_dbg_event_out_if.spc3_softstop_request,
1204 tcu_dbg_event_out_if.spc2_softstop_request,
1205 tcu_dbg_event_out_if.spc1_softstop_request,
1206 tcu_dbg_event_out_if.spc0_softstop_request
1207 };
1208 trigger_pulse
1209 {
1210 tcu_dbg_event_out_if.spc7_trigger_pulse,
1211 tcu_dbg_event_out_if.spc6_trigger_pulse,
1212 tcu_dbg_event_out_if.spc5_trigger_pulse,
1213 tcu_dbg_event_out_if.spc4_trigger_pulse,
1214 tcu_dbg_event_out_if.spc3_trigger_pulse,
1215 tcu_dbg_event_out_if.spc2_trigger_pulse,
1216 tcu_dbg_event_out_if.spc1_trigger_pulse,
1217 tcu_dbg_event_out_if.spc0_trigger_pulse
1218 };
1219 soc_hard_stop void; // internal signal
1220 soc_trigout void; // internal signal
1221 tcu_mio_trigout void; // internal signal
1222 mio_tcu_trigin void; // internal signal
1223}
1224
1225bind stci__port stci_bind {
1226 tck stci.TCK;
1227 tcu_stciclk stci.tcu_stciclk;
1228 tcu_stcicfg stci.tcu_stcicfg;
1229 tcu_stcid stci.tcu_stcid;
1230 STCIQ stci.STCIQ;
1231 stciq_tcu stci.stciq_tcu;
1232 io_tdi stci.io_tdi;
1233 STCICLK stci.STCICLK;
1234 STCICFG stci.STCICFG;
1235 STCID stci.STCID;
1236 update_dr_state stci.update_dr_state;
1237 capture_dr_state stci.capture_dr_state;
1238 shift_dr_state stci.shift_dr_state;
1239#ifndef TCU_GATE
1240 clockdr stci.clockdr;
1241#endif
1242 stci_acc_mode stci.stci_acc_mode;
1243 tap_state stci.tap_state;
1244 signal_to_disable_checker stci.signal_to_disable_checker;
1245}
1246
1247
1248#endif
Full OpenSPARC design & verification tarball including full HDL.