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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / model / pcie / csr / csr.hpp
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: csr.hpp
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
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8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
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20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
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33//
34// ========== Copyright Header End ============================================
35
36#ifndef INC_csr_hpp__
37#define INC_csr_hpp__
38
39#include <systemc.h>
40
41#include "pcie_common/config.hpp"
42
43#include "pcie_common/csr_if.hpp"
44#include "pcie_common/peu_csr_defines.hpp"
45#include "pcie_common/peu_defines.hpp"
46#include "csr_base_if.hpp"
47
48#include <map>
49#include <list>
50#define MAX_NOTIFY_EVENTS 50
51
52namespace pcie {
53
54 typedef sc_event* sc_event_handle;
55
56 /// CSR Data Element
57 template <typename DATA>
58 class csr_data {
59 public:
60 DATA val;
61 sc_event_handle events[MAX_NOTIFY_EVENTS];
62 uint32 num_events;
63
64 csr_data() : val(0), num_events(0) {};
65 };
66
67 typedef enum {READ_ONLY, READ_WRITE, WRITE1_SET, WRITE1_CLEAR} intf_type_t;
68 enum {POR_L, RST_L};
69
70 template <typename DATA>
71 class csr_data_intf {
72 public:
73 csr_data<DATA> *data;
74 DATA rd_mask;
75 DATA wr_mask;
76 DATA clr_mask;
77 DATA set_mask;
78 DATA toggle_mask;
79 DATA por_val;
80 intf_type_t intf_type;
81 bool sw_reset_val_hold;
82 //All error and log registers should have this set to true
83
84 csr_data_intf () {
85 data = NULL;
86 sw_reset_val_hold=true;
87 intf_type = READ_WRITE;
88 }
89
90 /**
91 * This method resets the value of the CSR entry based on the type of the reset
92 * and warm reset behavior specification
93 */
94 DATA reset_data(uint8 rst_type){
95 if(rst_type==POR_L || (rst_type==RST_L && !sw_reset_val_hold)) {
96 data->val = por_val;
97 for (uint32 i = 0; i < data->num_events; i++) {
98 notify (*(data->events[i]));
99 }
100 }
101 return data->val;
102 }
103 };
104
105
106 template < typename ADDR, typename DATA>
107 class csr : public sc_module,
108 public virtual csr_base_if <ADDR, DATA>
109 {
110 public:
111 typedef tlm_transport_if <csr_req < ADDR, DATA > ,
112 csr_rsp < DATA > > if_type;
113 csr(sc_module_name module_name, sc_event *parent_global_event, uint8 *parent_global_event_type, int N = 10) :
114 sc_module (module_name),
115 target_port("csr_target_port")
116 {
117 target_port(*this);
118 this->parent_global_event = parent_global_event;
119 this->parent_global_event_type = parent_global_event_type;
120 SC_THREAD(reset_handler);
121 rst_type=POR_L;
122 }
123
124 SC_HAS_PROCESS(csr);
125
126 /**
127 * This method checks if the specified CSR address is present in the CSR database.
128 */
129 bool is_mapped (const ADDR reg_addr) {
130 if (csr_db[reg_addr] == NULL) {
131 return false;
132 }
133 return true;
134 }
135
136 /**
137 * This method returns the data stored at the requested address.
138 */
139 DATA read_csr (const ADDR reg_addr) {
140 if (csr_db[reg_addr] == NULL) {
141 LOG_ERROR << "Read_CSR address not mapped " << reg_addr;
142 return DATA(0);
143 }
144 DATA rd_data = csr_db[reg_addr]->data->val & csr_db[reg_addr]->rd_mask;
145 return rd_data;
146 }
147
148 /**
149 * This method updates the value at the specified address, based on the type of interface
150 * for that CSR data element.
151 */
152 DATA write_csr(const ADDR reg_addr, const DATA wr_val) {
153 if (csr_db[reg_addr] == NULL) {
154 LOG_ERROR << "WRITE_CSR address not mapped " << reg_addr;
155 return DATA(0);
156 }
157 if(POR_RESET){
158 return csr_db[reg_addr]->data->val;
159 }
160 DATA new_val;
161 new_val = wr_val & csr_db[reg_addr]->rd_mask;
162 if (csr_db[reg_addr]->intf_type == WRITE1_CLEAR) {
163 LOG_DEBUG << "write_csr for a WRITE1_CLEAR type intf, addr: " << reg_addr ;
164 LOG_DEBUG << " new_val: " << new_val << " data->val: " << csr_db[reg_addr]->data->val << " clr_mask: " << csr_db[reg_addr]->clr_mask;
165 new_val = new_val & csr_db[reg_addr]->clr_mask;
166 new_val = new_val & csr_db[reg_addr]->data->val;
167 new_val ^= csr_db[reg_addr]->data->val;
168 csr_db[reg_addr]->data->val = new_val;
169 } else if (csr_db[reg_addr]->intf_type == WRITE1_SET) {
170 LOG_DEBUG << "write_csr for a WRITE1_SET type intf, addr: " << reg_addr ;
171 LOG_DEBUG << " new_val: " << new_val << " data->val: " << csr_db[reg_addr]->data->val << " set_mask: " << csr_db[reg_addr]->set_mask;
172 new_val = new_val & csr_db[reg_addr]->set_mask;
173 new_val |= csr_db[reg_addr]->data->val;
174 csr_db[reg_addr]->data->val = new_val;
175 } else {
176 LOG_DEBUG << "write_csr for a READ_WRITE type intf, addr: " << reg_addr ;
177 LOG_DEBUG << " new_val: " << new_val << " data->val: " << csr_db[reg_addr]->data->val << " clr_mask: " << csr_db[reg_addr]->clr_mask;
178 LOG_DEBUG << " (csr_db[reg_addr]->clr_mask & new_val): " << (csr_db[reg_addr]->clr_mask & new_val) ;
179 csr_db[reg_addr]->data->val = (((csr_db[reg_addr]->data->val & ~csr_db[reg_addr]->wr_mask) ^ (csr_db[reg_addr]->clr_mask & new_val & csr_db[reg_addr]->data->val)) | (new_val & csr_db[reg_addr]->wr_mask));
180 //Original version: csr_db[reg_addr]->data->val = ((csr_db[reg_addr]->data->val & ~csr_db[reg_addr]->wr_mask) | (new_val & csr_db[reg_addr]->wr_mask));
181 }
182 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
183 notify (*(csr_db[reg_addr]->data->events[i]));
184 }
185
186 return csr_db[reg_addr]->data->val;
187 }
188
189 /**
190 * This method updates the value at the specified address using the specified mask,
191 * based on the tyep of interface for that CSR data element.
192 */
193 DATA write_csr_mask(const ADDR reg_addr, const DATA wr_val, const DATA field_mask) {
194
195 if (csr_db[reg_addr] == NULL) {
196 LOG_ERROR << "WRITE_CSR_mask address not mapped " << reg_addr;
197 return DATA(0);
198 }
199 if(POR_RESET){
200 return csr_db[reg_addr]->data->val;
201 }
202 DATA new_val;
203 new_val = csr_db[reg_addr]->data->val & csr_db[reg_addr]->rd_mask;
204 LOG_DEBUG << " new_val: " << new_val << " data->val: " << csr_db[reg_addr]->data->val << " field_mask: " << field_mask;
205 new_val = (new_val & ~field_mask) | wr_val;
206 LOG_DEBUG << " new_val: " << new_val ;
207 csr_db[reg_addr]->data->val = new_val;
208 LOG_DEBUG << " data->val: " << csr_db[reg_addr]->data->val ;
209 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
210 notify (*(csr_db[reg_addr]->data->events[i]));
211 }
212 return csr_db[reg_addr]->data->val;
213 }
214
215 /**
216 * This method registers event notifications with the specified CSR address.
217 */
218 void set_notify_event(ADDR reg_addr, sc_event* event_handle){
219 LOG_DEBUG << "Set_Notify_Event (Addr: " << reg_addr
220 << ", EvHandle " << uint64(event_handle) << ")";
221
222 if (csr_db[reg_addr] == NULL) {
223 LOG_ERROR << "Address " << reg_addr << " not mapped on this addres space";
224 exit(0);
225 }
226 csr_db[reg_addr]->data->events[csr_db[reg_addr]->data->num_events++] = event_handle;
227 }
228
229 /**
230 * This method populates the CSR database with the required CSRs and their
231 * desired characteristics.
232 */
233 void create_csr_db() {
234 ADDR reg_addr;
235
236 LOG_DEBUG << "Create CSR DB";
237 POR_RESET=false;
238
239 reg_addr = PEU_CSR_A_TLU_CTL_HW_ADDR;
240 if (csr_db[reg_addr] == NULL) {
241 csr_db[reg_addr] = new csr_data_intf<DATA> ();
242 csr_db[reg_addr]->data = new csr_data<DATA> ();
243 }
244
245 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_CTL_READ_MASK;
246 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_CTL_WRITE_MASK;
247 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_CTL_CLEAR_MASK;
248 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_CTL_SET_MASK;
249 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_CTL_TOGGLE_MASK;
250 csr_db[reg_addr]->por_val = PEU_CSR_TLU_CTL_POR_VALUE;
251 csr_db[reg_addr]->data->val = PEU_CSR_TLU_CTL_POR_VALUE;
252 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
253 notify (*(csr_db[reg_addr]->data->events[i]));
254 }
255
256 reg_addr = PEU_CSR_B_TLU_CTL_HW_ADDR;
257 if (csr_db[reg_addr] == NULL) {
258 csr_db[reg_addr] = new csr_data_intf<DATA> ();
259 csr_db[reg_addr]->data = new csr_data<DATA> ();
260 }
261
262 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_CTL_READ_MASK;
263 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_CTL_WRITE_MASK;
264 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_CTL_CLEAR_MASK;
265 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_CTL_SET_MASK;
266 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_CTL_TOGGLE_MASK;
267 csr_db[reg_addr]->por_val = PEU_CSR_TLU_CTL_POR_VALUE;
268
269 csr_db[reg_addr]->data->val = PEU_CSR_TLU_CTL_POR_VALUE;
270 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
271 notify (*(csr_db[reg_addr]->data->events[i]));
272 }
273
274 reg_addr = PEU_CSR_A_TLU_STS_HW_ADDR;
275 if (csr_db[reg_addr] == NULL) {
276 csr_db[reg_addr] = new csr_data_intf<DATA> ();
277 csr_db[reg_addr]->data = new csr_data<DATA> ();
278 }
279
280 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_STS_READ_MASK;
281 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_STS_WRITE_MASK;
282 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_STS_CLEAR_MASK;
283 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_STS_SET_MASK;
284 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_STS_TOGGLE_MASK;
285 csr_db[reg_addr]->por_val = PEU_CSR_TLU_STS_POR_VALUE;
286
287 csr_db[reg_addr]->data->val = PEU_CSR_TLU_STS_POR_VALUE;
288 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
289 notify (*(csr_db[reg_addr]->data->events[i]));
290 }
291
292 reg_addr = PEU_CSR_B_TLU_STS_HW_ADDR;
293 if (csr_db[reg_addr] == NULL) {
294 csr_db[reg_addr] = new csr_data_intf<DATA> ();
295 csr_db[reg_addr]->data = new csr_data<DATA> ();
296 }
297
298 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_STS_READ_MASK;
299 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_STS_WRITE_MASK;
300 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_STS_CLEAR_MASK;
301 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_STS_SET_MASK;
302 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_STS_TOGGLE_MASK;
303 csr_db[reg_addr]->por_val = PEU_CSR_TLU_STS_POR_VALUE;
304
305 csr_db[reg_addr]->data->val = PEU_CSR_TLU_STS_POR_VALUE;
306 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
307 notify (*(csr_db[reg_addr]->data->events[i]));
308 }
309
310 reg_addr = PEU_CSR_A_TRN_OFF_HW_ADDR;
311 if (csr_db[reg_addr] == NULL) {
312 csr_db[reg_addr] = new csr_data_intf<DATA> ();
313 csr_db[reg_addr]->data = new csr_data<DATA> ();
314 }
315
316 csr_db[reg_addr]->rd_mask = PEU_CSR_TRN_OFF_READ_MASK;
317 csr_db[reg_addr]->wr_mask = PEU_CSR_TRN_OFF_WRITE_MASK;
318 csr_db[reg_addr]->clr_mask = PEU_CSR_TRN_OFF_CLEAR_MASK;
319 csr_db[reg_addr]->set_mask = PEU_CSR_TRN_OFF_SET_MASK;
320 csr_db[reg_addr]->toggle_mask = PEU_CSR_TRN_OFF_TOGGLE_MASK;
321 csr_db[reg_addr]->por_val = PEU_CSR_TRN_OFF_POR_VALUE;
322
323 csr_db[reg_addr]->data->val = PEU_CSR_TRN_OFF_POR_VALUE;
324
325 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
326 notify (*(csr_db[reg_addr]->data->events[i]));
327 }
328
329 reg_addr = PEU_CSR_B_TRN_OFF_HW_ADDR;
330 if (csr_db[reg_addr] == NULL) {
331 csr_db[reg_addr] = new csr_data_intf<DATA> ();
332 csr_db[reg_addr]->data = new csr_data<DATA> ();
333 }
334
335 csr_db[reg_addr]->rd_mask = PEU_CSR_TRN_OFF_READ_MASK;
336 csr_db[reg_addr]->wr_mask = PEU_CSR_TRN_OFF_WRITE_MASK;
337 csr_db[reg_addr]->clr_mask = PEU_CSR_TRN_OFF_CLEAR_MASK;
338 csr_db[reg_addr]->set_mask = PEU_CSR_TRN_OFF_SET_MASK;
339 csr_db[reg_addr]->toggle_mask = PEU_CSR_TRN_OFF_TOGGLE_MASK;
340 csr_db[reg_addr]->por_val = PEU_CSR_TRN_OFF_POR_VALUE;
341
342 csr_db[reg_addr]->data->val = PEU_CSR_TRN_OFF_POR_VALUE;
343
344 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
345 notify (*(csr_db[reg_addr]->data->events[i]));
346 }
347
348 reg_addr = PEU_CSR_A_TLU_ICI_HW_ADDR;
349 if (csr_db[reg_addr] == NULL) {
350 csr_db[reg_addr] = new csr_data_intf<DATA> ();
351 csr_db[reg_addr]->data = new csr_data<DATA> ();
352 }
353
354 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_ICI_READ_MASK;
355 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_ICI_WRITE_MASK;
356 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_ICI_CLEAR_MASK;
357 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_ICI_SET_MASK;
358 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_ICI_TOGGLE_MASK;
359 csr_db[reg_addr]->por_val = PEU_CSR_TLU_ICI_POR_VALUE;
360 csr_db[reg_addr]->data->val = PEU_CSR_TLU_ICI_POR_VALUE;
361
362 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
363 notify (*(csr_db[reg_addr]->data->events[i]));
364 }
365
366 reg_addr = PEU_CSR_B_TLU_ICI_HW_ADDR;
367 if (csr_db[reg_addr] == NULL) {
368 csr_db[reg_addr] = new csr_data_intf<DATA> ();
369 csr_db[reg_addr]->data = new csr_data<DATA> ();
370 }
371
372 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_ICI_READ_MASK;
373 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_ICI_WRITE_MASK;
374 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_ICI_CLEAR_MASK;
375 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_ICI_SET_MASK;
376 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_ICI_TOGGLE_MASK;
377 csr_db[reg_addr]->por_val = PEU_CSR_TLU_ICI_POR_VALUE;
378
379 csr_db[reg_addr]->data->val = PEU_CSR_TLU_ICI_POR_VALUE;
380
381 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
382 notify (*(csr_db[reg_addr]->data->events[i]));
383 }
384
385 reg_addr = PEU_CSR_A_TLU_DIAG_HW_ADDR;
386 if (csr_db[reg_addr] == NULL) {
387 csr_db[reg_addr] = new csr_data_intf<DATA> ();
388 csr_db[reg_addr]->data = new csr_data<DATA> ();
389 }
390
391 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_DIAG_READ_MASK;
392 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_DIAG_WRITE_MASK;
393 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_DIAG_CLEAR_MASK;
394 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_DIAG_SET_MASK;
395 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_DIAG_TOGGLE_MASK;
396 csr_db[reg_addr]->por_val = PEU_CSR_TLU_DIAG_POR_VALUE;
397
398 csr_db[reg_addr]->data->val = PEU_CSR_TLU_DIAG_POR_VALUE;
399
400 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
401 notify (*(csr_db[reg_addr]->data->events[i]));
402 }
403
404 reg_addr = PEU_CSR_B_TLU_DIAG_HW_ADDR;
405 if (csr_db[reg_addr] == NULL) {
406 csr_db[reg_addr] = new csr_data_intf<DATA> ();
407 csr_db[reg_addr]->data = new csr_data<DATA> ();
408 }
409
410 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_DIAG_READ_MASK;
411 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_DIAG_WRITE_MASK;
412 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_DIAG_CLEAR_MASK;
413 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_DIAG_SET_MASK;
414 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_DIAG_TOGGLE_MASK;
415 csr_db[reg_addr]->por_val = PEU_CSR_TLU_DIAG_POR_VALUE;
416
417 csr_db[reg_addr]->data->val = PEU_CSR_TLU_DIAG_POR_VALUE;
418
419 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
420 notify (*(csr_db[reg_addr]->data->events[i]));
421 }
422
423 reg_addr = PEU_CSR_A_TLU_ECC_HW_ADDR;
424 if (csr_db[reg_addr] == NULL) {
425 csr_db[reg_addr] = new csr_data_intf<DATA> ();
426 csr_db[reg_addr]->data = new csr_data<DATA> ();
427 }
428
429 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_ECC_READ_MASK;
430 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_ECC_WRITE_MASK;
431 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_ECC_CLEAR_MASK;
432 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_ECC_SET_MASK;
433 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_ECC_TOGGLE_MASK;
434 csr_db[reg_addr]->por_val = PEU_CSR_TLU_ECC_POR_VALUE;
435
436 csr_db[reg_addr]->data->val = PEU_CSR_TLU_ECC_POR_VALUE;
437
438 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
439 notify (*(csr_db[reg_addr]->data->events[i]));
440 }
441
442 reg_addr = PEU_CSR_B_TLU_ECC_HW_ADDR;
443 if (csr_db[reg_addr] == NULL) {
444 csr_db[reg_addr] = new csr_data_intf<DATA> ();
445 csr_db[reg_addr]->data = new csr_data<DATA> ();
446 }
447
448 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_ECC_READ_MASK;
449 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_ECC_WRITE_MASK;
450 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_ECC_CLEAR_MASK;
451 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_ECC_SET_MASK;
452 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_ECC_TOGGLE_MASK;
453 csr_db[reg_addr]->por_val = PEU_CSR_TLU_ECC_POR_VALUE;
454
455 csr_db[reg_addr]->data->val = PEU_CSR_TLU_ECC_POR_VALUE;
456
457 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
458 notify (*(csr_db[reg_addr]->data->events[i]));
459 }
460
461 reg_addr = PEU_CSR_A_TLU_ECL_HW_ADDR;
462 if (csr_db[reg_addr] == NULL) {
463 csr_db[reg_addr] = new csr_data_intf<DATA> ();
464 csr_db[reg_addr]->data = new csr_data<DATA> ();
465 }
466
467 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_ECL_READ_MASK;
468 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_ECL_WRITE_MASK;
469 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_ECL_CLEAR_MASK;
470 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_ECL_SET_MASK;
471 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_ECL_TOGGLE_MASK;
472 csr_db[reg_addr]->por_val = PEU_CSR_TLU_ECL_POR_VALUE;
473
474 csr_db[reg_addr]->data->val = PEU_CSR_TLU_ECL_POR_VALUE;
475
476 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
477 notify (*(csr_db[reg_addr]->data->events[i]));
478 }
479
480 reg_addr = PEU_CSR_B_TLU_ECL_HW_ADDR;
481 if (csr_db[reg_addr] == NULL) {
482 csr_db[reg_addr] = new csr_data_intf<DATA> ();
483 csr_db[reg_addr]->data = new csr_data<DATA> ();
484 }
485
486 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_ECL_READ_MASK;
487 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_ECL_WRITE_MASK;
488 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_ECL_CLEAR_MASK;
489 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_ECL_SET_MASK;
490 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_ECL_TOGGLE_MASK;
491 csr_db[reg_addr]->por_val = PEU_CSR_TLU_ECL_POR_VALUE;
492
493 csr_db[reg_addr]->data->val = PEU_CSR_TLU_ECL_POR_VALUE;
494
495 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
496 notify (*(csr_db[reg_addr]->data->events[i]));
497 }
498
499 reg_addr = PEU_CSR_A_TLU_ERB_HW_ADDR;
500 if (csr_db[reg_addr] == NULL) {
501 csr_db[reg_addr] = new csr_data_intf<DATA> ();
502 csr_db[reg_addr]->data = new csr_data<DATA> ();
503 }
504
505 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_ERB_READ_MASK;
506 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_ERB_WRITE_MASK;
507 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_ERB_CLEAR_MASK;
508 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_ERB_SET_MASK;
509 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_ERB_TOGGLE_MASK;
510 csr_db[reg_addr]->por_val = PEU_CSR_TLU_ERB_POR_VALUE;
511
512 csr_db[reg_addr]->data->val = PEU_CSR_TLU_ERB_POR_VALUE;
513
514 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
515 notify (*(csr_db[reg_addr]->data->events[i]));
516 }
517
518 reg_addr = PEU_CSR_B_TLU_ERB_HW_ADDR;
519 if (csr_db[reg_addr] == NULL) {
520 csr_db[reg_addr] = new csr_data_intf<DATA> ();
521 csr_db[reg_addr]->data = new csr_data<DATA> ();
522 }
523
524 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_ERB_READ_MASK;
525 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_ERB_WRITE_MASK;
526 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_ERB_CLEAR_MASK;
527 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_ERB_SET_MASK;
528 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_ERB_TOGGLE_MASK;
529 csr_db[reg_addr]->por_val = PEU_CSR_TLU_ERB_POR_VALUE;
530
531 csr_db[reg_addr]->data->val = PEU_CSR_TLU_ERB_POR_VALUE;
532
533 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
534 notify (*(csr_db[reg_addr]->data->events[i]));
535 }
536
537 reg_addr = PEU_CSR_A_TLU_ICA_HW_ADDR;
538 if (csr_db[reg_addr] == NULL) {
539 csr_db[reg_addr] = new csr_data_intf<DATA> ();
540 csr_db[reg_addr]->data = new csr_data<DATA> ();
541 }
542
543 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_ICA_READ_MASK;
544 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_ICA_WRITE_MASK;
545 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_ICA_CLEAR_MASK;
546 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_ICA_SET_MASK;
547 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_ICA_TOGGLE_MASK;
548 csr_db[reg_addr]->por_val = PEU_CSR_TLU_ICA_POR_VALUE;
549
550 csr_db[reg_addr]->data->val = PEU_CSR_TLU_ICA_POR_VALUE;
551
552 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
553 notify (*(csr_db[reg_addr]->data->events[i]));
554 }
555
556 reg_addr = PEU_CSR_B_TLU_ICA_HW_ADDR;
557 if (csr_db[reg_addr] == NULL) {
558 csr_db[reg_addr] = new csr_data_intf<DATA> ();
559 csr_db[reg_addr]->data = new csr_data<DATA> ();
560 }
561
562 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_ICA_READ_MASK;
563 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_ICA_WRITE_MASK;
564 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_ICA_CLEAR_MASK;
565 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_ICA_SET_MASK;
566 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_ICA_TOGGLE_MASK;
567 csr_db[reg_addr]->por_val = PEU_CSR_TLU_ICA_POR_VALUE;
568
569 csr_db[reg_addr]->data->val = PEU_CSR_TLU_ICA_POR_VALUE;
570
571 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
572 notify (*(csr_db[reg_addr]->data->events[i]));
573 }
574
575 reg_addr = PEU_CSR_A_TLU_ICR_HW_ADDR;
576 if (csr_db[reg_addr] == NULL) {
577 csr_db[reg_addr] = new csr_data_intf<DATA> ();
578 csr_db[reg_addr]->data = new csr_data<DATA> ();
579 }
580
581 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_ICR_READ_MASK;
582 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_ICR_WRITE_MASK;
583 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_ICR_CLEAR_MASK;
584 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_ICR_SET_MASK;
585 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_ICR_TOGGLE_MASK;
586 csr_db[reg_addr]->por_val = PEU_CSR_TLU_ICR_POR_VALUE;
587
588 csr_db[reg_addr]->data->val = PEU_CSR_TLU_ICR_POR_VALUE;
589
590 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
591 notify (*(csr_db[reg_addr]->data->events[i]));
592 }
593
594 reg_addr = PEU_CSR_B_TLU_ICR_HW_ADDR;
595 if (csr_db[reg_addr] == NULL) {
596 csr_db[reg_addr] = new csr_data_intf<DATA> ();
597 csr_db[reg_addr]->data = new csr_data<DATA> ();
598 }
599
600 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_ICR_READ_MASK;
601 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_ICR_WRITE_MASK;
602 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_ICR_CLEAR_MASK;
603 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_ICR_SET_MASK;
604 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_ICR_TOGGLE_MASK;
605 csr_db[reg_addr]->por_val = PEU_CSR_TLU_ICR_POR_VALUE;
606
607 csr_db[reg_addr]->data->val = PEU_CSR_TLU_ICR_POR_VALUE;
608
609 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
610 notify (*(csr_db[reg_addr]->data->events[i]));
611 }
612
613 reg_addr = PEU_CSR_A_OE_LOG_HW_ADDR;
614 if (csr_db[reg_addr] == NULL) {
615 csr_db[reg_addr] = new csr_data_intf<DATA> ();
616 csr_db[reg_addr]->data = new csr_data<DATA> ();
617 }
618
619 csr_db[reg_addr]->rd_mask = PEU_CSR_OE_LOG_READ_MASK;
620 csr_db[reg_addr]->wr_mask = PEU_CSR_OE_LOG_WRITE_MASK;
621 csr_db[reg_addr]->clr_mask = PEU_CSR_OE_LOG_CLEAR_MASK;
622 csr_db[reg_addr]->set_mask = PEU_CSR_OE_LOG_SET_MASK;
623 csr_db[reg_addr]->toggle_mask = PEU_CSR_OE_LOG_TOGGLE_MASK;
624 csr_db[reg_addr]->por_val = PEU_CSR_OE_LOG_POR_VALUE;
625
626 csr_db[reg_addr]->data->val = PEU_CSR_OE_LOG_POR_VALUE;
627
628 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
629 notify (*(csr_db[reg_addr]->data->events[i]));
630 }
631
632 reg_addr = PEU_CSR_B_OE_LOG_HW_ADDR;
633 if (csr_db[reg_addr] == NULL) {
634 csr_db[reg_addr] = new csr_data_intf<DATA> ();
635 csr_db[reg_addr]->data = new csr_data<DATA> ();
636 }
637
638 csr_db[reg_addr]->rd_mask = PEU_CSR_OE_LOG_READ_MASK;
639 csr_db[reg_addr]->wr_mask = PEU_CSR_OE_LOG_WRITE_MASK;
640 csr_db[reg_addr]->clr_mask = PEU_CSR_OE_LOG_CLEAR_MASK;
641 csr_db[reg_addr]->set_mask = PEU_CSR_OE_LOG_SET_MASK;
642 csr_db[reg_addr]->toggle_mask = PEU_CSR_OE_LOG_TOGGLE_MASK;
643 csr_db[reg_addr]->por_val = PEU_CSR_OE_LOG_POR_VALUE;
644
645 csr_db[reg_addr]->data->val = PEU_CSR_OE_LOG_POR_VALUE;
646
647 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
648 notify (*(csr_db[reg_addr]->data->events[i]));
649 }
650
651 reg_addr = PEU_CSR_A_OE_INT_EN_HW_ADDR;
652 if (csr_db[reg_addr] == NULL) {
653 csr_db[reg_addr] = new csr_data_intf<DATA> ();
654 csr_db[reg_addr]->data = new csr_data<DATA> ();
655 }
656
657 csr_db[reg_addr]->rd_mask = PEU_CSR_OE_INT_EN_READ_MASK;
658 csr_db[reg_addr]->wr_mask = PEU_CSR_OE_INT_EN_WRITE_MASK;
659 csr_db[reg_addr]->clr_mask = PEU_CSR_OE_INT_EN_CLEAR_MASK;
660 csr_db[reg_addr]->set_mask = PEU_CSR_OE_INT_EN_SET_MASK;
661 csr_db[reg_addr]->toggle_mask = PEU_CSR_OE_INT_EN_TOGGLE_MASK;
662 csr_db[reg_addr]->por_val = PEU_CSR_OE_INT_EN_POR_VALUE;
663
664 csr_db[reg_addr]->data->val = PEU_CSR_OE_INT_EN_POR_VALUE;
665
666 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
667 notify (*(csr_db[reg_addr]->data->events[i]));
668 }
669
670 reg_addr = PEU_CSR_B_OE_INT_EN_HW_ADDR;
671 if (csr_db[reg_addr] == NULL) {
672 csr_db[reg_addr] = new csr_data_intf<DATA> ();
673 csr_db[reg_addr]->data = new csr_data<DATA> ();
674 }
675
676 csr_db[reg_addr]->rd_mask = PEU_CSR_OE_INT_EN_READ_MASK;
677 csr_db[reg_addr]->wr_mask = PEU_CSR_OE_INT_EN_WRITE_MASK;
678 csr_db[reg_addr]->clr_mask = PEU_CSR_OE_INT_EN_CLEAR_MASK;
679 csr_db[reg_addr]->set_mask = PEU_CSR_OE_INT_EN_SET_MASK;
680 csr_db[reg_addr]->toggle_mask = PEU_CSR_OE_INT_EN_TOGGLE_MASK;
681 csr_db[reg_addr]->por_val = PEU_CSR_OE_INT_EN_POR_VALUE;
682
683 csr_db[reg_addr]->data->val = PEU_CSR_OE_INT_EN_POR_VALUE;
684
685 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
686 notify (*(csr_db[reg_addr]->data->events[i]));
687 }
688
689 reg_addr = PEU_CSR_A_OE_EN_ERR_HW_ADDR;
690 if (csr_db[reg_addr] == NULL) {
691 csr_db[reg_addr] = new csr_data_intf<DATA> ();
692 csr_db[reg_addr]->data = new csr_data<DATA> ();
693 }
694
695 csr_db[reg_addr]->rd_mask = PEU_CSR_OE_EN_ERR_READ_MASK;
696 csr_db[reg_addr]->wr_mask = PEU_CSR_OE_EN_ERR_WRITE_MASK;
697 csr_db[reg_addr]->clr_mask = PEU_CSR_OE_EN_ERR_CLEAR_MASK;
698 csr_db[reg_addr]->set_mask = PEU_CSR_OE_EN_ERR_SET_MASK;
699 csr_db[reg_addr]->toggle_mask = PEU_CSR_OE_EN_ERR_TOGGLE_MASK;
700 csr_db[reg_addr]->por_val = PEU_CSR_OE_EN_ERR_POR_VALUE;
701
702 csr_db[reg_addr]->data->val = PEU_CSR_OE_EN_ERR_POR_VALUE;
703
704 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
705 notify (*(csr_db[reg_addr]->data->events[i]));
706 }
707
708 reg_addr = PEU_CSR_B_OE_EN_ERR_HW_ADDR;
709 if (csr_db[reg_addr] == NULL) {
710 csr_db[reg_addr] = new csr_data_intf<DATA> ();
711 csr_db[reg_addr]->data = new csr_data<DATA> ();
712 }
713
714 csr_db[reg_addr]->rd_mask = PEU_CSR_OE_EN_ERR_READ_MASK;
715 csr_db[reg_addr]->wr_mask = PEU_CSR_OE_EN_ERR_WRITE_MASK;
716 csr_db[reg_addr]->clr_mask = PEU_CSR_OE_EN_ERR_CLEAR_MASK;
717 csr_db[reg_addr]->set_mask = PEU_CSR_OE_EN_ERR_SET_MASK;
718 csr_db[reg_addr]->toggle_mask = PEU_CSR_OE_EN_ERR_TOGGLE_MASK;
719 csr_db[reg_addr]->por_val = PEU_CSR_OE_EN_ERR_POR_VALUE;
720
721 csr_db[reg_addr]->data->val = PEU_CSR_OE_EN_ERR_POR_VALUE;
722
723 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
724 notify (*(csr_db[reg_addr]->data->events[i]));
725 }
726
727 reg_addr = PEU_CSR_A_OE_ERR_RW1C_ALIAS_HW_ADDR;
728 if (csr_db[reg_addr] == NULL) {
729 csr_db[reg_addr] = new csr_data_intf<DATA> ();
730 csr_db[reg_addr]->data = new csr_data<DATA> ();
731 }
732
733 csr_db[reg_addr]->rd_mask = PEU_CSR_OE_ERR_RW1C_ALIAS_READ_MASK;
734 csr_db[reg_addr]->wr_mask = PEU_CSR_OE_ERR_RW1C_ALIAS_WRITE_MASK;
735 csr_db[reg_addr]->clr_mask = PEU_CSR_OE_ERR_RW1C_ALIAS_CLEAR_MASK;
736 csr_db[reg_addr]->set_mask = PEU_CSR_OE_ERR_RW1C_ALIAS_SET_MASK;
737 csr_db[reg_addr]->toggle_mask = PEU_CSR_OE_ERR_RW1C_ALIAS_TOGGLE_MASK;
738 csr_db[reg_addr]->por_val = PEU_CSR_OE_ERR_RW1C_ALIAS_POR_VALUE;
739
740 csr_db[reg_addr]->data->val = PEU_CSR_OE_ERR_RW1C_ALIAS_POR_VALUE;
741 csr_db[reg_addr]->intf_type = WRITE1_CLEAR;
742 csr_db[reg_addr]->sw_reset_val_hold = false;
743
744 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
745 notify (*(csr_db[reg_addr]->data->events[i]));
746 }
747
748 reg_addr = PEU_CSR_B_OE_ERR_RW1C_ALIAS_HW_ADDR;
749 if (csr_db[reg_addr] == NULL) {
750 csr_db[reg_addr] = new csr_data_intf<DATA> ();
751 csr_db[reg_addr]->data = new csr_data<DATA> ();
752 }
753
754 csr_db[reg_addr]->rd_mask = PEU_CSR_OE_ERR_RW1C_ALIAS_READ_MASK;
755 csr_db[reg_addr]->wr_mask = PEU_CSR_OE_ERR_RW1C_ALIAS_WRITE_MASK;
756 csr_db[reg_addr]->clr_mask = PEU_CSR_OE_ERR_RW1C_ALIAS_CLEAR_MASK;
757 csr_db[reg_addr]->set_mask = PEU_CSR_OE_ERR_RW1C_ALIAS_SET_MASK;
758 csr_db[reg_addr]->toggle_mask = PEU_CSR_OE_ERR_RW1C_ALIAS_TOGGLE_MASK;
759 csr_db[reg_addr]->por_val = PEU_CSR_OE_ERR_RW1C_ALIAS_POR_VALUE;
760
761 csr_db[reg_addr]->data->val = PEU_CSR_OE_ERR_RW1C_ALIAS_POR_VALUE;
762 csr_db[reg_addr]->intf_type = WRITE1_CLEAR;
763 csr_db[reg_addr]->sw_reset_val_hold = false;
764
765 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
766 notify (*(csr_db[reg_addr]->data->events[i]));
767 }
768
769 reg_addr = PEU_CSR_A_OE_ERR_RW1S_ALIAS_HW_ADDR;
770 if (csr_db[reg_addr] == NULL) {
771 csr_db[reg_addr] = new csr_data_intf<DATA> ();
772 csr_db[reg_addr]->data = csr_db[PEU_CSR_A_OE_ERR_RW1C_ALIAS_HW_ADDR]->data;
773
774 }
775
776 csr_db[reg_addr]->rd_mask = PEU_CSR_OE_ERR_RW1S_ALIAS_READ_MASK;
777 csr_db[reg_addr]->wr_mask = PEU_CSR_OE_ERR_RW1S_ALIAS_WRITE_MASK;
778 csr_db[reg_addr]->clr_mask = PEU_CSR_OE_ERR_RW1S_ALIAS_CLEAR_MASK;
779 csr_db[reg_addr]->set_mask = PEU_CSR_OE_ERR_RW1S_ALIAS_SET_MASK;
780 csr_db[reg_addr]->toggle_mask = PEU_CSR_OE_ERR_RW1S_ALIAS_TOGGLE_MASK;
781 csr_db[reg_addr]->por_val = PEU_CSR_OE_ERR_RW1S_ALIAS_POR_VALUE;
782
783 csr_db[reg_addr]->data->val = PEU_CSR_OE_ERR_RW1S_ALIAS_POR_VALUE;
784 csr_db[reg_addr]->intf_type = WRITE1_SET;
785 csr_db[reg_addr]->sw_reset_val_hold = false;
786
787 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
788 notify (*(csr_db[reg_addr]->data->events[i]));
789 }
790
791 reg_addr = PEU_CSR_B_OE_ERR_RW1S_ALIAS_HW_ADDR;
792 if (csr_db[reg_addr] == NULL) {
793 csr_db[reg_addr] = new csr_data_intf<DATA> ();
794 csr_db[reg_addr]->data = csr_db[PEU_CSR_B_OE_ERR_RW1C_ALIAS_HW_ADDR]->data;
795
796 }
797
798 csr_db[reg_addr]->rd_mask = PEU_CSR_OE_ERR_RW1S_ALIAS_READ_MASK;
799 csr_db[reg_addr]->wr_mask = PEU_CSR_OE_ERR_RW1S_ALIAS_WRITE_MASK;
800 csr_db[reg_addr]->clr_mask = PEU_CSR_OE_ERR_RW1S_ALIAS_CLEAR_MASK;
801 csr_db[reg_addr]->set_mask = PEU_CSR_OE_ERR_RW1S_ALIAS_SET_MASK;
802 csr_db[reg_addr]->toggle_mask = PEU_CSR_OE_ERR_RW1S_ALIAS_TOGGLE_MASK;
803 csr_db[reg_addr]->por_val = PEU_CSR_OE_ERR_RW1S_ALIAS_POR_VALUE;
804
805 csr_db[reg_addr]->data->val = PEU_CSR_OE_ERR_RW1S_ALIAS_POR_VALUE;
806 csr_db[reg_addr]->intf_type = WRITE1_SET;
807 csr_db[reg_addr]->sw_reset_val_hold = false;
808
809 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
810 notify (*(csr_db[reg_addr]->data->events[i]));
811 }
812
813 reg_addr = PEU_CSR_A_ROE_HDR1_HW_ADDR;
814 if (csr_db[reg_addr] == NULL) {
815 csr_db[reg_addr] = new csr_data_intf<DATA> ();
816 csr_db[reg_addr]->data = new csr_data<DATA> ();
817 }
818
819 csr_db[reg_addr]->rd_mask = PEU_CSR_ROE_HDR1_READ_MASK;
820 csr_db[reg_addr]->wr_mask = PEU_CSR_ROE_HDR1_WRITE_MASK;
821 csr_db[reg_addr]->clr_mask = PEU_CSR_ROE_HDR1_CLEAR_MASK;
822 csr_db[reg_addr]->set_mask = PEU_CSR_ROE_HDR1_SET_MASK;
823 csr_db[reg_addr]->toggle_mask = PEU_CSR_ROE_HDR1_TOGGLE_MASK;
824 csr_db[reg_addr]->por_val = PEU_CSR_ROE_HDR1_POR_VALUE;
825
826 csr_db[reg_addr]->data->val = PEU_CSR_ROE_HDR1_POR_VALUE;
827
828 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
829 notify (*(csr_db[reg_addr]->data->events[i]));
830 }
831
832 reg_addr = PEU_CSR_B_ROE_HDR1_HW_ADDR;
833 if (csr_db[reg_addr] == NULL) {
834 csr_db[reg_addr] = new csr_data_intf<DATA> ();
835 csr_db[reg_addr]->data = new csr_data<DATA> ();
836 }
837
838 csr_db[reg_addr]->rd_mask = PEU_CSR_ROE_HDR1_READ_MASK;
839 csr_db[reg_addr]->wr_mask = PEU_CSR_ROE_HDR1_WRITE_MASK;
840 csr_db[reg_addr]->clr_mask = PEU_CSR_ROE_HDR1_CLEAR_MASK;
841 csr_db[reg_addr]->set_mask = PEU_CSR_ROE_HDR1_SET_MASK;
842 csr_db[reg_addr]->toggle_mask = PEU_CSR_ROE_HDR1_TOGGLE_MASK;
843 csr_db[reg_addr]->por_val = PEU_CSR_ROE_HDR1_POR_VALUE;
844
845 csr_db[reg_addr]->data->val = PEU_CSR_ROE_HDR1_POR_VALUE;
846
847 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
848 notify (*(csr_db[reg_addr]->data->events[i]));
849 }
850
851 reg_addr = PEU_CSR_A_ROE_HDR2_HW_ADDR;
852 if (csr_db[reg_addr] == NULL) {
853 csr_db[reg_addr] = new csr_data_intf<DATA> ();
854 csr_db[reg_addr]->data = new csr_data<DATA> ();
855 }
856
857 csr_db[reg_addr]->rd_mask = PEU_CSR_ROE_HDR2_READ_MASK;
858 csr_db[reg_addr]->wr_mask = PEU_CSR_ROE_HDR2_WRITE_MASK;
859 csr_db[reg_addr]->clr_mask = PEU_CSR_ROE_HDR2_CLEAR_MASK;
860 csr_db[reg_addr]->set_mask = PEU_CSR_ROE_HDR2_SET_MASK;
861 csr_db[reg_addr]->toggle_mask = PEU_CSR_ROE_HDR2_TOGGLE_MASK;
862 csr_db[reg_addr]->por_val = PEU_CSR_ROE_HDR2_POR_VALUE;
863
864 csr_db[reg_addr]->data->val = PEU_CSR_ROE_HDR2_POR_VALUE;
865
866 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
867 notify (*(csr_db[reg_addr]->data->events[i]));
868 }
869
870 reg_addr = PEU_CSR_B_ROE_HDR2_HW_ADDR;
871 if (csr_db[reg_addr] == NULL) {
872 csr_db[reg_addr] = new csr_data_intf<DATA> ();
873 csr_db[reg_addr]->data = new csr_data<DATA> ();
874 }
875
876 csr_db[reg_addr]->rd_mask = PEU_CSR_ROE_HDR2_READ_MASK;
877 csr_db[reg_addr]->wr_mask = PEU_CSR_ROE_HDR2_WRITE_MASK;
878 csr_db[reg_addr]->clr_mask = PEU_CSR_ROE_HDR2_CLEAR_MASK;
879 csr_db[reg_addr]->set_mask = PEU_CSR_ROE_HDR2_SET_MASK;
880 csr_db[reg_addr]->toggle_mask = PEU_CSR_ROE_HDR2_TOGGLE_MASK;
881 csr_db[reg_addr]->por_val = PEU_CSR_ROE_HDR2_POR_VALUE;
882
883 csr_db[reg_addr]->data->val = PEU_CSR_ROE_HDR2_POR_VALUE;
884
885 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
886 notify (*(csr_db[reg_addr]->data->events[i]));
887 }
888
889 reg_addr = PEU_CSR_A_TOE_HDR1_HW_ADDR;
890 if (csr_db[reg_addr] == NULL) {
891 csr_db[reg_addr] = new csr_data_intf<DATA> ();
892 csr_db[reg_addr]->data = new csr_data<DATA> ();
893 }
894
895 csr_db[reg_addr]->rd_mask = PEU_CSR_TOE_HDR1_READ_MASK;
896 csr_db[reg_addr]->wr_mask = PEU_CSR_TOE_HDR1_WRITE_MASK;
897 csr_db[reg_addr]->clr_mask = PEU_CSR_TOE_HDR1_CLEAR_MASK;
898 csr_db[reg_addr]->set_mask = PEU_CSR_TOE_HDR1_SET_MASK;
899 csr_db[reg_addr]->toggle_mask = PEU_CSR_TOE_HDR1_TOGGLE_MASK;
900 csr_db[reg_addr]->por_val = PEU_CSR_TOE_HDR1_POR_VALUE;
901
902 csr_db[reg_addr]->data->val = PEU_CSR_TOE_HDR1_POR_VALUE;
903
904 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
905 notify (*(csr_db[reg_addr]->data->events[i]));
906 }
907
908 reg_addr = PEU_CSR_B_TOE_HDR1_HW_ADDR;
909 if (csr_db[reg_addr] == NULL) {
910 csr_db[reg_addr] = new csr_data_intf<DATA> ();
911 csr_db[reg_addr]->data = new csr_data<DATA> ();
912 }
913
914 csr_db[reg_addr]->rd_mask = PEU_CSR_TOE_HDR1_READ_MASK;
915 csr_db[reg_addr]->wr_mask = PEU_CSR_TOE_HDR1_WRITE_MASK;
916 csr_db[reg_addr]->clr_mask = PEU_CSR_TOE_HDR1_CLEAR_MASK;
917 csr_db[reg_addr]->set_mask = PEU_CSR_TOE_HDR1_SET_MASK;
918 csr_db[reg_addr]->toggle_mask = PEU_CSR_TOE_HDR1_TOGGLE_MASK;
919 csr_db[reg_addr]->por_val = PEU_CSR_TOE_HDR1_POR_VALUE;
920
921 csr_db[reg_addr]->data->val = PEU_CSR_TOE_HDR1_POR_VALUE;
922
923 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
924 notify (*(csr_db[reg_addr]->data->events[i]));
925 }
926
927 reg_addr = PEU_CSR_A_TOE_HDR2_HW_ADDR;
928 if (csr_db[reg_addr] == NULL) {
929 csr_db[reg_addr] = new csr_data_intf<DATA> ();
930 csr_db[reg_addr]->data = new csr_data<DATA> ();
931 }
932
933 csr_db[reg_addr]->rd_mask = PEU_CSR_TOE_HDR2_READ_MASK;
934 csr_db[reg_addr]->wr_mask = PEU_CSR_TOE_HDR2_WRITE_MASK;
935 csr_db[reg_addr]->clr_mask = PEU_CSR_TOE_HDR2_CLEAR_MASK;
936 csr_db[reg_addr]->set_mask = PEU_CSR_TOE_HDR2_SET_MASK;
937 csr_db[reg_addr]->toggle_mask = PEU_CSR_TOE_HDR2_TOGGLE_MASK;
938 csr_db[reg_addr]->por_val = PEU_CSR_TOE_HDR2_POR_VALUE;
939
940 csr_db[reg_addr]->data->val = PEU_CSR_TOE_HDR2_POR_VALUE;
941
942 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
943 notify (*(csr_db[reg_addr]->data->events[i]));
944 }
945
946 reg_addr = PEU_CSR_B_TOE_HDR2_HW_ADDR;
947 if (csr_db[reg_addr] == NULL) {
948 csr_db[reg_addr] = new csr_data_intf<DATA> ();
949 csr_db[reg_addr]->data = new csr_data<DATA> ();
950 }
951
952 csr_db[reg_addr]->rd_mask = PEU_CSR_TOE_HDR2_READ_MASK;
953 csr_db[reg_addr]->wr_mask = PEU_CSR_TOE_HDR2_WRITE_MASK;
954 csr_db[reg_addr]->clr_mask = PEU_CSR_TOE_HDR2_CLEAR_MASK;
955 csr_db[reg_addr]->set_mask = PEU_CSR_TOE_HDR2_SET_MASK;
956 csr_db[reg_addr]->toggle_mask = PEU_CSR_TOE_HDR2_TOGGLE_MASK;
957 csr_db[reg_addr]->por_val = PEU_CSR_TOE_HDR2_POR_VALUE;
958
959 csr_db[reg_addr]->data->val = PEU_CSR_TOE_HDR2_POR_VALUE;
960
961 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
962 notify (*(csr_db[reg_addr]->data->events[i]));
963 }
964
965 reg_addr = PEU_CSR_A_TLU_PRFC_HW_ADDR;
966 if (csr_db[reg_addr] == NULL) {
967 csr_db[reg_addr] = new csr_data_intf<DATA> ();
968 csr_db[reg_addr]->data = new csr_data<DATA> ();
969 }
970
971 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_PRFC_READ_MASK;
972 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_PRFC_WRITE_MASK;
973 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_PRFC_CLEAR_MASK;
974 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_PRFC_SET_MASK;
975 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_PRFC_TOGGLE_MASK;
976 csr_db[reg_addr]->por_val = PEU_CSR_TLU_PRFC_POR_VALUE;
977
978 csr_db[reg_addr]->data->val = PEU_CSR_TLU_PRFC_POR_VALUE;
979
980 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
981 notify (*(csr_db[reg_addr]->data->events[i]));
982 }
983
984 reg_addr = PEU_CSR_B_TLU_PRFC_HW_ADDR;
985 if (csr_db[reg_addr] == NULL) {
986 csr_db[reg_addr] = new csr_data_intf<DATA> ();
987 csr_db[reg_addr]->data = new csr_data<DATA> ();
988 }
989
990 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_PRFC_READ_MASK;
991 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_PRFC_WRITE_MASK;
992 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_PRFC_CLEAR_MASK;
993 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_PRFC_SET_MASK;
994 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_PRFC_TOGGLE_MASK;
995 csr_db[reg_addr]->por_val = PEU_CSR_TLU_PRFC_POR_VALUE;
996
997 csr_db[reg_addr]->data->val = PEU_CSR_TLU_PRFC_POR_VALUE;
998
999 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1000 notify (*(csr_db[reg_addr]->data->events[i]));
1001 }
1002
1003 reg_addr = PEU_CSR_A_TLU_PRF0_HW_ADDR;
1004 if (csr_db[reg_addr] == NULL) {
1005 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1006 csr_db[reg_addr]->data = new csr_data<DATA> ();
1007 }
1008
1009 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_PRF0_READ_MASK;
1010 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_PRF0_WRITE_MASK;
1011 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_PRF0_CLEAR_MASK;
1012 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_PRF0_SET_MASK;
1013 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_PRF0_TOGGLE_MASK;
1014 csr_db[reg_addr]->por_val = PEU_CSR_TLU_PRF0_POR_VALUE;
1015
1016 csr_db[reg_addr]->data->val = PEU_CSR_TLU_PRF0_POR_VALUE;
1017
1018 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1019 notify (*(csr_db[reg_addr]->data->events[i]));
1020 }
1021
1022 reg_addr = PEU_CSR_B_TLU_PRF0_HW_ADDR;
1023 if (csr_db[reg_addr] == NULL) {
1024 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1025 csr_db[reg_addr]->data = new csr_data<DATA> ();
1026 }
1027
1028 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_PRF0_READ_MASK;
1029 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_PRF0_WRITE_MASK;
1030 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_PRF0_CLEAR_MASK;
1031 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_PRF0_SET_MASK;
1032 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_PRF0_TOGGLE_MASK;
1033 csr_db[reg_addr]->por_val = PEU_CSR_TLU_PRF0_POR_VALUE;
1034
1035 csr_db[reg_addr]->data->val = PEU_CSR_TLU_PRF0_POR_VALUE;
1036
1037 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1038 notify (*(csr_db[reg_addr]->data->events[i]));
1039 }
1040
1041 reg_addr = PEU_CSR_A_TLU_PRF1_HW_ADDR;
1042 if (csr_db[reg_addr] == NULL) {
1043 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1044 csr_db[reg_addr]->data = new csr_data<DATA> ();
1045 }
1046
1047 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_PRF1_READ_MASK;
1048 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_PRF1_WRITE_MASK;
1049 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_PRF1_CLEAR_MASK;
1050 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_PRF1_SET_MASK;
1051 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_PRF1_TOGGLE_MASK;
1052 csr_db[reg_addr]->por_val = PEU_CSR_TLU_PRF1_POR_VALUE;
1053
1054 csr_db[reg_addr]->data->val = PEU_CSR_TLU_PRF1_POR_VALUE;
1055
1056 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1057 notify (*(csr_db[reg_addr]->data->events[i]));
1058 }
1059
1060 reg_addr = PEU_CSR_B_TLU_PRF1_HW_ADDR;
1061 if (csr_db[reg_addr] == NULL) {
1062 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1063 csr_db[reg_addr]->data = new csr_data<DATA> ();
1064 }
1065
1066 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_PRF1_READ_MASK;
1067 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_PRF1_WRITE_MASK;
1068 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_PRF1_CLEAR_MASK;
1069 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_PRF1_SET_MASK;
1070 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_PRF1_TOGGLE_MASK;
1071 csr_db[reg_addr]->por_val = PEU_CSR_TLU_PRF1_POR_VALUE;
1072
1073 csr_db[reg_addr]->data->val = PEU_CSR_TLU_PRF1_POR_VALUE;
1074
1075 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1076 notify (*(csr_db[reg_addr]->data->events[i]));
1077 }
1078
1079 reg_addr = PEU_CSR_A_TLU_PRF2_HW_ADDR;
1080 if (csr_db[reg_addr] == NULL) {
1081 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1082 csr_db[reg_addr]->data = new csr_data<DATA> ();
1083 }
1084
1085 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_PRF2_READ_MASK;
1086 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_PRF2_WRITE_MASK;
1087 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_PRF2_CLEAR_MASK;
1088 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_PRF2_SET_MASK;
1089 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_PRF2_TOGGLE_MASK;
1090 csr_db[reg_addr]->por_val = PEU_CSR_TLU_PRF2_POR_VALUE;
1091
1092 csr_db[reg_addr]->data->val = PEU_CSR_TLU_PRF2_POR_VALUE;
1093
1094 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1095 notify (*(csr_db[reg_addr]->data->events[i]));
1096 }
1097
1098 reg_addr = PEU_CSR_B_TLU_PRF2_HW_ADDR;
1099 if (csr_db[reg_addr] == NULL) {
1100 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1101 csr_db[reg_addr]->data = new csr_data<DATA> ();
1102 }
1103
1104 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_PRF2_READ_MASK;
1105 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_PRF2_WRITE_MASK;
1106 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_PRF2_CLEAR_MASK;
1107 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_PRF2_SET_MASK;
1108 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_PRF2_TOGGLE_MASK;
1109 csr_db[reg_addr]->por_val = PEU_CSR_TLU_PRF2_POR_VALUE;
1110
1111 csr_db[reg_addr]->data->val = PEU_CSR_TLU_PRF2_POR_VALUE;
1112
1113 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1114 notify (*(csr_db[reg_addr]->data->events[i]));
1115 }
1116
1117 reg_addr = PEU_CSR_A_TLU_DBG_SEL_A_HW_ADDR;
1118 if (csr_db[reg_addr] == NULL) {
1119 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1120 csr_db[reg_addr]->data = new csr_data<DATA> ();
1121 }
1122
1123 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_DBG_SEL_A_READ_MASK;
1124 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_DBG_SEL_A_WRITE_MASK;
1125 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_DBG_SEL_A_CLEAR_MASK;
1126 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_DBG_SEL_A_SET_MASK;
1127 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_DBG_SEL_A_TOGGLE_MASK;
1128 csr_db[reg_addr]->por_val = PEU_CSR_TLU_DBG_SEL_A_POR_VALUE;
1129
1130 csr_db[reg_addr]->data->val = PEU_CSR_TLU_DBG_SEL_A_POR_VALUE;
1131
1132 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1133 notify (*(csr_db[reg_addr]->data->events[i]));
1134 }
1135
1136 reg_addr = PEU_CSR_B_TLU_DBG_SEL_A_HW_ADDR;
1137 if (csr_db[reg_addr] == NULL) {
1138 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1139 csr_db[reg_addr]->data = new csr_data<DATA> ();
1140 }
1141
1142 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_DBG_SEL_A_READ_MASK;
1143 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_DBG_SEL_A_WRITE_MASK;
1144 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_DBG_SEL_A_CLEAR_MASK;
1145 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_DBG_SEL_A_SET_MASK;
1146 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_DBG_SEL_A_TOGGLE_MASK;
1147 csr_db[reg_addr]->por_val = PEU_CSR_TLU_DBG_SEL_A_POR_VALUE;
1148
1149 csr_db[reg_addr]->data->val = PEU_CSR_TLU_DBG_SEL_A_POR_VALUE;
1150
1151 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1152 notify (*(csr_db[reg_addr]->data->events[i]));
1153 }
1154
1155 reg_addr = PEU_CSR_A_TLU_DBG_SEL_B_HW_ADDR;
1156 if (csr_db[reg_addr] == NULL) {
1157 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1158 csr_db[reg_addr]->data = new csr_data<DATA> ();
1159 }
1160
1161 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_DBG_SEL_B_READ_MASK;
1162 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_DBG_SEL_B_WRITE_MASK;
1163 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_DBG_SEL_B_CLEAR_MASK;
1164 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_DBG_SEL_B_SET_MASK;
1165 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_DBG_SEL_B_TOGGLE_MASK;
1166 csr_db[reg_addr]->por_val = PEU_CSR_TLU_DBG_SEL_B_POR_VALUE;
1167
1168 csr_db[reg_addr]->data->val = PEU_CSR_TLU_DBG_SEL_B_POR_VALUE;
1169
1170 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1171 notify (*(csr_db[reg_addr]->data->events[i]));
1172 }
1173
1174 reg_addr = PEU_CSR_B_TLU_DBG_SEL_B_HW_ADDR;
1175 if (csr_db[reg_addr] == NULL) {
1176 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1177 csr_db[reg_addr]->data = new csr_data<DATA> ();
1178 }
1179
1180 csr_db[reg_addr]->rd_mask = PEU_CSR_TLU_DBG_SEL_B_READ_MASK;
1181 csr_db[reg_addr]->wr_mask = PEU_CSR_TLU_DBG_SEL_B_WRITE_MASK;
1182 csr_db[reg_addr]->clr_mask = PEU_CSR_TLU_DBG_SEL_B_CLEAR_MASK;
1183 csr_db[reg_addr]->set_mask = PEU_CSR_TLU_DBG_SEL_B_SET_MASK;
1184 csr_db[reg_addr]->toggle_mask = PEU_CSR_TLU_DBG_SEL_B_TOGGLE_MASK;
1185 csr_db[reg_addr]->por_val = PEU_CSR_TLU_DBG_SEL_B_POR_VALUE;
1186
1187 csr_db[reg_addr]->data->val = PEU_CSR_TLU_DBG_SEL_B_POR_VALUE;
1188
1189 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1190 notify (*(csr_db[reg_addr]->data->events[i]));
1191 }
1192
1193 reg_addr = PEU_CSR_A_DEV_CAP_HW_ADDR;
1194 if (csr_db[reg_addr] == NULL) {
1195 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1196 csr_db[reg_addr]->data = new csr_data<DATA> ();
1197 }
1198
1199 csr_db[reg_addr]->rd_mask = PEU_CSR_DEV_CAP_READ_MASK;
1200 csr_db[reg_addr]->wr_mask = PEU_CSR_DEV_CAP_WRITE_MASK;
1201 csr_db[reg_addr]->clr_mask = PEU_CSR_DEV_CAP_CLEAR_MASK;
1202 csr_db[reg_addr]->set_mask = PEU_CSR_DEV_CAP_SET_MASK;
1203 csr_db[reg_addr]->toggle_mask = PEU_CSR_DEV_CAP_TOGGLE_MASK;
1204 csr_db[reg_addr]->por_val = PEU_CSR_DEV_CAP_POR_VALUE;
1205
1206 csr_db[reg_addr]->data->val = PEU_CSR_DEV_CAP_POR_VALUE;
1207
1208 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1209 notify (*(csr_db[reg_addr]->data->events[i]));
1210 }
1211
1212 reg_addr = PEU_CSR_B_DEV_CAP_HW_ADDR;
1213 if (csr_db[reg_addr] == NULL) {
1214 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1215 csr_db[reg_addr]->data = new csr_data<DATA> ();
1216 }
1217
1218 csr_db[reg_addr]->rd_mask = PEU_CSR_DEV_CAP_READ_MASK;
1219 csr_db[reg_addr]->wr_mask = PEU_CSR_DEV_CAP_WRITE_MASK;
1220 csr_db[reg_addr]->clr_mask = PEU_CSR_DEV_CAP_CLEAR_MASK;
1221 csr_db[reg_addr]->set_mask = PEU_CSR_DEV_CAP_SET_MASK;
1222 csr_db[reg_addr]->toggle_mask = PEU_CSR_DEV_CAP_TOGGLE_MASK;
1223 csr_db[reg_addr]->por_val = PEU_CSR_DEV_CAP_POR_VALUE;
1224
1225 csr_db[reg_addr]->data->val = PEU_CSR_DEV_CAP_POR_VALUE;
1226
1227 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1228 notify (*(csr_db[reg_addr]->data->events[i]));
1229 }
1230
1231 reg_addr = PEU_CSR_A_DEV_CTL_HW_ADDR;
1232 if (csr_db[reg_addr] == NULL) {
1233 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1234 csr_db[reg_addr]->data = new csr_data<DATA> ();
1235 }
1236
1237 csr_db[reg_addr]->rd_mask = PEU_CSR_DEV_CTL_READ_MASK;
1238 csr_db[reg_addr]->wr_mask = PEU_CSR_DEV_CTL_WRITE_MASK;
1239 csr_db[reg_addr]->clr_mask = PEU_CSR_DEV_CTL_CLEAR_MASK;
1240 csr_db[reg_addr]->set_mask = PEU_CSR_DEV_CTL_SET_MASK;
1241 csr_db[reg_addr]->toggle_mask = PEU_CSR_DEV_CTL_TOGGLE_MASK;
1242 csr_db[reg_addr]->por_val = PEU_CSR_DEV_CTL_POR_VALUE;
1243
1244 csr_db[reg_addr]->data->val = PEU_CSR_DEV_CTL_POR_VALUE;
1245
1246 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1247 notify (*(csr_db[reg_addr]->data->events[i]));
1248 }
1249
1250 reg_addr = PEU_CSR_B_DEV_CTL_HW_ADDR;
1251 if (csr_db[reg_addr] == NULL) {
1252 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1253 csr_db[reg_addr]->data = new csr_data<DATA> ();
1254 }
1255
1256 csr_db[reg_addr]->rd_mask = PEU_CSR_DEV_CTL_READ_MASK;
1257 csr_db[reg_addr]->wr_mask = PEU_CSR_DEV_CTL_WRITE_MASK;
1258 csr_db[reg_addr]->clr_mask = PEU_CSR_DEV_CTL_CLEAR_MASK;
1259 csr_db[reg_addr]->set_mask = PEU_CSR_DEV_CTL_SET_MASK;
1260 csr_db[reg_addr]->toggle_mask = PEU_CSR_DEV_CTL_TOGGLE_MASK;
1261 csr_db[reg_addr]->por_val = PEU_CSR_DEV_CTL_POR_VALUE;
1262
1263 csr_db[reg_addr]->data->val = PEU_CSR_DEV_CTL_POR_VALUE;
1264
1265 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1266 notify (*(csr_db[reg_addr]->data->events[i]));
1267 }
1268
1269 reg_addr = PEU_CSR_A_DEV_STS_HW_ADDR;
1270 if (csr_db[reg_addr] == NULL) {
1271 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1272 csr_db[reg_addr]->data = new csr_data<DATA> ();
1273 }
1274
1275 csr_db[reg_addr]->rd_mask = PEU_CSR_DEV_STS_READ_MASK;
1276 csr_db[reg_addr]->wr_mask = PEU_CSR_DEV_STS_WRITE_MASK;
1277 csr_db[reg_addr]->clr_mask = PEU_CSR_DEV_STS_CLEAR_MASK;
1278 csr_db[reg_addr]->set_mask = PEU_CSR_DEV_STS_SET_MASK;
1279 csr_db[reg_addr]->toggle_mask = PEU_CSR_DEV_STS_TOGGLE_MASK;
1280 csr_db[reg_addr]->por_val = PEU_CSR_DEV_STS_POR_VALUE;
1281
1282 csr_db[reg_addr]->data->val = PEU_CSR_DEV_STS_POR_VALUE;
1283
1284 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1285 notify (*(csr_db[reg_addr]->data->events[i]));
1286 }
1287
1288 reg_addr = PEU_CSR_B_DEV_STS_HW_ADDR;
1289 if (csr_db[reg_addr] == NULL) {
1290 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1291 csr_db[reg_addr]->data = new csr_data<DATA> ();
1292 }
1293
1294 csr_db[reg_addr]->rd_mask = PEU_CSR_DEV_STS_READ_MASK;
1295 csr_db[reg_addr]->wr_mask = PEU_CSR_DEV_STS_WRITE_MASK;
1296 csr_db[reg_addr]->clr_mask = PEU_CSR_DEV_STS_CLEAR_MASK;
1297 csr_db[reg_addr]->set_mask = PEU_CSR_DEV_STS_SET_MASK;
1298 csr_db[reg_addr]->toggle_mask = PEU_CSR_DEV_STS_TOGGLE_MASK;
1299 csr_db[reg_addr]->por_val = PEU_CSR_DEV_STS_POR_VALUE;
1300
1301 csr_db[reg_addr]->data->val = PEU_CSR_DEV_STS_POR_VALUE;
1302
1303 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1304 notify (*(csr_db[reg_addr]->data->events[i]));
1305 }
1306
1307 reg_addr = PEU_CSR_A_LNK_CAP_HW_ADDR;
1308 if (csr_db[reg_addr] == NULL) {
1309 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1310 csr_db[reg_addr]->data = new csr_data<DATA> ();
1311 }
1312
1313 csr_db[reg_addr]->rd_mask = PEU_CSR_LNK_CAP_READ_MASK;
1314 csr_db[reg_addr]->wr_mask = PEU_CSR_LNK_CAP_WRITE_MASK;
1315 csr_db[reg_addr]->clr_mask = PEU_CSR_LNK_CAP_CLEAR_MASK;
1316 csr_db[reg_addr]->set_mask = PEU_CSR_LNK_CAP_SET_MASK;
1317 csr_db[reg_addr]->toggle_mask = PEU_CSR_LNK_CAP_TOGGLE_MASK;
1318 csr_db[reg_addr]->por_val = PEU_CSR_LNK_CAP_POR_VALUE;
1319
1320 csr_db[reg_addr]->data->val = PEU_CSR_LNK_CAP_POR_VALUE;
1321
1322 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1323 notify (*(csr_db[reg_addr]->data->events[i]));
1324 }
1325
1326 reg_addr = PEU_CSR_B_LNK_CAP_HW_ADDR;
1327 if (csr_db[reg_addr] == NULL) {
1328 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1329 csr_db[reg_addr]->data = new csr_data<DATA> ();
1330 }
1331
1332 csr_db[reg_addr]->rd_mask = PEU_CSR_LNK_CAP_READ_MASK;
1333 csr_db[reg_addr]->wr_mask = PEU_CSR_LNK_CAP_WRITE_MASK;
1334 csr_db[reg_addr]->clr_mask = PEU_CSR_LNK_CAP_CLEAR_MASK;
1335 csr_db[reg_addr]->set_mask = PEU_CSR_LNK_CAP_SET_MASK;
1336 csr_db[reg_addr]->toggle_mask = PEU_CSR_LNK_CAP_TOGGLE_MASK;
1337 csr_db[reg_addr]->por_val = PEU_CSR_LNK_CAP_POR_VALUE;
1338
1339 csr_db[reg_addr]->data->val = PEU_CSR_LNK_CAP_POR_VALUE;
1340
1341 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1342 notify (*(csr_db[reg_addr]->data->events[i]));
1343 }
1344
1345 reg_addr = PEU_CSR_A_LNK_CTL_HW_ADDR;
1346 if (csr_db[reg_addr] == NULL) {
1347 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1348 csr_db[reg_addr]->data = new csr_data<DATA> ();
1349 }
1350
1351 csr_db[reg_addr]->rd_mask = PEU_CSR_LNK_CTL_READ_MASK;
1352 csr_db[reg_addr]->wr_mask = PEU_CSR_LNK_CTL_WRITE_MASK;
1353 csr_db[reg_addr]->clr_mask = PEU_CSR_LNK_CTL_CLEAR_MASK;
1354 csr_db[reg_addr]->set_mask = PEU_CSR_LNK_CTL_SET_MASK;
1355 csr_db[reg_addr]->toggle_mask = PEU_CSR_LNK_CTL_TOGGLE_MASK;
1356 csr_db[reg_addr]->por_val = PEU_CSR_LNK_CTL_POR_VALUE;
1357
1358 csr_db[reg_addr]->data->val = PEU_CSR_LNK_CTL_POR_VALUE;
1359
1360 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1361 notify (*(csr_db[reg_addr]->data->events[i]));
1362 }
1363
1364 reg_addr = PEU_CSR_B_LNK_CTL_HW_ADDR;
1365 if (csr_db[reg_addr] == NULL) {
1366 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1367 csr_db[reg_addr]->data = new csr_data<DATA> ();
1368 }
1369
1370 csr_db[reg_addr]->rd_mask = PEU_CSR_LNK_CTL_READ_MASK;
1371 csr_db[reg_addr]->wr_mask = PEU_CSR_LNK_CTL_WRITE_MASK;
1372 csr_db[reg_addr]->clr_mask = PEU_CSR_LNK_CTL_CLEAR_MASK;
1373 csr_db[reg_addr]->set_mask = PEU_CSR_LNK_CTL_SET_MASK;
1374 csr_db[reg_addr]->toggle_mask = PEU_CSR_LNK_CTL_TOGGLE_MASK;
1375 csr_db[reg_addr]->por_val = PEU_CSR_LNK_CTL_POR_VALUE;
1376
1377 csr_db[reg_addr]->data->val = PEU_CSR_LNK_CTL_POR_VALUE;
1378
1379 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1380 notify (*(csr_db[reg_addr]->data->events[i]));
1381 }
1382
1383 reg_addr = PEU_CSR_A_LNK_STS_HW_ADDR;
1384 if (csr_db[reg_addr] == NULL) {
1385 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1386 csr_db[reg_addr]->data = new csr_data<DATA> ();
1387 }
1388
1389 csr_db[reg_addr]->rd_mask = PEU_CSR_LNK_STS_READ_MASK;
1390 csr_db[reg_addr]->wr_mask = PEU_CSR_LNK_STS_WRITE_MASK;
1391 csr_db[reg_addr]->clr_mask = PEU_CSR_LNK_STS_CLEAR_MASK;
1392 csr_db[reg_addr]->set_mask = PEU_CSR_LNK_STS_SET_MASK;
1393 csr_db[reg_addr]->toggle_mask = PEU_CSR_LNK_STS_TOGGLE_MASK;
1394 csr_db[reg_addr]->por_val = PEU_CSR_LNK_STS_POR_VALUE;
1395
1396 csr_db[reg_addr]->data->val = PEU_CSR_LNK_STS_POR_VALUE;
1397
1398 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1399 notify (*(csr_db[reg_addr]->data->events[i]));
1400 }
1401
1402 reg_addr = PEU_CSR_B_LNK_STS_HW_ADDR;
1403 if (csr_db[reg_addr] == NULL) {
1404 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1405 csr_db[reg_addr]->data = new csr_data<DATA> ();
1406 }
1407
1408 csr_db[reg_addr]->rd_mask = PEU_CSR_LNK_STS_READ_MASK;
1409 csr_db[reg_addr]->wr_mask = PEU_CSR_LNK_STS_WRITE_MASK;
1410 csr_db[reg_addr]->clr_mask = PEU_CSR_LNK_STS_CLEAR_MASK;
1411 csr_db[reg_addr]->set_mask = PEU_CSR_LNK_STS_SET_MASK;
1412 csr_db[reg_addr]->toggle_mask = PEU_CSR_LNK_STS_TOGGLE_MASK;
1413 csr_db[reg_addr]->por_val = PEU_CSR_LNK_STS_POR_VALUE;
1414
1415 csr_db[reg_addr]->data->val = PEU_CSR_LNK_STS_POR_VALUE;
1416
1417 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1418 notify (*(csr_db[reg_addr]->data->events[i]));
1419 }
1420
1421 reg_addr = PEU_CSR_A_SLT_CAP_HW_ADDR;
1422 if (csr_db[reg_addr] == NULL) {
1423 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1424 csr_db[reg_addr]->data = new csr_data<DATA> ();
1425 }
1426
1427 csr_db[reg_addr]->rd_mask = PEU_CSR_SLT_CAP_READ_MASK;
1428 csr_db[reg_addr]->wr_mask = PEU_CSR_SLT_CAP_WRITE_MASK;
1429 csr_db[reg_addr]->clr_mask = PEU_CSR_SLT_CAP_CLEAR_MASK;
1430 csr_db[reg_addr]->set_mask = PEU_CSR_SLT_CAP_SET_MASK;
1431 csr_db[reg_addr]->toggle_mask = PEU_CSR_SLT_CAP_TOGGLE_MASK;
1432 csr_db[reg_addr]->por_val = PEU_CSR_SLT_CAP_POR_VALUE;
1433
1434 csr_db[reg_addr]->data->val = PEU_CSR_SLT_CAP_POR_VALUE;
1435
1436 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1437 notify (*(csr_db[reg_addr]->data->events[i]));
1438 }
1439
1440 reg_addr = PEU_CSR_B_SLT_CAP_HW_ADDR;
1441 if (csr_db[reg_addr] == NULL) {
1442 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1443 csr_db[reg_addr]->data = new csr_data<DATA> ();
1444 }
1445
1446 csr_db[reg_addr]->rd_mask = PEU_CSR_SLT_CAP_READ_MASK;
1447 csr_db[reg_addr]->wr_mask = PEU_CSR_SLT_CAP_WRITE_MASK;
1448 csr_db[reg_addr]->clr_mask = PEU_CSR_SLT_CAP_CLEAR_MASK;
1449 csr_db[reg_addr]->set_mask = PEU_CSR_SLT_CAP_SET_MASK;
1450 csr_db[reg_addr]->toggle_mask = PEU_CSR_SLT_CAP_TOGGLE_MASK;
1451 csr_db[reg_addr]->por_val = PEU_CSR_SLT_CAP_POR_VALUE;
1452
1453 csr_db[reg_addr]->data->val = PEU_CSR_SLT_CAP_POR_VALUE;
1454
1455 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1456 notify (*(csr_db[reg_addr]->data->events[i]));
1457 }
1458
1459 reg_addr = PEU_CSR_A_UE_LOG_HW_ADDR;
1460 if (csr_db[reg_addr] == NULL) {
1461 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1462 csr_db[reg_addr]->data = new csr_data<DATA> ();
1463 }
1464
1465 csr_db[reg_addr]->rd_mask = PEU_CSR_UE_LOG_READ_MASK;
1466 csr_db[reg_addr]->wr_mask = PEU_CSR_UE_LOG_WRITE_MASK;
1467 csr_db[reg_addr]->clr_mask = PEU_CSR_UE_LOG_CLEAR_MASK;
1468 csr_db[reg_addr]->set_mask = PEU_CSR_UE_LOG_SET_MASK;
1469 csr_db[reg_addr]->toggle_mask = PEU_CSR_UE_LOG_TOGGLE_MASK;
1470 csr_db[reg_addr]->por_val = PEU_CSR_UE_LOG_POR_VALUE;
1471
1472 csr_db[reg_addr]->data->val = PEU_CSR_UE_LOG_POR_VALUE;
1473
1474 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1475 notify (*(csr_db[reg_addr]->data->events[i]));
1476 }
1477
1478 reg_addr = PEU_CSR_B_UE_LOG_HW_ADDR;
1479 if (csr_db[reg_addr] == NULL) {
1480 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1481 csr_db[reg_addr]->data = new csr_data<DATA> ();
1482 }
1483
1484 csr_db[reg_addr]->rd_mask = PEU_CSR_UE_LOG_READ_MASK;
1485 csr_db[reg_addr]->wr_mask = PEU_CSR_UE_LOG_WRITE_MASK;
1486 csr_db[reg_addr]->clr_mask = PEU_CSR_UE_LOG_CLEAR_MASK;
1487 csr_db[reg_addr]->set_mask = PEU_CSR_UE_LOG_SET_MASK;
1488 csr_db[reg_addr]->toggle_mask = PEU_CSR_UE_LOG_TOGGLE_MASK;
1489 csr_db[reg_addr]->por_val = PEU_CSR_UE_LOG_POR_VALUE;
1490
1491 csr_db[reg_addr]->data->val = PEU_CSR_UE_LOG_POR_VALUE;
1492
1493 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1494 notify (*(csr_db[reg_addr]->data->events[i]));
1495 }
1496
1497 reg_addr = PEU_CSR_A_UE_INT_EN_HW_ADDR;
1498 if (csr_db[reg_addr] == NULL) {
1499 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1500 csr_db[reg_addr]->data = new csr_data<DATA> ();
1501 }
1502
1503 csr_db[reg_addr]->rd_mask = PEU_CSR_UE_INT_EN_READ_MASK;
1504 csr_db[reg_addr]->wr_mask = PEU_CSR_UE_INT_EN_WRITE_MASK;
1505 csr_db[reg_addr]->clr_mask = PEU_CSR_UE_INT_EN_CLEAR_MASK;
1506 csr_db[reg_addr]->set_mask = PEU_CSR_UE_INT_EN_SET_MASK;
1507 csr_db[reg_addr]->toggle_mask = PEU_CSR_UE_INT_EN_TOGGLE_MASK;
1508 csr_db[reg_addr]->por_val = PEU_CSR_UE_INT_EN_POR_VALUE;
1509
1510 csr_db[reg_addr]->data->val = PEU_CSR_UE_INT_EN_POR_VALUE;
1511
1512 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1513 notify (*(csr_db[reg_addr]->data->events[i]));
1514 }
1515
1516 reg_addr = PEU_CSR_B_UE_INT_EN_HW_ADDR;
1517 if (csr_db[reg_addr] == NULL) {
1518 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1519 csr_db[reg_addr]->data = new csr_data<DATA> ();
1520 }
1521
1522 csr_db[reg_addr]->rd_mask = PEU_CSR_UE_INT_EN_READ_MASK;
1523 csr_db[reg_addr]->wr_mask = PEU_CSR_UE_INT_EN_WRITE_MASK;
1524 csr_db[reg_addr]->clr_mask = PEU_CSR_UE_INT_EN_CLEAR_MASK;
1525 csr_db[reg_addr]->set_mask = PEU_CSR_UE_INT_EN_SET_MASK;
1526 csr_db[reg_addr]->toggle_mask = PEU_CSR_UE_INT_EN_TOGGLE_MASK;
1527 csr_db[reg_addr]->por_val = PEU_CSR_UE_INT_EN_POR_VALUE;
1528
1529 csr_db[reg_addr]->data->val = PEU_CSR_UE_INT_EN_POR_VALUE;
1530
1531 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1532 notify (*(csr_db[reg_addr]->data->events[i]));
1533 }
1534
1535 reg_addr = PEU_CSR_A_UE_EN_ERR_HW_ADDR;
1536 if (csr_db[reg_addr] == NULL) {
1537 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1538 csr_db[reg_addr]->data = new csr_data<DATA> ();
1539 }
1540
1541 csr_db[reg_addr]->rd_mask = PEU_CSR_UE_EN_ERR_READ_MASK;
1542 csr_db[reg_addr]->wr_mask = PEU_CSR_UE_EN_ERR_WRITE_MASK;
1543 csr_db[reg_addr]->clr_mask = PEU_CSR_UE_EN_ERR_CLEAR_MASK;
1544 csr_db[reg_addr]->set_mask = PEU_CSR_UE_EN_ERR_SET_MASK;
1545 csr_db[reg_addr]->toggle_mask = PEU_CSR_UE_EN_ERR_TOGGLE_MASK;
1546 csr_db[reg_addr]->por_val = PEU_CSR_UE_EN_ERR_POR_VALUE;
1547
1548 csr_db[reg_addr]->data->val = PEU_CSR_UE_EN_ERR_POR_VALUE;
1549
1550 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1551 notify (*(csr_db[reg_addr]->data->events[i]));
1552 }
1553
1554 reg_addr = PEU_CSR_B_UE_EN_ERR_HW_ADDR;
1555 if (csr_db[reg_addr] == NULL) {
1556 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1557 csr_db[reg_addr]->data = new csr_data<DATA> ();
1558 }
1559
1560 csr_db[reg_addr]->rd_mask = PEU_CSR_UE_EN_ERR_READ_MASK;
1561 csr_db[reg_addr]->wr_mask = PEU_CSR_UE_EN_ERR_WRITE_MASK;
1562 csr_db[reg_addr]->clr_mask = PEU_CSR_UE_EN_ERR_CLEAR_MASK;
1563 csr_db[reg_addr]->set_mask = PEU_CSR_UE_EN_ERR_SET_MASK;
1564 csr_db[reg_addr]->toggle_mask = PEU_CSR_UE_EN_ERR_TOGGLE_MASK;
1565 csr_db[reg_addr]->por_val = PEU_CSR_UE_EN_ERR_POR_VALUE;
1566
1567 csr_db[reg_addr]->data->val = PEU_CSR_UE_EN_ERR_POR_VALUE;
1568
1569 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1570 notify (*(csr_db[reg_addr]->data->events[i]));
1571 }
1572
1573 reg_addr = PEU_CSR_A_UE_ERR_RW1C_ALIAS_HW_ADDR;
1574 if (csr_db[reg_addr] == NULL) {
1575 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1576 csr_db[reg_addr]->data = new csr_data<DATA> ();
1577 }
1578
1579 csr_db[reg_addr]->rd_mask = PEU_CSR_UE_ERR_RW1C_ALIAS_READ_MASK;
1580 csr_db[reg_addr]->wr_mask = PEU_CSR_UE_ERR_RW1C_ALIAS_WRITE_MASK;
1581 csr_db[reg_addr]->clr_mask = PEU_CSR_UE_ERR_RW1C_ALIAS_CLEAR_MASK;
1582 csr_db[reg_addr]->set_mask = PEU_CSR_UE_ERR_RW1C_ALIAS_SET_MASK;
1583 csr_db[reg_addr]->toggle_mask = PEU_CSR_UE_ERR_RW1C_ALIAS_TOGGLE_MASK;
1584 csr_db[reg_addr]->por_val = PEU_CSR_UE_ERR_RW1C_ALIAS_POR_VALUE;
1585
1586 csr_db[reg_addr]->data->val = PEU_CSR_UE_ERR_RW1C_ALIAS_POR_VALUE;
1587 csr_db[reg_addr]->intf_type = WRITE1_CLEAR;
1588 csr_db[reg_addr]->sw_reset_val_hold = false;
1589
1590 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1591 notify (*(csr_db[reg_addr]->data->events[i]));
1592 }
1593
1594 reg_addr = PEU_CSR_B_UE_ERR_RW1C_ALIAS_HW_ADDR;
1595 if (csr_db[reg_addr] == NULL) {
1596 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1597 csr_db[reg_addr]->data = new csr_data<DATA> ();
1598 }
1599
1600 csr_db[reg_addr]->rd_mask = PEU_CSR_UE_ERR_RW1C_ALIAS_READ_MASK;
1601 csr_db[reg_addr]->wr_mask = PEU_CSR_UE_ERR_RW1C_ALIAS_WRITE_MASK;
1602 csr_db[reg_addr]->clr_mask = PEU_CSR_UE_ERR_RW1C_ALIAS_CLEAR_MASK;
1603 csr_db[reg_addr]->set_mask = PEU_CSR_UE_ERR_RW1C_ALIAS_SET_MASK;
1604 csr_db[reg_addr]->toggle_mask = PEU_CSR_UE_ERR_RW1C_ALIAS_TOGGLE_MASK;
1605 csr_db[reg_addr]->por_val = PEU_CSR_UE_ERR_RW1C_ALIAS_POR_VALUE;
1606
1607 csr_db[reg_addr]->data->val = PEU_CSR_UE_ERR_RW1C_ALIAS_POR_VALUE;
1608 csr_db[reg_addr]->intf_type = WRITE1_CLEAR;
1609 csr_db[reg_addr]->sw_reset_val_hold = false;
1610
1611 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1612 notify (*(csr_db[reg_addr]->data->events[i]));
1613 }
1614
1615 reg_addr = PEU_CSR_A_UE_ERR_RW1S_ALIAS_HW_ADDR;
1616 if (csr_db[reg_addr] == NULL) {
1617 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1618 csr_db[reg_addr]->data = csr_db[PEU_CSR_A_UE_ERR_RW1C_ALIAS_HW_ADDR]->data;
1619 }
1620
1621 csr_db[reg_addr]->rd_mask = PEU_CSR_UE_ERR_RW1S_ALIAS_READ_MASK;
1622 csr_db[reg_addr]->wr_mask = PEU_CSR_UE_ERR_RW1S_ALIAS_WRITE_MASK;
1623 csr_db[reg_addr]->clr_mask = PEU_CSR_UE_ERR_RW1S_ALIAS_CLEAR_MASK;
1624 csr_db[reg_addr]->set_mask = PEU_CSR_UE_ERR_RW1S_ALIAS_SET_MASK;
1625 csr_db[reg_addr]->toggle_mask = PEU_CSR_UE_ERR_RW1S_ALIAS_TOGGLE_MASK;
1626 csr_db[reg_addr]->por_val = PEU_CSR_UE_ERR_RW1S_ALIAS_POR_VALUE;
1627
1628 csr_db[reg_addr]->data->val = PEU_CSR_UE_ERR_RW1S_ALIAS_POR_VALUE;
1629 csr_db[reg_addr]->intf_type = WRITE1_SET;
1630 csr_db[reg_addr]->sw_reset_val_hold = false;
1631
1632 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1633 notify (*(csr_db[reg_addr]->data->events[i]));
1634 }
1635
1636 reg_addr = PEU_CSR_B_UE_ERR_RW1S_ALIAS_HW_ADDR;
1637 if (csr_db[reg_addr] == NULL) {
1638 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1639 csr_db[reg_addr]->data = csr_db[PEU_CSR_B_UE_ERR_RW1C_ALIAS_HW_ADDR]->data;
1640 }
1641
1642 csr_db[reg_addr]->rd_mask = PEU_CSR_UE_ERR_RW1S_ALIAS_READ_MASK;
1643 csr_db[reg_addr]->wr_mask = PEU_CSR_UE_ERR_RW1S_ALIAS_WRITE_MASK;
1644 csr_db[reg_addr]->clr_mask = PEU_CSR_UE_ERR_RW1S_ALIAS_CLEAR_MASK;
1645 csr_db[reg_addr]->set_mask = PEU_CSR_UE_ERR_RW1S_ALIAS_SET_MASK;
1646 csr_db[reg_addr]->toggle_mask = PEU_CSR_UE_ERR_RW1S_ALIAS_TOGGLE_MASK;
1647 csr_db[reg_addr]->por_val = PEU_CSR_UE_ERR_RW1S_ALIAS_POR_VALUE;
1648
1649 csr_db[reg_addr]->data->val = PEU_CSR_UE_ERR_RW1S_ALIAS_POR_VALUE;
1650 csr_db[reg_addr]->intf_type = WRITE1_SET;
1651 csr_db[reg_addr]->sw_reset_val_hold = false;
1652
1653 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1654 notify (*(csr_db[reg_addr]->data->events[i]));
1655 }
1656
1657 reg_addr = PEU_CSR_A_RUE_HDR1_HW_ADDR;
1658 if (csr_db[reg_addr] == NULL) {
1659 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1660 csr_db[reg_addr]->data = new csr_data<DATA> ();
1661 }
1662
1663 csr_db[reg_addr]->rd_mask = PEU_CSR_RUE_HDR1_READ_MASK;
1664 csr_db[reg_addr]->wr_mask = PEU_CSR_RUE_HDR1_WRITE_MASK;
1665 csr_db[reg_addr]->clr_mask = PEU_CSR_RUE_HDR1_CLEAR_MASK;
1666 csr_db[reg_addr]->set_mask = PEU_CSR_RUE_HDR1_SET_MASK;
1667 csr_db[reg_addr]->toggle_mask = PEU_CSR_RUE_HDR1_TOGGLE_MASK;
1668 csr_db[reg_addr]->por_val = PEU_CSR_RUE_HDR1_POR_VALUE;
1669
1670 csr_db[reg_addr]->data->val = PEU_CSR_RUE_HDR1_POR_VALUE;
1671
1672 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1673 notify (*(csr_db[reg_addr]->data->events[i]));
1674 }
1675
1676 reg_addr = PEU_CSR_B_RUE_HDR1_HW_ADDR;
1677 if (csr_db[reg_addr] == NULL) {
1678 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1679 csr_db[reg_addr]->data = new csr_data<DATA> ();
1680 }
1681
1682 csr_db[reg_addr]->rd_mask = PEU_CSR_RUE_HDR1_READ_MASK;
1683 csr_db[reg_addr]->wr_mask = PEU_CSR_RUE_HDR1_WRITE_MASK;
1684 csr_db[reg_addr]->clr_mask = PEU_CSR_RUE_HDR1_CLEAR_MASK;
1685 csr_db[reg_addr]->set_mask = PEU_CSR_RUE_HDR1_SET_MASK;
1686 csr_db[reg_addr]->toggle_mask = PEU_CSR_RUE_HDR1_TOGGLE_MASK;
1687 csr_db[reg_addr]->por_val = PEU_CSR_RUE_HDR1_POR_VALUE;
1688
1689 csr_db[reg_addr]->data->val = PEU_CSR_RUE_HDR1_POR_VALUE;
1690
1691 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1692 notify (*(csr_db[reg_addr]->data->events[i]));
1693 }
1694
1695 reg_addr = PEU_CSR_A_RUE_HDR2_HW_ADDR;
1696 if (csr_db[reg_addr] == NULL) {
1697 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1698 csr_db[reg_addr]->data = new csr_data<DATA> ();
1699 }
1700
1701 csr_db[reg_addr]->rd_mask = PEU_CSR_RUE_HDR2_READ_MASK;
1702 csr_db[reg_addr]->wr_mask = PEU_CSR_RUE_HDR2_WRITE_MASK;
1703 csr_db[reg_addr]->clr_mask = PEU_CSR_RUE_HDR2_CLEAR_MASK;
1704 csr_db[reg_addr]->set_mask = PEU_CSR_RUE_HDR2_SET_MASK;
1705 csr_db[reg_addr]->toggle_mask = PEU_CSR_RUE_HDR2_TOGGLE_MASK;
1706 csr_db[reg_addr]->por_val = PEU_CSR_RUE_HDR2_POR_VALUE;
1707
1708 csr_db[reg_addr]->data->val = PEU_CSR_RUE_HDR2_POR_VALUE;
1709
1710 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1711 notify (*(csr_db[reg_addr]->data->events[i]));
1712 }
1713
1714 reg_addr = PEU_CSR_B_RUE_HDR2_HW_ADDR;
1715 if (csr_db[reg_addr] == NULL) {
1716 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1717 csr_db[reg_addr]->data = new csr_data<DATA> ();
1718 }
1719
1720 csr_db[reg_addr]->rd_mask = PEU_CSR_RUE_HDR2_READ_MASK;
1721 csr_db[reg_addr]->wr_mask = PEU_CSR_RUE_HDR2_WRITE_MASK;
1722 csr_db[reg_addr]->clr_mask = PEU_CSR_RUE_HDR2_CLEAR_MASK;
1723 csr_db[reg_addr]->set_mask = PEU_CSR_RUE_HDR2_SET_MASK;
1724 csr_db[reg_addr]->toggle_mask = PEU_CSR_RUE_HDR2_TOGGLE_MASK;
1725 csr_db[reg_addr]->por_val = PEU_CSR_RUE_HDR2_POR_VALUE;
1726
1727 csr_db[reg_addr]->data->val = PEU_CSR_RUE_HDR2_POR_VALUE;
1728
1729 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1730 notify (*(csr_db[reg_addr]->data->events[i]));
1731 }
1732
1733 reg_addr = PEU_CSR_A_TUE_HDR1_HW_ADDR;
1734 if (csr_db[reg_addr] == NULL) {
1735 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1736 csr_db[reg_addr]->data = new csr_data<DATA> ();
1737 }
1738
1739 csr_db[reg_addr]->rd_mask = PEU_CSR_TUE_HDR1_READ_MASK;
1740 csr_db[reg_addr]->wr_mask = PEU_CSR_TUE_HDR1_WRITE_MASK;
1741 csr_db[reg_addr]->clr_mask = PEU_CSR_TUE_HDR1_CLEAR_MASK;
1742 csr_db[reg_addr]->set_mask = PEU_CSR_TUE_HDR1_SET_MASK;
1743 csr_db[reg_addr]->toggle_mask = PEU_CSR_TUE_HDR1_TOGGLE_MASK;
1744 csr_db[reg_addr]->por_val = PEU_CSR_TUE_HDR1_POR_VALUE;
1745
1746 csr_db[reg_addr]->data->val = PEU_CSR_TUE_HDR1_POR_VALUE;
1747
1748 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1749 notify (*(csr_db[reg_addr]->data->events[i]));
1750 }
1751
1752 reg_addr = PEU_CSR_B_TUE_HDR1_HW_ADDR;
1753 if (csr_db[reg_addr] == NULL) {
1754 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1755 csr_db[reg_addr]->data = new csr_data<DATA> ();
1756 }
1757
1758 csr_db[reg_addr]->rd_mask = PEU_CSR_TUE_HDR1_READ_MASK;
1759 csr_db[reg_addr]->wr_mask = PEU_CSR_TUE_HDR1_WRITE_MASK;
1760 csr_db[reg_addr]->clr_mask = PEU_CSR_TUE_HDR1_CLEAR_MASK;
1761 csr_db[reg_addr]->set_mask = PEU_CSR_TUE_HDR1_SET_MASK;
1762 csr_db[reg_addr]->toggle_mask = PEU_CSR_TUE_HDR1_TOGGLE_MASK;
1763 csr_db[reg_addr]->por_val = PEU_CSR_TUE_HDR1_POR_VALUE;
1764
1765 csr_db[reg_addr]->data->val = PEU_CSR_TUE_HDR1_POR_VALUE;
1766
1767 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1768 notify (*(csr_db[reg_addr]->data->events[i]));
1769 }
1770
1771 reg_addr = PEU_CSR_A_TUE_HDR2_HW_ADDR;
1772 if (csr_db[reg_addr] == NULL) {
1773 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1774 csr_db[reg_addr]->data = new csr_data<DATA> ();
1775 }
1776
1777 csr_db[reg_addr]->rd_mask = PEU_CSR_TUE_HDR2_READ_MASK;
1778 csr_db[reg_addr]->wr_mask = PEU_CSR_TUE_HDR2_WRITE_MASK;
1779 csr_db[reg_addr]->clr_mask = PEU_CSR_TUE_HDR2_CLEAR_MASK;
1780 csr_db[reg_addr]->set_mask = PEU_CSR_TUE_HDR2_SET_MASK;
1781 csr_db[reg_addr]->toggle_mask = PEU_CSR_TUE_HDR2_TOGGLE_MASK;
1782 csr_db[reg_addr]->por_val = PEU_CSR_TUE_HDR2_POR_VALUE;
1783
1784 csr_db[reg_addr]->data->val = PEU_CSR_TUE_HDR2_POR_VALUE;
1785
1786 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1787 notify (*(csr_db[reg_addr]->data->events[i]));
1788 }
1789
1790 reg_addr = PEU_CSR_B_TUE_HDR2_HW_ADDR;
1791 if (csr_db[reg_addr] == NULL) {
1792 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1793 csr_db[reg_addr]->data = new csr_data<DATA> ();
1794 }
1795
1796 csr_db[reg_addr]->rd_mask = PEU_CSR_TUE_HDR2_READ_MASK;
1797 csr_db[reg_addr]->wr_mask = PEU_CSR_TUE_HDR2_WRITE_MASK;
1798 csr_db[reg_addr]->clr_mask = PEU_CSR_TUE_HDR2_CLEAR_MASK;
1799 csr_db[reg_addr]->set_mask = PEU_CSR_TUE_HDR2_SET_MASK;
1800 csr_db[reg_addr]->toggle_mask = PEU_CSR_TUE_HDR2_TOGGLE_MASK;
1801 csr_db[reg_addr]->por_val = PEU_CSR_TUE_HDR2_POR_VALUE;
1802
1803 csr_db[reg_addr]->data->val = PEU_CSR_TUE_HDR2_POR_VALUE;
1804
1805 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1806 notify (*(csr_db[reg_addr]->data->events[i]));
1807 }
1808
1809 reg_addr = PEU_CSR_A_CE_LOG_HW_ADDR;
1810 if (csr_db[reg_addr] == NULL) {
1811 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1812 csr_db[reg_addr]->data = new csr_data<DATA> ();
1813 }
1814
1815 csr_db[reg_addr]->rd_mask = PEU_CSR_CE_LOG_READ_MASK;
1816 csr_db[reg_addr]->wr_mask = PEU_CSR_CE_LOG_WRITE_MASK;
1817 csr_db[reg_addr]->clr_mask = PEU_CSR_CE_LOG_CLEAR_MASK;
1818 csr_db[reg_addr]->set_mask = PEU_CSR_CE_LOG_SET_MASK;
1819 csr_db[reg_addr]->toggle_mask = PEU_CSR_CE_LOG_TOGGLE_MASK;
1820 csr_db[reg_addr]->por_val = PEU_CSR_CE_LOG_POR_VALUE;
1821
1822 csr_db[reg_addr]->data->val = PEU_CSR_CE_LOG_POR_VALUE;
1823
1824 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1825 notify (*(csr_db[reg_addr]->data->events[i]));
1826 }
1827
1828 reg_addr = PEU_CSR_B_CE_LOG_HW_ADDR;
1829 if (csr_db[reg_addr] == NULL) {
1830 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1831 csr_db[reg_addr]->data = new csr_data<DATA> ();
1832 }
1833
1834 csr_db[reg_addr]->rd_mask = PEU_CSR_CE_LOG_READ_MASK;
1835 csr_db[reg_addr]->wr_mask = PEU_CSR_CE_LOG_WRITE_MASK;
1836 csr_db[reg_addr]->clr_mask = PEU_CSR_CE_LOG_CLEAR_MASK;
1837 csr_db[reg_addr]->set_mask = PEU_CSR_CE_LOG_SET_MASK;
1838 csr_db[reg_addr]->toggle_mask = PEU_CSR_CE_LOG_TOGGLE_MASK;
1839 csr_db[reg_addr]->por_val = PEU_CSR_CE_LOG_POR_VALUE;
1840
1841 csr_db[reg_addr]->data->val = PEU_CSR_CE_LOG_POR_VALUE;
1842
1843 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1844 notify (*(csr_db[reg_addr]->data->events[i]));
1845 }
1846
1847 reg_addr = PEU_CSR_A_CE_INT_EN_HW_ADDR;
1848 if (csr_db[reg_addr] == NULL) {
1849 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1850 csr_db[reg_addr]->data = new csr_data<DATA> ();
1851 }
1852
1853 csr_db[reg_addr]->rd_mask = PEU_CSR_CE_INT_EN_READ_MASK;
1854 csr_db[reg_addr]->wr_mask = PEU_CSR_CE_INT_EN_WRITE_MASK;
1855 csr_db[reg_addr]->clr_mask = PEU_CSR_CE_INT_EN_CLEAR_MASK;
1856 csr_db[reg_addr]->set_mask = PEU_CSR_CE_INT_EN_SET_MASK;
1857 csr_db[reg_addr]->toggle_mask = PEU_CSR_CE_INT_EN_TOGGLE_MASK;
1858 csr_db[reg_addr]->por_val = PEU_CSR_CE_INT_EN_POR_VALUE;
1859
1860 csr_db[reg_addr]->data->val = PEU_CSR_CE_INT_EN_POR_VALUE;
1861
1862 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1863 notify (*(csr_db[reg_addr]->data->events[i]));
1864 }
1865
1866 reg_addr = PEU_CSR_B_CE_INT_EN_HW_ADDR;
1867 if (csr_db[reg_addr] == NULL) {
1868 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1869 csr_db[reg_addr]->data = new csr_data<DATA> ();
1870 }
1871
1872 csr_db[reg_addr]->rd_mask = PEU_CSR_CE_INT_EN_READ_MASK;
1873 csr_db[reg_addr]->wr_mask = PEU_CSR_CE_INT_EN_WRITE_MASK;
1874 csr_db[reg_addr]->clr_mask = PEU_CSR_CE_INT_EN_CLEAR_MASK;
1875 csr_db[reg_addr]->set_mask = PEU_CSR_CE_INT_EN_SET_MASK;
1876 csr_db[reg_addr]->toggle_mask = PEU_CSR_CE_INT_EN_TOGGLE_MASK;
1877 csr_db[reg_addr]->por_val = PEU_CSR_CE_INT_EN_POR_VALUE;
1878
1879 csr_db[reg_addr]->data->val = PEU_CSR_CE_INT_EN_POR_VALUE;
1880
1881 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1882 notify (*(csr_db[reg_addr]->data->events[i]));
1883 }
1884
1885 reg_addr = PEU_CSR_A_CE_EN_ERR_HW_ADDR;
1886 if (csr_db[reg_addr] == NULL) {
1887 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1888 csr_db[reg_addr]->data = new csr_data<DATA> ();
1889 }
1890
1891 csr_db[reg_addr]->rd_mask = PEU_CSR_CE_EN_ERR_READ_MASK;
1892 csr_db[reg_addr]->wr_mask = PEU_CSR_CE_EN_ERR_WRITE_MASK;
1893 csr_db[reg_addr]->clr_mask = PEU_CSR_CE_EN_ERR_CLEAR_MASK;
1894 csr_db[reg_addr]->set_mask = PEU_CSR_CE_EN_ERR_SET_MASK;
1895 csr_db[reg_addr]->toggle_mask = PEU_CSR_CE_EN_ERR_TOGGLE_MASK;
1896 csr_db[reg_addr]->por_val = PEU_CSR_CE_EN_ERR_POR_VALUE;
1897
1898 csr_db[reg_addr]->data->val = PEU_CSR_CE_EN_ERR_POR_VALUE;
1899
1900 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1901 notify (*(csr_db[reg_addr]->data->events[i]));
1902 }
1903
1904 reg_addr = PEU_CSR_B_CE_EN_ERR_HW_ADDR;
1905 if (csr_db[reg_addr] == NULL) {
1906 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1907 csr_db[reg_addr]->data = new csr_data<DATA> ();
1908 }
1909
1910 csr_db[reg_addr]->rd_mask = PEU_CSR_CE_EN_ERR_READ_MASK;
1911 csr_db[reg_addr]->wr_mask = PEU_CSR_CE_EN_ERR_WRITE_MASK;
1912 csr_db[reg_addr]->clr_mask = PEU_CSR_CE_EN_ERR_CLEAR_MASK;
1913 csr_db[reg_addr]->set_mask = PEU_CSR_CE_EN_ERR_SET_MASK;
1914 csr_db[reg_addr]->toggle_mask = PEU_CSR_CE_EN_ERR_TOGGLE_MASK;
1915 csr_db[reg_addr]->por_val = PEU_CSR_CE_EN_ERR_POR_VALUE;
1916
1917 csr_db[reg_addr]->data->val = PEU_CSR_CE_EN_ERR_POR_VALUE;
1918
1919 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1920 notify (*(csr_db[reg_addr]->data->events[i]));
1921 }
1922
1923 reg_addr = PEU_CSR_A_CE_ERR_RW1C_ALIAS_HW_ADDR;
1924 if (csr_db[reg_addr] == NULL) {
1925 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1926 csr_db[reg_addr]->data = new csr_data<DATA> ();
1927 }
1928
1929 csr_db[reg_addr]->rd_mask = PEU_CSR_CE_ERR_RW1C_ALIAS_READ_MASK;
1930 csr_db[reg_addr]->wr_mask = PEU_CSR_CE_ERR_RW1C_ALIAS_WRITE_MASK;
1931 csr_db[reg_addr]->clr_mask = PEU_CSR_CE_ERR_RW1C_ALIAS_CLEAR_MASK;
1932 csr_db[reg_addr]->set_mask = PEU_CSR_CE_ERR_RW1C_ALIAS_SET_MASK;
1933 csr_db[reg_addr]->toggle_mask = PEU_CSR_CE_ERR_RW1C_ALIAS_TOGGLE_MASK;
1934 csr_db[reg_addr]->por_val = PEU_CSR_CE_ERR_RW1C_ALIAS_POR_VALUE;
1935
1936 csr_db[reg_addr]->data->val = PEU_CSR_CE_ERR_RW1C_ALIAS_POR_VALUE;
1937 csr_db[reg_addr]->intf_type = WRITE1_CLEAR;
1938 csr_db[reg_addr]->sw_reset_val_hold = false;
1939
1940 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1941 notify (*(csr_db[reg_addr]->data->events[i]));
1942 }
1943
1944 reg_addr = PEU_CSR_B_CE_ERR_RW1C_ALIAS_HW_ADDR;
1945 if (csr_db[reg_addr] == NULL) {
1946 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1947 csr_db[reg_addr]->data = new csr_data<DATA> ();
1948 }
1949
1950 csr_db[reg_addr]->rd_mask = PEU_CSR_CE_ERR_RW1C_ALIAS_READ_MASK;
1951 csr_db[reg_addr]->wr_mask = PEU_CSR_CE_ERR_RW1C_ALIAS_WRITE_MASK;
1952 csr_db[reg_addr]->clr_mask = PEU_CSR_CE_ERR_RW1C_ALIAS_CLEAR_MASK;
1953 csr_db[reg_addr]->set_mask = PEU_CSR_CE_ERR_RW1C_ALIAS_SET_MASK;
1954 csr_db[reg_addr]->toggle_mask = PEU_CSR_CE_ERR_RW1C_ALIAS_TOGGLE_MASK;
1955 csr_db[reg_addr]->por_val = PEU_CSR_CE_ERR_RW1C_ALIAS_POR_VALUE;
1956
1957 csr_db[reg_addr]->data->val = PEU_CSR_CE_ERR_RW1C_ALIAS_POR_VALUE;
1958 csr_db[reg_addr]->intf_type = WRITE1_CLEAR;
1959 csr_db[reg_addr]->sw_reset_val_hold = false;
1960
1961 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1962 notify (*(csr_db[reg_addr]->data->events[i]));
1963 }
1964
1965 reg_addr = PEU_CSR_A_CE_ERR_RW1S_ALIAS_HW_ADDR;
1966 if (csr_db[reg_addr] == NULL) {
1967 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1968 csr_db[reg_addr]->data = csr_db[PEU_CSR_A_CE_ERR_RW1C_ALIAS_HW_ADDR]->data;
1969 }
1970
1971 csr_db[reg_addr]->rd_mask = PEU_CSR_CE_ERR_RW1S_ALIAS_READ_MASK;
1972 csr_db[reg_addr]->wr_mask = PEU_CSR_CE_ERR_RW1S_ALIAS_WRITE_MASK;
1973 csr_db[reg_addr]->clr_mask = PEU_CSR_CE_ERR_RW1S_ALIAS_CLEAR_MASK;
1974 csr_db[reg_addr]->set_mask = PEU_CSR_CE_ERR_RW1S_ALIAS_SET_MASK;
1975 csr_db[reg_addr]->toggle_mask = PEU_CSR_CE_ERR_RW1S_ALIAS_TOGGLE_MASK;
1976 csr_db[reg_addr]->por_val = PEU_CSR_CE_ERR_RW1S_ALIAS_POR_VALUE;
1977
1978 csr_db[reg_addr]->data->val = PEU_CSR_CE_ERR_RW1S_ALIAS_POR_VALUE;
1979 csr_db[reg_addr]->intf_type = WRITE1_SET;
1980 csr_db[reg_addr]->sw_reset_val_hold = false;
1981
1982 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
1983 notify (*(csr_db[reg_addr]->data->events[i]));
1984 }
1985
1986 reg_addr = PEU_CSR_B_CE_ERR_RW1S_ALIAS_HW_ADDR;
1987 if (csr_db[reg_addr] == NULL) {
1988 csr_db[reg_addr] = new csr_data_intf<DATA> ();
1989 csr_db[reg_addr]->data = csr_db[PEU_CSR_B_CE_ERR_RW1C_ALIAS_HW_ADDR]->data;
1990 }
1991
1992 csr_db[reg_addr]->rd_mask = PEU_CSR_CE_ERR_RW1S_ALIAS_READ_MASK;
1993 csr_db[reg_addr]->wr_mask = PEU_CSR_CE_ERR_RW1S_ALIAS_WRITE_MASK;
1994 csr_db[reg_addr]->clr_mask = PEU_CSR_CE_ERR_RW1S_ALIAS_CLEAR_MASK;
1995 csr_db[reg_addr]->set_mask = PEU_CSR_CE_ERR_RW1S_ALIAS_SET_MASK;
1996 csr_db[reg_addr]->toggle_mask = PEU_CSR_CE_ERR_RW1S_ALIAS_TOGGLE_MASK;
1997 csr_db[reg_addr]->por_val = PEU_CSR_CE_ERR_RW1S_ALIAS_POR_VALUE;
1998
1999 csr_db[reg_addr]->data->val = PEU_CSR_CE_ERR_RW1S_ALIAS_POR_VALUE;
2000 csr_db[reg_addr]->intf_type = WRITE1_SET;
2001 csr_db[reg_addr]->sw_reset_val_hold = false;
2002
2003 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2004 notify (*(csr_db[reg_addr]->data->events[i]));
2005 }
2006
2007 reg_addr = PEU_CSR_A_PEU_DLPL_SERDES_REV_HW_ADDR;
2008 if (csr_db[reg_addr] == NULL) {
2009 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2010 csr_db[reg_addr]->data = new csr_data<DATA> ();
2011 }
2012
2013 csr_db[reg_addr]->rd_mask = PEU_CSR_PEU_DLPL_SERDES_REV_READ_MASK;
2014 csr_db[reg_addr]->wr_mask = PEU_CSR_PEU_DLPL_SERDES_REV_WRITE_MASK;
2015 csr_db[reg_addr]->clr_mask = PEU_CSR_PEU_DLPL_SERDES_REV_CLEAR_MASK;
2016 csr_db[reg_addr]->set_mask = PEU_CSR_PEU_DLPL_SERDES_REV_SET_MASK;
2017 csr_db[reg_addr]->toggle_mask = PEU_CSR_PEU_DLPL_SERDES_REV_TOGGLE_MASK;
2018 csr_db[reg_addr]->por_val = PEU_CSR_PEU_DLPL_SERDES_REV_POR_VALUE;
2019
2020 csr_db[reg_addr]->data->val = PEU_CSR_PEU_DLPL_SERDES_REV_POR_VALUE;
2021
2022 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2023 notify (*(csr_db[reg_addr]->data->events[i]));
2024 }
2025
2026 reg_addr = PEU_CSR_B_PEU_DLPL_SERDES_REV_HW_ADDR;
2027 if (csr_db[reg_addr] == NULL) {
2028 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2029 csr_db[reg_addr]->data = new csr_data<DATA> ();
2030 }
2031
2032 csr_db[reg_addr]->rd_mask = PEU_CSR_PEU_DLPL_SERDES_REV_READ_MASK;
2033 csr_db[reg_addr]->wr_mask = PEU_CSR_PEU_DLPL_SERDES_REV_WRITE_MASK;
2034 csr_db[reg_addr]->clr_mask = PEU_CSR_PEU_DLPL_SERDES_REV_CLEAR_MASK;
2035 csr_db[reg_addr]->set_mask = PEU_CSR_PEU_DLPL_SERDES_REV_SET_MASK;
2036 csr_db[reg_addr]->toggle_mask = PEU_CSR_PEU_DLPL_SERDES_REV_TOGGLE_MASK;
2037 csr_db[reg_addr]->por_val = PEU_CSR_PEU_DLPL_SERDES_REV_POR_VALUE;
2038
2039 csr_db[reg_addr]->data->val = PEU_CSR_PEU_DLPL_SERDES_REV_POR_VALUE;
2040
2041 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2042 notify (*(csr_db[reg_addr]->data->events[i]));
2043 }
2044
2045 reg_addr = PEU_CSR_A_ACKNAK_THRESH_HW_ADDR;
2046 if (csr_db[reg_addr] == NULL) {
2047 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2048 csr_db[reg_addr]->data = new csr_data<DATA> ();
2049 }
2050
2051 csr_db[reg_addr]->rd_mask = PEU_CSR_ACKNAK_THRESH_READ_MASK;
2052 csr_db[reg_addr]->wr_mask = PEU_CSR_ACKNAK_THRESH_WRITE_MASK;
2053 csr_db[reg_addr]->clr_mask = PEU_CSR_ACKNAK_THRESH_CLEAR_MASK;
2054 csr_db[reg_addr]->set_mask = PEU_CSR_ACKNAK_THRESH_SET_MASK;
2055 csr_db[reg_addr]->toggle_mask = PEU_CSR_ACKNAK_THRESH_TOGGLE_MASK;
2056 csr_db[reg_addr]->por_val = PEU_CSR_ACKNAK_THRESH_POR_VALUE;
2057
2058 csr_db[reg_addr]->data->val = PEU_CSR_ACKNAK_THRESH_POR_VALUE;
2059
2060 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2061 notify (*(csr_db[reg_addr]->data->events[i]));
2062 }
2063
2064 reg_addr = PEU_CSR_B_ACKNAK_THRESH_HW_ADDR;
2065 if (csr_db[reg_addr] == NULL) {
2066 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2067 csr_db[reg_addr]->data = new csr_data<DATA> ();
2068 }
2069
2070 csr_db[reg_addr]->rd_mask = PEU_CSR_ACKNAK_THRESH_READ_MASK;
2071 csr_db[reg_addr]->wr_mask = PEU_CSR_ACKNAK_THRESH_WRITE_MASK;
2072 csr_db[reg_addr]->clr_mask = PEU_CSR_ACKNAK_THRESH_CLEAR_MASK;
2073 csr_db[reg_addr]->set_mask = PEU_CSR_ACKNAK_THRESH_SET_MASK;
2074 csr_db[reg_addr]->toggle_mask = PEU_CSR_ACKNAK_THRESH_TOGGLE_MASK;
2075 csr_db[reg_addr]->por_val = PEU_CSR_ACKNAK_THRESH_POR_VALUE;
2076
2077 csr_db[reg_addr]->data->val = PEU_CSR_ACKNAK_THRESH_POR_VALUE;
2078
2079 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2080 notify (*(csr_db[reg_addr]->data->events[i]));
2081 }
2082
2083 reg_addr = PEU_CSR_A_ACKNAK_TIMER_HW_ADDR;
2084 if (csr_db[reg_addr] == NULL) {
2085 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2086 csr_db[reg_addr]->data = new csr_data<DATA> ();
2087 }
2088
2089 csr_db[reg_addr]->rd_mask = PEU_CSR_ACKNAK_TIMER_READ_MASK;
2090 csr_db[reg_addr]->wr_mask = PEU_CSR_ACKNAK_TIMER_WRITE_MASK;
2091 csr_db[reg_addr]->clr_mask = PEU_CSR_ACKNAK_TIMER_CLEAR_MASK;
2092 csr_db[reg_addr]->set_mask = PEU_CSR_ACKNAK_TIMER_SET_MASK;
2093 csr_db[reg_addr]->toggle_mask = PEU_CSR_ACKNAK_TIMER_TOGGLE_MASK;
2094 csr_db[reg_addr]->por_val = PEU_CSR_ACKNAK_TIMER_POR_VALUE;
2095
2096 csr_db[reg_addr]->data->val = PEU_CSR_ACKNAK_TIMER_POR_VALUE;
2097
2098 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2099 notify (*(csr_db[reg_addr]->data->events[i]));
2100 }
2101
2102 reg_addr = PEU_CSR_B_ACKNAK_TIMER_HW_ADDR;
2103 if (csr_db[reg_addr] == NULL) {
2104 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2105 csr_db[reg_addr]->data = new csr_data<DATA> ();
2106 }
2107
2108 csr_db[reg_addr]->rd_mask = PEU_CSR_ACKNAK_TIMER_READ_MASK;
2109 csr_db[reg_addr]->wr_mask = PEU_CSR_ACKNAK_TIMER_WRITE_MASK;
2110 csr_db[reg_addr]->clr_mask = PEU_CSR_ACKNAK_TIMER_CLEAR_MASK;
2111 csr_db[reg_addr]->set_mask = PEU_CSR_ACKNAK_TIMER_SET_MASK;
2112 csr_db[reg_addr]->toggle_mask = PEU_CSR_ACKNAK_TIMER_TOGGLE_MASK;
2113 csr_db[reg_addr]->por_val = PEU_CSR_ACKNAK_TIMER_POR_VALUE;
2114
2115 csr_db[reg_addr]->data->val = PEU_CSR_ACKNAK_TIMER_POR_VALUE;
2116
2117 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2118 notify (*(csr_db[reg_addr]->data->events[i]));
2119 }
2120
2121 reg_addr = PEU_CSR_A_REPLAY_TIM_THRESH_HW_ADDR;
2122 if (csr_db[reg_addr] == NULL) {
2123 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2124 csr_db[reg_addr]->data = new csr_data<DATA> ();
2125 }
2126
2127 csr_db[reg_addr]->rd_mask = PEU_CSR_REPLAY_TIM_THRESH_READ_MASK;
2128 csr_db[reg_addr]->wr_mask = PEU_CSR_REPLAY_TIM_THRESH_WRITE_MASK;
2129 csr_db[reg_addr]->clr_mask = PEU_CSR_REPLAY_TIM_THRESH_CLEAR_MASK;
2130 csr_db[reg_addr]->set_mask = PEU_CSR_REPLAY_TIM_THRESH_SET_MASK;
2131 csr_db[reg_addr]->toggle_mask = PEU_CSR_REPLAY_TIM_THRESH_TOGGLE_MASK;
2132 csr_db[reg_addr]->por_val = PEU_CSR_REPLAY_TIM_THRESH_POR_VALUE;
2133
2134 csr_db[reg_addr]->data->val = PEU_CSR_REPLAY_TIM_THRESH_POR_VALUE;
2135
2136 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2137 notify (*(csr_db[reg_addr]->data->events[i]));
2138 }
2139
2140 reg_addr = PEU_CSR_B_REPLAY_TIM_THRESH_HW_ADDR;
2141 if (csr_db[reg_addr] == NULL) {
2142 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2143 csr_db[reg_addr]->data = new csr_data<DATA> ();
2144 }
2145
2146 csr_db[reg_addr]->rd_mask = PEU_CSR_REPLAY_TIM_THRESH_READ_MASK;
2147 csr_db[reg_addr]->wr_mask = PEU_CSR_REPLAY_TIM_THRESH_WRITE_MASK;
2148 csr_db[reg_addr]->clr_mask = PEU_CSR_REPLAY_TIM_THRESH_CLEAR_MASK;
2149 csr_db[reg_addr]->set_mask = PEU_CSR_REPLAY_TIM_THRESH_SET_MASK;
2150 csr_db[reg_addr]->toggle_mask = PEU_CSR_REPLAY_TIM_THRESH_TOGGLE_MASK;
2151 csr_db[reg_addr]->por_val = PEU_CSR_REPLAY_TIM_THRESH_POR_VALUE;
2152
2153 csr_db[reg_addr]->data->val = PEU_CSR_REPLAY_TIM_THRESH_POR_VALUE;
2154
2155 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2156 notify (*(csr_db[reg_addr]->data->events[i]));
2157 }
2158
2159 reg_addr = PEU_CSR_A_REPLAY_TIMER_HW_ADDR;
2160 if (csr_db[reg_addr] == NULL) {
2161 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2162 csr_db[reg_addr]->data = new csr_data<DATA> ();
2163 }
2164
2165 csr_db[reg_addr]->rd_mask = PEU_CSR_REPLAY_TIMER_READ_MASK;
2166 csr_db[reg_addr]->wr_mask = PEU_CSR_REPLAY_TIMER_WRITE_MASK;
2167 csr_db[reg_addr]->clr_mask = PEU_CSR_REPLAY_TIMER_CLEAR_MASK;
2168 csr_db[reg_addr]->set_mask = PEU_CSR_REPLAY_TIMER_SET_MASK;
2169 csr_db[reg_addr]->toggle_mask = PEU_CSR_REPLAY_TIMER_TOGGLE_MASK;
2170 csr_db[reg_addr]->por_val = PEU_CSR_REPLAY_TIMER_POR_VALUE;
2171
2172 csr_db[reg_addr]->data->val = PEU_CSR_REPLAY_TIMER_POR_VALUE;
2173
2174 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2175 notify (*(csr_db[reg_addr]->data->events[i]));
2176 }
2177
2178 reg_addr = PEU_CSR_B_REPLAY_TIMER_HW_ADDR;
2179 if (csr_db[reg_addr] == NULL) {
2180 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2181 csr_db[reg_addr]->data = new csr_data<DATA> ();
2182 }
2183
2184 csr_db[reg_addr]->rd_mask = PEU_CSR_REPLAY_TIMER_READ_MASK;
2185 csr_db[reg_addr]->wr_mask = PEU_CSR_REPLAY_TIMER_WRITE_MASK;
2186 csr_db[reg_addr]->clr_mask = PEU_CSR_REPLAY_TIMER_CLEAR_MASK;
2187 csr_db[reg_addr]->set_mask = PEU_CSR_REPLAY_TIMER_SET_MASK;
2188 csr_db[reg_addr]->toggle_mask = PEU_CSR_REPLAY_TIMER_TOGGLE_MASK;
2189 csr_db[reg_addr]->por_val = PEU_CSR_REPLAY_TIMER_POR_VALUE;
2190
2191 csr_db[reg_addr]->data->val = PEU_CSR_REPLAY_TIMER_POR_VALUE;
2192
2193 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2194 notify (*(csr_db[reg_addr]->data->events[i]));
2195 }
2196
2197 reg_addr = PEU_CSR_A_VEN_DLLP_MSG_HW_ADDR;
2198 if (csr_db[reg_addr] == NULL) {
2199 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2200 csr_db[reg_addr]->data = new csr_data<DATA> ();
2201 }
2202
2203 csr_db[reg_addr]->rd_mask = PEU_CSR_VEN_DLLP_MSG_READ_MASK;
2204 csr_db[reg_addr]->wr_mask = PEU_CSR_VEN_DLLP_MSG_WRITE_MASK;
2205 csr_db[reg_addr]->clr_mask = PEU_CSR_VEN_DLLP_MSG_CLEAR_MASK;
2206 csr_db[reg_addr]->set_mask = PEU_CSR_VEN_DLLP_MSG_SET_MASK;
2207 csr_db[reg_addr]->toggle_mask = PEU_CSR_VEN_DLLP_MSG_TOGGLE_MASK;
2208 csr_db[reg_addr]->por_val = PEU_CSR_VEN_DLLP_MSG_POR_VALUE;
2209
2210 csr_db[reg_addr]->data->val = PEU_CSR_VEN_DLLP_MSG_POR_VALUE;
2211
2212 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2213 notify (*(csr_db[reg_addr]->data->events[i]));
2214 }
2215
2216 reg_addr = PEU_CSR_B_VEN_DLLP_MSG_HW_ADDR;
2217 if (csr_db[reg_addr] == NULL) {
2218 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2219 csr_db[reg_addr]->data = new csr_data<DATA> ();
2220 }
2221
2222 csr_db[reg_addr]->rd_mask = PEU_CSR_VEN_DLLP_MSG_READ_MASK;
2223 csr_db[reg_addr]->wr_mask = PEU_CSR_VEN_DLLP_MSG_WRITE_MASK;
2224 csr_db[reg_addr]->clr_mask = PEU_CSR_VEN_DLLP_MSG_CLEAR_MASK;
2225 csr_db[reg_addr]->set_mask = PEU_CSR_VEN_DLLP_MSG_SET_MASK;
2226 csr_db[reg_addr]->toggle_mask = PEU_CSR_VEN_DLLP_MSG_TOGGLE_MASK;
2227 csr_db[reg_addr]->por_val = PEU_CSR_VEN_DLLP_MSG_POR_VALUE;
2228
2229 csr_db[reg_addr]->data->val = PEU_CSR_VEN_DLLP_MSG_POR_VALUE;
2230
2231 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2232 notify (*(csr_db[reg_addr]->data->events[i]));
2233 }
2234
2235 reg_addr = PEU_CSR_A_FORCE_LTSSM_HW_ADDR;
2236 if (csr_db[reg_addr] == NULL) {
2237 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2238 csr_db[reg_addr]->data = new csr_data<DATA> ();
2239 }
2240
2241 csr_db[reg_addr]->rd_mask = PEU_CSR_FORCE_LTSSM_READ_MASK;
2242 csr_db[reg_addr]->wr_mask = PEU_CSR_FORCE_LTSSM_WRITE_MASK;
2243 csr_db[reg_addr]->clr_mask = PEU_CSR_FORCE_LTSSM_CLEAR_MASK;
2244 csr_db[reg_addr]->set_mask = PEU_CSR_FORCE_LTSSM_SET_MASK;
2245 csr_db[reg_addr]->toggle_mask = PEU_CSR_FORCE_LTSSM_TOGGLE_MASK;
2246 csr_db[reg_addr]->por_val = PEU_CSR_FORCE_LTSSM_POR_VALUE;
2247
2248 csr_db[reg_addr]->data->val = PEU_CSR_FORCE_LTSSM_POR_VALUE;
2249
2250 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2251 notify (*(csr_db[reg_addr]->data->events[i]));
2252 }
2253
2254 reg_addr = PEU_CSR_B_FORCE_LTSSM_HW_ADDR;
2255 if (csr_db[reg_addr] == NULL) {
2256 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2257 csr_db[reg_addr]->data = new csr_data<DATA> ();
2258 }
2259
2260 csr_db[reg_addr]->rd_mask = PEU_CSR_FORCE_LTSSM_READ_MASK;
2261 csr_db[reg_addr]->wr_mask = PEU_CSR_FORCE_LTSSM_WRITE_MASK;
2262 csr_db[reg_addr]->clr_mask = PEU_CSR_FORCE_LTSSM_CLEAR_MASK;
2263 csr_db[reg_addr]->set_mask = PEU_CSR_FORCE_LTSSM_SET_MASK;
2264 csr_db[reg_addr]->toggle_mask = PEU_CSR_FORCE_LTSSM_TOGGLE_MASK;
2265 csr_db[reg_addr]->por_val = PEU_CSR_FORCE_LTSSM_POR_VALUE;
2266
2267 csr_db[reg_addr]->data->val = PEU_CSR_FORCE_LTSSM_POR_VALUE;
2268
2269 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2270 notify (*(csr_db[reg_addr]->data->events[i]));
2271 }
2272
2273 reg_addr = PEU_CSR_A_LINK_CFG_HW_ADDR;
2274 if (csr_db[reg_addr] == NULL) {
2275 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2276 csr_db[reg_addr]->data = new csr_data<DATA> ();
2277 }
2278
2279 csr_db[reg_addr]->rd_mask = PEU_CSR_LINK_CFG_READ_MASK;
2280 csr_db[reg_addr]->wr_mask = PEU_CSR_LINK_CFG_WRITE_MASK;
2281 csr_db[reg_addr]->clr_mask = PEU_CSR_LINK_CFG_CLEAR_MASK;
2282 csr_db[reg_addr]->set_mask = PEU_CSR_LINK_CFG_SET_MASK;
2283 csr_db[reg_addr]->toggle_mask = PEU_CSR_LINK_CFG_TOGGLE_MASK;
2284 csr_db[reg_addr]->por_val = PEU_CSR_LINK_CFG_POR_VALUE;
2285
2286 csr_db[reg_addr]->data->val = PEU_CSR_LINK_CFG_POR_VALUE;
2287
2288 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2289 notify (*(csr_db[reg_addr]->data->events[i]));
2290 }
2291
2292 reg_addr = PEU_CSR_B_LINK_CFG_HW_ADDR;
2293 if (csr_db[reg_addr] == NULL) {
2294 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2295 csr_db[reg_addr]->data = new csr_data<DATA> ();
2296 }
2297
2298 csr_db[reg_addr]->rd_mask = PEU_CSR_LINK_CFG_READ_MASK;
2299 csr_db[reg_addr]->wr_mask = PEU_CSR_LINK_CFG_WRITE_MASK;
2300 csr_db[reg_addr]->clr_mask = PEU_CSR_LINK_CFG_CLEAR_MASK;
2301 csr_db[reg_addr]->set_mask = PEU_CSR_LINK_CFG_SET_MASK;
2302 csr_db[reg_addr]->toggle_mask = PEU_CSR_LINK_CFG_TOGGLE_MASK;
2303 csr_db[reg_addr]->por_val = PEU_CSR_LINK_CFG_POR_VALUE;
2304
2305 csr_db[reg_addr]->data->val = PEU_CSR_LINK_CFG_POR_VALUE;
2306
2307 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2308 notify (*(csr_db[reg_addr]->data->events[i]));
2309 }
2310
2311 reg_addr = PEU_CSR_A_LINK_CTL_HW_ADDR;
2312 if (csr_db[reg_addr] == NULL) {
2313 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2314 csr_db[reg_addr]->data = new csr_data<DATA> ();
2315 }
2316
2317 csr_db[reg_addr]->rd_mask = PEU_CSR_LINK_CTL_READ_MASK;
2318 csr_db[reg_addr]->wr_mask = PEU_CSR_LINK_CTL_WRITE_MASK;
2319 csr_db[reg_addr]->clr_mask = PEU_CSR_LINK_CTL_CLEAR_MASK;
2320 csr_db[reg_addr]->set_mask = PEU_CSR_LINK_CTL_SET_MASK;
2321 csr_db[reg_addr]->toggle_mask = PEU_CSR_LINK_CTL_TOGGLE_MASK;
2322 csr_db[reg_addr]->por_val = PEU_CSR_LINK_CTL_POR_VALUE;
2323
2324 csr_db[reg_addr]->data->val = PEU_CSR_LINK_CTL_POR_VALUE;
2325
2326 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2327 notify (*(csr_db[reg_addr]->data->events[i]));
2328 }
2329
2330 reg_addr = PEU_CSR_B_LINK_CTL_HW_ADDR;
2331 if (csr_db[reg_addr] == NULL) {
2332 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2333 csr_db[reg_addr]->data = new csr_data<DATA> ();
2334 }
2335
2336 csr_db[reg_addr]->rd_mask = PEU_CSR_LINK_CTL_READ_MASK;
2337 csr_db[reg_addr]->wr_mask = PEU_CSR_LINK_CTL_WRITE_MASK;
2338 csr_db[reg_addr]->clr_mask = PEU_CSR_LINK_CTL_CLEAR_MASK;
2339 csr_db[reg_addr]->set_mask = PEU_CSR_LINK_CTL_SET_MASK;
2340 csr_db[reg_addr]->toggle_mask = PEU_CSR_LINK_CTL_TOGGLE_MASK;
2341 csr_db[reg_addr]->por_val = PEU_CSR_LINK_CTL_POR_VALUE;
2342
2343 csr_db[reg_addr]->data->val = PEU_CSR_LINK_CTL_POR_VALUE;
2344
2345 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2346 notify (*(csr_db[reg_addr]->data->events[i]));
2347 }
2348
2349 reg_addr = PEU_CSR_A_LANE_SKEW_HW_ADDR;
2350 if (csr_db[reg_addr] == NULL) {
2351 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2352 csr_db[reg_addr]->data = new csr_data<DATA> ();
2353 }
2354
2355 csr_db[reg_addr]->rd_mask = PEU_CSR_LANE_SKEW_READ_MASK;
2356 csr_db[reg_addr]->wr_mask = PEU_CSR_LANE_SKEW_WRITE_MASK;
2357 csr_db[reg_addr]->clr_mask = PEU_CSR_LANE_SKEW_CLEAR_MASK;
2358 csr_db[reg_addr]->set_mask = PEU_CSR_LANE_SKEW_SET_MASK;
2359 csr_db[reg_addr]->toggle_mask = PEU_CSR_LANE_SKEW_TOGGLE_MASK;
2360 csr_db[reg_addr]->por_val = PEU_CSR_LANE_SKEW_POR_VALUE;
2361
2362 csr_db[reg_addr]->data->val = PEU_CSR_LANE_SKEW_POR_VALUE;
2363
2364 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2365 notify (*(csr_db[reg_addr]->data->events[i]));
2366 }
2367
2368 reg_addr = PEU_CSR_B_LANE_SKEW_HW_ADDR;
2369 if (csr_db[reg_addr] == NULL) {
2370 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2371 csr_db[reg_addr]->data = new csr_data<DATA> ();
2372 }
2373
2374 csr_db[reg_addr]->rd_mask = PEU_CSR_LANE_SKEW_READ_MASK;
2375 csr_db[reg_addr]->wr_mask = PEU_CSR_LANE_SKEW_WRITE_MASK;
2376 csr_db[reg_addr]->clr_mask = PEU_CSR_LANE_SKEW_CLEAR_MASK;
2377 csr_db[reg_addr]->set_mask = PEU_CSR_LANE_SKEW_SET_MASK;
2378 csr_db[reg_addr]->toggle_mask = PEU_CSR_LANE_SKEW_TOGGLE_MASK;
2379 csr_db[reg_addr]->por_val = PEU_CSR_LANE_SKEW_POR_VALUE;
2380
2381 csr_db[reg_addr]->data->val = PEU_CSR_LANE_SKEW_POR_VALUE;
2382
2383 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2384 notify (*(csr_db[reg_addr]->data->events[i]));
2385 }
2386
2387 reg_addr = PEU_CSR_A_SYMBOL_NUM_HW_ADDR;
2388 if (csr_db[reg_addr] == NULL) {
2389 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2390 csr_db[reg_addr]->data = new csr_data<DATA> ();
2391 }
2392
2393 csr_db[reg_addr]->rd_mask = PEU_CSR_SYMBOL_NUM_READ_MASK;
2394 csr_db[reg_addr]->wr_mask = PEU_CSR_SYMBOL_NUM_WRITE_MASK;
2395 csr_db[reg_addr]->clr_mask = PEU_CSR_SYMBOL_NUM_CLEAR_MASK;
2396 csr_db[reg_addr]->set_mask = PEU_CSR_SYMBOL_NUM_SET_MASK;
2397 csr_db[reg_addr]->toggle_mask = PEU_CSR_SYMBOL_NUM_TOGGLE_MASK;
2398 csr_db[reg_addr]->por_val = PEU_CSR_SYMBOL_NUM_POR_VALUE;
2399
2400 csr_db[reg_addr]->data->val = PEU_CSR_SYMBOL_NUM_POR_VALUE;
2401
2402 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2403 notify (*(csr_db[reg_addr]->data->events[i]));
2404 }
2405
2406 reg_addr = PEU_CSR_B_SYMBOL_NUM_HW_ADDR;
2407 if (csr_db[reg_addr] == NULL) {
2408 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2409 csr_db[reg_addr]->data = new csr_data<DATA> ();
2410 }
2411
2412 csr_db[reg_addr]->rd_mask = PEU_CSR_SYMBOL_NUM_READ_MASK;
2413 csr_db[reg_addr]->wr_mask = PEU_CSR_SYMBOL_NUM_WRITE_MASK;
2414 csr_db[reg_addr]->clr_mask = PEU_CSR_SYMBOL_NUM_CLEAR_MASK;
2415 csr_db[reg_addr]->set_mask = PEU_CSR_SYMBOL_NUM_SET_MASK;
2416 csr_db[reg_addr]->toggle_mask = PEU_CSR_SYMBOL_NUM_TOGGLE_MASK;
2417 csr_db[reg_addr]->por_val = PEU_CSR_SYMBOL_NUM_POR_VALUE;
2418
2419 csr_db[reg_addr]->data->val = PEU_CSR_SYMBOL_NUM_POR_VALUE;
2420
2421 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2422 notify (*(csr_db[reg_addr]->data->events[i]));
2423 }
2424
2425 reg_addr = PEU_CSR_A_SYMBOL_TIMER_HW_ADDR;
2426 if (csr_db[reg_addr] == NULL) {
2427 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2428 csr_db[reg_addr]->data = new csr_data<DATA> ();
2429 }
2430
2431 csr_db[reg_addr]->rd_mask = PEU_CSR_SYMBOL_TIMER_READ_MASK;
2432 csr_db[reg_addr]->wr_mask = PEU_CSR_SYMBOL_TIMER_WRITE_MASK;
2433 csr_db[reg_addr]->clr_mask = PEU_CSR_SYMBOL_TIMER_CLEAR_MASK;
2434 csr_db[reg_addr]->set_mask = PEU_CSR_SYMBOL_TIMER_SET_MASK;
2435 csr_db[reg_addr]->toggle_mask = PEU_CSR_SYMBOL_TIMER_TOGGLE_MASK;
2436 csr_db[reg_addr]->por_val = PEU_CSR_SYMBOL_TIMER_POR_VALUE;
2437
2438 csr_db[reg_addr]->data->val = PEU_CSR_SYMBOL_TIMER_POR_VALUE;
2439
2440 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2441 notify (*(csr_db[reg_addr]->data->events[i]));
2442 }
2443
2444 reg_addr = PEU_CSR_B_SYMBOL_TIMER_HW_ADDR;
2445 if (csr_db[reg_addr] == NULL) {
2446 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2447 csr_db[reg_addr]->data = new csr_data<DATA> ();
2448 }
2449
2450 csr_db[reg_addr]->rd_mask = PEU_CSR_SYMBOL_TIMER_READ_MASK;
2451 csr_db[reg_addr]->wr_mask = PEU_CSR_SYMBOL_TIMER_WRITE_MASK;
2452 csr_db[reg_addr]->clr_mask = PEU_CSR_SYMBOL_TIMER_CLEAR_MASK;
2453 csr_db[reg_addr]->set_mask = PEU_CSR_SYMBOL_TIMER_SET_MASK;
2454 csr_db[reg_addr]->toggle_mask = PEU_CSR_SYMBOL_TIMER_TOGGLE_MASK;
2455 csr_db[reg_addr]->por_val = PEU_CSR_SYMBOL_TIMER_POR_VALUE;
2456
2457 csr_db[reg_addr]->data->val = PEU_CSR_SYMBOL_TIMER_POR_VALUE;
2458
2459 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2460 notify (*(csr_db[reg_addr]->data->events[i]));
2461 }
2462
2463 reg_addr = PEU_CSR_A_CORE_STATUS_HW_ADDR;
2464 if (csr_db[reg_addr] == NULL) {
2465 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2466 csr_db[reg_addr]->data = new csr_data<DATA> ();
2467 }
2468
2469 csr_db[reg_addr]->rd_mask = PEU_CSR_CORE_STATUS_READ_MASK;
2470 csr_db[reg_addr]->wr_mask = PEU_CSR_CORE_STATUS_WRITE_MASK;
2471 csr_db[reg_addr]->clr_mask = PEU_CSR_CORE_STATUS_CLEAR_MASK;
2472 csr_db[reg_addr]->set_mask = PEU_CSR_CORE_STATUS_SET_MASK;
2473 csr_db[reg_addr]->toggle_mask = PEU_CSR_CORE_STATUS_TOGGLE_MASK;
2474 csr_db[reg_addr]->por_val = PEU_CSR_CORE_STATUS_POR_VALUE;
2475
2476 csr_db[reg_addr]->data->val = PEU_CSR_CORE_STATUS_POR_VALUE;
2477
2478 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2479 notify (*(csr_db[reg_addr]->data->events[i]));
2480 }
2481
2482 reg_addr = PEU_CSR_B_CORE_STATUS_HW_ADDR;
2483 if (csr_db[reg_addr] == NULL) {
2484 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2485 csr_db[reg_addr]->data = new csr_data<DATA> ();
2486 }
2487
2488 csr_db[reg_addr]->rd_mask = PEU_CSR_CORE_STATUS_READ_MASK;
2489 csr_db[reg_addr]->wr_mask = PEU_CSR_CORE_STATUS_WRITE_MASK;
2490 csr_db[reg_addr]->clr_mask = PEU_CSR_CORE_STATUS_CLEAR_MASK;
2491 csr_db[reg_addr]->set_mask = PEU_CSR_CORE_STATUS_SET_MASK;
2492 csr_db[reg_addr]->toggle_mask = PEU_CSR_CORE_STATUS_TOGGLE_MASK;
2493 csr_db[reg_addr]->por_val = PEU_CSR_CORE_STATUS_POR_VALUE;
2494
2495 csr_db[reg_addr]->data->val = PEU_CSR_CORE_STATUS_POR_VALUE;
2496
2497 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2498 notify (*(csr_db[reg_addr]->data->events[i]));
2499 }
2500
2501 reg_addr = PEU_CSR_A_EVENT_ERR_LOG_EN_HW_ADDR;
2502 if (csr_db[reg_addr] == NULL) {
2503 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2504 csr_db[reg_addr]->data = new csr_data<DATA> ();
2505 }
2506
2507 csr_db[reg_addr]->rd_mask = PEU_CSR_EVENT_ERR_LOG_EN_READ_MASK;
2508 csr_db[reg_addr]->wr_mask = PEU_CSR_EVENT_ERR_LOG_EN_WRITE_MASK;
2509 csr_db[reg_addr]->clr_mask = PEU_CSR_EVENT_ERR_LOG_EN_CLEAR_MASK;
2510 csr_db[reg_addr]->set_mask = PEU_CSR_EVENT_ERR_LOG_EN_SET_MASK;
2511 csr_db[reg_addr]->toggle_mask = PEU_CSR_EVENT_ERR_LOG_EN_TOGGLE_MASK;
2512 csr_db[reg_addr]->por_val = PEU_CSR_EVENT_ERR_LOG_EN_POR_VALUE;
2513
2514 csr_db[reg_addr]->data->val = PEU_CSR_EVENT_ERR_LOG_EN_POR_VALUE;
2515
2516 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2517 notify (*(csr_db[reg_addr]->data->events[i]));
2518 }
2519
2520 reg_addr = PEU_CSR_B_EVENT_ERR_LOG_EN_HW_ADDR;
2521 if (csr_db[reg_addr] == NULL) {
2522 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2523 csr_db[reg_addr]->data = new csr_data<DATA> ();
2524 }
2525
2526 csr_db[reg_addr]->rd_mask = PEU_CSR_EVENT_ERR_LOG_EN_READ_MASK;
2527 csr_db[reg_addr]->wr_mask = PEU_CSR_EVENT_ERR_LOG_EN_WRITE_MASK;
2528 csr_db[reg_addr]->clr_mask = PEU_CSR_EVENT_ERR_LOG_EN_CLEAR_MASK;
2529 csr_db[reg_addr]->set_mask = PEU_CSR_EVENT_ERR_LOG_EN_SET_MASK;
2530 csr_db[reg_addr]->toggle_mask = PEU_CSR_EVENT_ERR_LOG_EN_TOGGLE_MASK;
2531 csr_db[reg_addr]->por_val = PEU_CSR_EVENT_ERR_LOG_EN_POR_VALUE;
2532
2533 csr_db[reg_addr]->data->val = PEU_CSR_EVENT_ERR_LOG_EN_POR_VALUE;
2534
2535 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2536 notify (*(csr_db[reg_addr]->data->events[i]));
2537 }
2538
2539 reg_addr = PEU_CSR_A_EVENT_ERR_INT_EN_HW_ADDR;
2540 if (csr_db[reg_addr] == NULL) {
2541 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2542 csr_db[reg_addr]->data = new csr_data<DATA> ();
2543 }
2544
2545 csr_db[reg_addr]->rd_mask = PEU_CSR_EVENT_ERR_INT_EN_READ_MASK;
2546 csr_db[reg_addr]->wr_mask = PEU_CSR_EVENT_ERR_INT_EN_WRITE_MASK;
2547 csr_db[reg_addr]->clr_mask = PEU_CSR_EVENT_ERR_INT_EN_CLEAR_MASK;
2548 csr_db[reg_addr]->set_mask = PEU_CSR_EVENT_ERR_INT_EN_SET_MASK;
2549 csr_db[reg_addr]->toggle_mask = PEU_CSR_EVENT_ERR_INT_EN_TOGGLE_MASK;
2550 csr_db[reg_addr]->por_val = PEU_CSR_EVENT_ERR_INT_EN_POR_VALUE;
2551
2552 csr_db[reg_addr]->data->val = PEU_CSR_EVENT_ERR_INT_EN_POR_VALUE;
2553
2554 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2555 notify (*(csr_db[reg_addr]->data->events[i]));
2556 }
2557
2558 reg_addr = PEU_CSR_B_EVENT_ERR_INT_EN_HW_ADDR;
2559 if (csr_db[reg_addr] == NULL) {
2560 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2561 csr_db[reg_addr]->data = new csr_data<DATA> ();
2562 }
2563
2564 csr_db[reg_addr]->rd_mask = PEU_CSR_EVENT_ERR_INT_EN_READ_MASK;
2565 csr_db[reg_addr]->wr_mask = PEU_CSR_EVENT_ERR_INT_EN_WRITE_MASK;
2566 csr_db[reg_addr]->clr_mask = PEU_CSR_EVENT_ERR_INT_EN_CLEAR_MASK;
2567 csr_db[reg_addr]->set_mask = PEU_CSR_EVENT_ERR_INT_EN_SET_MASK;
2568 csr_db[reg_addr]->toggle_mask = PEU_CSR_EVENT_ERR_INT_EN_TOGGLE_MASK;
2569 csr_db[reg_addr]->por_val = PEU_CSR_EVENT_ERR_INT_EN_POR_VALUE;
2570
2571 csr_db[reg_addr]->data->val = PEU_CSR_EVENT_ERR_INT_EN_POR_VALUE;
2572
2573 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2574 notify (*(csr_db[reg_addr]->data->events[i]));
2575 }
2576
2577 reg_addr = PEU_CSR_A_EVENT_ERR_INT_STS_HW_ADDR;
2578 if (csr_db[reg_addr] == NULL) {
2579 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2580 csr_db[reg_addr]->data = new csr_data<DATA> ();
2581 }
2582
2583 csr_db[reg_addr]->rd_mask = PEU_CSR_EVENT_ERR_INT_STS_READ_MASK;
2584 csr_db[reg_addr]->wr_mask = PEU_CSR_EVENT_ERR_INT_STS_WRITE_MASK;
2585 csr_db[reg_addr]->clr_mask = PEU_CSR_EVENT_ERR_INT_STS_CLEAR_MASK;
2586 csr_db[reg_addr]->set_mask = PEU_CSR_EVENT_ERR_INT_STS_SET_MASK;
2587 csr_db[reg_addr]->toggle_mask = PEU_CSR_EVENT_ERR_INT_STS_TOGGLE_MASK;
2588 csr_db[reg_addr]->por_val = PEU_CSR_EVENT_ERR_INT_STS_POR_VALUE;
2589
2590 csr_db[reg_addr]->data->val = PEU_CSR_EVENT_ERR_INT_STS_POR_VALUE;
2591
2592 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2593 notify (*(csr_db[reg_addr]->data->events[i]));
2594 }
2595
2596 reg_addr = PEU_CSR_B_EVENT_ERR_INT_STS_HW_ADDR;
2597 if (csr_db[reg_addr] == NULL) {
2598 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2599 csr_db[reg_addr]->data = new csr_data<DATA> ();
2600 }
2601
2602 csr_db[reg_addr]->rd_mask = PEU_CSR_EVENT_ERR_INT_STS_READ_MASK;
2603 csr_db[reg_addr]->wr_mask = PEU_CSR_EVENT_ERR_INT_STS_WRITE_MASK;
2604 csr_db[reg_addr]->clr_mask = PEU_CSR_EVENT_ERR_INT_STS_CLEAR_MASK;
2605 csr_db[reg_addr]->set_mask = PEU_CSR_EVENT_ERR_INT_STS_SET_MASK;
2606 csr_db[reg_addr]->toggle_mask = PEU_CSR_EVENT_ERR_INT_STS_TOGGLE_MASK;
2607 csr_db[reg_addr]->por_val = PEU_CSR_EVENT_ERR_INT_STS_POR_VALUE;
2608
2609 csr_db[reg_addr]->data->val = PEU_CSR_EVENT_ERR_INT_STS_POR_VALUE;
2610
2611 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2612 notify (*(csr_db[reg_addr]->data->events[i]));
2613 }
2614
2615 reg_addr = PEU_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_HW_ADDR;
2616 if (csr_db[reg_addr] == NULL) {
2617 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2618 csr_db[reg_addr]->data = new csr_data<DATA> ();
2619 }
2620
2621 csr_db[reg_addr]->rd_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_READ_MASK;
2622 csr_db[reg_addr]->wr_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_WRITE_MASK;
2623 csr_db[reg_addr]->clr_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_CLEAR_MASK;
2624 csr_db[reg_addr]->set_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_SET_MASK;
2625 csr_db[reg_addr]->toggle_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_TOGGLE_MASK;
2626 csr_db[reg_addr]->por_val = PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_POR_VALUE;
2627
2628 csr_db[reg_addr]->data->val = PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_POR_VALUE;
2629 csr_db[reg_addr]->intf_type = WRITE1_CLEAR;
2630 csr_db[reg_addr]->sw_reset_val_hold = false;
2631
2632 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2633 notify (*(csr_db[reg_addr]->data->events[i]));
2634 }
2635
2636 reg_addr = PEU_CSR_B_EVENT_ERR_STS_CLR_RW1C_ALIAS_HW_ADDR;
2637 if (csr_db[reg_addr] == NULL) {
2638 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2639 csr_db[reg_addr]->data = new csr_data<DATA> ();
2640 }
2641
2642 csr_db[reg_addr]->rd_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_READ_MASK;
2643 csr_db[reg_addr]->wr_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_WRITE_MASK;
2644 csr_db[reg_addr]->clr_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_CLEAR_MASK;
2645 csr_db[reg_addr]->set_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_SET_MASK;
2646 csr_db[reg_addr]->toggle_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_TOGGLE_MASK;
2647 csr_db[reg_addr]->por_val = PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_POR_VALUE;
2648
2649 csr_db[reg_addr]->data->val = PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_POR_VALUE;
2650 csr_db[reg_addr]->intf_type = WRITE1_CLEAR;
2651 csr_db[reg_addr]->sw_reset_val_hold = false;
2652
2653 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2654 notify (*(csr_db[reg_addr]->data->events[i]));
2655 }
2656
2657 reg_addr = PEU_CSR_A_EVENT_ERR_STS_CLR_RW1S_ALIAS_HW_ADDR;
2658 if (csr_db[reg_addr] == NULL) {
2659 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2660 csr_db[reg_addr]->data = csr_db[PEU_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_HW_ADDR]->data;
2661 }
2662
2663 csr_db[reg_addr]->rd_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_READ_MASK;
2664 csr_db[reg_addr]->wr_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_WRITE_MASK;
2665 csr_db[reg_addr]->clr_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_CLEAR_MASK;
2666 csr_db[reg_addr]->set_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_SET_MASK;
2667 csr_db[reg_addr]->toggle_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_TOGGLE_MASK;
2668 csr_db[reg_addr]->por_val = PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_POR_VALUE;
2669
2670 csr_db[reg_addr]->data->val = PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_POR_VALUE;
2671 csr_db[reg_addr]->intf_type = WRITE1_SET;
2672 csr_db[reg_addr]->sw_reset_val_hold = false;
2673
2674 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2675 notify (*(csr_db[reg_addr]->data->events[i]));
2676 }
2677
2678 reg_addr = PEU_CSR_B_EVENT_ERR_STS_CLR_RW1S_ALIAS_HW_ADDR;
2679 if (csr_db[reg_addr] == NULL) {
2680 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2681 csr_db[reg_addr]->data = csr_db[PEU_CSR_B_EVENT_ERR_STS_CLR_RW1C_ALIAS_HW_ADDR]->data;
2682 }
2683
2684 csr_db[reg_addr]->rd_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_READ_MASK;
2685 csr_db[reg_addr]->wr_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_WRITE_MASK;
2686 csr_db[reg_addr]->clr_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_CLEAR_MASK;
2687 csr_db[reg_addr]->set_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_SET_MASK;
2688 csr_db[reg_addr]->toggle_mask = PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_TOGGLE_MASK;
2689 csr_db[reg_addr]->por_val = PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_POR_VALUE;
2690
2691 csr_db[reg_addr]->data->val = PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_POR_VALUE;
2692 csr_db[reg_addr]->intf_type = WRITE1_SET;
2693 csr_db[reg_addr]->sw_reset_val_hold = false;
2694
2695 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2696 notify (*(csr_db[reg_addr]->data->events[i]));
2697 }
2698
2699 reg_addr = PEU_CSR_A_LNK_BIT_ERR_CNT_1_HW_ADDR;
2700 if (csr_db[reg_addr] == NULL) {
2701 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2702 csr_db[reg_addr]->data = new csr_data<DATA> ();
2703 }
2704
2705 csr_db[reg_addr]->rd_mask = PEU_CSR_LNK_BIT_ERR_CNT_1_READ_MASK;
2706 csr_db[reg_addr]->wr_mask = PEU_CSR_LNK_BIT_ERR_CNT_1_WRITE_MASK;
2707 csr_db[reg_addr]->clr_mask = PEU_CSR_LNK_BIT_ERR_CNT_1_CLEAR_MASK;
2708 csr_db[reg_addr]->set_mask = PEU_CSR_LNK_BIT_ERR_CNT_1_SET_MASK;
2709 csr_db[reg_addr]->toggle_mask = PEU_CSR_LNK_BIT_ERR_CNT_1_TOGGLE_MASK;
2710 csr_db[reg_addr]->por_val = PEU_CSR_LNK_BIT_ERR_CNT_1_POR_VALUE;
2711
2712 csr_db[reg_addr]->data->val = PEU_CSR_LNK_BIT_ERR_CNT_1_POR_VALUE;
2713
2714 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2715 notify (*(csr_db[reg_addr]->data->events[i]));
2716 }
2717
2718 reg_addr = PEU_CSR_B_LNK_BIT_ERR_CNT_1_HW_ADDR;
2719 if (csr_db[reg_addr] == NULL) {
2720 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2721 csr_db[reg_addr]->data = new csr_data<DATA> ();
2722 }
2723
2724 csr_db[reg_addr]->rd_mask = PEU_CSR_LNK_BIT_ERR_CNT_1_READ_MASK;
2725 csr_db[reg_addr]->wr_mask = PEU_CSR_LNK_BIT_ERR_CNT_1_WRITE_MASK;
2726 csr_db[reg_addr]->clr_mask = PEU_CSR_LNK_BIT_ERR_CNT_1_CLEAR_MASK;
2727 csr_db[reg_addr]->set_mask = PEU_CSR_LNK_BIT_ERR_CNT_1_SET_MASK;
2728 csr_db[reg_addr]->toggle_mask = PEU_CSR_LNK_BIT_ERR_CNT_1_TOGGLE_MASK;
2729 csr_db[reg_addr]->por_val = PEU_CSR_LNK_BIT_ERR_CNT_1_POR_VALUE;
2730
2731 csr_db[reg_addr]->data->val = PEU_CSR_LNK_BIT_ERR_CNT_1_POR_VALUE;
2732
2733 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2734 notify (*(csr_db[reg_addr]->data->events[i]));
2735 }
2736
2737 reg_addr = PEU_CSR_A_LNK_BIT_ERR_CNT_2_HW_ADDR;
2738 if (csr_db[reg_addr] == NULL) {
2739 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2740 csr_db[reg_addr]->data = new csr_data<DATA> ();
2741 }
2742
2743 csr_db[reg_addr]->rd_mask = PEU_CSR_LNK_BIT_ERR_CNT_2_READ_MASK;
2744 csr_db[reg_addr]->wr_mask = PEU_CSR_LNK_BIT_ERR_CNT_2_WRITE_MASK;
2745 csr_db[reg_addr]->clr_mask = PEU_CSR_LNK_BIT_ERR_CNT_2_CLEAR_MASK;
2746 csr_db[reg_addr]->set_mask = PEU_CSR_LNK_BIT_ERR_CNT_2_SET_MASK;
2747 csr_db[reg_addr]->toggle_mask = PEU_CSR_LNK_BIT_ERR_CNT_2_TOGGLE_MASK;
2748 csr_db[reg_addr]->por_val = PEU_CSR_LNK_BIT_ERR_CNT_2_POR_VALUE;
2749
2750 csr_db[reg_addr]->data->val = PEU_CSR_LNK_BIT_ERR_CNT_2_POR_VALUE;
2751
2752 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2753 notify (*(csr_db[reg_addr]->data->events[i]));
2754 }
2755
2756 reg_addr = PEU_CSR_B_LNK_BIT_ERR_CNT_2_HW_ADDR;
2757 if (csr_db[reg_addr] == NULL) {
2758 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2759 csr_db[reg_addr]->data = new csr_data<DATA> ();
2760 }
2761
2762 csr_db[reg_addr]->rd_mask = PEU_CSR_LNK_BIT_ERR_CNT_2_READ_MASK;
2763 csr_db[reg_addr]->wr_mask = PEU_CSR_LNK_BIT_ERR_CNT_2_WRITE_MASK;
2764 csr_db[reg_addr]->clr_mask = PEU_CSR_LNK_BIT_ERR_CNT_2_CLEAR_MASK;
2765 csr_db[reg_addr]->set_mask = PEU_CSR_LNK_BIT_ERR_CNT_2_SET_MASK;
2766 csr_db[reg_addr]->toggle_mask = PEU_CSR_LNK_BIT_ERR_CNT_2_TOGGLE_MASK;
2767 csr_db[reg_addr]->por_val = PEU_CSR_LNK_BIT_ERR_CNT_2_POR_VALUE;
2768
2769 csr_db[reg_addr]->data->val = PEU_CSR_LNK_BIT_ERR_CNT_2_POR_VALUE;
2770
2771 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2772 notify (*(csr_db[reg_addr]->data->events[i]));
2773 }
2774
2775 reg_addr = PEU_CSR_A_SERDES_PLL_HW_ADDR;
2776 if (csr_db[reg_addr] == NULL) {
2777 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2778 csr_db[reg_addr]->data = new csr_data<DATA> ();
2779 }
2780
2781 csr_db[reg_addr]->rd_mask = PEU_CSR_SERDES_PLL_READ_MASK;
2782 csr_db[reg_addr]->wr_mask = PEU_CSR_SERDES_PLL_WRITE_MASK;
2783 csr_db[reg_addr]->clr_mask = PEU_CSR_SERDES_PLL_CLEAR_MASK;
2784 csr_db[reg_addr]->set_mask = PEU_CSR_SERDES_PLL_SET_MASK;
2785 csr_db[reg_addr]->toggle_mask = PEU_CSR_SERDES_PLL_TOGGLE_MASK;
2786 csr_db[reg_addr]->por_val = PEU_CSR_SERDES_PLL_POR_VALUE;
2787
2788 csr_db[reg_addr]->data->val = PEU_CSR_SERDES_PLL_POR_VALUE;
2789
2790 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2791 notify (*(csr_db[reg_addr]->data->events[i]));
2792 }
2793
2794 reg_addr = PEU_CSR_B_SERDES_PLL_HW_ADDR;
2795 if (csr_db[reg_addr] == NULL) {
2796 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2797 csr_db[reg_addr]->data = new csr_data<DATA> ();
2798 }
2799
2800 csr_db[reg_addr]->rd_mask = PEU_CSR_SERDES_PLL_READ_MASK;
2801 csr_db[reg_addr]->wr_mask = PEU_CSR_SERDES_PLL_WRITE_MASK;
2802 csr_db[reg_addr]->clr_mask = PEU_CSR_SERDES_PLL_CLEAR_MASK;
2803 csr_db[reg_addr]->set_mask = PEU_CSR_SERDES_PLL_SET_MASK;
2804 csr_db[reg_addr]->toggle_mask = PEU_CSR_SERDES_PLL_TOGGLE_MASK;
2805 csr_db[reg_addr]->por_val = PEU_CSR_SERDES_PLL_POR_VALUE;
2806
2807 csr_db[reg_addr]->data->val = PEU_CSR_SERDES_PLL_POR_VALUE;
2808
2809 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2810 notify (*(csr_db[reg_addr]->data->events[i]));
2811 }
2812
2813 reg_addr = PEU_CSR_A_SERDES_RECEIVER_LANE_CTL_HW_ADDR;
2814 if (csr_db[reg_addr] == NULL) {
2815 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2816 csr_db[reg_addr]->data = new csr_data<DATA> ();
2817 }
2818
2819 csr_db[reg_addr]->rd_mask = PEU_CSR_SERDES_RECEIVER_LANE_CTL_READ_MASK;
2820 csr_db[reg_addr]->wr_mask = PEU_CSR_SERDES_RECEIVER_LANE_CTL_WRITE_MASK;
2821 csr_db[reg_addr]->clr_mask = PEU_CSR_SERDES_RECEIVER_LANE_CTL_CLEAR_MASK;
2822 csr_db[reg_addr]->set_mask = PEU_CSR_SERDES_RECEIVER_LANE_CTL_SET_MASK;
2823 csr_db[reg_addr]->toggle_mask = PEU_CSR_SERDES_RECEIVER_LANE_CTL_TOGGLE_MASK;
2824 csr_db[reg_addr]->por_val = PEU_CSR_SERDES_RECEIVER_LANE_CTL_POR_VALUE;
2825
2826 csr_db[reg_addr]->data->val = PEU_CSR_SERDES_RECEIVER_LANE_CTL_POR_VALUE;
2827
2828 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2829 notify (*(csr_db[reg_addr]->data->events[i]));
2830 }
2831
2832 reg_addr = PEU_CSR_B_SERDES_RECEIVER_LANE_CTL_HW_ADDR;
2833 if (csr_db[reg_addr] == NULL) {
2834 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2835 csr_db[reg_addr]->data = new csr_data<DATA> ();
2836 }
2837
2838 csr_db[reg_addr]->rd_mask = PEU_CSR_SERDES_RECEIVER_LANE_CTL_READ_MASK;
2839 csr_db[reg_addr]->wr_mask = PEU_CSR_SERDES_RECEIVER_LANE_CTL_WRITE_MASK;
2840 csr_db[reg_addr]->clr_mask = PEU_CSR_SERDES_RECEIVER_LANE_CTL_CLEAR_MASK;
2841 csr_db[reg_addr]->set_mask = PEU_CSR_SERDES_RECEIVER_LANE_CTL_SET_MASK;
2842 csr_db[reg_addr]->toggle_mask = PEU_CSR_SERDES_RECEIVER_LANE_CTL_TOGGLE_MASK;
2843 csr_db[reg_addr]->por_val = PEU_CSR_SERDES_RECEIVER_LANE_CTL_POR_VALUE;
2844
2845 csr_db[reg_addr]->data->val = PEU_CSR_SERDES_RECEIVER_LANE_CTL_POR_VALUE;
2846
2847 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2848 notify (*(csr_db[reg_addr]->data->events[i]));
2849 }
2850
2851 reg_addr = PEU_CSR_A_SERDES_RECEIVER_LANE_STATUS_HW_ADDR;
2852 if (csr_db[reg_addr] == NULL) {
2853 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2854 csr_db[reg_addr]->data = new csr_data<DATA> ();
2855 }
2856
2857 csr_db[reg_addr]->rd_mask = PEU_CSR_SERDES_RECEIVER_LANE_STATUS_READ_MASK;
2858 csr_db[reg_addr]->wr_mask = PEU_CSR_SERDES_RECEIVER_LANE_STATUS_WRITE_MASK;
2859 csr_db[reg_addr]->clr_mask = PEU_CSR_SERDES_RECEIVER_LANE_STATUS_CLEAR_MASK;
2860 csr_db[reg_addr]->set_mask = PEU_CSR_SERDES_RECEIVER_LANE_STATUS_SET_MASK;
2861 csr_db[reg_addr]->toggle_mask = PEU_CSR_SERDES_RECEIVER_LANE_STATUS_TOGGLE_MASK;
2862 csr_db[reg_addr]->por_val = PEU_CSR_SERDES_RECEIVER_LANE_STATUS_POR_VALUE;
2863
2864 csr_db[reg_addr]->data->val = PEU_CSR_SERDES_RECEIVER_LANE_STATUS_POR_VALUE;
2865
2866 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2867 notify (*(csr_db[reg_addr]->data->events[i]));
2868 }
2869
2870 reg_addr = PEU_CSR_B_SERDES_RECEIVER_LANE_STATUS_HW_ADDR;
2871 if (csr_db[reg_addr] == NULL) {
2872 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2873 csr_db[reg_addr]->data = new csr_data<DATA> ();
2874 }
2875
2876 csr_db[reg_addr]->rd_mask = PEU_CSR_SERDES_RECEIVER_LANE_STATUS_READ_MASK;
2877 csr_db[reg_addr]->wr_mask = PEU_CSR_SERDES_RECEIVER_LANE_STATUS_WRITE_MASK;
2878 csr_db[reg_addr]->clr_mask = PEU_CSR_SERDES_RECEIVER_LANE_STATUS_CLEAR_MASK;
2879 csr_db[reg_addr]->set_mask = PEU_CSR_SERDES_RECEIVER_LANE_STATUS_SET_MASK;
2880 csr_db[reg_addr]->toggle_mask = PEU_CSR_SERDES_RECEIVER_LANE_STATUS_TOGGLE_MASK;
2881 csr_db[reg_addr]->por_val = PEU_CSR_SERDES_RECEIVER_LANE_STATUS_POR_VALUE;
2882
2883 csr_db[reg_addr]->data->val = PEU_CSR_SERDES_RECEIVER_LANE_STATUS_POR_VALUE;
2884
2885 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2886 notify (*(csr_db[reg_addr]->data->events[i]));
2887 }
2888
2889 reg_addr = PEU_CSR_A_SERDES_XMITTER_LANE_CTL_HW_ADDR;
2890 if (csr_db[reg_addr] == NULL) {
2891 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2892 csr_db[reg_addr]->data = new csr_data<DATA> ();
2893 }
2894
2895 csr_db[reg_addr]->rd_mask = PEU_CSR_SERDES_XMITTER_LANE_CTL_READ_MASK;
2896 csr_db[reg_addr]->wr_mask = PEU_CSR_SERDES_XMITTER_LANE_CTL_WRITE_MASK;
2897 csr_db[reg_addr]->clr_mask = PEU_CSR_SERDES_XMITTER_LANE_CTL_CLEAR_MASK;
2898 csr_db[reg_addr]->set_mask = PEU_CSR_SERDES_XMITTER_LANE_CTL_SET_MASK;
2899 csr_db[reg_addr]->toggle_mask = PEU_CSR_SERDES_XMITTER_LANE_CTL_TOGGLE_MASK;
2900 csr_db[reg_addr]->por_val = PEU_CSR_SERDES_XMITTER_LANE_CTL_POR_VALUE;
2901
2902 csr_db[reg_addr]->data->val = PEU_CSR_SERDES_XMITTER_LANE_CTL_POR_VALUE;
2903
2904 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2905 notify (*(csr_db[reg_addr]->data->events[i]));
2906 }
2907
2908 reg_addr = PEU_CSR_B_SERDES_XMITTER_LANE_CTL_HW_ADDR;
2909 if (csr_db[reg_addr] == NULL) {
2910 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2911 csr_db[reg_addr]->data = new csr_data<DATA> ();
2912 }
2913
2914 csr_db[reg_addr]->rd_mask = PEU_CSR_SERDES_XMITTER_LANE_CTL_READ_MASK;
2915 csr_db[reg_addr]->wr_mask = PEU_CSR_SERDES_XMITTER_LANE_CTL_WRITE_MASK;
2916 csr_db[reg_addr]->clr_mask = PEU_CSR_SERDES_XMITTER_LANE_CTL_CLEAR_MASK;
2917 csr_db[reg_addr]->set_mask = PEU_CSR_SERDES_XMITTER_LANE_CTL_SET_MASK;
2918 csr_db[reg_addr]->toggle_mask = PEU_CSR_SERDES_XMITTER_LANE_CTL_TOGGLE_MASK;
2919 csr_db[reg_addr]->por_val = PEU_CSR_SERDES_XMITTER_LANE_CTL_POR_VALUE;
2920
2921 csr_db[reg_addr]->data->val = PEU_CSR_SERDES_XMITTER_LANE_CTL_POR_VALUE;
2922
2923 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2924 notify (*(csr_db[reg_addr]->data->events[i]));
2925 }
2926
2927 reg_addr = PEU_CSR_A_SERDES_XMITTER_LANE_STATUS_HW_ADDR;
2928 if (csr_db[reg_addr] == NULL) {
2929 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2930 csr_db[reg_addr]->data = new csr_data<DATA> ();
2931 }
2932
2933 csr_db[reg_addr]->rd_mask = PEU_CSR_SERDES_XMITTER_LANE_STATUS_READ_MASK;
2934 csr_db[reg_addr]->wr_mask = PEU_CSR_SERDES_XMITTER_LANE_STATUS_WRITE_MASK;
2935 csr_db[reg_addr]->clr_mask = PEU_CSR_SERDES_XMITTER_LANE_STATUS_CLEAR_MASK;
2936 csr_db[reg_addr]->set_mask = PEU_CSR_SERDES_XMITTER_LANE_STATUS_SET_MASK;
2937 csr_db[reg_addr]->toggle_mask = PEU_CSR_SERDES_XMITTER_LANE_STATUS_TOGGLE_MASK;
2938 csr_db[reg_addr]->por_val = PEU_CSR_SERDES_XMITTER_LANE_STATUS_POR_VALUE;
2939
2940 csr_db[reg_addr]->data->val = PEU_CSR_SERDES_XMITTER_LANE_STATUS_POR_VALUE;
2941
2942 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2943 notify (*(csr_db[reg_addr]->data->events[i]));
2944 }
2945
2946 reg_addr = PEU_CSR_B_SERDES_XMITTER_LANE_STATUS_HW_ADDR;
2947 if (csr_db[reg_addr] == NULL) {
2948 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2949 csr_db[reg_addr]->data = new csr_data<DATA> ();
2950 }
2951
2952 csr_db[reg_addr]->rd_mask = PEU_CSR_SERDES_XMITTER_LANE_STATUS_READ_MASK;
2953 csr_db[reg_addr]->wr_mask = PEU_CSR_SERDES_XMITTER_LANE_STATUS_WRITE_MASK;
2954 csr_db[reg_addr]->clr_mask = PEU_CSR_SERDES_XMITTER_LANE_STATUS_CLEAR_MASK;
2955 csr_db[reg_addr]->set_mask = PEU_CSR_SERDES_XMITTER_LANE_STATUS_SET_MASK;
2956 csr_db[reg_addr]->toggle_mask = PEU_CSR_SERDES_XMITTER_LANE_STATUS_TOGGLE_MASK;
2957 csr_db[reg_addr]->por_val = PEU_CSR_SERDES_XMITTER_LANE_STATUS_POR_VALUE;
2958
2959 csr_db[reg_addr]->data->val = PEU_CSR_SERDES_XMITTER_LANE_STATUS_POR_VALUE;
2960
2961 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2962 notify (*(csr_db[reg_addr]->data->events[i]));
2963 }
2964
2965 reg_addr = PEU_CSR_A_SERDES_MACRO_TEST_CFG_HW_ADDR;
2966 if (csr_db[reg_addr] == NULL) {
2967 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2968 csr_db[reg_addr]->data = new csr_data<DATA> ();
2969 }
2970
2971 csr_db[reg_addr]->rd_mask = PEU_CSR_SERDES_MACRO_TEST_CFG_READ_MASK;
2972 csr_db[reg_addr]->wr_mask = PEU_CSR_SERDES_MACRO_TEST_CFG_WRITE_MASK;
2973 csr_db[reg_addr]->clr_mask = PEU_CSR_SERDES_MACRO_TEST_CFG_CLEAR_MASK;
2974 csr_db[reg_addr]->set_mask = PEU_CSR_SERDES_MACRO_TEST_CFG_SET_MASK;
2975 csr_db[reg_addr]->toggle_mask = PEU_CSR_SERDES_MACRO_TEST_CFG_TOGGLE_MASK;
2976 csr_db[reg_addr]->por_val = PEU_CSR_SERDES_MACRO_TEST_CFG_POR_VALUE;
2977
2978 csr_db[reg_addr]->data->val = PEU_CSR_SERDES_MACRO_TEST_CFG_POR_VALUE;
2979
2980 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
2981 notify (*(csr_db[reg_addr]->data->events[i]));
2982 }
2983
2984 reg_addr = PEU_CSR_B_SERDES_MACRO_TEST_CFG_HW_ADDR;
2985 if (csr_db[reg_addr] == NULL) {
2986 csr_db[reg_addr] = new csr_data_intf<DATA> ();
2987 csr_db[reg_addr]->data = new csr_data<DATA> ();
2988 }
2989
2990 csr_db[reg_addr]->rd_mask = PEU_CSR_SERDES_MACRO_TEST_CFG_READ_MASK;
2991 csr_db[reg_addr]->wr_mask = PEU_CSR_SERDES_MACRO_TEST_CFG_WRITE_MASK;
2992 csr_db[reg_addr]->clr_mask = PEU_CSR_SERDES_MACRO_TEST_CFG_CLEAR_MASK;
2993 csr_db[reg_addr]->set_mask = PEU_CSR_SERDES_MACRO_TEST_CFG_SET_MASK;
2994 csr_db[reg_addr]->toggle_mask = PEU_CSR_SERDES_MACRO_TEST_CFG_TOGGLE_MASK;
2995 csr_db[reg_addr]->por_val = PEU_CSR_SERDES_MACRO_TEST_CFG_POR_VALUE;
2996
2997 csr_db[reg_addr]->data->val = PEU_CSR_SERDES_MACRO_TEST_CFG_POR_VALUE;
2998
2999 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
3000 notify (*(csr_db[reg_addr]->data->events[i]));
3001 }
3002
3003 reg_addr = ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_ADDR;
3004 if (csr_db[reg_addr] == NULL) {
3005 csr_db[reg_addr] = new csr_data_intf<DATA> ();
3006 csr_db[reg_addr]->data = new csr_data<DATA> ();
3007 }
3008
3009 csr_db[reg_addr]->rd_mask = ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_READ_MASK;
3010 csr_db[reg_addr]->wr_mask = ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_WRITE_MASK;
3011 csr_db[reg_addr]->clr_mask = ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_CLEAR_MASK;
3012 csr_db[reg_addr]->set_mask = ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SET_MASK;
3013 csr_db[reg_addr]->toggle_mask = ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_TOGGLE_MASK;
3014 csr_db[reg_addr]->por_val = ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_POR_VALUE;
3015
3016 csr_db[reg_addr]->data->val = ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_POR_VALUE;
3017 csr_db[reg_addr]->intf_type = WRITE1_SET;
3018 csr_db[reg_addr]->sw_reset_val_hold = false;
3019
3020 for (uint32 i = 0; i < csr_db[reg_addr]->data->num_events; i++) {
3021 notify (*(csr_db[reg_addr]->data->events[i]));
3022 }
3023
3024 LOG_DEBUG << "Create CSR DB .. Done";
3025 }
3026
3027 /**
3028 * This method resets the CSR data element, based on the specified rst_type
3029 */
3030 void reset_csr_db(){
3031 LOG_DEBUG << "Reset CSR DB";
3032 if(rst_type==POR_L)
3033 LOG_INFO<<"CSR: POR_L reset..";
3034 else if(rst_type==RST_L)
3035 LOG_INFO<<"CSR: RST_L reset..";
3036 else LOG_WARNING << "CSR: WARNING: Undefined reset type!";
3037
3038 USE_NAMESPACE(std)map<ADDR, csr_data_intf <DATA>* >::iterator it;
3039 for(it=csr_db.begin(); it!=csr_db.end(); ++it){
3040 ((*it).second)->reset_data(rst_type);
3041 }
3042 LOG_DEBUG << "Reset CSR DB .. Done";
3043 } //end reset_csr_db()
3044
3045 /**
3046 * This thread handles reset behavior of the module. On the arrival of a
3047 * reset global event, it issues a reset to the CSR DB.
3048 */
3049 void reset_handler(){
3050 while(1){
3051 wait(*parent_global_event);
3052 switch(*parent_global_event_type){
3053 case POR_RESET_ENTER:
3054 LOG_WARNING<<"CSR: Entering reset state...";
3055 rst_type=POR_L;
3056 reset_csr_db();
3057 POR_RESET=true;
3058 break;
3059 case WMR_RESET_ENTER:
3060 LOG_WARNING<<"CSR: Entering reset state...";
3061 rst_type=RST_L;
3062 reset_csr_db();
3063 POR_RESET=true;
3064 break;
3065 case POR_RESET_EXIT:
3066 case WMR_RESET_EXIT:
3067 LOG_INFO<<"CSR: Exiting reset state...";
3068 POR_RESET = false;
3069 break;
3070 }
3071 }
3072 } //end reset_handler()
3073
3074 sc_export<if_type> target_port;
3075 sc_event *parent_global_event; ///< Global event for CSR module
3076 uint8 *parent_global_event_type; ///< Global event type
3077 bool POR_RESET; ///< Power-on reset flag
3078 uint8 rst_type; ///< Reset type
3079
3080 private:
3081 USE_NAMESPACE(std)map<ADDR, csr_data_intf <DATA>* > csr_db;
3082 };
3083} // namespace pcie_tl
3084
3085#endif // INC_csr_hpp__
3086
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