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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / model / pcie / dll / dll_ctrl_mgmt.cpp
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dll_ctrl_mgmt.cpp
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include "dll_top.hpp"
36
37namespace pcie {
38
39
40
41 /** This function initializes values to be used at DLL **/
42
43 void dll_top::init()
44 {
45 FC_INIT1_Complete = 0;
46 FC_INIT2_Complete = 0;
47 FC_Init_Complete = 0;
48 DL_State = DL_INACTIVE;
49 NAK_SCHEDULED = 0;
50 dllp_crc = 0xffff;
51 lcrc = 0xffffffff;
52 ltssm_L0s =0;
53 replay_buffer_size=128;
54
55 Flag_FC1=0;
56 Flag_FC1_P=0;
57 Flag_FC1_NP=0;
58 Flag_FC1_CPL=0;
59 Flag_FC2=0;
60 Flag_FC2_P=0;
61 Flag_FC2_NP=0;
62 Flag_FC2_CPL=0;
63
64 DO_NAK_SCHEDULED_CHECK = 0;
65 NEXT_TRANSMIT_SEQ = 0;
66 NEXT_RECEIVE_SEQ = 0;
67 ACKD_SEQ=0;
68 REPLAY_NUM=0;
69
70 POR_RESET=false;
71 STOP_TIMER=false;
72 pl_consumer_ph = sc_spawn(sc_bind(&dll_top::pl_consumer,this));
73 tl_consumer_ph = sc_spawn(sc_bind(&dll_top::tl_consumer,this));
74 tl_producer_ph = sc_spawn(sc_bind(&dll_top::tl_producer,this));
75 pl_dllp_producer_ph = sc_spawn(sc_bind(&dll_top::pl_dllp_producer,this));
76 pl_tlp_producer_ph = sc_spawn(sc_bind(&dll_top::pl_tlp_producer,this));
77 ltssm_state_check_ph = sc_spawn(sc_bind(&dll_top::ltssm_state_check,this));
78 fc_init_ph = sc_spawn(sc_bind(&dll_top::fc_init,this));
79 fc_update_ph = sc_spawn(sc_bind(&dll_top::fc_update,this));
80 dll_ctrl_mgmt_ph = sc_spawn(sc_bind(&dll_top::dll_ctrl_mgmt,this));
81 LOG_DEBUG << "DLL: SW Reset : threads re-spawned" ;
82 }
83
84 void dll_top::reset_handler()
85 {
86 csr_port.set_notify_event(PEU_CSR_A_CORE_STATUS_HW_ADDR,&csr_core_status_ev);
87 csr_port.set_notify_event(PEU_CSR_A_TLU_ECL_HW_ADDR,&tlu_ecl_ev);
88 while(1){
89 //Step 1: Detect reset event
90 wait(*parent_global_ev);
91 switch(*global_event_type){
92 case POR_RESET_ENTER:
93 case WMR_RESET_ENTER:
94 //Step 2: SW Reset activities
95 LOG_DEBUG << "\tDLL: WMR/POR_RESET enter signal..." ;
96 POR_RESET=true;
97 reset_ev.notify();
98 //Wait for all thread to terminate
99 while(1){
100 if(pl_consumer_ph.terminated() && tl_consumer_ph.terminated() &&
101 tl_producer_ph.terminated() && pl_dllp_producer_ph.terminated() &&
102 pl_tlp_producer_ph.terminated() && ltssm_state_check_ph.terminated() &&
103 fc_init_ph.terminated() && fc_update_ph.terminated() &&
104 dll_ctrl_mgmt_ph.terminated() )
105 break;
106 wait(pl_consumer_ph.terminated_event()|tl_consumer_ph.terminated_event()|tl_producer_ph.terminated_event()|pl_dllp_producer_ph.terminated_event()|pl_tlp_producer_ph.terminated_event()|ltssm_state_check_ph.terminated_event()|fc_init_ph.terminated_event()|fc_update_ph.terminated_event()|dll_ctrl_mgmt_ph.terminated_event());
107 }
108 LOG_DEBUG << "DLL: WMR/POR Reset threads terminated" ;
109 while(!queueTL.empty()) queueTL.pop();
110 while(!queue_DLLP.empty()) queue_DLLP.pop();
111 while(!queue_TLP.empty()) queue_TLP.pop();
112 LOG_DEBUG << "DLL: WMR/POR Reset dbs cleared" ;
113 break;
114
115 case POR_RESET_EXIT:
116 case WMR_RESET_EXIT:
117 LOG_DEBUG << "\tDLL: WMR/POR_RESET exit signal..." ;
118 init();
119 //while((csr_port.read_csr(PEU_CSR_A_CORE_STATUS_HW_ADDR)).range(48,44)!=16) wait(csr_core_status_ev);
120 //cs2_ev.notify(); //notify FC_INIT that its good to go.
121 break;
122
123 case SW_RESET_ENTER:
124 LOG_DEBUG<<"DLL: SW_RESET_ENTER";
125 STOP_TIMER=true;
126 break;
127
128 case SW_RESET_EXIT:
129 LOG_DEBUG<<"DLL: SW_RESET_EXIT";
130 STOP_TIMER=false;
131 break;
132 }
133 }//end while(1)
134 }
135
136 void dll_top::dll_ctrl_mgmt()
137 {
138 LOG_DEBUG<<"DLL: dll_ctrl_mgmt begins...";
139 try
140 {
141 while (true)
142 {
143 WAIT1(csr_core_status_ev);
144 csr_data_reg = csr_port.read_csr(PEU_CSR_A_CORE_STATUS_HW_ADDR);
145
146 switch(DL_State)
147 {
148 case DL_INACTIVE:
149 LOG_DEBUG << " Entered DL_INACTIVE state";
150 NAK_SCHEDULED = 0;
151 if ( csr_data_reg.range(48,44) == 16 ) // L) state
152 DL_State = DL_INIT;
153 break;
154 case DL_INIT :
155 LOG_DEBUG << " Entered DL_INIT stage" ;
156
157 if ( INIT_State == FC_INIT1 ) {
158 Csr_Write_Mask = 0;
159 Csr_Write_Mask.range(53,52) = MASK3;
160 Csr_Write_Data = 0;
161 Csr_Write_Data.range(53,52) = MASK1;
162 csr_port.write_csr_mask(PEU_CSR_A_CORE_STATUS_HW_ADDR,Csr_Write_Data,Csr_Write_Mask);
163 }
164 else if ( INIT_State == FC_INIT2 )
165 {
166 Csr_Write_Mask = 0;
167 Csr_Write_Mask.range(53,52) = MASK3;
168 Csr_Write_Data = 0;
169 Csr_Write_Data.range(53,52) = MASK3;
170 csr_port.write_csr_mask(PEU_CSR_A_CORE_STATUS_HW_ADDR,Csr_Write_Data,Csr_Write_Mask);
171 }
172 if ( FC_Init_Complete & (csr_data_reg.range(48,44) == 16) )
173 {
174 Csr_Write_Mask = 0;
175 Csr_Write_Mask.range(53,52) = MASK3;
176 Csr_Write_Data = 0;
177 Csr_Write_Data.range(53,52) = MASK2;
178 csr_port.write_csr_mask(PEU_CSR_A_CORE_STATUS_HW_ADDR,Csr_Write_Data,Csr_Write_Mask);
179 DL_State = DL_ACTIVE;
180 }
181 if ( csr_data_reg.range(48,44) != 16 )
182 {
183 Csr_Write_Mask = 0;
184 Csr_Write_Mask.range(53,52) = MASK3;
185 Csr_Write_Data = 0;
186 Csr_Write_Data.range(53,52) = MASK0;
187 csr_port.write_csr_mask(PEU_CSR_A_CORE_STATUS_HW_ADDR,Csr_Write_Data,Csr_Write_Mask);
188 DL_State = DL_INACTIVE;
189 }
190 break;
191 case DL_ACTIVE :
192 LOG_DEBUG << " Entered DL_ACTIVE stage";
193 DL_Status = 1; // Report DL_UP to TL
194 if ( csr_data_reg.range(48,44) != 16 )
195 {
196 Csr_Write_Mask = 0;
197 Csr_Write_Mask.range(53,52) = MASK3;
198 Csr_Write_Data = 0;
199 Csr_Write_Data.range(53,52) = MASK0;
200 csr_port.write_csr_mask(PEU_CSR_A_CORE_STATUS_HW_ADDR,Csr_Write_Data,Csr_Write_Mask);
201 DL_State = DL_INACTIVE;
202 }
203 break;
204 } // switch
205 }
206 }
207 catch(sc_exception &e){
208 LOG_DEBUG<<"DLL: Out of dll_ctrl_mgmt";
209 }
210 }
211
212}
Full OpenSPARC design & verification tarball including full HDL.