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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / model / pcie / dll / fc_init.cpp
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86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fc_init.cpp
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35
36#include "dll_top.hpp"
37#include "pcie_common/config.hpp"
38#include "pcie_common/packetRefCount.hpp"
39#include "pcie_common/packet.hpp"
40#include "pcie_common/basePacket.hpp"
41#include "pcie_common/logger.hpp"
42
43namespace pcie {
44
45 /** This function sends initialization packets to EP **/
46
47 void dll_top::fc_init(){
48 LOG_DEBUG<<"DLL: fc_init begins...";
49 try{
50 RefPciePacket send_packet1;
51 RefPciePacket send_packet2;
52 RefPciePacket send_packet3;
53 RefPciePacket send_packet4;
54 RefPciePacket send_packet5;
55 RefPciePacket send_packet6;
56 sc_uint<8> data,dllp_byte1,dllp_byte2,dllp_byte3;
57 sc_uint<16> dllp_crc_mapped;
58 sc_uint<64> tlu_ici_hw_reg,tlu_ecl_hw_reg;
59 sc_uint<8> nhc_reg,chc_reg,phc_reg;
60 sc_uint<12> ndc_reg,cdc_reg,pdc_reg;
61
62 /// Main Loop
63 while ( true)
64 {
65 /// Wait for core status register to be updated
66 WAIT(csr_core_status_ev);
67 csr_data_reg = csr_port.read_csr(PEU_CSR_A_CORE_STATUS_HW_ADDR);
68
69 tlu_ici_hw_reg = csr_port.read_csr(PEU_CSR_A_TLU_ICI_HW_ADDR);
70
71 nhc_reg=tlu_ici_hw_reg.range(39,32);
72 chc_reg=tlu_ici_hw_reg.range(59,52);
73 phc_reg=tlu_ici_hw_reg.range(19,12);
74 ndc_reg=tlu_ici_hw_reg.range(31,20);
75 cdc_reg=tlu_ici_hw_reg.range(51,40);
76 pdc_reg=tlu_ici_hw_reg.range(11,0) ;
77
78 if ( (csr_data_reg.range(48,44) == 16) & ~FC_INIT1_Complete )
79 {
80 LOG_DEBUG << "_DLL_: Sending FCINIT1 DLLPS ";
81
82 wait(100,SC_NS);
83 //wait(700,SC_NS);
84
85 dllp_byte1.range(7,6)=0;
86 dllp_byte1.range(5,0)=phc_reg.range(7,2);
87
88 dllp_byte2.range(7,6)=phc_reg.range(1,0);
89 dllp_byte2.range(5,4)=0;
90 dllp_byte2.range(3,0)=pdc_reg.range(11,8);
91
92 dllp_byte3 = pdc_reg.range(7,0);
93
94 send_packet1 = new pciePacket(6);
95 send_packet1->modify_byte(0,DLLP_INITFC1_P); // initfc1_p vc=0
96 send_packet1->modify_byte(1,dllp_byte1);
97 send_packet1->modify_byte(2,dllp_byte2);
98 send_packet1->modify_byte(3,dllp_byte3);
99
100 dllp_crc_mapped=calculate_dllp_crc(send_packet1,0,4);
101 send_packet1->modify_byte(4,dllp_crc_mapped.range(15,8));
102 send_packet1->modify_byte(5,dllp_crc_mapped.range(7,0));
103
104 send_packet1->set_control(SDP_CONTROL);
105
106 dll_pl_dllp_out.send_packet(send_packet1);
107 //send_packet1->dll2pl_display_sdp_packet(1);
108
109
110 wait(5,SC_NS);
111
112 dllp_byte1.range(7,6)=0;
113 dllp_byte1.range(5,0)=nhc_reg.range(7,2);
114
115 dllp_byte2.range(7,6)=nhc_reg.range(1,0);
116 dllp_byte2.range(5,4)=0;
117 dllp_byte2.range(3,0)=ndc_reg.range(11,8);
118
119 dllp_byte3 = ndc_reg.range(7,0);
120
121 send_packet2 = new pciePacket(6);
122 send_packet2->modify_byte(0,DLLP_INITFC1_NP);
123 send_packet2->modify_byte(1,dllp_byte1);
124 send_packet2->modify_byte(2,dllp_byte2);
125 send_packet2->modify_byte(3,dllp_byte3);
126
127 dllp_crc_mapped=calculate_dllp_crc(send_packet2,0,4);
128 send_packet2->modify_byte(4,dllp_crc_mapped.range(15,8));
129 send_packet2->modify_byte(5,dllp_crc_mapped.range(7,0));
130 send_packet2->set_control(SDP_CONTROL);
131
132 dll_pl_dllp_out.send_packet(send_packet2);
133 //send_packet2->dll2pl_display_sdp_packet(1);
134
135 wait(5,SC_NS);
136
137 LOG_DEBUG << " FCINIT1: Sending InitFC1_Cpl " ;
138
139 send_packet3 = new pciePacket(6);
140
141 dllp_byte1.range(7,6)=0;
142 dllp_byte1.range(5,0)=chc_reg.range(7,2);
143
144 dllp_byte2.range(7,6)=chc_reg.range(1,0);
145 dllp_byte2.range(5,4)=0;
146 dllp_byte2.range(3,0)=cdc_reg.range(11,8);
147
148 dllp_byte3 = cdc_reg.range(7,0);
149
150 send_packet3->modify_byte(0,DLLP_INITFC1_CPL);
151 send_packet3->modify_byte(1,dllp_byte1);
152 send_packet3->modify_byte(2,dllp_byte2);
153 send_packet3->modify_byte(3,dllp_byte3);
154
155 dllp_crc_mapped=calculate_dllp_crc(send_packet3,0,4);
156 send_packet3->modify_byte(4,dllp_crc_mapped.range(15,8));
157 send_packet3->modify_byte(5,dllp_crc_mapped.range(7,0));
158
159 send_packet3->set_control(SDP_CONTROL);
160
161 dll_pl_dllp_out.send_packet(send_packet3);
162 //send_packet3->dll2pl_display_sdp_packet(1);
163
164 wait(5,SC_NS);
165
166 FC_INIT1_Complete=1;
167 }
168
169 if ( (csr_data_reg.range(48,44) == 16) & ~FC_INIT2_Complete & FC_INIT1_Complete )
170 {
171 LOG_DEBUG << "_DLL_: Sending FCINIT2 DLLPS " ;
172
173 dllp_byte1.range(7,6)=0;
174 dllp_byte1.range(5,0)=phc_reg.range(7,2);
175
176 dllp_byte2.range(7,6)=phc_reg.range(1,0);
177 dllp_byte2.range(5,4)=0;
178 dllp_byte2.range(3,0)=pdc_reg.range(11,8);
179
180 dllp_byte3 = pdc_reg.range(7,0);
181
182 send_packet4 = new pciePacket(6);
183 send_packet4->modify_byte(0,DLLP_INITFC2_P);
184 send_packet4->modify_byte(1,dllp_byte1);
185 send_packet4->modify_byte(2,dllp_byte2);
186 send_packet4->modify_byte(3,dllp_byte3);
187
188 dllp_crc_mapped=calculate_dllp_crc(send_packet4,0,4);
189 send_packet4->modify_byte(4,dllp_crc_mapped.range(15,8));
190 send_packet4->modify_byte(5,dllp_crc_mapped.range(7,0));
191 send_packet4->set_control(SDP_CONTROL);
192
193 dll_pl_dllp_out.send_packet(send_packet4);
194 //send_packet4->dll2pl_display_sdp_packet(1);
195
196 wait(5,SC_NS);
197
198 dllp_byte1.range(7,6)=0;
199 dllp_byte1.range(5,0)=nhc_reg.range(7,2);
200
201 dllp_byte2.range(7,6)=nhc_reg.range(1,0);
202 dllp_byte2.range(5,4)=0;
203 dllp_byte2.range(3,0)=ndc_reg.range(11,8);
204
205 dllp_byte3 = ndc_reg.range(7,0);
206
207 send_packet5 = new pciePacket(6);
208
209 send_packet5->modify_byte(0,DLLP_INITFC2_NP);
210 send_packet5->modify_byte(1,dllp_byte1);
211 send_packet5->modify_byte(2,dllp_byte2);
212 send_packet5->modify_byte(3,dllp_byte3);
213
214 dllp_crc_mapped=calculate_dllp_crc(send_packet5,0,4);
215 send_packet5->modify_byte(4,dllp_crc_mapped.range(15,8));
216 send_packet5->modify_byte(5,dllp_crc_mapped.range(7,0));
217 send_packet5->set_control(SDP_CONTROL);
218
219 dll_pl_dllp_out.send_packet(send_packet5);
220 //send_packet5->dll2pl_display_sdp_packet(1);
221
222 wait(5,SC_NS);
223
224 dllp_byte1.range(7,6)=0;
225 dllp_byte1.range(5,0)=chc_reg.range(7,2);
226
227 dllp_byte2.range(7,6)=chc_reg.range(1,0);
228 dllp_byte2.range(5,4)=0;
229 dllp_byte2.range(3,0)=cdc_reg.range(11,8);
230
231 dllp_byte3 = cdc_reg.range(7,0);
232
233 send_packet6 = new pciePacket(6);
234
235 send_packet6->modify_byte(0,DLLP_INITFC2_CPL);
236 send_packet6->modify_byte(1,dllp_byte1);
237 send_packet6->modify_byte(2,dllp_byte2);
238 send_packet6->modify_byte(3,dllp_byte3);
239
240 dllp_crc_mapped=calculate_dllp_crc(send_packet6,0,4);
241 send_packet6->modify_byte(4,dllp_crc_mapped.range(15,8));
242 send_packet6->modify_byte(5,dllp_crc_mapped.range(7,0));
243 send_packet6->set_control(SDP_CONTROL);
244
245 dll_pl_dllp_out.send_packet(send_packet6);
246 //send_packet6->dll2pl_display_sdp_packet(1);
247
248 FC_INIT2_Complete=1;
249 wait(5,SC_NS);
250 }
251
252 if ( FC_INIT1_Complete & FC_INIT2_Complete )
253 {
254 LOG_DEBUG << "_DLL_: FC_Init_Complete is true! \n";
255 FC_Init_Complete =1;
256 break;
257 }
258 } // while
259 }
260 catch(sc_exception &e){
261 LOG_DEBUG<<"DLL: Out of fc_init";
262 }
263 } // fc_init
264
265
266 /** This function sends update packets to EP **/
267
268 void dll_top::fc_update(){
269 LOG_DEBUG<<"DLL: fc_update begins...";
270 try{
271 RefPciePacket send_packet1;
272 RefPciePacket send_packet2;
273 RefPciePacket send_packet3;
274
275 sc_uint<8> data,dllp_byte1,dllp_byte2,dllp_byte3;
276 sc_uint<16> dllp_crc_mapped;
277 sc_uint<8> nhc_reg,chc_reg,phc_reg;
278 sc_uint<12> ndc_reg,cdc_reg,pdc_reg;
279
280 sc_uint<8> prev_nhc_reg,prev_chc_reg,prev_phc_reg;
281 sc_uint<12> prev_ndc_reg,prev_cdc_reg,prev_pdc_reg;
282
283 sc_uint<64> tlu_ica_reg;
284 sc_uint<64> tlu_ici_reg;
285 sc_uint<64> tlu_icr_reg;
286
287 tlu_ica_reg = csr_port.read_csr(PEU_CSR_A_TLU_ICA_HW_ADDR);
288 tlu_ici_reg = csr_port.read_csr(PEU_CSR_A_TLU_ICI_HW_ADDR);
289 tlu_icr_reg = csr_port.read_csr(PEU_CSR_A_TLU_ICR_HW_ADDR);
290
291 prev_chc_reg=tlu_ica_reg.range(59,52);
292 prev_cdc_reg=tlu_ica_reg.range(51,40);
293 prev_nhc_reg=tlu_ica_reg.range(39,32);
294 prev_ndc_reg=tlu_ica_reg.range(31,20) ;
295 prev_phc_reg=tlu_ica_reg.range(19,12) ;
296 prev_pdc_reg=tlu_ica_reg.range(11,0) ;
297 chc_reg=tlu_ica_reg.range(59,52);
298 cdc_reg=tlu_ica_reg.range(51,40);
299 nhc_reg=tlu_ica_reg.range(39,32);
300 ndc_reg=tlu_ica_reg.range(31,20) ;
301 phc_reg=tlu_ica_reg.range(19,12) ;
302 pdc_reg=tlu_ica_reg.range(11,0) ;
303
304 while(true)
305 {
306 //if(!POR_RESET) wait(sc_time(25,SC_NS),credit_consumed_ev,reset_ev);
307 if(!POR_RESET) wait(sc_time(400,SC_NS),credit_consumed_ev|reset_ev);
308 if(POR_RESET) throw sc_exception();
309
310 if(FC_Init_Complete && (csr_port.read_csr(PEU_CSR_A_CORE_STATUS_HW_ADDR)).range(48,44)==16){
311
312 if(STOP_TIMER){
313 if(!POR_RESET) wait(sc_time(125,SC_NS),reset_ev);
314 if(POR_RESET) throw sc_exception();
315 tlu_icr_reg = csr_port.read_csr(PEU_CSR_A_TLU_ICR_HW_ADDR);
316 }
317
318 tlu_ica_reg = csr_port.read_csr(PEU_CSR_A_TLU_ICA_HW_ADDR);
319
320 chc_reg=tlu_ica_reg.range(59,52);
321 cdc_reg=tlu_ica_reg.range(51,40);
322 nhc_reg=tlu_ica_reg.range(39,32);
323 ndc_reg=tlu_ica_reg.range(31,20) ;
324 phc_reg=tlu_ica_reg.range(19,12) ;
325 pdc_reg=tlu_ica_reg.range(11,0) ;
326
327 if( chc_reg!=prev_chc_reg ||
328 cdc_reg!=prev_cdc_reg ||
329 (STOP_TIMER && ( (chc_reg!=0 && chc_reg==tlu_icr_reg.range(59,52)) ||
330 (cdc_reg!=0 && cdc_reg==tlu_icr_reg.range(51,40)) ))
331 ){
332
333 LOG_DEBUG<<"== DLL: Sending UpdateFC_CPL...";
334
335 if(STOP_TIMER){
336 if(!chc_reg==0) chc_reg += tlu_ici_reg.range(59,52);
337 if(!cdc_reg==0) cdc_reg += tlu_ici_reg.range(51,40);
338 }
339
340 dllp_byte1.range(7,6)=0;
341 dllp_byte1.range(5,0)=chc_reg.range(7,2);
342
343 dllp_byte2.range(7,6)=chc_reg.range(1,0);
344 dllp_byte2.range(5,4)=0;
345 dllp_byte2.range(3,0)=cdc_reg.range(11,8);
346
347 dllp_byte3 = cdc_reg.range(7,0);
348
349 send_packet3 = new pciePacket(6);
350 send_packet3->modify_byte(0,DLLP_UPDATEFC_CPL);
351 send_packet3->modify_byte(1,dllp_byte1);
352 send_packet3->modify_byte(2,dllp_byte2);
353 send_packet3->modify_byte(3,dllp_byte3);
354
355 dllp_crc_mapped=calculate_dllp_crc(send_packet3,0,4);
356 send_packet3->modify_byte(4,dllp_crc_mapped.range(15,8));
357 send_packet3->modify_byte(5,dllp_crc_mapped.range(7,0));
358
359 send_packet3->set_control(SDP_CONTROL);
360
361 dll_pl_dllp_out.send_packet(send_packet3);
362 //send_packet3->dll2pl_display_sdp_packet(1);
363 }
364
365 if(nhc_reg!=prev_nhc_reg || ndc_reg!=prev_ndc_reg ||
366 (STOP_TIMER && ((nhc_reg!=0 && nhc_reg==tlu_icr_reg.range(39,32)) ||
367 (ndc_reg!=0 && ndc_reg==tlu_icr_reg.range(31,20)) ) )){
368
369 LOG_DEBUG<<"== DLL: Sending UpdateFC_NP...";
370
371 if(STOP_TIMER){
372 if(!nhc_reg==0) nhc_reg = nhc_reg + tlu_ici_reg.range(39,32);
373 if(!ndc_reg==0) ndc_reg = ndc_reg + tlu_ici_reg.range(31,20);
374 }
375
376 dllp_byte1.range(7,6)=0;
377 dllp_byte1.range(5,0)=nhc_reg.range(7,2);
378
379 dllp_byte2.range(7,6)=nhc_reg.range(1,0);
380 dllp_byte2.range(5,4)=0;
381 dllp_byte2.range(3,0)=ndc_reg.range(11,8);
382
383 dllp_byte3 = ndc_reg.range(7,0);
384
385 send_packet2 = new pciePacket(6);
386 send_packet2->modify_byte(0,DLLP_UPDATEFC_NP);
387 send_packet2->modify_byte(1,dllp_byte1);
388 send_packet2->modify_byte(2,dllp_byte2);
389 send_packet2->modify_byte(3,dllp_byte3);
390
391 dllp_crc_mapped=calculate_dllp_crc(send_packet2,0,4);
392 send_packet2->modify_byte(4,dllp_crc_mapped.range(15,8));
393 send_packet2->modify_byte(5,dllp_crc_mapped.range(7,0));
394 send_packet2->set_control(SDP_CONTROL);
395
396 dll_pl_dllp_out.send_packet(send_packet2);
397 //send_packet2->dll2pl_display_sdp_packet(1);
398 }
399
400 if(phc_reg!=prev_phc_reg || pdc_reg!=prev_pdc_reg ||
401 (STOP_TIMER && ((phc_reg!=0 && phc_reg==tlu_icr_reg.range(19,12)) ||
402 ( pdc_reg!=0 &&pdc_reg==tlu_icr_reg.range(11,0)) ) )){
403
404 LOG_DEBUG<<"==== DLL: Sending UpdateFC_P ====";
405 if(STOP_TIMER){
406 if(!phc_reg==0) phc_reg = phc_reg + tlu_ici_reg.range(19,12);
407 if(!pdc_reg==0) pdc_reg = pdc_reg + tlu_ici_reg.range(11,0);
408 }
409
410 dllp_byte1.range(7,6)=0;
411 dllp_byte1.range(5,0)=phc_reg.range(7,2);
412
413 dllp_byte2.range(7,6)=phc_reg.range(1,0);
414 dllp_byte2.range(5,4)=0;
415 dllp_byte2.range(3,0)=pdc_reg.range(11,8);
416
417 dllp_byte3 = pdc_reg.range(7,0);
418
419 send_packet1 = new pciePacket(6);
420 send_packet1->modify_byte(0,DLLP_UPDATEFC_P);
421 send_packet1->modify_byte(1,dllp_byte1);
422 send_packet1->modify_byte(2,dllp_byte2);
423 send_packet1->modify_byte(3,dllp_byte3);
424
425 dllp_crc_mapped=calculate_dllp_crc(send_packet1,0,4);
426 send_packet1->modify_byte(4,dllp_crc_mapped.range(15,8));
427 send_packet1->modify_byte(5,dllp_crc_mapped.range(7,0));
428 send_packet1->set_control(SDP_CONTROL);
429
430 dll_pl_dllp_out.send_packet(send_packet1);
431 //send_packet1->dll2pl_display_sdp_packet(1);
432 }
433 if(STOP_TIMER){
434 tlu_ica_reg.range(59,52)=chc_reg;
435 tlu_ica_reg.range(51,40)=cdc_reg;
436 tlu_ica_reg.range(19,12)=phc_reg;
437 tlu_ica_reg.range(11,0)=pdc_reg;
438 tlu_ica_reg.range(39,32)=nhc_reg;
439 tlu_ica_reg.range(31,20)=ndc_reg;
440 csr_port.write_csr(PEU_CSR_A_TLU_ICA_HW_ADDR,tlu_ica_reg);
441 }
442
443 prev_chc_reg=chc_reg;
444 prev_cdc_reg=cdc_reg;
445 prev_nhc_reg=nhc_reg;
446 prev_ndc_reg=ndc_reg;
447 prev_phc_reg=phc_reg;
448 prev_pdc_reg=pdc_reg;
449 } // if
450 } // while
451 }
452 catch(sc_exception &e){
453 LOG_DEBUG<<"DLL: Out of fc_update";
454 }
455 } //fc_update
456
457 sc_uint<14> dll_top::get_mps(){
458 sc_uint<14> mps;
459 sc_uint<64> dev_ctl;
460 sc_uint<3> dev_mps;
461 dev_ctl = csr_port.read_csr(PEU_CSR_A_DEV_CTL_HW_ADDR);
462 dev_mps = dev_ctl(7,5);
463 switch(dev_mps){
464 case 0: return 128;
465 case 1: return 256;
466 case 2: return 512;
467 case 3: return 1024;
468 case 4: return 2048;
469 case 5: return 4096;
470 default: LOG_ERROR<<"ERROR: Reserved mps field value in PEU Device Control CSR";
471 return 0; //cause simulation to end with divide by zero
472 }
473 }//end get_mps
474
475
476 void dll_top::credit_checker(){
477 sc_event ica_event, icr_event;
478 csr_port.set_notify_event(PEU_CSR_A_TLU_ICA_HW_ADDR, &ica_event);
479 csr_port.set_notify_event(PEU_CSR_A_TLU_ICR_HW_ADDR, &icr_event);
480 sc_uint<64> tlu_ica_reg = csr_port.read_csr(PEU_CSR_A_TLU_ICA_HW_ADDR);
481 sc_uint<64> tlu_icr_reg = csr_port.read_csr(PEU_CSR_A_TLU_ICR_HW_ADDR);
482
483 while(1){
484 wait(ica_event|icr_event);
485 tlu_ica_reg = csr_port.read_csr(PEU_CSR_A_TLU_ICA_HW_ADDR);
486 tlu_icr_reg = csr_port.read_csr(PEU_CSR_A_TLU_ICR_HW_ADDR);
487 if( (tlu_ica_reg.range(59,52)!=0 && tlu_ica_reg.range(59,52)==tlu_icr_reg.range(59,52)) ||
488 (tlu_ica_reg.range(51,40)!=0 && tlu_ica_reg.range(51,40)==tlu_icr_reg.range(51,40)) ||
489 (tlu_ica_reg.range(39,32)!=0 && tlu_ica_reg.range(39,32)==tlu_icr_reg.range(39,32)) ||
490 (tlu_ica_reg.range(31,20)!=0 && tlu_ica_reg.range(31,20)==tlu_icr_reg.range(31,20)) ||
491 (tlu_ica_reg.range(19,12)!=0 && tlu_ica_reg.range(19,12)==tlu_icr_reg.range(19,12)) ||
492 (tlu_ica_reg.range(11,0)!=0 && tlu_ica_reg.range(11,0)==tlu_icr_reg.range(11,0)) )
493 credit_consumed_ev.notify();
494 }
495
496
497 }
498
499}
Full OpenSPARC design & verification tarball including full HDL.