projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: peu_csr_defines.hpp | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | #ifndef INC_peu_csr_defines_hpp__ | |
| 36 | #define INC_peu_csr_defines_hpp__ | |
| 37 | ||
| 38 | ||
| 39 | #define PEU_INSTANCE_ID_VALUE_A 0 | |
| 40 | #define PEU_INSTANCE_ID_VALUE_B 1 | |
| 41 | ||
| 42 | #define PEU_CSR_A_TLU_CTL_HW_ADDR sc_uint<64>("0b000000011010000000000000000") | |
| 43 | #define PEU_CSR_B_TLU_CTL_HW_ADDR sc_uint<64>("0b000000011110000000000000000") | |
| 44 | #define PEU_CSR_A_TLU_STS_HW_ADDR sc_uint<64>("0b000000011010000000000000001") | |
| 45 | #define PEU_CSR_B_TLU_STS_HW_ADDR sc_uint<64>("0b000000011110000000000000001") | |
| 46 | #define PEU_CSR_A_TRN_OFF_HW_ADDR sc_uint<64>("0b000000011010000000000000010") | |
| 47 | #define PEU_CSR_B_TRN_OFF_HW_ADDR sc_uint<64>("0b000000011110000000000000010") | |
| 48 | #define PEU_CSR_A_TLU_ICI_HW_ADDR sc_uint<64>("0b000000011010000000000000011") | |
| 49 | #define PEU_CSR_B_TLU_ICI_HW_ADDR sc_uint<64>("0b000000011110000000000000011") | |
| 50 | #define PEU_CSR_A_TLU_DIAG_HW_ADDR sc_uint<64>("0b000000011010000000000100000") | |
| 51 | #define PEU_CSR_B_TLU_DIAG_HW_ADDR sc_uint<64>("0b000000011110000000000100000") | |
| 52 | #define PEU_CSR_A_TLU_ECC_HW_ADDR sc_uint<64>("0b000000011010000000001000000") | |
| 53 | #define PEU_CSR_B_TLU_ECC_HW_ADDR sc_uint<64>("0b000000011110000000001000000") | |
| 54 | #define PEU_CSR_A_TLU_ECL_HW_ADDR sc_uint<64>("0b000000011010000000001000001") | |
| 55 | #define PEU_CSR_B_TLU_ECL_HW_ADDR sc_uint<64>("0b000000011110000000001000001") | |
| 56 | #define PEU_CSR_A_TLU_ERB_HW_ADDR sc_uint<64>("0b000000011010000000001000010") | |
| 57 | #define PEU_CSR_B_TLU_ERB_HW_ADDR sc_uint<64>("0b000000011110000000001000010") | |
| 58 | #define PEU_CSR_A_TLU_ICA_HW_ADDR sc_uint<64>("0b000000011010000000001000011") | |
| 59 | #define PEU_CSR_B_TLU_ICA_HW_ADDR sc_uint<64>("0b000000011110000000001000011") | |
| 60 | #define PEU_CSR_A_TLU_ICR_HW_ADDR sc_uint<64>("0b000000011010000000001000100") | |
| 61 | #define PEU_CSR_B_TLU_ICR_HW_ADDR sc_uint<64>("0b000000011110000000001000100") | |
| 62 | #define PEU_CSR_A_OE_LOG_HW_ADDR sc_uint<64>("0b000000011010000001000000000") | |
| 63 | #define PEU_CSR_B_OE_LOG_HW_ADDR sc_uint<64>("0b000000011110000001000000000") | |
| 64 | #define PEU_CSR_A_OE_INT_EN_HW_ADDR sc_uint<64>("0b000000011010000001000000001") | |
| 65 | #define PEU_CSR_B_OE_INT_EN_HW_ADDR sc_uint<64>("0b000000011110000001000000001") | |
| 66 | #define PEU_CSR_A_OE_EN_ERR_HW_ADDR sc_uint<64>("0b000000011010000001000000010") | |
| 67 | #define PEU_CSR_B_OE_EN_ERR_HW_ADDR sc_uint<64>("0b000000011110000001000000010") | |
| 68 | #define PEU_CSR_A_OE_ERR_RW1C_ALIAS_HW_ADDR sc_uint<64>("0b000000011010000001000000011") | |
| 69 | #define PEU_CSR_B_OE_ERR_RW1C_ALIAS_HW_ADDR sc_uint<64>("0b000000011110000001000000011") | |
| 70 | #define PEU_CSR_A_OE_ERR_RW1S_ALIAS_HW_ADDR sc_uint<64>("0b000000011010000001000000100") | |
| 71 | #define PEU_CSR_B_OE_ERR_RW1S_ALIAS_HW_ADDR sc_uint<64>("0b000000011110000001000000100") | |
| 72 | #define PEU_CSR_A_ROE_HDR1_HW_ADDR sc_uint<64>("0b000000011010000001000000101") | |
| 73 | #define PEU_CSR_B_ROE_HDR1_HW_ADDR sc_uint<64>("0b000000011110000001000000101") | |
| 74 | #define PEU_CSR_A_ROE_HDR2_HW_ADDR sc_uint<64>("0b000000011010000001000000110") | |
| 75 | #define PEU_CSR_B_ROE_HDR2_HW_ADDR sc_uint<64>("0b000000011110000001000000110") | |
| 76 | #define PEU_CSR_A_TOE_HDR1_HW_ADDR sc_uint<64>("0b000000011010000001000000111") | |
| 77 | #define PEU_CSR_B_TOE_HDR1_HW_ADDR sc_uint<64>("0b000000011110000001000000111") | |
| 78 | #define PEU_CSR_A_TOE_HDR2_HW_ADDR sc_uint<64>("0b000000011010000001000001000") | |
| 79 | #define PEU_CSR_B_TOE_HDR2_HW_ADDR sc_uint<64>("0b000000011110000001000001000") | |
| 80 | #define PEU_CSR_A_TLU_PRFC_HW_ADDR sc_uint<64>("0b000000011010000010000000000") | |
| 81 | #define PEU_CSR_B_TLU_PRFC_HW_ADDR sc_uint<64>("0b000000011110000010000000000") | |
| 82 | #define PEU_CSR_A_TLU_PRF0_HW_ADDR sc_uint<64>("0b000000011010000010000000001") | |
| 83 | #define PEU_CSR_B_TLU_PRF0_HW_ADDR sc_uint<64>("0b000000011110000010000000001") | |
| 84 | #define PEU_CSR_A_TLU_PRF1_HW_ADDR sc_uint<64>("0b000000011010000010000000010") | |
| 85 | #define PEU_CSR_B_TLU_PRF1_HW_ADDR sc_uint<64>("0b000000011110000010000000010") | |
| 86 | #define PEU_CSR_A_TLU_PRF2_HW_ADDR sc_uint<64>("0b000000011010000010000000011") | |
| 87 | #define PEU_CSR_B_TLU_PRF2_HW_ADDR sc_uint<64>("0b000000011110000010000000011") | |
| 88 | #define PEU_CSR_A_TLU_DBG_SEL_A_HW_ADDR sc_uint<64>("0b000000011010000011000000000") | |
| 89 | #define PEU_CSR_B_TLU_DBG_SEL_A_HW_ADDR sc_uint<64>("0b000000011110000011000000000") | |
| 90 | #define PEU_CSR_A_TLU_DBG_SEL_B_HW_ADDR sc_uint<64>("0b000000011010000011000000001") | |
| 91 | #define PEU_CSR_B_TLU_DBG_SEL_B_HW_ADDR sc_uint<64>("0b000000011110000011000000001") | |
| 92 | #define PEU_CSR_A_DEV_CAP_HW_ADDR sc_uint<64>("0b000000011010010000000000000") | |
| 93 | #define PEU_CSR_B_DEV_CAP_HW_ADDR sc_uint<64>("0b000000011110010000000000000") | |
| 94 | #define PEU_CSR_A_DEV_CTL_HW_ADDR sc_uint<64>("0b000000011010010000000000001") | |
| 95 | #define PEU_CSR_B_DEV_CTL_HW_ADDR sc_uint<64>("0b000000011110010000000000001") | |
| 96 | #define PEU_CSR_A_DEV_STS_HW_ADDR sc_uint<64>("0b000000011010010000000000010") | |
| 97 | #define PEU_CSR_B_DEV_STS_HW_ADDR sc_uint<64>("0b000000011110010000000000010") | |
| 98 | #define PEU_CSR_A_LNK_CAP_HW_ADDR sc_uint<64>("0b000000011010010000000000011") | |
| 99 | #define PEU_CSR_B_LNK_CAP_HW_ADDR sc_uint<64>("0b000000011110010000000000011") | |
| 100 | #define PEU_CSR_A_LNK_CTL_HW_ADDR sc_uint<64>("0b000000011010010000000000100") | |
| 101 | #define PEU_CSR_B_LNK_CTL_HW_ADDR sc_uint<64>("0b000000011110010000000000100") | |
| 102 | #define PEU_CSR_A_LNK_STS_HW_ADDR sc_uint<64>("0b000000011010010000000000101") | |
| 103 | #define PEU_CSR_B_LNK_STS_HW_ADDR sc_uint<64>("0b000000011110010000000000101") | |
| 104 | #define PEU_CSR_A_SLT_CAP_HW_ADDR sc_uint<64>("0b000000011010010000000000110") | |
| 105 | #define PEU_CSR_B_SLT_CAP_HW_ADDR sc_uint<64>("0b000000011110010000000000110") | |
| 106 | #define PEU_CSR_A_UE_LOG_HW_ADDR sc_uint<64>("0b000000011010010001000000000") | |
| 107 | #define PEU_CSR_B_UE_LOG_HW_ADDR sc_uint<64>("0b000000011110010001000000000") | |
| 108 | #define PEU_CSR_A_UE_INT_EN_HW_ADDR sc_uint<64>("0b000000011010010001000000001") | |
| 109 | #define PEU_CSR_B_UE_INT_EN_HW_ADDR sc_uint<64>("0b000000011110010001000000001") | |
| 110 | #define PEU_CSR_A_UE_EN_ERR_HW_ADDR sc_uint<64>("0b000000011010010001000000010") | |
| 111 | #define PEU_CSR_B_UE_EN_ERR_HW_ADDR sc_uint<64>("0b000000011110010001000000010") | |
| 112 | #define PEU_CSR_A_UE_ERR_RW1C_ALIAS_HW_ADDR sc_uint<64>("0b000000011010010001000000011") | |
| 113 | #define PEU_CSR_B_UE_ERR_RW1C_ALIAS_HW_ADDR sc_uint<64>("0b000000011110010001000000011") | |
| 114 | #define PEU_CSR_A_UE_ERR_RW1S_ALIAS_HW_ADDR sc_uint<64>("0b000000011010010001000000100") | |
| 115 | #define PEU_CSR_B_UE_ERR_RW1S_ALIAS_HW_ADDR sc_uint<64>("0b000000011110010001000000100") | |
| 116 | #define PEU_CSR_A_RUE_HDR1_HW_ADDR sc_uint<64>("0b000000011010010001000000101") | |
| 117 | #define PEU_CSR_B_RUE_HDR1_HW_ADDR sc_uint<64>("0b000000011110010001000000101") | |
| 118 | #define PEU_CSR_A_RUE_HDR2_HW_ADDR sc_uint<64>("0b000000011010010001000000110") | |
| 119 | #define PEU_CSR_B_RUE_HDR2_HW_ADDR sc_uint<64>("0b000000011110010001000000110") | |
| 120 | #define PEU_CSR_A_TUE_HDR1_HW_ADDR sc_uint<64>("0b000000011010010001000000111") | |
| 121 | #define PEU_CSR_B_TUE_HDR1_HW_ADDR sc_uint<64>("0b000000011110010001000000111") | |
| 122 | #define PEU_CSR_A_TUE_HDR2_HW_ADDR sc_uint<64>("0b000000011010010001000001000") | |
| 123 | #define PEU_CSR_B_TUE_HDR2_HW_ADDR sc_uint<64>("0b000000011110010001000001000") | |
| 124 | #define PEU_CSR_A_CE_LOG_HW_ADDR sc_uint<64>("0b000000011010100001000000000") | |
| 125 | #define PEU_CSR_B_CE_LOG_HW_ADDR sc_uint<64>("0b000000011110100001000000000") | |
| 126 | #define PEU_CSR_A_CE_INT_EN_HW_ADDR sc_uint<64>("0b000000011010100001000000001") | |
| 127 | #define PEU_CSR_B_CE_INT_EN_HW_ADDR sc_uint<64>("0b000000011110100001000000001") | |
| 128 | #define PEU_CSR_A_CE_EN_ERR_HW_ADDR sc_uint<64>("0b000000011010100001000000010") | |
| 129 | #define PEU_CSR_B_CE_EN_ERR_HW_ADDR sc_uint<64>("0b000000011110100001000000010") | |
| 130 | #define PEU_CSR_A_CE_ERR_RW1C_ALIAS_HW_ADDR sc_uint<64>("0b000000011010100001000000011") | |
| 131 | #define PEU_CSR_B_CE_ERR_RW1C_ALIAS_HW_ADDR sc_uint<64>("0b000000011110100001000000011") | |
| 132 | #define PEU_CSR_A_CE_ERR_RW1S_ALIAS_HW_ADDR sc_uint<64>("0b000000011010100001000000100") | |
| 133 | #define PEU_CSR_B_CE_ERR_RW1S_ALIAS_HW_ADDR sc_uint<64>("0b000000011110100001000000100") | |
| 134 | #define PEU_CSR_A_PEU_DLPL_SERDES_REV_HW_ADDR sc_uint<64>("0b000000011011100010000000000") | |
| 135 | #define PEU_CSR_B_PEU_DLPL_SERDES_REV_HW_ADDR sc_uint<64>("0b000000011111100010000000000") | |
| 136 | #define PEU_CSR_A_ACKNAK_THRESH_HW_ADDR sc_uint<64>("0b000000011011100010000000001") | |
| 137 | #define PEU_CSR_B_ACKNAK_THRESH_HW_ADDR sc_uint<64>("0b000000011111100010000000001") | |
| 138 | #define PEU_CSR_A_ACKNAK_TIMER_HW_ADDR sc_uint<64>("0b000000011011100010000000010") | |
| 139 | #define PEU_CSR_B_ACKNAK_TIMER_HW_ADDR sc_uint<64>("0b000000011111100010000000010") | |
| 140 | #define PEU_CSR_A_REPLAY_TIM_THRESH_HW_ADDR sc_uint<64>("0b000000011011100010000000011") | |
| 141 | #define PEU_CSR_B_REPLAY_TIM_THRESH_HW_ADDR sc_uint<64>("0b000000011111100010000000011") | |
| 142 | #define PEU_CSR_A_REPLAY_TIMER_HW_ADDR sc_uint<64>("0b000000011011100010000000100") | |
| 143 | #define PEU_CSR_B_REPLAY_TIMER_HW_ADDR sc_uint<64>("0b000000011111100010000000100") | |
| 144 | #define PEU_CSR_A_VEN_DLLP_MSG_HW_ADDR sc_uint<64>("0b000000011011100010000001000") | |
| 145 | #define PEU_CSR_B_VEN_DLLP_MSG_HW_ADDR sc_uint<64>("0b000000011111100010000001000") | |
| 146 | #define PEU_CSR_A_FORCE_LTSSM_HW_ADDR sc_uint<64>("0b000000011011100010000001010") | |
| 147 | #define PEU_CSR_B_FORCE_LTSSM_HW_ADDR sc_uint<64>("0b000000011111100010000001010") | |
| 148 | #define PEU_CSR_A_LINK_CFG_HW_ADDR sc_uint<64>("0b000000011011100010000001011") | |
| 149 | #define PEU_CSR_B_LINK_CFG_HW_ADDR sc_uint<64>("0b000000011111100010000001011") | |
| 150 | #define PEU_CSR_A_LINK_CTL_HW_ADDR sc_uint<64>("0b000000011011100010000001100") | |
| 151 | #define PEU_CSR_B_LINK_CTL_HW_ADDR sc_uint<64>("0b000000011111100010000001100") | |
| 152 | #define PEU_CSR_A_LANE_SKEW_HW_ADDR sc_uint<64>("0b000000011011100010000001101") | |
| 153 | #define PEU_CSR_B_LANE_SKEW_HW_ADDR sc_uint<64>("0b000000011111100010000001101") | |
| 154 | #define PEU_CSR_A_SYMBOL_NUM_HW_ADDR sc_uint<64>("0b000000011011100010000001110") | |
| 155 | #define PEU_CSR_B_SYMBOL_NUM_HW_ADDR sc_uint<64>("0b000000011111100010000001110") | |
| 156 | #define PEU_CSR_A_SYMBOL_TIMER_HW_ADDR sc_uint<64>("0b000000011011100010000001111") | |
| 157 | #define PEU_CSR_B_SYMBOL_TIMER_HW_ADDR sc_uint<64>("0b000000011111100010000001111") | |
| 158 | #define PEU_CSR_A_CORE_STATUS_HW_ADDR sc_uint<64>("0b000000011011100010000100000") | |
| 159 | #define PEU_CSR_B_CORE_STATUS_HW_ADDR sc_uint<64>("0b000000011111100010000100000") | |
| 160 | #define PEU_CSR_A_EVENT_ERR_LOG_EN_HW_ADDR sc_uint<64>("0b000000011011100010000100001") | |
| 161 | #define PEU_CSR_B_EVENT_ERR_LOG_EN_HW_ADDR sc_uint<64>("0b000000011111100010000100001") | |
| 162 | #define PEU_CSR_A_EVENT_ERR_INT_EN_HW_ADDR sc_uint<64>("0b000000011011100010000100010") | |
| 163 | #define PEU_CSR_B_EVENT_ERR_INT_EN_HW_ADDR sc_uint<64>("0b000000011111100010000100010") | |
| 164 | #define PEU_CSR_A_EVENT_ERR_INT_STS_HW_ADDR sc_uint<64>("0b000000011011100010000100011") | |
| 165 | #define PEU_CSR_B_EVENT_ERR_INT_STS_HW_ADDR sc_uint<64>("0b000000011111100010000100011") | |
| 166 | #define PEU_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_HW_ADDR sc_uint<64>("0b000000011011100010000100100") | |
| 167 | #define PEU_CSR_B_EVENT_ERR_STS_CLR_RW1C_ALIAS_HW_ADDR sc_uint<64>("0b000000011111100010000100100") | |
| 168 | #define PEU_CSR_A_EVENT_ERR_STS_CLR_RW1S_ALIAS_HW_ADDR sc_uint<64>("0b000000011011100010000100101") | |
| 169 | #define PEU_CSR_B_EVENT_ERR_STS_CLR_RW1S_ALIAS_HW_ADDR sc_uint<64>("0b000000011111100010000100101") | |
| 170 | #define PEU_CSR_A_LNK_BIT_ERR_CNT_1_HW_ADDR sc_uint<64>("0b000000011011100010000100110") | |
| 171 | #define PEU_CSR_B_LNK_BIT_ERR_CNT_1_HW_ADDR sc_uint<64>("0b000000011111100010000100110") | |
| 172 | #define PEU_CSR_A_LNK_BIT_ERR_CNT_2_HW_ADDR sc_uint<64>("0b000000011011100010000100111") | |
| 173 | #define PEU_CSR_B_LNK_BIT_ERR_CNT_2_HW_ADDR sc_uint<64>("0b000000011111100010000100111") | |
| 174 | #define PEU_CSR_A_SERDES_PLL_HW_ADDR sc_uint<64>("0b000000011011100010001000000") | |
| 175 | #define PEU_CSR_B_SERDES_PLL_HW_ADDR sc_uint<64>("0b000000011111100010001000000") | |
| 176 | #define PEU_CSR_A_SERDES_RECEIVER_LANE_CTL_HW_ADDR sc_uint<64>("0b000000011011100010001100000") | |
| 177 | #define PEU_CSR_B_SERDES_RECEIVER_LANE_CTL_HW_ADDR sc_uint<64>("0b000000011111100010001100000") | |
| 178 | #define PEU_CSR_A_SERDES_RECEIVER_LANE_STATUS_HW_ADDR sc_uint<64>("0b000000011011100010001110000") | |
| 179 | #define PEU_CSR_B_SERDES_RECEIVER_LANE_STATUS_HW_ADDR sc_uint<64>("0b000000011111100010001110000") | |
| 180 | #define PEU_CSR_A_SERDES_XMITTER_LANE_CTL_HW_ADDR sc_uint<64>("0b000000011011100010010000000") | |
| 181 | #define PEU_CSR_B_SERDES_XMITTER_LANE_CTL_HW_ADDR sc_uint<64>("0b000000011111100010010000000") | |
| 182 | #define PEU_CSR_A_SERDES_XMITTER_LANE_STATUS_HW_ADDR sc_uint<64>("0b000000011011100010010010000") | |
| 183 | #define PEU_CSR_B_SERDES_XMITTER_LANE_STATUS_HW_ADDR sc_uint<64>("0b000000011111100010010010000") | |
| 184 | #define PEU_CSR_A_SERDES_MACRO_TEST_CFG_HW_ADDR sc_uint<64>("0b000000011011100010010100000") | |
| 185 | #define PEU_CSR_B_SERDES_MACRO_TEST_CFG_HW_ADDR sc_uint<64>("0b000000011111100010010100000") | |
| 186 | ||
| 187 | #define PEU_CSR_TLU_CTL_READ_MASK sc_uint<64>("0b0000000000000000000000000000000011111111000101111111111111111111") | |
| 188 | #define PEU_CSR_TLU_STS_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000111111111") | |
| 189 | #define PEU_CSR_TRN_OFF_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000001") | |
| 190 | #define PEU_CSR_TLU_ICI_READ_MASK sc_uint<64>("0b0000111111111111111111111111111111111111111111111111111111111111") | |
| 191 | #define PEU_CSR_TLU_DIAG_READ_MASK sc_uint<64>("0b0000111110000000111111111111111111111111111111111111111111110011") | |
| 192 | #define PEU_CSR_TLU_ECC_READ_MASK sc_uint<64>("0b0111111111111111111111111111111111111111111111111111111111111111") | |
| 193 | #define PEU_CSR_TLU_ECL_READ_MASK sc_uint<64>("0b0111111111111111111111111111111111111111111111111111111111111111") | |
| 194 | #define PEU_CSR_TLU_ERB_READ_MASK sc_uint<64>("0b0000000000000000111111111111111100000000000000001111111111111111") | |
| 195 | #define PEU_CSR_TLU_ICA_READ_MASK sc_uint<64>("0b0000111111111111111111111111111111111111111111111111111111111111") | |
| 196 | #define PEU_CSR_TLU_ICR_READ_MASK sc_uint<64>("0b0000111111111111111111111111111111111111111111111111111111111111") | |
| 197 | #define PEU_CSR_OE_LOG_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000111111111111111111111111") | |
| 198 | #define PEU_CSR_OE_INT_EN_READ_MASK sc_uint<64>("0b0000000011111111111111111111111100000000111111111111111111111111") | |
| 199 | #define PEU_CSR_OE_EN_ERR_READ_MASK sc_uint<64>("0b0000000011111111111111111111111100000000111111111111111111111111") | |
| 200 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_READ_MASK sc_uint<64>("0b0000000011111111111111111111111100000000111111111111111111111111") | |
| 201 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_READ_MASK sc_uint<64>("0b0000000011111111111111111111111100000000111111111111111111111111") | |
| 202 | #define PEU_CSR_ROE_HDR1_READ_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 203 | #define PEU_CSR_ROE_HDR2_READ_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 204 | #define PEU_CSR_TOE_HDR1_READ_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 205 | #define PEU_CSR_TOE_HDR2_READ_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 206 | #define PEU_CSR_TLU_PRFC_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000111111111111111111") | |
| 207 | #define PEU_CSR_TLU_PRF0_READ_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 208 | #define PEU_CSR_TLU_PRF1_READ_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 209 | #define PEU_CSR_TLU_PRF2_READ_MASK sc_uint<64>("0b0000000000000000000000000000000011111111111111111111111111111111") | |
| 210 | #define PEU_CSR_TLU_DBG_SEL_A_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000111111111") | |
| 211 | #define PEU_CSR_TLU_DBG_SEL_B_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000111111111") | |
| 212 | #define PEU_CSR_DEV_CAP_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000111111000111") | |
| 213 | #define PEU_CSR_DEV_CTL_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000111000011100000") | |
| 214 | #define PEU_CSR_DEV_STS_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000100000") | |
| 215 | #define PEU_CSR_LNK_CAP_READ_MASK sc_uint<64>("0b0000000000000000000000000000000011111111000000111111111111111111") | |
| 216 | #define PEU_CSR_LNK_CTL_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000011111011") | |
| 217 | #define PEU_CSR_LNK_STS_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000001111111111111") | |
| 218 | #define PEU_CSR_SLT_CAP_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000011111111110000000") | |
| 219 | #define PEU_CSR_UE_LOG_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000111111111111111111111") | |
| 220 | #define PEU_CSR_UE_INT_EN_READ_MASK sc_uint<64>("0b0000000000011111111111111111111100000000000111111111111111111111") | |
| 221 | #define PEU_CSR_UE_EN_ERR_READ_MASK sc_uint<64>("0b0000000000011111111111111111111100000000000111111111111111111111") | |
| 222 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_READ_MASK sc_uint<64>("0b0000000000010111111100000001000100000000000101111111000000010001") | |
| 223 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_READ_MASK sc_uint<64>("0b0000000000010111111100000001000100000000000101111111000000010001") | |
| 224 | #define PEU_CSR_RUE_HDR1_READ_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 225 | #define PEU_CSR_RUE_HDR2_READ_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 226 | #define PEU_CSR_TUE_HDR1_READ_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 227 | #define PEU_CSR_TUE_HDR2_READ_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 228 | #define PEU_CSR_CE_LOG_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000001111111111111") | |
| 229 | #define PEU_CSR_CE_INT_EN_READ_MASK sc_uint<64>("0b0000000000000000000111111111111100000000000000000001111111111111") | |
| 230 | #define PEU_CSR_CE_EN_ERR_READ_MASK sc_uint<64>("0b0000000000000000000111111111111100000000000000000001111111111111") | |
| 231 | #define PEU_CSR_CE_ERR_RW1C_ALIAS_READ_MASK sc_uint<64>("0b0000000000000000000100011100000100000000000000000001000111000001") | |
| 232 | #define PEU_CSR_CE_ERR_RW1S_ALIAS_READ_MASK sc_uint<64>("0b0000000000000000000100011100000100000000000000000001000111000001") | |
| 233 | #define PEU_CSR_PEU_DLPL_SERDES_REV_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000011111111") | |
| 234 | #define PEU_CSR_ACKNAK_THRESH_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000001111111111111111") | |
| 235 | #define PEU_CSR_ACKNAK_TIMER_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000001111111111111111") | |
| 236 | #define PEU_CSR_REPLAY_TIM_THRESH_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000001111111111111111") | |
| 237 | #define PEU_CSR_REPLAY_TIMER_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000111111111111111111") | |
| 238 | #define PEU_CSR_VEN_DLLP_MSG_READ_MASK sc_uint<64>("0b0000000000000000000000000000000011111111111111111111111111111111") | |
| 239 | #define PEU_CSR_FORCE_LTSSM_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000100011111") | |
| 240 | #define PEU_CSR_LINK_CFG_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000001111111100011111") | |
| 241 | #define PEU_CSR_LINK_CTL_READ_MASK sc_uint<64>("0b0000000000000000000000000000000011111111111111110011111100011111") | |
| 242 | #define PEU_CSR_LANE_SKEW_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000011111111111111111111111111") | |
| 243 | #define PEU_CSR_SYMBOL_NUM_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000111011111111111") | |
| 244 | #define PEU_CSR_SYMBOL_TIMER_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000011111111111") | |
| 245 | #define PEU_CSR_CORE_STATUS_READ_MASK sc_uint<64>("0b0000011111110011111111111111111111111111111111111111111111111111") | |
| 246 | #define PEU_CSR_EVENT_ERR_LOG_EN_READ_MASK sc_uint<64>("0b0000000000000000000000000000000011111111000000111111111111111111") | |
| 247 | #define PEU_CSR_EVENT_ERR_INT_EN_READ_MASK sc_uint<64>("0b0000000000000000000000000000000011111111000000111111111111111111") | |
| 248 | #define PEU_CSR_EVENT_ERR_INT_STS_READ_MASK sc_uint<64>("0b0000000000000000000000000000000011111111000000111111111111111111") | |
| 249 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_READ_MASK sc_uint<64>("0b0000000000000000000000000000000011111111000000111111111111111111") | |
| 250 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_READ_MASK sc_uint<64>("0b0000000000000000000000000000000011111111000000111111111111111111") | |
| 251 | #define PEU_CSR_LNK_BIT_ERR_CNT_1_READ_MASK sc_uint<64>("0b1100000000000000000000000000000011111111111111110000001111111111") | |
| 252 | #define PEU_CSR_LNK_BIT_ERR_CNT_2_READ_MASK sc_uint<64>("0b0011111100111111001111110011111100111111001111110011111100111111") | |
| 253 | #define PEU_CSR_SERDES_PLL_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000011111111") | |
| 254 | #define PEU_CSR_SERDES_RECEIVER_LANE_CTL_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000001111111111111111") | |
| 255 | #define PEU_CSR_SERDES_RECEIVER_LANE_STATUS_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000001011") | |
| 256 | #define PEU_CSR_SERDES_XMITTER_LANE_CTL_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000011111111111") | |
| 257 | #define PEU_CSR_SERDES_XMITTER_LANE_STATUS_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000011") | |
| 258 | #define PEU_CSR_SERDES_MACRO_TEST_CFG_READ_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000111111111111111") | |
| 259 | ||
| 260 | #define PEU_CSR_TLU_CTL_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000011111111000101111111111111111111") | |
| 261 | //#define PEU_CSR_TLU_STS_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000100000000") | |
| 262 | #define PEU_CSR_TLU_STS_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 263 | #define PEU_CSR_TRN_OFF_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 264 | #define PEU_CSR_TLU_ICI_WRITE_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 265 | #define PEU_CSR_TLU_DIAG_WRITE_MASK sc_uint<64>("0b0000111100000000111111111111111111111111111111111111111100000011") | |
| 266 | //#define PEU_CSR_TLU_ECC_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 267 | #define PEU_CSR_TLU_ECC_WRITE_MASK sc_uint<64>("0b0111111111111111111111111111111111111111111111111111111111111111") | |
| 268 | #define PEU_CSR_TLU_ECL_WRITE_MASK sc_uint<64>("0b0111111111111111111111111111111111111111111111111111111111111111") | |
| 269 | ||
| 270 | //#define PEU_CSR_TLU_ECL_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 271 | ||
| 272 | #define PEU_CSR_TLU_ECL_UPDATEP_WRITE_MASK sc_uint<64>("0b01110000000000000000000000000000000000000000011111111111111111111") | |
| 273 | #define PEU_CSR_TLU_ECL_UPDATENP_WRITE_MASK sc_uint<64>("0b01110000000000000000000000000000001111111111111111111100000000000000000000") | |
| 274 | #define PEU_CSR_TLU_ECL_UPDATECPL_WRITE_MASK sc_uint<64>("0b011100000000000000000000000000000011111111111111111111000000000000000000000000000000000000000") | |
| 275 | ||
| 276 | ||
| 277 | #define PEU_CSR_TLU_ERB_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 278 | #define PEU_CSR_TLU_ICA_WRITE_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 279 | #define PEU_CSR_TLU_ICR_WRITE_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 280 | //#define PEU_CSR_TLU_ICR_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 281 | #define PEU_CSR_OE_LOG_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000111111111111111111111111") | |
| 282 | #define PEU_CSR_OE_INT_EN_WRITE_MASK sc_uint<64>("0b0000000011111111111111111111111100000000111111111111111111111111") | |
| 283 | #define PEU_CSR_OE_EN_ERR_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 284 | //#define PEU_CSR_OE_ERR_RW1C_ALIAS_WRITE_MASK sc_uint<64>("0b0000000011111111111111111111111100000000111111111111111111111111") | |
| 285 | //#define PEU_CSR_OE_ERR_RW1S_ALIAS_WRITE_MASK sc_uint<64>("0b0000000011111111111111111111111100000000111111111111111111111111") | |
| 286 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 287 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 288 | #define PEU_CSR_ROE_HDR1_WRITE_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 289 | #define PEU_CSR_ROE_HDR2_WRITE_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 290 | #define PEU_CSR_TOE_HDR1_WRITE_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 291 | #define PEU_CSR_TOE_HDR2_WRITE_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 292 | #define PEU_CSR_TLU_PRFC_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000111111111111111111") | |
| 293 | #define PEU_CSR_TLU_PRF0_WRITE_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 294 | #define PEU_CSR_TLU_PRF1_WRITE_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 295 | #define PEU_CSR_TLU_PRF2_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000011111111111111111111111111111111") | |
| 296 | #define PEU_CSR_TLU_DBG_SEL_A_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000111111111") | |
| 297 | #define PEU_CSR_TLU_DBG_SEL_B_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000111111111") | |
| 298 | #define PEU_CSR_DEV_CAP_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 299 | #define PEU_CSR_DEV_CTL_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000011100000") | |
| 300 | #define PEU_CSR_DEV_STS_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 301 | #define PEU_CSR_LNK_CAP_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 302 | #define PEU_CSR_LNK_CTL_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000011110011") | |
| 303 | #define PEU_CSR_LNK_CTL_RETRAIN_MASK sc_uint<64>("0b0000000000100000") | |
| 304 | #define PEU_CSR_LNK_STS_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 305 | #define PEU_CSR_LNK_STS_TRAIN_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000100000000000") | |
| 306 | #define PEU_CSR_LNK_STS_WIDTH_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000001111110000") | |
| 307 | #define PEU_CSR_LNK_STS_SPEED_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000001111") | |
| 308 | #define PEU_CSR_SLT_CAP_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000011111111110000000") | |
| 309 | #define PEU_CSR_UE_LOG_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000111111111111111111111") | |
| 310 | #define PEU_CSR_UE_INT_EN_WRITE_MASK sc_uint<64>("0b0000000000011111111111111111111100000000000111111111111111111111") | |
| 311 | #define PEU_CSR_UE_EN_ERR_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 312 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 313 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 314 | #define PEU_CSR_RUE_HDR1_WRITE_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 315 | #define PEU_CSR_RUE_HDR2_WRITE_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 316 | #define PEU_CSR_TUE_HDR1_WRITE_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 317 | #define PEU_CSR_TUE_HDR2_WRITE_MASK sc_uint<64>("0b1111111111111111111111111111111111111111111111111111111111111111") | |
| 318 | #define PEU_CSR_CE_LOG_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000001111111111111") | |
| 319 | #define PEU_CSR_CE_INT_EN_WRITE_MASK sc_uint<64>("0b0000000000000000000111111111111100000000000000000001111111111111") | |
| 320 | #define PEU_CSR_CE_EN_ERR_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 321 | #define PEU_CSR_CE_ERR_RW1C_ALIAS_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 322 | #define PEU_CSR_CE_ERR_RW1S_ALIAS_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 323 | #define PEU_CSR_PEU_DLPL_SERDES_REV_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 324 | #define PEU_CSR_ACKNAK_THRESH_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000001111111111111111") | |
| 325 | #define PEU_CSR_ACKNAK_TIMER_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 326 | #define PEU_CSR_REPLAY_TIM_THRESH_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000001111111111111111") | |
| 327 | #define PEU_CSR_REPLAY_TIMER_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 328 | #define PEU_CSR_VEN_DLLP_MSG_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000011111111111111111111111111111111") | |
| 329 | #define PEU_CSR_FORCE_LTSSM_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000100011111") | |
| 330 | #define PEU_CSR_LINK_CFG_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000001111111100011111") | |
| 331 | #define PEU_CSR_LINK_CTL_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000011111111111111110011111100011111") | |
| 332 | #define PEU_CSR_LANE_SKEW_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000011111111111111111111111111") | |
| 333 | #define PEU_CSR_SYMBOL_NUM_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000111011111111111") | |
| 334 | #define PEU_CSR_SYMBOL_TIMER_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000011111111111") | |
| 335 | #define PEU_CSR_CORE_STATUS_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 336 | #define PEU_CSR_EVENT_ERR_LOG_EN_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000011111111000000111111111111111111") | |
| 337 | #define PEU_CSR_EVENT_ERR_INT_EN_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000011111111000000111111111111111111") | |
| 338 | #define PEU_CSR_EVENT_ERR_INT_STS_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 339 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 340 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 341 | #define PEU_CSR_LNK_BIT_ERR_CNT_1_WRITE_MASK sc_uint<64>("0b1000000000000000000000000000000000000000000000000000000000000000") | |
| 342 | #define PEU_CSR_LNK_BIT_ERR_CNT_2_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 343 | #define PEU_CSR_SERDES_PLL_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000011111111") | |
| 344 | #define PEU_CSR_SERDES_RECEIVER_LANE_CTL_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000001111111111111111") | |
| 345 | #define PEU_CSR_SERDES_RECEIVER_LANE_STATUS_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 346 | #define PEU_CSR_SERDES_XMITTER_LANE_CTL_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000011111111111") | |
| 347 | #define PEU_CSR_SERDES_XMITTER_LANE_STATUS_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 348 | #define PEU_CSR_SERDES_MACRO_TEST_CFG_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000111111111111111") | |
| 349 | ||
| 350 | #define PEU_CSR_TLU_CTL_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000100000001") | |
| 351 | #define PEU_CSR_TLU_CTL_L0S_TIM_POR_VALUE sc_uint<64>("0b00000000") | |
| 352 | #define PEU_CSR_TLU_CTL_NPWR_EN_POR_VALUE sc_uint<64>("0b0") | |
| 353 | #define PEU_CSR_TLU_CTL_CTO_SEL_POR_VALUE sc_uint<64>("0b000") | |
| 354 | #define PEU_CSR_TLU_CTL_CONFIG_POR_VALUE sc_uint<64>("0b0000000100000001") | |
| 355 | #define PEU_CSR_TLU_STS_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000100") | |
| 356 | //#define PEU_CSR_TLU_STS_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000100") | |
| 357 | #define PEU_CSR_TLU_STS_DRAIN_POR_VALUE sc_uint<64>("0b0") | |
| 358 | #define PEU_CSR_TLU_STS_STATUS_POR_VALUE sc_uint<64>("0b00000001") | |
| 359 | #define PEU_CSR_TRN_OFF_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 360 | #define PEU_CSR_TRN_OFF_PTO_POR_VALUE sc_uint<64>("0b0") | |
| 361 | #define PEU_CSR_TLU_ICI_POR_VALUE sc_uint<64>("0b0000000000000000000000000001000000000000000000100000000011000000") | |
| 362 | // 0000 | |
| 363 | // CHC : 00000000 | |
| 364 | // CDC : 000000000000 | |
| 365 | // NHC : 10000000 : 0x80 // changed to 0x10 | |
| 366 | // NDC : 000000000000 : | |
| 367 | // PHC : 00100000 : 0x20 | |
| 368 | // PDC : 000011000000 : 0xC0 | |
| 369 | //#define PEU_CSR_TLU_ICI_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 370 | #define PEU_CSR_TLU_ICI_CHC_POR_VALUE sc_uint<64>("0b00000000") | |
| 371 | #define PEU_CSR_TLU_ICI_CDC_POR_VALUE sc_uint<64>("0b000000000000") | |
| 372 | #define PEU_CSR_TLU_ICI_NHC_POR_VALUE sc_uint<64>("0b00010000") | |
| 373 | #define PEU_CSR_TLU_ICI_NDC_POR_VALUE sc_uint<64>("0b000000000000") | |
| 374 | #define PEU_CSR_TLU_ICI_PHC_POR_VALUE sc_uint<64>("0b00100000") | |
| 375 | #define PEU_CSR_TLU_ICI_PDC_POR_VALUE sc_uint<64>("0b000011000000") | |
| 376 | #define PEU_CSR_TLU_DIAG_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 377 | #define PEU_CSR_TLU_DIAG_ERBI_PAR_POR_VALUE sc_uint<64>("0b0000") | |
| 378 | #define PEU_CSR_TLU_DIAG_ERBI_TRG_POR_VALUE sc_uint<64>("0b0") | |
| 379 | #define PEU_CSR_TLU_DIAG_CHK_DIS_POR_VALUE sc_uint<64>("0b0000000000000000") | |
| 380 | #define PEU_CSR_TLU_DIAG_EPI_PAR_POR_VALUE sc_uint<64>("0b0000000000000000") | |
| 381 | #define PEU_CSR_TLU_DIAG_IDI_PAR_POR_VALUE sc_uint<64>("0b0000") | |
| 382 | #define PEU_CSR_TLU_DIAG_IHI_PAR_POR_VALUE sc_uint<64>("0b0000") | |
| 383 | #define PEU_CSR_TLU_DIAG_EPI_TRG_POR_VALUE sc_uint<64>("0b0") | |
| 384 | #define PEU_CSR_TLU_DIAG_IDI_TRG_POR_VALUE sc_uint<64>("0b0") | |
| 385 | #define PEU_CSR_TLU_DIAG_IHI_TRG_POR_VALUE sc_uint<64>("0b0") | |
| 386 | #define PEU_CSR_TLU_DIAG_MRC_TRG_POR_VALUE sc_uint<64>("0b0") | |
| 387 | #define PEU_CSR_TLU_DIAG_EPP_DIS_POR_VALUE sc_uint<64>("0b0") | |
| 388 | #define PEU_CSR_TLU_DIAG_IFC_DIS_POR_VALUE sc_uint<64>("0b0") | |
| 389 | #define PEU_CSR_TLU_ECC_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 390 | #define PEU_CSR_TLU_ECC_CHI_POR_VALUE sc_uint<64>("0b0") | |
| 391 | #define PEU_CSR_TLU_ECC_NHI_POR_VALUE sc_uint<64>("0b0") | |
| 392 | #define PEU_CSR_TLU_ECC_PHI_POR_VALUE sc_uint<64>("0b0") | |
| 393 | #define PEU_CSR_TLU_ECC_CHC_POR_VALUE sc_uint<64>("0b00000000") | |
| 394 | #define PEU_CSR_TLU_ECC_CDC_POR_VALUE sc_uint<64>("0b000000000000") | |
| 395 | #define PEU_CSR_TLU_ECC_NHC_POR_VALUE sc_uint<64>("0b00000000") | |
| 396 | #define PEU_CSR_TLU_ECC_NDC_POR_VALUE sc_uint<64>("0b000000000000") | |
| 397 | #define PEU_CSR_TLU_ECC_PHC_POR_VALUE sc_uint<64>("0b00000000") | |
| 398 | #define PEU_CSR_TLU_ECC_PDC_POR_VALUE sc_uint<64>("0b000000000000") | |
| 399 | //#define PEU_CSR_TLU_ECL_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 400 | #define PEU_CSR_TLU_ECL_POR_VALUE sc_uint<64>("0b0111000000000000000000000000000000000000000000000000000000000000") | |
| 401 | #define PEU_CSR_TLU_ECL_CDI_POR_VALUE sc_uint<64>("0b0") | |
| 402 | #define PEU_CSR_TLU_ECL_NDI_POR_VALUE sc_uint<64>("0b0") | |
| 403 | #define PEU_CSR_TLU_ECL_PDI_POR_VALUE sc_uint<64>("0b0") | |
| 404 | #define PEU_CSR_TLU_ECL_CHC_POR_VALUE sc_uint<64>("0b00000000") | |
| 405 | #define PEU_CSR_TLU_ECL_CDC_POR_VALUE sc_uint<64>("0b000000000000") | |
| 406 | #define PEU_CSR_TLU_ECL_NHC_POR_VALUE sc_uint<64>("0b00000000") | |
| 407 | #define PEU_CSR_TLU_ECL_NDC_POR_VALUE sc_uint<64>("0b000000000000") | |
| 408 | #define PEU_CSR_TLU_ECL_PHC_POR_VALUE sc_uint<64>("0b00000000") | |
| 409 | #define PEU_CSR_TLU_ECL_PDC_POR_VALUE sc_uint<64>("0b000000000000") | |
| 410 | #define PEU_CSR_TLU_ERB_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000001000000000000") | |
| 411 | #define PEU_CSR_TLU_ERB_CC_POR_VALUE sc_uint<64>("0b0000000000000000") | |
| 412 | #define PEU_CSR_TLU_ERB_CL_POR_VALUE sc_uint<64>("0b0001000000000000") | |
| 413 | //#define PEU_CSR_TLU_ICI_POR_VALUE sc_uint<64>("0b0000000000000000000000000001000000000000000000100000000011000000") | |
| 414 | #define PEU_CSR_TLU_ICA_POR_VALUE sc_uint<64>("0b0000000000000000000000000001000000000000000000100000000011000000") | |
| 415 | //#define PEU_CSR_TLU_ICA_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 416 | #define PEU_CSR_TLU_ICA_CHC_POR_VALUE sc_uint<64>("0b00000000") | |
| 417 | #define PEU_CSR_TLU_ICA_CDC_POR_VALUE sc_uint<64>("0b000000000000") | |
| 418 | #define PEU_CSR_TLU_ICA_NHC_POR_VALUE sc_uint<64>("0b00010000") | |
| 419 | #define PEU_CSR_TLU_ICA_NDC_POR_VALUE sc_uint<64>("0b000000000000") | |
| 420 | #define PEU_CSR_TLU_ICA_PHC_POR_VALUE sc_uint<64>("0b00100000") | |
| 421 | #define PEU_CSR_TLU_ICA_PDC_POR_VALUE sc_uint<64>("0b000011000000") | |
| 422 | #define PEU_CSR_TLU_ICR_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 423 | #define PEU_CSR_TLU_ICR_CHC_POR_VALUE sc_uint<64>("0b00000000") | |
| 424 | #define PEU_CSR_TLU_ICR_CDC_POR_VALUE sc_uint<64>("0b000000000000") | |
| 425 | #define PEU_CSR_TLU_ICR_NHC_POR_VALUE sc_uint<64>("0b00000000") | |
| 426 | #define PEU_CSR_TLU_ICR_NDC_POR_VALUE sc_uint<64>("0b000000000000") | |
| 427 | #define PEU_CSR_TLU_ICR_PHC_POR_VALUE sc_uint<64>("0b00000000") | |
| 428 | #define PEU_CSR_TLU_ICR_PDC_POR_VALUE sc_uint<64>("0b000000000000") | |
| 429 | #define PEU_CSR_OE_LOG_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000111111111111111111111111") | |
| 430 | #define PEU_CSR_OE_LOG_EN_POR_VALUE sc_uint<64>("0b111111111111111111111111") | |
| 431 | #define PEU_CSR_OE_INT_EN_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 432 | #define PEU_CSR_OE_INT_EN_EN_S_POR_VALUE sc_uint<64>("0b000000000000000000000000") | |
| 433 | #define PEU_CSR_OE_INT_EN_EN_P_POR_VALUE sc_uint<64>("0b000000000000000000000000") | |
| 434 | #define PEU_CSR_OE_EN_ERR_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 435 | #define PEU_CSR_OE_EN_ERR_ERR_S_POR_VALUE sc_uint<64>("0b000000000000000000000000") | |
| 436 | #define PEU_CSR_OE_EN_ERR_ERR_P_POR_VALUE sc_uint<64>("0b000000000000000000000000") | |
| 437 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 438 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_SPARE_S_POR_VALUE sc_uint<64>("0b0") | |
| 439 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_MFC_S_POR_VALUE sc_uint<64>("0b0") | |
| 440 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_CTO_S_POR_VALUE sc_uint<64>("0b0") | |
| 441 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_NFP_S_POR_VALUE sc_uint<64>("0b0") | |
| 442 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_LWC_S_POR_VALUE sc_uint<64>("0b0") | |
| 443 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_MRC_S_POR_VALUE sc_uint<64>("0b0") | |
| 444 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_WUC_S_POR_VALUE sc_uint<64>("0b0") | |
| 445 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_RUC_S_POR_VALUE sc_uint<64>("0b0") | |
| 446 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_CRS_S_POR_VALUE sc_uint<64>("0b0") | |
| 447 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_IIP_S_POR_VALUE sc_uint<64>("0b0") | |
| 448 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_EDP_S_POR_VALUE sc_uint<64>("0b0") | |
| 449 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_EHP_S_POR_VALUE sc_uint<64>("0b0") | |
| 450 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_LIN_S_POR_VALUE sc_uint<64>("0b0") | |
| 451 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_LRS_S_POR_VALUE sc_uint<64>("0b0") | |
| 452 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_LDN_S_POR_VALUE sc_uint<64>("0b0") | |
| 453 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_LUP_S_POR_VALUE sc_uint<64>("0b0") | |
| 454 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_LPU_S_POR_VALUE sc_uint<64>("0b00") | |
| 455 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_ERU_S_POR_VALUE sc_uint<64>("0b0") | |
| 456 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_ERO_S_POR_VALUE sc_uint<64>("0b0") | |
| 457 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_EMP_S_POR_VALUE sc_uint<64>("0b0") | |
| 458 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_EPE_S_POR_VALUE sc_uint<64>("0b0") | |
| 459 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_ERP_S_POR_VALUE sc_uint<64>("0b0") | |
| 460 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_EIP_S_POR_VALUE sc_uint<64>("0b0") | |
| 461 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_SPARE_P_POR_VALUE sc_uint<64>("0b0") | |
| 462 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_MFC_P_POR_VALUE sc_uint<64>("0b0") | |
| 463 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_CTO_P_POR_VALUE sc_uint<64>("0b0") | |
| 464 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_NFP_P_POR_VALUE sc_uint<64>("0b0") | |
| 465 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_LWC_P_POR_VALUE sc_uint<64>("0b0") | |
| 466 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_MRC_P_POR_VALUE sc_uint<64>("0b0") | |
| 467 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_WUC_P_POR_VALUE sc_uint<64>("0b0") | |
| 468 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_RUC_P_POR_VALUE sc_uint<64>("0b0") | |
| 469 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_CRS_P_POR_VALUE sc_uint<64>("0b0") | |
| 470 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_IIP_P_POR_VALUE sc_uint<64>("0b0") | |
| 471 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_EDP_P_POR_VALUE sc_uint<64>("0b0") | |
| 472 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_EHP_P_POR_VALUE sc_uint<64>("0b0") | |
| 473 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_LIN_P_POR_VALUE sc_uint<64>("0b0") | |
| 474 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_LRS_P_POR_VALUE sc_uint<64>("0b0") | |
| 475 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_LDN_P_POR_VALUE sc_uint<64>("0b0") | |
| 476 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_LUP_P_POR_VALUE sc_uint<64>("0b0") | |
| 477 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_LPU_P_POR_VALUE sc_uint<64>("0b00") | |
| 478 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_ERU_P_POR_VALUE sc_uint<64>("0b0") | |
| 479 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_ERO_P_POR_VALUE sc_uint<64>("0b0") | |
| 480 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_EMP_P_POR_VALUE sc_uint<64>("0b0") | |
| 481 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_EPE_P_POR_VALUE sc_uint<64>("0b0") | |
| 482 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_ERP_P_POR_VALUE sc_uint<64>("0b0") | |
| 483 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_EIP_P_POR_VALUE sc_uint<64>("0b0") | |
| 484 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 485 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_SPARE_S_POR_VALUE sc_uint<64>("0b0") | |
| 486 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_MFC_S_POR_VALUE sc_uint<64>("0b0") | |
| 487 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_CTO_S_POR_VALUE sc_uint<64>("0b0") | |
| 488 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_NFP_S_POR_VALUE sc_uint<64>("0b0") | |
| 489 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_LWC_S_POR_VALUE sc_uint<64>("0b0") | |
| 490 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_MRC_S_POR_VALUE sc_uint<64>("0b0") | |
| 491 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_WUC_S_POR_VALUE sc_uint<64>("0b0") | |
| 492 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_RUC_S_POR_VALUE sc_uint<64>("0b0") | |
| 493 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_CRS_S_POR_VALUE sc_uint<64>("0b0") | |
| 494 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_IIP_S_POR_VALUE sc_uint<64>("0b0") | |
| 495 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_EDP_S_POR_VALUE sc_uint<64>("0b0") | |
| 496 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_EHP_S_POR_VALUE sc_uint<64>("0b0") | |
| 497 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_LIN_S_POR_VALUE sc_uint<64>("0b0") | |
| 498 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_LRS_S_POR_VALUE sc_uint<64>("0b0") | |
| 499 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_LDN_S_POR_VALUE sc_uint<64>("0b0") | |
| 500 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_LUP_S_POR_VALUE sc_uint<64>("0b0") | |
| 501 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_LPU_S_POR_VALUE sc_uint<64>("0b00") | |
| 502 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_ERU_S_POR_VALUE sc_uint<64>("0b0") | |
| 503 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_ERO_S_POR_VALUE sc_uint<64>("0b0") | |
| 504 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_EMP_S_POR_VALUE sc_uint<64>("0b0") | |
| 505 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_EPE_S_POR_VALUE sc_uint<64>("0b0") | |
| 506 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_ERP_S_POR_VALUE sc_uint<64>("0b0") | |
| 507 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_EIP_S_POR_VALUE sc_uint<64>("0b0") | |
| 508 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_SPARE_P_POR_VALUE sc_uint<64>("0b0") | |
| 509 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_MFC_P_POR_VALUE sc_uint<64>("0b0") | |
| 510 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_CTO_P_POR_VALUE sc_uint<64>("0b0") | |
| 511 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_NFP_P_POR_VALUE sc_uint<64>("0b0") | |
| 512 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_LWC_P_POR_VALUE sc_uint<64>("0b0") | |
| 513 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_MRC_P_POR_VALUE sc_uint<64>("0b0") | |
| 514 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_WUC_P_POR_VALUE sc_uint<64>("0b0") | |
| 515 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_RUC_P_POR_VALUE sc_uint<64>("0b0") | |
| 516 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_CRS_P_POR_VALUE sc_uint<64>("0b0") | |
| 517 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_IIP_P_POR_VALUE sc_uint<64>("0b0") | |
| 518 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_EDP_P_POR_VALUE sc_uint<64>("0b0") | |
| 519 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_EHP_P_POR_VALUE sc_uint<64>("0b0") | |
| 520 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_LIN_P_POR_VALUE sc_uint<64>("0b0") | |
| 521 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_LRS_P_POR_VALUE sc_uint<64>("0b0") | |
| 522 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_LDN_P_POR_VALUE sc_uint<64>("0b0") | |
| 523 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_LUP_P_POR_VALUE sc_uint<64>("0b0") | |
| 524 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_LPU_P_POR_VALUE sc_uint<64>("0b00") | |
| 525 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_ERU_P_POR_VALUE sc_uint<64>("0b0") | |
| 526 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_ERO_P_POR_VALUE sc_uint<64>("0b0") | |
| 527 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_EMP_P_POR_VALUE sc_uint<64>("0b0") | |
| 528 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_EPE_P_POR_VALUE sc_uint<64>("0b0") | |
| 529 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_ERP_P_POR_VALUE sc_uint<64>("0b0") | |
| 530 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_EIP_P_POR_VALUE sc_uint<64>("0b0") | |
| 531 | #define PEU_CSR_ROE_HDR1_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 532 | #define PEU_CSR_ROE_HDR1_HDR_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 533 | #define PEU_CSR_ROE_HDR2_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 534 | #define PEU_CSR_ROE_HDR2_HDR_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 535 | #define PEU_CSR_TOE_HDR1_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 536 | #define PEU_CSR_TOE_HDR1_HDR_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 537 | #define PEU_CSR_TOE_HDR2_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 538 | #define PEU_CSR_TOE_HDR2_HDR_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 539 | #define PEU_CSR_TLU_PRFC_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 540 | #define PEU_CSR_TLU_PRFC_SEL2_POR_VALUE sc_uint<64>("0b00") | |
| 541 | #define PEU_CSR_TLU_PRFC_SEL1_POR_VALUE sc_uint<64>("0b00000000") | |
| 542 | #define PEU_CSR_TLU_PRFC_SEL0_POR_VALUE sc_uint<64>("0b00000000") | |
| 543 | #define PEU_CSR_TLU_PRF0_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 544 | #define PEU_CSR_TLU_PRF0_CNT_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 545 | #define PEU_CSR_TLU_PRF1_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 546 | #define PEU_CSR_TLU_PRF1_CNT_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 547 | #define PEU_CSR_TLU_PRF2_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 548 | #define PEU_CSR_TLU_PRF2_CNT_POR_VALUE sc_uint<64>("0b00000000000000000000000000000000") | |
| 549 | #define PEU_CSR_TLU_DBG_SEL_A_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 550 | #define PEU_CSR_TLU_DBG_SEL_A_BLOCK_POR_VALUE sc_uint<64>("0b000") | |
| 551 | #define PEU_CSR_TLU_DBG_SEL_A_MODULE_POR_VALUE sc_uint<64>("0b000") | |
| 552 | #define PEU_CSR_TLU_DBG_SEL_A_SIGNAL_POR_VALUE sc_uint<64>("0b000") | |
| 553 | #define PEU_CSR_TLU_DBG_SEL_B_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 554 | #define PEU_CSR_TLU_DBG_SEL_B_BLOCK_POR_VALUE sc_uint<64>("0b000") | |
| 555 | #define PEU_CSR_TLU_DBG_SEL_B_MODULE_POR_VALUE sc_uint<64>("0b000") | |
| 556 | #define PEU_CSR_TLU_DBG_SEL_B_SIGNAL_POR_VALUE sc_uint<64>("0b000") | |
| 557 | #define PEU_CSR_DEV_CAP_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000010") | |
| 558 | #define PEU_CSR_DEV_CAP_L1_POR_VALUE sc_uint<64>("0b000") | |
| 559 | #define PEU_CSR_DEV_CAP_L0S_POR_VALUE sc_uint<64>("0b000") | |
| 560 | #define PEU_CSR_DEV_CAP_MPS_POR_VALUE sc_uint<64>("0b010") | |
| 561 | #define PEU_CSR_DEV_CTL_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 562 | #define PEU_CSR_DEV_CTL_MRRS_POR_VALUE sc_uint<64>("0b000") | |
| 563 | #define PEU_CSR_DEV_CTL_MPS_POR_VALUE sc_uint<64>("0b000") | |
| 564 | #define PEU_CSR_DEV_STS_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 565 | #define PEU_CSR_DEV_STS_TP_POR_VALUE sc_uint<64>("0b0") | |
| 566 | #define PEU_CSR_LNK_CAP_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000010100110010000001") | |
| 567 | #define PEU_CSR_LNK_CAP_PORT_POR_VALUE sc_uint<64>("0b00000000") | |
| 568 | #define PEU_CSR_LNK_CAP_L1_POR_VALUE sc_uint<64>("0b010") | |
| 569 | #define PEU_CSR_LNK_CAP_L0S_POR_VALUE sc_uint<64>("0b100") | |
| 570 | #define PEU_CSR_LNK_CAP_ASPM_POR_VALUE sc_uint<64>("0b11") | |
| 571 | #define PEU_CSR_LNK_CAP_WIDTH_POR_VALUE sc_uint<64>("0b001000") | |
| 572 | #define PEU_CSR_LNK_CAP_SPEED_POR_VALUE sc_uint<64>("0b0001") | |
| 573 | #define PEU_CSR_LNK_CTL_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 574 | #define PEU_CSR_LNK_CTL_EXTSYNC_POR_VALUE sc_uint<64>("0b0") | |
| 575 | #define PEU_CSR_LNK_CTL_CLOCK_POR_VALUE sc_uint<64>("0b0") | |
| 576 | #define PEU_CSR_LNK_CTL_RETRAIN_POR_VALUE sc_uint<64>("0b0") | |
| 577 | #define PEU_CSR_LNK_CTL_DISABLE_POR_VALUE sc_uint<64>("0b0") | |
| 578 | #define PEU_CSR_LNK_CTL_RCB_POR_VALUE sc_uint<64>("0b0") | |
| 579 | #define PEU_CSR_LNK_CTL_ASPM_POR_VALUE sc_uint<64>("0b00") | |
| 580 | #define PEU_CSR_LNK_STS_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 581 | #define PEU_CSR_LNK_STS_CLOCK_POR_VALUE sc_uint<64>("0b0") | |
| 582 | #define PEU_CSR_LNK_STS_TRAIN_POR_VALUE sc_uint<64>("0b0") | |
| 583 | #define PEU_CSR_LNK_STS_SPARE_POR_VALUE sc_uint<64>("0b0") | |
| 584 | #define PEU_CSR_LNK_STS_WIDTH_POR_VALUE sc_uint<64>("0b000000") | |
| 585 | #define PEU_CSR_LNK_STS_SPEED_POR_VALUE sc_uint<64>("0b0000") | |
| 586 | #define PEU_CSR_SLT_CAP_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 587 | #define PEU_CSR_SLT_CAP_SPLS_POR_VALUE sc_uint<64>("0b00") | |
| 588 | #define PEU_CSR_SLT_CAP_SPLV_POR_VALUE sc_uint<64>("0b00000000") | |
| 589 | #define PEU_CSR_UE_LOG_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000101111111000000010001") | |
| 590 | #define PEU_CSR_UE_LOG_EN_POR_VALUE sc_uint<64>("0b101111111000000010001") | |
| 591 | #define PEU_CSR_UE_INT_EN_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 592 | #define PEU_CSR_UE_INT_EN_EN_S_POR_VALUE sc_uint<64>("0b000000000000000000000") | |
| 593 | #define PEU_CSR_UE_INT_EN_EN_P_POR_VALUE sc_uint<64>("0b000000000000000000000") | |
| 594 | #define PEU_CSR_UE_EN_ERR_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 595 | #define PEU_CSR_UE_EN_ERR_ERR_S_POR_VALUE sc_uint<64>("0b000000000000000000000") | |
| 596 | #define PEU_CSR_UE_EN_ERR_ERR_P_POR_VALUE sc_uint<64>("0b000000000000000000000") | |
| 597 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 598 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_UR_S_POR_VALUE sc_uint<64>("0b0") | |
| 599 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_MFP_S_POR_VALUE sc_uint<64>("0b0") | |
| 600 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_ROF_S_POR_VALUE sc_uint<64>("0b0") | |
| 601 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_UC_S_POR_VALUE sc_uint<64>("0b0") | |
| 602 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_SPARE1_POR_VALUE sc_uint<64>("0b0") | |
| 603 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_CTO_S_POR_VALUE sc_uint<64>("0b0") | |
| 604 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_FCP_S_POR_VALUE sc_uint<64>("0b0") | |
| 605 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_PP_S_POR_VALUE sc_uint<64>("0b0") | |
| 606 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_DLP_S_POR_VALUE sc_uint<64>("0b0") | |
| 607 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_SPARE_S_POR_VALUE sc_uint<64>("0b0") | |
| 608 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_UR_P_POR_VALUE sc_uint<64>("0b0") | |
| 609 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_MFP_P_POR_VALUE sc_uint<64>("0b0") | |
| 610 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_ROF_P_POR_VALUE sc_uint<64>("0b0") | |
| 611 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_UC_P_POR_VALUE sc_uint<64>("0b0") | |
| 612 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_SPARE2_POR_VALUE sc_uint<64>("0b0") | |
| 613 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_CTO_P_POR_VALUE sc_uint<64>("0b0") | |
| 614 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_FCP_P_POR_VALUE sc_uint<64>("0b0") | |
| 615 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_PP_P_POR_VALUE sc_uint<64>("0b0") | |
| 616 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_DLP_P_POR_VALUE sc_uint<64>("0b0") | |
| 617 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_SPARE_P_POR_VALUE sc_uint<64>("0b0") | |
| 618 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 619 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_UR_S_POR_VALUE sc_uint<64>("0b0") | |
| 620 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_MFP_S_POR_VALUE sc_uint<64>("0b0") | |
| 621 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_ROF_S_POR_VALUE sc_uint<64>("0b0") | |
| 622 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_UC_S_POR_VALUE sc_uint<64>("0b0") | |
| 623 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_SPARE1_POR_VALUE sc_uint<64>("0b0") | |
| 624 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_CTO_S_POR_VALUE sc_uint<64>("0b0") | |
| 625 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_FCP_S_POR_VALUE sc_uint<64>("0b0") | |
| 626 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_PP_S_POR_VALUE sc_uint<64>("0b0") | |
| 627 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_DLP_S_POR_VALUE sc_uint<64>("0b0") | |
| 628 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_SPARE_S_POR_VALUE sc_uint<64>("0b0") | |
| 629 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_UR_P_POR_VALUE sc_uint<64>("0b0") | |
| 630 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_MFP_P_POR_VALUE sc_uint<64>("0b0") | |
| 631 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_ROF_P_POR_VALUE sc_uint<64>("0b0") | |
| 632 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_UC_P_POR_VALUE sc_uint<64>("0b0") | |
| 633 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_SPARE2_POR_VALUE sc_uint<64>("0b0") | |
| 634 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_CTO_P_POR_VALUE sc_uint<64>("0b0") | |
| 635 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_FCP_P_POR_VALUE sc_uint<64>("0b0") | |
| 636 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_PP_P_POR_VALUE sc_uint<64>("0b0") | |
| 637 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_DLP_P_POR_VALUE sc_uint<64>("0b0") | |
| 638 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_SPARE_P_POR_VALUE sc_uint<64>("0b0") | |
| 639 | #define PEU_CSR_RUE_HDR1_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 640 | #define PEU_CSR_RUE_HDR1_HDR_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 641 | #define PEU_CSR_RUE_HDR2_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 642 | #define PEU_CSR_RUE_HDR2_HDR_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 643 | #define PEU_CSR_TUE_HDR1_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 644 | #define PEU_CSR_TUE_HDR1_HDR_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 645 | #define PEU_CSR_TUE_HDR2_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 646 | #define PEU_CSR_TUE_HDR2_HDR_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 647 | #define PEU_CSR_CE_LOG_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000001000111000001") | |
| 648 | #define PEU_CSR_CE_LOG_EN_POR_VALUE sc_uint<64>("0b1000111000001") | |
| 649 | #define PEU_CSR_CE_INT_EN_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 650 | #define PEU_CSR_CE_INT_EN_EN_S_POR_VALUE sc_uint<64>("0b0000000000000") | |
| 651 | #define PEU_CSR_CE_INT_EN_EN_P_POR_VALUE sc_uint<64>("0b0000000000000") | |
| 652 | #define PEU_CSR_CE_EN_ERR_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 653 | #define PEU_CSR_CE_EN_ERR_ERR_S_POR_VALUE sc_uint<64>("0b0000000000000") | |
| 654 | #define PEU_CSR_CE_EN_ERR_ERR_P_POR_VALUE sc_uint<64>("0b0000000000000") | |
| 655 | #define PEU_CSR_CE_ERR_RW1C_ALIAS_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 656 | #define PEU_CSR_CE_ERR_RW1C_ALIAS_RTO_S_POR_VALUE sc_uint<64>("0b0") | |
| 657 | #define PEU_CSR_CE_ERR_RW1C_ALIAS_RNR_S_POR_VALUE sc_uint<64>("0b0") | |
| 658 | #define PEU_CSR_CE_ERR_RW1C_ALIAS_BDP_S_POR_VALUE sc_uint<64>("0b0") | |
| 659 | #define PEU_CSR_CE_ERR_RW1C_ALIAS_BTP_S_POR_VALUE sc_uint<64>("0b0") | |
| 660 | #define PEU_CSR_CE_ERR_RW1C_ALIAS_RE_S_POR_VALUE sc_uint<64>("0b0") | |
| 661 | #define PEU_CSR_CE_ERR_RW1C_ALIAS_RTO_P_POR_VALUE sc_uint<64>("0b0") | |
| 662 | #define PEU_CSR_CE_ERR_RW1C_ALIAS_RNR_P_POR_VALUE sc_uint<64>("0b0") | |
| 663 | #define PEU_CSR_CE_ERR_RW1C_ALIAS_BDP_P_POR_VALUE sc_uint<64>("0b0") | |
| 664 | #define PEU_CSR_CE_ERR_RW1C_ALIAS_BTP_P_POR_VALUE sc_uint<64>("0b0") | |
| 665 | #define PEU_CSR_CE_ERR_RW1C_ALIAS_RE_P_POR_VALUE sc_uint<64>("0b0") | |
| 666 | #define PEU_CSR_CE_ERR_RW1S_ALIAS_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 667 | #define PEU_CSR_CE_ERR_RW1S_ALIAS_RTO_S_POR_VALUE sc_uint<64>("0b0") | |
| 668 | #define PEU_CSR_CE_ERR_RW1S_ALIAS_RNR_S_POR_VALUE sc_uint<64>("0b0") | |
| 669 | #define PEU_CSR_CE_ERR_RW1S_ALIAS_BDP_S_POR_VALUE sc_uint<64>("0b0") | |
| 670 | #define PEU_CSR_CE_ERR_RW1S_ALIAS_BTP_S_POR_VALUE sc_uint<64>("0b0") | |
| 671 | #define PEU_CSR_CE_ERR_RW1S_ALIAS_RE_S_POR_VALUE sc_uint<64>("0b0") | |
| 672 | #define PEU_CSR_CE_ERR_RW1S_ALIAS_RTO_P_POR_VALUE sc_uint<64>("0b0") | |
| 673 | #define PEU_CSR_CE_ERR_RW1S_ALIAS_RNR_P_POR_VALUE sc_uint<64>("0b0") | |
| 674 | #define PEU_CSR_CE_ERR_RW1S_ALIAS_BDP_P_POR_VALUE sc_uint<64>("0b0") | |
| 675 | #define PEU_CSR_CE_ERR_RW1S_ALIAS_BTP_P_POR_VALUE sc_uint<64>("0b0") | |
| 676 | #define PEU_CSR_CE_ERR_RW1S_ALIAS_RE_P_POR_VALUE sc_uint<64>("0b0") | |
| 677 | #define PEU_CSR_PEU_DLPL_SERDES_REV_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 678 | #define PEU_CSR_PEU_DLPL_SERDES_REV_DLPL_ID_POR_VALUE sc_uint<64>("0b0000") | |
| 679 | #define PEU_CSR_PEU_DLPL_SERDES_REV_SERDES_ID_POR_VALUE sc_uint<64>("0b0000") | |
| 680 | #define PEU_CSR_ACKNAK_THRESH_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000001000011") | |
| 681 | #define PEU_CSR_ACKNAK_THRESH_ACK_NAK_THR_POR_VALUE sc_uint<64>("0b0000000001000011") | |
| 682 | #define PEU_CSR_ACKNAK_TIMER_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 683 | #define PEU_CSR_ACKNAK_TIMER_ACK_NAK_TMR_POR_VALUE sc_uint<64>("0b0000000000000000") | |
| 684 | #define PEU_CSR_REPLAY_TIM_THRESH_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000011111100") | |
| 685 | #define PEU_CSR_REPLAY_TIM_THRESH_RPLAY_TMR_THR_POR_VALUE sc_uint<64>("0b0000000011111100") | |
| 686 | #define PEU_CSR_REPLAY_TIMER_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 687 | #define PEU_CSR_REPLAY_TIMER_REPLAY_NUM_POR_VALUE sc_uint<64>("0b00") | |
| 688 | #define PEU_CSR_REPLAY_TIMER_RPLAY_TMR_POR_VALUE sc_uint<64>("0b0000000000000000") | |
| 689 | #define PEU_CSR_VEN_DLLP_MSG_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 690 | #define PEU_CSR_VEN_DLLP_MSG_V_MESSAGE_POR_VALUE sc_uint<64>("0b00000000000000000000000000000000") | |
| 691 | #define PEU_CSR_FORCE_LTSSM_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 692 | #define PEU_CSR_FORCE_LTSSM_FORCE_EN_POR_VALUE sc_uint<64>("0b0") | |
| 693 | #define PEU_CSR_FORCE_LTSSM_FORCED_LTSSM_POR_VALUE sc_uint<64>("0b00000") | |
| 694 | #define PEU_CSR_LINK_CFG_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000100000001") | |
| 695 | #define PEU_CSR_LINK_CFG_ACK_FREQ_POR_VALUE sc_uint<64>("0b00000001") | |
| 696 | #define PEU_CSR_LINK_CFG_FLOW_CONTROL_DISABLE_POR_VALUE sc_uint<64>("0b0") | |
| 697 | #define PEU_CSR_LINK_CFG_SPARE_POR_VALUE sc_uint<64>("0b0") | |
| 698 | #define PEU_CSR_LINK_CFG_OTHER_MESSAGE_REQUEST_POR_VALUE sc_uint<64>("0b0") | |
| 699 | #define PEU_CSR_LINK_CFG_ACK_NAK_DISABLE_POR_VALUE sc_uint<64>("0b0") | |
| 700 | #define PEU_CSR_LINK_CFG_DATA_LINK_ENABLE_POR_VALUE sc_uint<64>("0b1") | |
| 701 | #define PEU_CSR_LINK_CTL_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000110110000100000000000") | |
| 702 | #define PEU_CSR_LINK_CTL_LINK_NUM_POR_VALUE sc_uint<64>("0b00000000") | |
| 703 | #define PEU_CSR_LINK_CTL_N_FTS_POR_VALUE sc_uint<64>("0b00011011") | |
| 704 | #define PEU_CSR_LINK_CTL_SPARE_POR_VALUE sc_uint<64>("0b00") | |
| 705 | #define PEU_CSR_LINK_CTL_LINK_CAPABLE_POR_VALUE sc_uint<64>("0b1000") | |
| 706 | #define PEU_CSR_LINK_CTL_FAST_LINK_MODE_POR_VALUE sc_uint<64>("0b0") | |
| 707 | #define PEU_CSR_LINK_CTL_RX_HIGH_IMP_DIS_POR_VALUE sc_uint<64>("0b0") | |
| 708 | #define PEU_CSR_LINK_CTL_ELASTICAL_BUFFER_DISABLE_POR_VALUE sc_uint<64>("0b0") | |
| 709 | #define PEU_CSR_LINK_CTL_SCRAMBLE_DISABLE_POR_VALUE sc_uint<64>("0b0") | |
| 710 | #define PEU_CSR_LINK_CTL_RESET_ASSERT_POR_VALUE sc_uint<64>("0b0") | |
| 711 | #define PEU_CSR_LANE_SKEW_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 712 | #define PEU_CSR_LANE_SKEW_DESKEW_DISABLE_POR_VALUE sc_uint<64>("0b0") | |
| 713 | #define PEU_CSR_LANE_SKEW_SPARE_POR_VALUE sc_uint<64>("0b0") | |
| 714 | #define PEU_CSR_LANE_SKEW_SPARE2_POR_VALUE sc_uint<64>("0b000000000000000") | |
| 715 | #define PEU_CSR_LANE_SKEW_FORCE_RCV_PRESENT_EN_POR_VALUE sc_uint<64>("0b0") | |
| 716 | #define PEU_CSR_LANE_SKEW_LN_7_RCV_PRESENT_POR_VALUE sc_uint<64>("0b0") | |
| 717 | #define PEU_CSR_LANE_SKEW_LN_6_RCV_PRESENT_POR_VALUE sc_uint<64>("0b0") | |
| 718 | #define PEU_CSR_LANE_SKEW_LN_5_RCV_PRESENT_POR_VALUE sc_uint<64>("0b0") | |
| 719 | #define PEU_CSR_LANE_SKEW_LN_4_RCV_PRESENT_POR_VALUE sc_uint<64>("0b0") | |
| 720 | #define PEU_CSR_LANE_SKEW_LN_3_RCV_PRESENT_POR_VALUE sc_uint<64>("0b0") | |
| 721 | #define PEU_CSR_LANE_SKEW_LN_2_RCV_PRESENT_POR_VALUE sc_uint<64>("0b0") | |
| 722 | #define PEU_CSR_LANE_SKEW_LN_1_RCV_PRESENT_POR_VALUE sc_uint<64>("0b0") | |
| 723 | #define PEU_CSR_LANE_SKEW_LN_0_RCV_PRESENT_POR_VALUE sc_uint<64>("0b0") | |
| 724 | #define PEU_CSR_SYMBOL_NUM_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000011001110101010") | |
| 725 | #define PEU_CSR_SYMBOL_NUM_SPARE_POR_VALUE sc_uint<64>("0b011") | |
| 726 | #define PEU_CSR_SYMBOL_NUM_SKIP_SYMBOLS_POR_VALUE sc_uint<64>("0b011") | |
| 727 | #define PEU_CSR_SYMBOL_NUM_SPARE2_POR_VALUE sc_uint<64>("0b1010") | |
| 728 | #define PEU_CSR_SYMBOL_NUM_TS1_SYMBOLS_POR_VALUE sc_uint<64>("0b1010") | |
| 729 | #define PEU_CSR_SYMBOL_TIMER_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000010100000000") | |
| 730 | #define PEU_CSR_SYMBOL_TIMER_SKIP_INTERVAL_POR_VALUE sc_uint<64>("0b10100000000") | |
| 731 | #define PEU_CSR_CORE_STATUS_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000011") | |
| 732 | /// Following is temp for power up test | |
| 733 | //#define PEU_CSR_CORE_STATUS_POR_VALUE sc_uint<64>("0b0000000000000001000000000000000000000000000011111111000000000111") | |
| 734 | #define PEU_CSR_CORE_STATUS_TX_LOS_STATE_POR_VALUE sc_uint<64>("0b000") | |
| 735 | #define PEU_CSR_CORE_STATUS_RV_LOS_STATE_POR_VALUE sc_uint<64>("0b00") | |
| 736 | #define PEU_CSR_CORE_STATUS_INT_FCSM_STATE_POR_VALUE sc_uint<64>("0b00") | |
| 737 | #define PEU_CSR_CORE_STATUS_RBUF_NOT_EMPTY_POR_VALUE sc_uint<64>("0b0") | |
| 738 | #define PEU_CSR_CORE_STATUS_LTSSM_STATE_POR_VALUE sc_uint<64>("0b00000") | |
| 739 | #define PEU_CSR_CORE_STATUS_RCV_POLARITY_REV_POR_VALUE sc_uint<64>("0b00000000") | |
| 740 | #define PEU_CSR_CORE_STATUS_RCV_FTS_NUM_POR_VALUE sc_uint<64>("0b00000000") | |
| 741 | #define PEU_CSR_CORE_STATUS_RCV_LINK_NUM_POR_VALUE sc_uint<64>("0b00000000") | |
| 742 | #define PEU_CSR_CORE_STATUS_PCS_LOCK_STS_POR_VALUE sc_uint<64>("0b00000000") | |
| 743 | #define PEU_CSR_CORE_STATUS_RCVR_DETECT_STS_POR_VALUE sc_uint<64>("0b00000000") | |
| 744 | #define PEU_CSR_CORE_STATUS_PCS_LANE_REV_POR_VALUE sc_uint<64>("0b0") | |
| 745 | #define PEU_CSR_CORE_STATUS_PCS_ALIGN_STS_POR_VALUE sc_uint<64>("0b0") | |
| 746 | #define PEU_CSR_CORE_STATUS_SDS_READY_1_POR_VALUE sc_uint<64>("0b0") | |
| 747 | #define PEU_CSR_CORE_STATUS_SDS_READY_0_POR_VALUE sc_uint<64>("0b0") | |
| 748 | #define PEU_CSR_EVENT_ERR_LOG_EN_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000001111000000111111111111111111") | |
| 749 | #define PEU_CSR_EVENT_ERR_LOG_EN_EN_EVENT_POR_VALUE sc_uint<64>("0b00001111") | |
| 750 | #define PEU_CSR_EVENT_ERR_LOG_EN_EN_ERROR_POR_VALUE sc_uint<64>("0b111111111111111111") | |
| 751 | #define PEU_CSR_EVENT_ERR_INT_EN_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 752 | #define PEU_CSR_EVENT_ERR_INT_EN_EN_EVENT_POR_VALUE sc_uint<64>("0b00000000") | |
| 753 | #define PEU_CSR_EVENT_ERR_INT_EN_EN_ERROR_POR_VALUE sc_uint<64>("0b000000000000000000") | |
| 754 | #define PEU_CSR_EVENT_ERR_INT_STS_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 755 | #define PEU_CSR_EVENT_ERR_INT_STS_EN_EVENT_POR_VALUE sc_uint<64>("0b00000000") | |
| 756 | #define PEU_CSR_EVENT_ERR_INT_STS_EN_ERROR_POR_VALUE sc_uint<64>("0b000000000000000000") | |
| 757 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 758 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_EVT_RCV_EN_LB_POR_VALUE sc_uint<64>("0b0") | |
| 759 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_EVT_RCV_DIS_LINK_POR_VALUE sc_uint<64>("0b0") | |
| 760 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_EVT_RCV_HOT_RST_POR_VALUE sc_uint<64>("0b0") | |
| 761 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_EVT_RCV_EIDLE_EXIT_POR_VALUE sc_uint<64>("0b0") | |
| 762 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_EVT_RCV_EIDLE_POR_VALUE sc_uint<64>("0b0") | |
| 763 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_EVT_RCV_TS1_POR_VALUE sc_uint<64>("0b0") | |
| 764 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_EVT_RCV_TS2_POR_VALUE sc_uint<64>("0b0") | |
| 765 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_EVT_SEND_SKP_B2B_POR_VALUE sc_uint<64>("0b0") | |
| 766 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_OUTSTANDING_SKIP_POR_VALUE sc_uint<64>("0b0") | |
| 767 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_ELASTIC_FIFO_UNDRFLW_POR_VALUE sc_uint<64>("0b0") | |
| 768 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_ELASTIC_FIFO_OVRFLW_POR_VALUE sc_uint<64>("0b0") | |
| 769 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_ALIGN_POR_VALUE sc_uint<64>("0b0") | |
| 770 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_KCHAR_DLLP_POR_VALUE sc_uint<64>("0b0") | |
| 771 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_ILL_END_POS_POR_VALUE sc_uint<64>("0b0") | |
| 772 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_SYNC_POR_VALUE sc_uint<64>("0b0") | |
| 773 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_END_EDB_NO_STP_SDP_POR_VALUE sc_uint<64>("0b0") | |
| 774 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_SDP_NO_END_POR_VALUE sc_uint<64>("0b0") | |
| 775 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_STP_NO_END_EDB_POR_VALUE sc_uint<64>("0b0") | |
| 776 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_ILL_PAD_POS_POR_VALUE sc_uint<64>("0b0") | |
| 777 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_MULTI_SDP_POR_VALUE sc_uint<64>("0b0") | |
| 778 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_MULTI_STP_POR_VALUE sc_uint<64>("0b0") | |
| 779 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_ILL_SDP_POS_POR_VALUE sc_uint<64>("0b0") | |
| 780 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_ILL_STP_POS_POR_VALUE sc_uint<64>("0b0") | |
| 781 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_UNSUP_DLLP_POR_VALUE sc_uint<64>("0b0") | |
| 782 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_SRC_TLP_POR_VALUE sc_uint<64>("0b0") | |
| 783 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_SDS_LOS_POR_VALUE sc_uint<64>("0b0") | |
| 784 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 785 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_EVT_RCV_EN_LB_POR_VALUE sc_uint<64>("0b0") | |
| 786 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_EVT_RCV_DIS_LINK_POR_VALUE sc_uint<64>("0b0") | |
| 787 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_EVT_RCV_HOT_RST_POR_VALUE sc_uint<64>("0b0") | |
| 788 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_EVT_RCV_EIDLE_EXIT_POR_VALUE sc_uint<64>("0b0") | |
| 789 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_EVT_RCV_EIDLE_POR_VALUE sc_uint<64>("0b0") | |
| 790 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_EVT_RCV_TS1_POR_VALUE sc_uint<64>("0b0") | |
| 791 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_EVT_RCV_TS2_POR_VALUE sc_uint<64>("0b0") | |
| 792 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_EVT_SEND_SKP_B2B_POR_VALUE sc_uint<64>("0b0") | |
| 793 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_ERR_OUTSTANDING_SKIP_POR_VALUE sc_uint<64>("0b0") | |
| 794 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_ERR_ELASTIC_FIFO_UNDRFLW_POR_VALUE sc_uint<64>("0b0") | |
| 795 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_ERR_ELASTIC_FIFO_OVRFLW_POR_VALUE sc_uint<64>("0b0") | |
| 796 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_ERR_ALIGN_POR_VALUE sc_uint<64>("0b0") | |
| 797 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_ERR_KCHAR_DLLP_POR_VALUE sc_uint<64>("0b0") | |
| 798 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_ERR_ILL_END_POS_POR_VALUE sc_uint<64>("0b0") | |
| 799 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_ERR_SYNC_POR_VALUE sc_uint<64>("0b0") | |
| 800 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_ERR_END_EDB_NO_STP_SDP_POR_VALUE sc_uint<64>("0b0") | |
| 801 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_ERR_SDP_NO_END_POR_VALUE sc_uint<64>("0b0") | |
| 802 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_ERR_STP_NO_END_EDB_POR_VALUE sc_uint<64>("0b0") | |
| 803 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_ERR_ILL_PAD_POS_POR_VALUE sc_uint<64>("0b0") | |
| 804 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_ERR_MULTI_SDP_POR_VALUE sc_uint<64>("0b0") | |
| 805 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_ERR_MULTI_STP_POR_VALUE sc_uint<64>("0b0") | |
| 806 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_ERR_ILL_SDP_POS_POR_VALUE sc_uint<64>("0b0") | |
| 807 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_ERR_ILL_STP_POS_POR_VALUE sc_uint<64>("0b0") | |
| 808 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_ERR_UNSUP_DLLP_POR_VALUE sc_uint<64>("0b0") | |
| 809 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_ERR_SRC_TLP_POR_VALUE sc_uint<64>("0b0") | |
| 810 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_ERR_SDS_LOS_POR_VALUE sc_uint<64>("0b0") | |
| 811 | #define PEU_CSR_LNK_BIT_ERR_CNT_1_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 812 | #define PEU_CSR_LNK_BIT_ERR_CNT_1_BER_COUNT_EN_POR_VALUE sc_uint<64>("0b0") | |
| 813 | #define PEU_CSR_LNK_BIT_ERR_CNT_1_BER_COUNT_CLR_POR_VALUE sc_uint<64>("0b0") | |
| 814 | #define PEU_CSR_LNK_BIT_ERR_CNT_1_CNT_BAD_DLLP_POR_VALUE sc_uint<64>("0b00000000") | |
| 815 | #define PEU_CSR_LNK_BIT_ERR_CNT_1_CNT_BAD_TLP_POR_VALUE sc_uint<64>("0b00000000") | |
| 816 | #define PEU_CSR_LNK_BIT_ERR_CNT_1_CNT_PRE_POR_VALUE sc_uint<64>("0b0000000000") | |
| 817 | #define PEU_CSR_LNK_BIT_ERR_CNT_2_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 818 | #define PEU_CSR_LNK_BIT_ERR_CNT_2_CNT_BAD_SYMBOL_7_POR_VALUE sc_uint<64>("0b000000") | |
| 819 | #define PEU_CSR_LNK_BIT_ERR_CNT_2_CNT_BAD_SYMBOL_6_POR_VALUE sc_uint<64>("0b000000") | |
| 820 | #define PEU_CSR_LNK_BIT_ERR_CNT_2_CNT_BAD_SYMBOL_5_POR_VALUE sc_uint<64>("0b000000") | |
| 821 | #define PEU_CSR_LNK_BIT_ERR_CNT_2_CNT_BAD_SYMBOL_4_POR_VALUE sc_uint<64>("0b000000") | |
| 822 | #define PEU_CSR_LNK_BIT_ERR_CNT_2_CNT_BAD_SYMBOL_3_POR_VALUE sc_uint<64>("0b000000") | |
| 823 | #define PEU_CSR_LNK_BIT_ERR_CNT_2_CNT_BAD_SYMBOL_2_POR_VALUE sc_uint<64>("0b000000") | |
| 824 | #define PEU_CSR_LNK_BIT_ERR_CNT_2_CNT_BAD_SYMBOL_1_POR_VALUE sc_uint<64>("0b000000") | |
| 825 | #define PEU_CSR_LNK_BIT_ERR_CNT_2_CNT_BAD_SYMBOL_0_POR_VALUE sc_uint<64>("0b000000") | |
| 826 | #define PEU_CSR_SERDES_PLL_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000001") | |
| 827 | #define PEU_CSR_SERDES_PLL_SPARE_POR_VALUE sc_uint<64>("0b00") | |
| 828 | #define PEU_CSR_SERDES_PLL_LB_POR_VALUE sc_uint<64>("0b00") | |
| 829 | #define PEU_CSR_SERDES_PLL_MPY_POR_VALUE sc_uint<64>("0b0001") | |
| 830 | #define PEU_CSR_SERDES_RECEIVER_LANE_CTL_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000010101010010") | |
| 831 | #define PEU_CSR_SERDES_RECEIVER_LANE_CTL_BSINRXN_POR_VALUE sc_uint<64>("0b0") | |
| 832 | #define PEU_CSR_SERDES_RECEIVER_LANE_CTL_BSINRXP_POR_VALUE sc_uint<64>("0b0") | |
| 833 | #define PEU_CSR_SERDES_RECEIVER_LANE_CTL_EQ_POR_VALUE sc_uint<64>("0b0001") | |
| 834 | #define PEU_CSR_SERDES_RECEIVER_LANE_CTL_CDR_POR_VALUE sc_uint<64>("0b010") | |
| 835 | #define PEU_CSR_SERDES_RECEIVER_LANE_CTL_LOS_POR_VALUE sc_uint<64>("0b10") | |
| 836 | #define PEU_CSR_SERDES_RECEIVER_LANE_CTL_TERM_POR_VALUE sc_uint<64>("0b100") | |
| 837 | #define PEU_CSR_SERDES_RECEIVER_LANE_CTL_CMA_ALN_EN_POR_VALUE sc_uint<64>("0b1") | |
| 838 | #define PEU_CSR_SERDES_RECEIVER_LANE_CTL_ENTEST_POR_VALUE sc_uint<64>("0b0") | |
| 839 | #define PEU_CSR_SERDES_RECEIVER_LANE_STATUS_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 840 | #define PEU_CSR_SERDES_RECEIVER_LANE_STATUS_LOSDTCT_POR_VALUE sc_uint<64>("0b0") | |
| 841 | #define PEU_CSR_SERDES_RECEIVER_LANE_STATUS_SYNC_POR_VALUE sc_uint<64>("0b0") | |
| 842 | #define PEU_CSR_SERDES_RECEIVER_LANE_STATUS_TESTFAIL_POR_VALUE sc_uint<64>("0b0") | |
| 843 | #define PEU_CSR_SERDES_XMITTER_LANE_CTL_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000111101100") | |
| 844 | #define PEU_CSR_SERDES_XMITTER_LANE_CTL_SPARE_POR_VALUE sc_uint<64>("0b0") | |
| 845 | #define PEU_CSR_SERDES_XMITTER_LANE_CTL_DE_POR_VALUE sc_uint<64>("0b0111") | |
| 846 | #define PEU_CSR_SERDES_XMITTER_LANE_CTL_SWING_POR_VALUE sc_uint<64>("0b101") | |
| 847 | #define PEU_CSR_SERDES_XMITTER_LANE_CTL_CM_POR_VALUE sc_uint<64>("0b1") | |
| 848 | #define PEU_CSR_SERDES_XMITTER_LANE_CTL_INVPAIR_POR_VALUE sc_uint<64>("0b0") | |
| 849 | #define PEU_CSR_SERDES_XMITTER_LANE_CTL_ENTEST_POR_VALUE sc_uint<64>("0b0") | |
| 850 | #define PEU_CSR_SERDES_XMITTER_LANE_STATUS_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 851 | #define PEU_CSR_SERDES_XMITTER_LANE_STATUS_RDTCTIP_POR_VALUE sc_uint<64>("0b0") | |
| 852 | #define PEU_CSR_SERDES_XMITTER_LANE_STATUS_TESTFAIL_POR_VALUE sc_uint<64>("0b0") | |
| 853 | #define PEU_CSR_SERDES_MACRO_TEST_CFG_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000011") | |
| 854 | #define PEU_CSR_SERDES_MACRO_TEST_CFG_INVPATT_POR_VALUE sc_uint<64>("0b0") | |
| 855 | #define PEU_CSR_SERDES_MACRO_TEST_CFG_RATE_POR_VALUE sc_uint<64>("0b00") | |
| 856 | #define PEU_CSR_SERDES_MACRO_TEST_CFG_RESERVED_POR_VALUE sc_uint<64>("0b0") | |
| 857 | #define PEU_CSR_SERDES_MACRO_TEST_CFG_ENBSPT_POR_VALUE sc_uint<64>("0b0") | |
| 858 | #define PEU_CSR_SERDES_MACRO_TEST_CFG_ENBSRX_POR_VALUE sc_uint<64>("0b0") | |
| 859 | #define PEU_CSR_SERDES_MACRO_TEST_CFG_ENBSTX_POR_VALUE sc_uint<64>("0b0") | |
| 860 | #define PEU_CSR_SERDES_MACRO_TEST_CFG_LOOPBACK_POR_VALUE sc_uint<64>("0b00") | |
| 861 | #define PEU_CSR_SERDES_MACRO_TEST_CFG_CLKBYP_POR_VALUE sc_uint<64>("0b00") | |
| 862 | #define PEU_CSR_SERDES_MACRO_TEST_CFG_ENRXPATT_POR_VALUE sc_uint<64>("0b0") | |
| 863 | #define PEU_CSR_SERDES_MACRO_TEST_CFG_ENTXPATT_POR_VALUE sc_uint<64>("0b0") | |
| 864 | #define PEU_CSR_SERDES_MACRO_TEST_CFG_TESTPATT_POR_VALUE sc_uint<64>("0b11") | |
| 865 | ||
| 866 | ||
| 867 | #define PEU_CSR_TLU_CTL_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 868 | #define PEU_CSR_TLU_STS_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000100000000") | |
| 869 | #define PEU_CSR_TRN_OFF_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 870 | #define PEU_CSR_TLU_ICI_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 871 | #define PEU_CSR_TLU_DIAG_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 872 | #define PEU_CSR_TLU_ECC_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 873 | #define PEU_CSR_TLU_ECL_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 874 | #define PEU_CSR_TLU_ERB_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 875 | #define PEU_CSR_TLU_ICA_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 876 | #define PEU_CSR_TLU_ICR_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 877 | #define PEU_CSR_OE_LOG_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 878 | #define PEU_CSR_OE_INT_EN_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 879 | #define PEU_CSR_OE_EN_ERR_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 880 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_CLEAR_MASK sc_uint<64>("0b0000000011111111111111111111111100000000111111111111111111111111") | |
| 881 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 882 | #define PEU_CSR_ROE_HDR1_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 883 | #define PEU_CSR_ROE_HDR2_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 884 | #define PEU_CSR_TOE_HDR1_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 885 | #define PEU_CSR_TOE_HDR2_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 886 | #define PEU_CSR_TLU_PRFC_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 887 | #define PEU_CSR_TLU_PRF0_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 888 | #define PEU_CSR_TLU_PRF1_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 889 | #define PEU_CSR_TLU_PRF2_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 890 | #define PEU_CSR_TLU_DBG_SEL_A_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 891 | #define PEU_CSR_TLU_DBG_SEL_B_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 892 | #define PEU_CSR_DEV_CAP_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 893 | #define PEU_CSR_DEV_CTL_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 894 | #define PEU_CSR_DEV_STS_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 895 | #define PEU_CSR_LNK_CAP_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 896 | #define PEU_CSR_LNK_CTL_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 897 | #define PEU_CSR_LNK_STS_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 898 | #define PEU_CSR_SLT_CAP_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 899 | #define PEU_CSR_UE_LOG_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 900 | #define PEU_CSR_UE_INT_EN_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 901 | #define PEU_CSR_UE_EN_ERR_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 902 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_CLEAR_MASK sc_uint<64>("0b0000000000010111111100000001000100000000000101111111000000010001") | |
| 903 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 904 | #define PEU_CSR_RUE_HDR1_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 905 | #define PEU_CSR_RUE_HDR2_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 906 | #define PEU_CSR_TUE_HDR1_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 907 | #define PEU_CSR_TUE_HDR2_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 908 | #define PEU_CSR_CE_LOG_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 909 | #define PEU_CSR_CE_INT_EN_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 910 | #define PEU_CSR_CE_EN_ERR_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 911 | #define PEU_CSR_CE_ERR_RW1C_ALIAS_CLEAR_MASK sc_uint<64>("0b0000000000000000000100011100000100000000000000000001000111000001") | |
| 912 | #define PEU_CSR_CE_ERR_RW1S_ALIAS_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 913 | #define PEU_CSR_PEU_DLPL_SERDES_REV_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 914 | #define PEU_CSR_ACKNAK_THRESH_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 915 | #define PEU_CSR_ACKNAK_TIMER_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 916 | #define PEU_CSR_REPLAY_TIM_THRESH_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 917 | #define PEU_CSR_REPLAY_TIMER_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 918 | #define PEU_CSR_VEN_DLLP_MSG_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 919 | #define PEU_CSR_FORCE_LTSSM_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 920 | #define PEU_CSR_LINK_CFG_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 921 | #define PEU_CSR_LINK_CTL_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 922 | #define PEU_CSR_LANE_SKEW_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 923 | #define PEU_CSR_SYMBOL_NUM_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 924 | #define PEU_CSR_SYMBOL_TIMER_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 925 | #define PEU_CSR_CORE_STATUS_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 926 | #define PEU_CSR_EVENT_ERR_LOG_EN_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 927 | #define PEU_CSR_EVENT_ERR_INT_EN_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 928 | #define PEU_CSR_EVENT_ERR_INT_STS_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 929 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000011111111000000111111111111111111") | |
| 930 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 931 | #define PEU_CSR_LNK_BIT_ERR_CNT_1_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 932 | #define PEU_CSR_LNK_BIT_ERR_CNT_2_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 933 | #define PEU_CSR_SERDES_PLL_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 934 | #define PEU_CSR_SERDES_RECEIVER_LANE_CTL_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 935 | #define PEU_CSR_SERDES_RECEIVER_LANE_STATUS_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 936 | #define PEU_CSR_SERDES_XMITTER_LANE_CTL_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 937 | #define PEU_CSR_SERDES_XMITTER_LANE_STATUS_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 938 | #define PEU_CSR_SERDES_MACRO_TEST_CFG_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 939 | ||
| 940 | #define PEU_CSR_TLU_CTL_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 941 | #define PEU_CSR_TLU_STS_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 942 | #define PEU_CSR_TRN_OFF_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000001") | |
| 943 | #define PEU_CSR_TLU_ICI_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 944 | #define PEU_CSR_TLU_DIAG_SET_MASK sc_uint<64>("0b0000000010000000000000000000000000000000000000000000000011110000") | |
| 945 | #define PEU_CSR_TLU_ECC_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 946 | #define PEU_CSR_TLU_ECL_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 947 | #define PEU_CSR_TLU_ERB_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 948 | #define PEU_CSR_TLU_ICA_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 949 | #define PEU_CSR_TLU_ICR_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 950 | #define PEU_CSR_OE_LOG_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 951 | #define PEU_CSR_OE_INT_EN_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 952 | #define PEU_CSR_OE_EN_ERR_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 953 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 954 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_SET_MASK sc_uint<64>("0b0000000011111111111111111111111100000000111111111111111111111111") | |
| 955 | #define PEU_CSR_ROE_HDR1_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 956 | #define PEU_CSR_ROE_HDR2_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 957 | #define PEU_CSR_TOE_HDR1_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 958 | #define PEU_CSR_TOE_HDR2_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 959 | #define PEU_CSR_TLU_PRFC_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 960 | #define PEU_CSR_TLU_PRF0_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 961 | #define PEU_CSR_TLU_PRF1_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 962 | #define PEU_CSR_TLU_PRF2_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 963 | #define PEU_CSR_TLU_DBG_SEL_A_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 964 | #define PEU_CSR_TLU_DBG_SEL_B_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 965 | #define PEU_CSR_DEV_CAP_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 966 | #define PEU_CSR_DEV_CTL_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 967 | #define PEU_CSR_DEV_STS_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 968 | #define PEU_CSR_LNK_CAP_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 969 | #define PEU_CSR_LNK_CTL_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 970 | #define PEU_CSR_LNK_STS_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 971 | #define PEU_CSR_SLT_CAP_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 972 | #define PEU_CSR_UE_LOG_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 973 | #define PEU_CSR_UE_INT_EN_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 974 | #define PEU_CSR_UE_EN_ERR_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 975 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 976 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_SET_MASK sc_uint<64>("0b0000000000010111111100000001000100000000000101111111000000010001") | |
| 977 | #define PEU_CSR_RUE_HDR1_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 978 | #define PEU_CSR_RUE_HDR2_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 979 | #define PEU_CSR_TUE_HDR1_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 980 | #define PEU_CSR_TUE_HDR2_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 981 | #define PEU_CSR_CE_LOG_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 982 | #define PEU_CSR_CE_INT_EN_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 983 | #define PEU_CSR_CE_EN_ERR_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 984 | #define PEU_CSR_CE_ERR_RW1C_ALIAS_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 985 | #define PEU_CSR_CE_ERR_RW1S_ALIAS_SET_MASK sc_uint<64>("0b0000000000000000000100011100000100000000000000000001000111000001") | |
| 986 | #define PEU_CSR_PEU_DLPL_SERDES_REV_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 987 | #define PEU_CSR_ACKNAK_THRESH_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 988 | #define PEU_CSR_ACKNAK_TIMER_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 989 | #define PEU_CSR_REPLAY_TIM_THRESH_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 990 | #define PEU_CSR_REPLAY_TIMER_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 991 | #define PEU_CSR_VEN_DLLP_MSG_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 992 | #define PEU_CSR_FORCE_LTSSM_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 993 | #define PEU_CSR_LINK_CFG_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 994 | #define PEU_CSR_LINK_CTL_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000001") | |
| 995 | #define PEU_CSR_LANE_SKEW_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 996 | #define PEU_CSR_SYMBOL_NUM_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 997 | #define PEU_CSR_SYMBOL_TIMER_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 998 | #define PEU_CSR_CORE_STATUS_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 999 | #define PEU_CSR_EVENT_ERR_LOG_EN_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1000 | #define PEU_CSR_EVENT_ERR_INT_EN_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1001 | #define PEU_CSR_EVENT_ERR_INT_STS_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1002 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1003 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_SET_MASK sc_uint<64>("0b0000000000000000000000000000000011111111000000111111111111111111") | |
| 1004 | #define PEU_CSR_LNK_BIT_ERR_CNT_1_SET_MASK sc_uint<64>("0b0100000000000000000000000000000000000000000000000000000000000000") | |
| 1005 | #define PEU_CSR_LNK_BIT_ERR_CNT_2_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1006 | #define PEU_CSR_SERDES_PLL_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1007 | #define PEU_CSR_SERDES_RECEIVER_LANE_CTL_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1008 | #define PEU_CSR_SERDES_RECEIVER_LANE_STATUS_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1009 | #define PEU_CSR_SERDES_XMITTER_LANE_CTL_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1010 | #define PEU_CSR_SERDES_XMITTER_LANE_STATUS_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1011 | #define PEU_CSR_SERDES_MACRO_TEST_CFG_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1012 | ||
| 1013 | #define PEU_CSR_TLU_CTL_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1014 | #define PEU_CSR_TLU_STS_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1015 | #define PEU_CSR_TRN_OFF_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1016 | #define PEU_CSR_TLU_ICI_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1017 | #define PEU_CSR_TLU_DIAG_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1018 | #define PEU_CSR_TLU_ECC_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1019 | #define PEU_CSR_TLU_ECL_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1020 | #define PEU_CSR_TLU_ERB_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1021 | #define PEU_CSR_TLU_ICA_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1022 | #define PEU_CSR_TLU_ICR_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1023 | #define PEU_CSR_OE_LOG_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1024 | #define PEU_CSR_OE_INT_EN_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1025 | #define PEU_CSR_OE_EN_ERR_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1026 | #define PEU_CSR_OE_ERR_RW1C_ALIAS_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1027 | #define PEU_CSR_OE_ERR_RW1S_ALIAS_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1028 | #define PEU_CSR_ROE_HDR1_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1029 | #define PEU_CSR_ROE_HDR2_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1030 | #define PEU_CSR_TOE_HDR1_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1031 | #define PEU_CSR_TOE_HDR2_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1032 | #define PEU_CSR_TLU_PRFC_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1033 | #define PEU_CSR_TLU_PRF0_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1034 | #define PEU_CSR_TLU_PRF1_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1035 | #define PEU_CSR_TLU_PRF2_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1036 | #define PEU_CSR_TLU_DBG_SEL_A_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1037 | #define PEU_CSR_TLU_DBG_SEL_B_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1038 | #define PEU_CSR_DEV_CAP_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1039 | #define PEU_CSR_DEV_CTL_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1040 | #define PEU_CSR_DEV_STS_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1041 | #define PEU_CSR_LNK_CAP_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1042 | #define PEU_CSR_LNK_CTL_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1043 | #define PEU_CSR_LNK_STS_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1044 | #define PEU_CSR_SLT_CAP_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1045 | #define PEU_CSR_UE_LOG_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1046 | #define PEU_CSR_UE_INT_EN_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1047 | #define PEU_CSR_UE_EN_ERR_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1048 | #define PEU_CSR_UE_ERR_RW1C_ALIAS_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1049 | #define PEU_CSR_UE_ERR_RW1S_ALIAS_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1050 | #define PEU_CSR_RUE_HDR1_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1051 | #define PEU_CSR_RUE_HDR2_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1052 | #define PEU_CSR_TUE_HDR1_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1053 | #define PEU_CSR_TUE_HDR2_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1054 | #define PEU_CSR_CE_LOG_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1055 | #define PEU_CSR_CE_INT_EN_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1056 | #define PEU_CSR_CE_EN_ERR_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1057 | #define PEU_CSR_CE_ERR_RW1C_ALIAS_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1058 | #define PEU_CSR_CE_ERR_RW1S_ALIAS_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1059 | #define PEU_CSR_PEU_DLPL_SERDES_REV_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1060 | #define PEU_CSR_ACKNAK_THRESH_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1061 | #define PEU_CSR_ACKNAK_TIMER_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1062 | #define PEU_CSR_REPLAY_TIM_THRESH_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1063 | #define PEU_CSR_REPLAY_TIMER_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1064 | #define PEU_CSR_VEN_DLLP_MSG_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1065 | #define PEU_CSR_FORCE_LTSSM_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1066 | #define PEU_CSR_LINK_CFG_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1067 | #define PEU_CSR_LINK_CTL_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1068 | #define PEU_CSR_LANE_SKEW_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1069 | #define PEU_CSR_SYMBOL_NUM_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1070 | #define PEU_CSR_SYMBOL_TIMER_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1071 | #define PEU_CSR_CORE_STATUS_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1072 | #define PEU_CSR_EVENT_ERR_LOG_EN_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1073 | #define PEU_CSR_EVENT_ERR_INT_EN_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1074 | #define PEU_CSR_EVENT_ERR_INT_STS_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1075 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1C_ALIAS_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1076 | #define PEU_CSR_EVENT_ERR_STS_CLR_RW1S_ALIAS_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1077 | #define PEU_CSR_LNK_BIT_ERR_CNT_1_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1078 | #define PEU_CSR_LNK_BIT_ERR_CNT_2_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1079 | #define PEU_CSR_SERDES_PLL_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1080 | #define PEU_CSR_SERDES_RECEIVER_LANE_CTL_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1081 | #define PEU_CSR_SERDES_RECEIVER_LANE_STATUS_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1082 | #define PEU_CSR_SERDES_XMITTER_LANE_CTL_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1083 | #define PEU_CSR_SERDES_XMITTER_LANE_STATUS_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1084 | #define PEU_CSR_SERDES_MACRO_TEST_CFG_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1085 | ||
| 1086 | //------------------------------------------------------- | |
| 1087 | //----- Variable definitions for register ptl_ctb_tlr_csr_core_status | |
| 1088 | //------------------------------------------------------- | |
| 1089 | #define PEU_CSR_CORE_STATUS_WIDTH 64 | |
| 1090 | #define PEU_CSR_CORE_STATUS_DEPTH 1 | |
| 1091 | #define PEU_CSR_CORE_STATUS_SLC (63,0) | |
| 1092 | #define PEU_CSR_CORE_STATUS_INT_SLC (63,0) | |
| 1093 | #define PEU_CSR_CORE_STATUS_POSITION 0 | |
| 1094 | #define PEU_CSR_CORE_STATUS_LOW_ADDR_WIDTH 0 | |
| 1095 | #define PEU_CSR_CORE_STATUS_ADDR_RANGE (26,0) | |
| 1096 | #define PEU_CSR_CORE_STATUS_READ_MASK sc_uint<64>("0b0000011111110011111111111111111111111111111111111111111111111111") | |
| 1097 | #define PEU_CSR_CORE_STATUS_READ_ONLY_MASK sc_uint<64>("0b0000011111110011111111111111111111111111111111111111111111111111") | |
| 1098 | #define PEU_CSR_CORE_STATUS_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1099 | #define PEU_CSR_CORE_STATUS_WRITE_ONLY_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1100 | #define PEU_CSR_CORE_STATUS_SET_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1101 | #define PEU_CSR_CORE_STATUS_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1102 | #define PEU_CSR_CORE_STATUS_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1103 | #define PEU_CSR_CORE_STATUS_RMASK sc_uint<64>("0b0000011111110011111111111111111111111111111111111111111111111111") | |
| 1104 | #define PEU_CSR_CORE_STATUS_RESERVED_BIT_MASK sc_uint<64>("0b1111100000001100000000000000000000000000000000000000000000000000") | |
| 1105 | #define PEU_CSR_CORE_STATUS_HW_LD_MASK sc_uint<64>("0b0000011111110011111111111111111111111111111111111111111111111111") | |
| 1106 | #define PEU_CSR_CORE_STATUS_INTERNAL_REG 1 | |
| 1107 | #define PEU_CSR_CORE_STATUS_ZERO_TIME_OMNI 1 | |
| 1108 | #define PEU_CSR_CORE_STATUS_NUM_FIELDS 14 | |
| 1109 | #define PEU_CSR_CORE_STATUS_TX_LOS_STATE_FID 0 | |
| 1110 | #define PEU_CSR_CORE_STATUS_TX_LOS_STATE_SLC (58,56) | |
| 1111 | #define PEU_CSR_CORE_STATUS_TX_LOS_STATE_WIDTH 3 | |
| 1112 | #define PEU_CSR_CORE_STATUS_TX_LOS_STATE_INT_SLC (2,0) | |
| 1113 | #define PEU_CSR_CORE_STATUS_TX_LOS_STATE_POSITION 56 | |
| 1114 | #define PEU_CSR_CORE_STATUS_TX_LOS_STATE_FMASK sc_uint<64>("0b0000011100000000000000000000000000000000000000000000000000000000") | |
| 1115 | #define PEU_CSR_CORE_STATUS_TX_LOS_STATE_HW_LD_MASK sc_uint<64>("0b0000011100000000000000000000000000000000000000000000000000000000") | |
| 1116 | #define PEU_CSR_CORE_STATUS_TX_LOS_STATE_POR_VALUE sc_uint<64>("0b000") | |
| 1117 | #define PEU_CSR_CORE_STATUS_RV_LOS_STATE_FID 1 | |
| 1118 | #define PEU_CSR_CORE_STATUS_RV_LOS_STATE_SLC (55,54) | |
| 1119 | #define PEU_CSR_CORE_STATUS_RV_LOS_STATE_WIDTH 2 | |
| 1120 | #define PEU_CSR_CORE_STATUS_RV_LOS_STATE_INT_SLC (1,0) | |
| 1121 | #define PEU_CSR_CORE_STATUS_RV_LOS_STATE_POSITION 54 | |
| 1122 | #define PEU_CSR_CORE_STATUS_RV_LOS_STATE_FMASK sc_uint<64>("0b0000000011000000000000000000000000000000000000000000000000000000") | |
| 1123 | #define PEU_CSR_CORE_STATUS_RV_LOS_STATE_HW_LD_MASK sc_uint<64>("0b0000000011000000000000000000000000000000000000000000000000000000") | |
| 1124 | #define PEU_CSR_CORE_STATUS_RV_LOS_STATE_POR_VALUE sc_uint<64>("0b00") | |
| 1125 | #define PEU_CSR_CORE_STATUS_INT_FCSM_STATE_FID 2 | |
| 1126 | #define PEU_CSR_CORE_STATUS_INT_FCSM_STATE_SLC (53,52) | |
| 1127 | #define PEU_CSR_CORE_STATUS_INT_FCSM_STATE_WIDTH 2 | |
| 1128 | #define PEU_CSR_CORE_STATUS_INT_FCSM_STATE_INT_SLC (1,0) | |
| 1129 | #define PEU_CSR_CORE_STATUS_INT_FCSM_STATE_POSITION 52 | |
| 1130 | #define PEU_CSR_CORE_STATUS_INT_FCSM_STATE_FMASK sc_uint<64>("0b0000000000110000000000000000000000000000000000000000000000000000") | |
| 1131 | #define PEU_CSR_CORE_STATUS_INT_FCSM_STATE_HW_LD_MASK sc_uint<64>("0b0000000000110000000000000000000000000000000000000000000000000000") | |
| 1132 | #define PEU_CSR_CORE_STATUS_INT_FCSM_STATE_POR_VALUE sc_uint<64>("0b00") | |
| 1133 | #define PEU_CSR_CORE_STATUS_RBUF_NOT_EMPTY_FID 3 | |
| 1134 | #define PEU_CSR_CORE_STATUS_RBUF_NOT_EMPTY_SLC [49] | |
| 1135 | #define PEU_CSR_CORE_STATUS_RBUF_NOT_EMPTY_WIDTH 1 | |
| 1136 | #define PEU_CSR_CORE_STATUS_RBUF_NOT_EMPTY_INT_SLC [0] | |
| 1137 | #define PEU_CSR_CORE_STATUS_RBUF_NOT_EMPTY_POSITION 49 | |
| 1138 | #define PEU_CSR_CORE_STATUS_RBUF_NOT_EMPTY_FMASK sc_uint<64>("0b0000000000000010000000000000000000000000000000000000000000000000") | |
| 1139 | #define PEU_CSR_CORE_STATUS_RBUF_NOT_EMPTY_HW_LD_MASK sc_uint<64>("0b0000000000000010000000000000000000000000000000000000000000000000") | |
| 1140 | #define PEU_CSR_CORE_STATUS_RBUF_NOT_EMPTY_POR_VALUE sc_uint<64>("0b0") | |
| 1141 | #define PEU_CSR_CORE_STATUS_LTSSM_STATE_FID 4 | |
| 1142 | #define PEU_CSR_CORE_STATUS_LTSSM_STATE_SLC (48,44) | |
| 1143 | #define PEU_CSR_CORE_STATUS_LTSSM_STATE_WIDTH 5 | |
| 1144 | #define PEU_CSR_CORE_STATUS_LTSSM_STATE_INT_SLC (4,0) | |
| 1145 | #define PEU_CSR_CORE_STATUS_LTSSM_STATE_POSITION 44 | |
| 1146 | #define PEU_CSR_CORE_STATUS_LTSSM_STATE_FMASK sc_uint<64>("0b0000000000000001111100000000000000000000000000000000000000000000") | |
| 1147 | #define PEU_CSR_CORE_STATUS_LTSSM_STATE_HW_LD_MASK sc_uint<64>("0b0000000000000001111100000000000000000000000000000000000000000000") | |
| 1148 | #define PEU_CSR_CORE_STATUS_LTSSM_STATE_POR_VALUE sc_uint<64>("0b00000") | |
| 1149 | #define PEU_CSR_CORE_STATUS_RCV_POLARITY_REV_FID 5 | |
| 1150 | #define PEU_CSR_CORE_STATUS_RCV_POLARITY_REV_SLC (43,36) | |
| 1151 | #define PEU_CSR_CORE_STATUS_RCV_POLARITY_REV_WIDTH 8 | |
| 1152 | #define PEU_CSR_CORE_STATUS_RCV_POLARITY_REV_INT_SLC (7,0) | |
| 1153 | #define PEU_CSR_CORE_STATUS_RCV_POLARITY_REV_POSITION 36 | |
| 1154 | #define PEU_CSR_CORE_STATUS_RCV_POLARITY_REV_FMASK sc_uint<64>("0b0000000000000000000011111111000000000000000000000000000000000000") | |
| 1155 | #define PEU_CSR_CORE_STATUS_RCV_POLARITY_REV_HW_LD_MASK sc_uint<64>("0b0000000000000000000011111111000000000000000000000000000000000000") | |
| 1156 | #define PEU_CSR_CORE_STATUS_RCV_POLARITY_REV_POR_VALUE sc_uint<64>("0b00000000") | |
| 1157 | #define PEU_CSR_CORE_STATUS_RCV_FTS_NUM_FID 6 | |
| 1158 | #define PEU_CSR_CORE_STATUS_RCV_FTS_NUM_SLC (35,28) | |
| 1159 | #define PEU_CSR_CORE_STATUS_RCV_FTS_NUM_WIDTH 8 | |
| 1160 | #define PEU_CSR_CORE_STATUS_RCV_FTS_NUM_INT_SLC (7,0) | |
| 1161 | #define PEU_CSR_CORE_STATUS_RCV_FTS_NUM_POSITION 28 | |
| 1162 | #define PEU_CSR_CORE_STATUS_RCV_FTS_NUM_FMASK sc_uint<64>("0b0000000000000000000000000000111111110000000000000000000000000000") | |
| 1163 | #define PEU_CSR_CORE_STATUS_RCV_FTS_NUM_HW_LD_MASK sc_uint<64>("0b0000000000000000000000000000111111110000000000000000000000000000") | |
| 1164 | #define PEU_CSR_CORE_STATUS_RCV_FTS_NUM_POR_VALUE sc_uint<64>("0b00000000") | |
| 1165 | #define PEU_CSR_CORE_STATUS_RCV_LINK_NUM_FID 7 | |
| 1166 | #define PEU_CSR_CORE_STATUS_RCV_LINK_NUM_SLC (27,20) | |
| 1167 | #define PEU_CSR_CORE_STATUS_RCV_LINK_NUM_WIDTH 8 | |
| 1168 | #define PEU_CSR_CORE_STATUS_RCV_LINK_NUM_INT_SLC (7,0) | |
| 1169 | #define PEU_CSR_CORE_STATUS_RCV_LINK_NUM_POSITION 20 | |
| 1170 | #define PEU_CSR_CORE_STATUS_RCV_LINK_NUM_FMASK sc_uint<64>("0b0000000000000000000000000000000000001111111100000000000000000000") | |
| 1171 | #define PEU_CSR_CORE_STATUS_RCV_LINK_NUM_HW_LD_MASK sc_uint<64>("0b0000000000000000000000000000000000001111111100000000000000000000") | |
| 1172 | #define PEU_CSR_CORE_STATUS_RCV_LINK_NUM_POR_VALUE sc_uint<64>("0b00000000") | |
| 1173 | #define PEU_CSR_CORE_STATUS_PCS_LOCK_STS_FID 8 | |
| 1174 | #define PEU_CSR_CORE_STATUS_PCS_LOCK_STS_SLC (19,12) | |
| 1175 | #define PEU_CSR_CORE_STATUS_PCS_LOCK_STS_WIDTH 8 | |
| 1176 | #define PEU_CSR_CORE_STATUS_PCS_LOCK_STS_INT_SLC (7,0) | |
| 1177 | #define PEU_CSR_CORE_STATUS_PCS_LOCK_STS_POSITION 12 | |
| 1178 | #define PEU_CSR_CORE_STATUS_PCS_LOCK_STS_FMASK sc_uint<64>("0b0000000000000000000000000000000000000000000011111111000000000000") | |
| 1179 | #define PEU_CSR_CORE_STATUS_PCS_LOCK_STS_HW_LD_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000011111111000000000000") | |
| 1180 | #define PEU_CSR_CORE_STATUS_PCS_LOCK_STS_POR_VALUE sc_uint<64>("0b00000000") | |
| 1181 | #define PEU_CSR_CORE_STATUS_RCVR_DETECT_STS_FID 9 | |
| 1182 | #define PEU_CSR_CORE_STATUS_RCVR_DETECT_STS_SLC (11,4) | |
| 1183 | #define PEU_CSR_CORE_STATUS_RCVR_DETECT_STS_WIDTH 8 | |
| 1184 | #define PEU_CSR_CORE_STATUS_RCVR_DETECT_STS_INT_SLC (7,0) | |
| 1185 | #define PEU_CSR_CORE_STATUS_RCVR_DETECT_STS_POSITION 4 | |
| 1186 | #define PEU_CSR_CORE_STATUS_RCVR_DETECT_STS_FMASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000111111110000") | |
| 1187 | #define PEU_CSR_CORE_STATUS_RCVR_DETECT_STS_HW_LD_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000111111110000") | |
| 1188 | #define PEU_CSR_CORE_STATUS_RCVR_DETECT_STS_POR_VALUE sc_uint<64>("0b00000000") | |
| 1189 | #define PEU_CSR_CORE_STATUS_PCS_LANE_REV_FID 10 | |
| 1190 | #define PEU_CSR_CORE_STATUS_PCS_LANE_REV_SLC [3] | |
| 1191 | #define PEU_CSR_CORE_STATUS_PCS_LANE_REV_WIDTH 1 | |
| 1192 | #define PEU_CSR_CORE_STATUS_PCS_LANE_REV_INT_SLC [0] | |
| 1193 | #define PEU_CSR_CORE_STATUS_PCS_LANE_REV_POSITION 3 | |
| 1194 | #define PEU_CSR_CORE_STATUS_PCS_LANE_REV_FMASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000001000") | |
| 1195 | #define PEU_CSR_CORE_STATUS_PCS_LANE_REV_HW_LD_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000001000") | |
| 1196 | #define PEU_CSR_CORE_STATUS_PCS_LANE_REV_POR_VALUE sc_uint<64>("0b0") | |
| 1197 | #define PEU_CSR_CORE_STATUS_PCS_ALIGN_STS_FID 11 | |
| 1198 | #define PEU_CSR_CORE_STATUS_PCS_ALIGN_STS_SLC [2] | |
| 1199 | #define PEU_CSR_CORE_STATUS_PCS_ALIGN_STS_WIDTH 1 | |
| 1200 | #define PEU_CSR_CORE_STATUS_PCS_ALIGN_STS_INT_SLC [0] | |
| 1201 | #define PEU_CSR_CORE_STATUS_PCS_ALIGN_STS_POSITION 2 | |
| 1202 | #define PEU_CSR_CORE_STATUS_PCS_ALIGN_STS_FMASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000100") | |
| 1203 | #define PEU_CSR_CORE_STATUS_PCS_ALIGN_STS_HW_LD_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000100") | |
| 1204 | #define PEU_CSR_CORE_STATUS_PCS_ALIGN_STS_POR_VALUE sc_uint<64>("0b0") | |
| 1205 | #define PEU_CSR_CORE_STATUS_SDS_READY_1_FID 12 | |
| 1206 | #define PEU_CSR_CORE_STATUS_SDS_READY_1_SLC [1] | |
| 1207 | #define PEU_CSR_CORE_STATUS_SDS_READY_1_WIDTH 1 | |
| 1208 | #define PEU_CSR_CORE_STATUS_SDS_READY_1_INT_SLC [0] | |
| 1209 | #define PEU_CSR_CORE_STATUS_SDS_READY_1_POSITION 1 | |
| 1210 | #define PEU_CSR_CORE_STATUS_SDS_READY_1_FMASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000010") | |
| 1211 | #define PEU_CSR_CORE_STATUS_SDS_READY_1_HW_LD_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000010") | |
| 1212 | #define PEU_CSR_CORE_STATUS_SDS_READY_1_POR_VALUE sc_uint<64>("0b0") | |
| 1213 | #define PEU_CSR_CORE_STATUS_SDS_READY_0_FID 13 | |
| 1214 | #define PEU_CSR_CORE_STATUS_SDS_READY_0_SLC [0] | |
| 1215 | #define PEU_CSR_CORE_STATUS_SDS_READY_0_WIDTH 1 | |
| 1216 | #define PEU_CSR_CORE_STATUS_SDS_READY_0_INT_SLC [0] | |
| 1217 | #define PEU_CSR_CORE_STATUS_SDS_READY_0_POSITION 0 | |
| 1218 | #define PEU_CSR_CORE_STATUS_SDS_READY_0_FMASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000001") | |
| 1219 | #define PEU_CSR_CORE_STATUS_SDS_READY_0_HW_LD_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000001") | |
| 1220 | #define PEU_CSR_CORE_STATUS_SDS_READY_0_POR_VALUE sc_uint<64>("0b0") | |
| 1221 | ||
| 1222 | #define PEU_CSR_MACL_PCS_RESET_FMASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000001") | |
| 1223 | ||
| 1224 | #define ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_ADDR sc_uint<64>("0b0000000000000000000000000000000000000000000011001010001000000100") | |
| 1225 | #define ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_READ_MASK sc_uint<64>("0b0000000000000000000000001111000000000000000000000000000011110000") | |
| 1226 | #define ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_WRITE_MASK sc_uint<64>("0b0000000000000000000000001111000000000000000000000000000011110000") | |
| 1227 | //#define ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_WRITE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1228 | #define ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_CLEAR_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1229 | #define ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SET_MASK sc_uint<64>("0b0000000000000000000000001111000000000000000000000000000011110000") | |
| 1230 | #define ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_TOGGLE_MASK sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1231 | #define ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_POR_VALUE sc_uint<64>("0b0000000000000000000000000000000000000000000000000000000000000000") | |
| 1232 | ||
| 1233 | ||
| 1234 | ||
| 1235 | #define CHC 59,52 | |
| 1236 | #define CDC 51,40 | |
| 1237 | #define NHC 39,32 | |
| 1238 | #define NDC 31,20 | |
| 1239 | #define PHC 19,12 | |
| 1240 | #define PDC 11,0 | |
| 1241 | #define CHI 62 | |
| 1242 | #define NHI 61 | |
| 1243 | #define PHI 60 | |
| 1244 | ||
| 1245 | #endif // INC_peu_csr_defines_hpp__ |