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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / model / pcie / peu / peu_csr_omni.cpp
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: peu_csr_omni.cpp
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35
36#include "peu_csr_omni.h"
37#include "pcie_common/logger.hpp"
38
39#ifndef __EDG__
40
41namespace pcie {
42
43 void peu_csr_omni::init(void) {
44
45 sc_uint<64> data_reg;
46 wait (10, SC_PS);
47
48 data_reg = csr_port.read_csr(PEU_CSR_A_ACKNAK_THRESH_HW_ADDR);
49 acknak_thresh_csrbus_read_data.write(data_reg);
50
51 data_reg = csr_port.read_csr(ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_ADDR);
52 ilu_err_rw1s_alias_csrbus_read_data.write(data_reg);
53
54 data_reg = csr_port.read_csr(PEU_CSR_A_TLU_CTL_HW_ADDR);
55 tlu_ctl_csrbus_read_data.write(data_reg);
56
57 data_reg = csr_port.read_csr(PEU_CSR_A_TLU_STS_HW_ADDR);
58 tlu_sts_csrbus_read_data.write(data_reg);
59
60 data_reg = csr_port.read_csr(PEU_CSR_A_TRN_OFF_HW_ADDR);
61 trn_off_csrbus_read_data.write(data_reg);
62
63 data_reg = csr_port.read_csr(PEU_CSR_A_TLU_ICI_HW_ADDR);
64 tlu_ici_csrbus_read_data.write(data_reg);
65
66 data_reg = csr_port.read_csr(PEU_CSR_A_TLU_DIAG_HW_ADDR);
67 tlu_diag_csrbus_read_data.write(data_reg);
68
69 data_reg = csr_port.read_csr(PEU_CSR_A_TLU_ECC_HW_ADDR);
70 tlu_ecc_csrbus_read_data.write(data_reg);
71
72 data_reg = csr_port.read_csr(PEU_CSR_A_TLU_ECL_HW_ADDR);
73 tlu_ecl_csrbus_read_data.write(data_reg);
74
75 data_reg = csr_port.read_csr(PEU_CSR_A_TLU_ERB_HW_ADDR);
76 tlu_erb_csrbus_read_data.write(data_reg);
77
78 data_reg = csr_port.read_csr(PEU_CSR_A_TLU_ICA_HW_ADDR);
79 tlu_ica_csrbus_read_data.write(data_reg);
80
81 data_reg = csr_port.read_csr(PEU_CSR_A_TLU_ICR_HW_ADDR);
82 tlu_icr_csrbus_read_data.write(data_reg);
83
84 data_reg = csr_port.read_csr(PEU_CSR_A_OE_LOG_HW_ADDR);
85 oe_log_csrbus_read_data.write(data_reg);
86
87 data_reg = csr_port.read_csr(PEU_CSR_A_OE_INT_EN_HW_ADDR);
88 oe_int_en_csrbus_read_data.write(data_reg);
89
90 data_reg = csr_port.read_csr(PEU_CSR_A_OE_EN_ERR_HW_ADDR);
91 oe_en_err_csrbus_read_data.write(data_reg);
92
93 data_reg = csr_port.read_csr(PEU_CSR_A_OE_ERR_RW1C_ALIAS_HW_ADDR);
94 oe_err_rw1c_alias_csrbus_read_data.write(data_reg);
95
96 data_reg = csr_port.read_csr(PEU_CSR_A_OE_ERR_RW1S_ALIAS_HW_ADDR);
97 oe_err_rw1s_alias_csrbus_read_data.write(data_reg);
98
99 data_reg = csr_port.read_csr(PEU_CSR_A_ROE_HDR1_HW_ADDR);
100 roe_hdr1_csrbus_read_data.write(data_reg);
101
102 data_reg = csr_port.read_csr(PEU_CSR_A_ROE_HDR2_HW_ADDR);
103 roe_hdr2_csrbus_read_data.write(data_reg);
104
105 data_reg = csr_port.read_csr(PEU_CSR_A_TOE_HDR1_HW_ADDR);
106 toe_hdr1_csrbus_read_data.write(data_reg);
107
108 data_reg = csr_port.read_csr(PEU_CSR_A_TOE_HDR2_HW_ADDR);
109 toe_hdr2_csrbus_read_data.write(data_reg);
110
111 data_reg = csr_port.read_csr(PEU_CSR_A_TLU_PRFC_HW_ADDR);
112 tlu_prfc_csrbus_read_data.write(data_reg);
113
114 data_reg = csr_port.read_csr(PEU_CSR_A_TLU_PRF0_HW_ADDR);
115 tlu_prf0_csrbus_read_data.write(data_reg);
116
117 data_reg = csr_port.read_csr(PEU_CSR_A_TLU_PRF1_HW_ADDR);
118 tlu_prf1_csrbus_read_data.write(data_reg);
119
120 data_reg = csr_port.read_csr(PEU_CSR_A_TLU_PRF2_HW_ADDR);
121 tlu_prf2_csrbus_read_data.write(data_reg);
122
123 data_reg = csr_port.read_csr(PEU_CSR_A_TLU_DBG_SEL_A_HW_ADDR);
124 tlu_dbg_sel_a_csrbus_read_data.write(data_reg);
125
126 data_reg = csr_port.read_csr(PEU_CSR_A_TLU_DBG_SEL_B_HW_ADDR);
127 tlu_dbg_sel_b_csrbus_read_data.write(data_reg);
128
129 data_reg = csr_port.read_csr(PEU_CSR_A_DEV_CAP_HW_ADDR);
130 dev_cap_csrbus_read_data.write(data_reg);
131
132 data_reg = csr_port.read_csr(PEU_CSR_A_DEV_CTL_HW_ADDR);
133 dev_ctl_csrbus_read_data.write(data_reg);
134
135 data_reg = csr_port.read_csr(PEU_CSR_A_DEV_STS_HW_ADDR);
136 dev_sts_csrbus_read_data.write(data_reg);
137
138 data_reg = csr_port.read_csr(PEU_CSR_A_LNK_CAP_HW_ADDR);
139 lnk_cap_csrbus_read_data.write(data_reg);
140
141 data_reg = csr_port.read_csr(PEU_CSR_A_LNK_CTL_HW_ADDR);
142 lnk_ctl_csrbus_read_data.write(data_reg);
143
144 data_reg = csr_port.read_csr(PEU_CSR_A_LNK_STS_HW_ADDR);
145 lnk_sts_csrbus_read_data.write(data_reg);
146
147 data_reg = csr_port.read_csr(PEU_CSR_A_SLT_CAP_HW_ADDR);
148 slt_cap_csrbus_read_data.write(data_reg);
149
150 data_reg = csr_port.read_csr(PEU_CSR_A_UE_LOG_HW_ADDR);
151 ue_log_csrbus_read_data.write(data_reg);
152
153 data_reg = csr_port.read_csr(PEU_CSR_A_UE_INT_EN_HW_ADDR);
154 ue_int_en_csrbus_read_data.write(data_reg);
155
156 data_reg = csr_port.read_csr(PEU_CSR_A_UE_EN_ERR_HW_ADDR);
157 ue_en_err_csrbus_read_data.write(data_reg);
158
159 data_reg = csr_port.read_csr(PEU_CSR_A_UE_ERR_RW1C_ALIAS_HW_ADDR);
160 ue_err_rw1c_alias_csrbus_read_data.write(data_reg);
161
162 data_reg = csr_port.read_csr(PEU_CSR_A_UE_ERR_RW1S_ALIAS_HW_ADDR);
163 ue_err_rw1s_alias_csrbus_read_data.write(data_reg);
164
165 data_reg = csr_port.read_csr(PEU_CSR_A_RUE_HDR1_HW_ADDR);
166 rue_hdr1_csrbus_read_data.write(data_reg);
167
168 data_reg = csr_port.read_csr(PEU_CSR_A_RUE_HDR2_HW_ADDR);
169 rue_hdr2_csrbus_read_data.write(data_reg);
170
171 data_reg = csr_port.read_csr(PEU_CSR_A_TUE_HDR1_HW_ADDR);
172 tue_hdr1_csrbus_read_data.write(data_reg);
173
174 data_reg = csr_port.read_csr(PEU_CSR_A_TUE_HDR2_HW_ADDR);
175 tue_hdr2_csrbus_read_data.write(data_reg);
176
177 data_reg = csr_port.read_csr(PEU_CSR_A_CE_LOG_HW_ADDR);
178 ce_log_csrbus_read_data.write(data_reg);
179
180 data_reg = csr_port.read_csr(PEU_CSR_A_CE_INT_EN_HW_ADDR);
181 ce_int_en_csrbus_read_data.write(data_reg);
182
183 data_reg = csr_port.read_csr(PEU_CSR_A_CE_EN_ERR_HW_ADDR);
184 ce_en_err_csrbus_read_data.write(data_reg);
185
186 data_reg = csr_port.read_csr(PEU_CSR_A_CE_ERR_RW1C_ALIAS_HW_ADDR);
187 ce_err_rw1c_alias_csrbus_read_data.write(data_reg);
188
189 data_reg = csr_port.read_csr(PEU_CSR_A_CE_ERR_RW1S_ALIAS_HW_ADDR);
190 ce_err_rw1s_alias_csrbus_read_data.write(data_reg);
191
192 data_reg = csr_port.read_csr(PEU_CSR_A_PEU_DLPL_SERDES_REV_HW_ADDR);
193 peu_dlpl_serdes_rev_csrbus_read_data.write(data_reg);
194
195 data_reg = csr_port.read_csr(PEU_CSR_A_ACKNAK_TIMER_HW_ADDR);
196 acknak_timer_csrbus_read_data.write(data_reg);
197
198 data_reg = csr_port.read_csr(PEU_CSR_A_REPLAY_TIM_THRESH_HW_ADDR);
199 replay_tim_thresh_csrbus_read_data.write(data_reg);
200
201 data_reg = csr_port.read_csr(PEU_CSR_A_REPLAY_TIMER_HW_ADDR);
202 replay_timer_csrbus_read_data.write(data_reg);
203
204 data_reg = csr_port.read_csr(PEU_CSR_A_VEN_DLLP_MSG_HW_ADDR);
205 ven_dllp_msg_csrbus_read_data.write(data_reg);
206
207 data_reg = csr_port.read_csr(PEU_CSR_A_FORCE_LTSSM_HW_ADDR);
208 force_ltssm_csrbus_read_data.write(data_reg);
209
210 data_reg = csr_port.read_csr(PEU_CSR_A_LINK_CFG_HW_ADDR);
211 link_cfg_csrbus_read_data.write(data_reg);
212
213 data_reg = csr_port.read_csr(PEU_CSR_A_LINK_CTL_HW_ADDR);
214 link_ctl_csrbus_read_data.write(data_reg);
215
216 data_reg = csr_port.read_csr(PEU_CSR_A_LANE_SKEW_HW_ADDR);
217 lane_skew_csrbus_read_data.write(data_reg);
218
219 data_reg = csr_port.read_csr(PEU_CSR_A_SYMBOL_NUM_HW_ADDR);
220 symbol_num_csrbus_read_data.write(data_reg);
221
222 data_reg = csr_port.read_csr(PEU_CSR_A_SYMBOL_TIMER_HW_ADDR);
223 symbol_timer_csrbus_read_data.write(data_reg);
224
225 data_reg = csr_port.read_csr(PEU_CSR_A_CORE_STATUS_HW_ADDR);
226 core_status_csrbus_read_data.write(data_reg);
227
228 data_reg = csr_port.read_csr(PEU_CSR_A_EVENT_ERR_LOG_EN_HW_ADDR);
229 event_err_log_en_csrbus_read_data.write(data_reg);
230
231 data_reg = csr_port.read_csr(PEU_CSR_A_EVENT_ERR_INT_EN_HW_ADDR);
232 event_err_int_en_csrbus_read_data.write(data_reg);
233
234 data_reg = csr_port.read_csr(PEU_CSR_A_EVENT_ERR_INT_STS_HW_ADDR);
235 event_err_int_sts_csrbus_read_data.write(data_reg);
236
237 data_reg = csr_port.read_csr(PEU_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_HW_ADDR);
238 event_err_sts_clr_rw1c_alias_csrbus_read_data.write(data_reg);
239
240 data_reg = csr_port.read_csr(PEU_CSR_A_EVENT_ERR_STS_CLR_RW1S_ALIAS_HW_ADDR);
241 event_err_sts_clr_rw1s_alias_csrbus_read_data.write(data_reg);
242
243 data_reg = csr_port.read_csr(PEU_CSR_A_LNK_BIT_ERR_CNT_1_HW_ADDR);
244 lnk_bit_err_cnt_1_csrbus_read_data.write(data_reg);
245
246 data_reg = csr_port.read_csr(PEU_CSR_A_LNK_BIT_ERR_CNT_2_HW_ADDR);
247 lnk_bit_err_cnt_2_csrbus_read_data.write(data_reg);
248
249 data_reg = csr_port.read_csr(PEU_CSR_A_SERDES_PLL_HW_ADDR);
250 serdes_pll_csrbus_read_data.write(data_reg);
251
252 data_reg = csr_port.read_csr(PEU_CSR_A_SERDES_RECEIVER_LANE_CTL_HW_ADDR);
253 serdes_receiver_lane_ctl_csrbus_read_data.write(data_reg);
254
255 data_reg = csr_port.read_csr(PEU_CSR_A_SERDES_RECEIVER_LANE_STATUS_HW_ADDR);
256 serdes_receiver_lane_status_csrbus_read_data.write(data_reg);
257
258 data_reg = csr_port.read_csr(PEU_CSR_A_SERDES_XMITTER_LANE_CTL_HW_ADDR);
259 serdes_xmitter_lane_ctl_csrbus_read_data.write(data_reg);
260
261 data_reg = csr_port.read_csr(PEU_CSR_A_SERDES_XMITTER_LANE_STATUS_HW_ADDR);
262 serdes_xmitter_lane_status_csrbus_read_data.write(data_reg);
263
264 data_reg = csr_port.read_csr(PEU_CSR_A_SERDES_MACRO_TEST_CFG_HW_ADDR);
265 serdes_macro_test_cfg_csrbus_read_data.write(data_reg);
266
267 csr_port.set_notify_event(PEU_CSR_A_ACKNAK_THRESH_HW_ADDR, &acknak_thresh_ev);
268 csr_port.set_notify_event(PEU_CSR_A_TLU_CTL_HW_ADDR, &tlu_ctl_ev);
269 csr_port.set_notify_event(ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_ADDR, &ilu_err_rw1s_alias_ev);
270 csr_port.set_notify_event(PEU_CSR_A_TLU_STS_HW_ADDR, &tlu_sts_ev);
271 csr_port.set_notify_event(PEU_CSR_A_TRN_OFF_HW_ADDR, &trn_off_ev);
272 csr_port.set_notify_event(PEU_CSR_A_TLU_ICI_HW_ADDR, &tlu_ici_ev);
273 csr_port.set_notify_event(PEU_CSR_A_TLU_DIAG_HW_ADDR, &tlu_diag_ev);
274 csr_port.set_notify_event(PEU_CSR_A_TLU_ECC_HW_ADDR, &tlu_ecc_ev);
275 csr_port.set_notify_event(PEU_CSR_A_TLU_ECL_HW_ADDR, &tlu_ecl_ev);
276 csr_port.set_notify_event(PEU_CSR_A_TLU_ERB_HW_ADDR, &tlu_erb_ev);
277 csr_port.set_notify_event(PEU_CSR_A_TLU_ICA_HW_ADDR, &tlu_ica_ev);
278 csr_port.set_notify_event(PEU_CSR_A_TLU_ICR_HW_ADDR, &tlu_icr_ev);
279 csr_port.set_notify_event(PEU_CSR_A_OE_LOG_HW_ADDR, &oe_log_ev);
280 csr_port.set_notify_event(PEU_CSR_A_OE_INT_EN_HW_ADDR, &oe_int_en_ev);
281 csr_port.set_notify_event(PEU_CSR_A_OE_EN_ERR_HW_ADDR, &oe_en_err_ev);
282 csr_port.set_notify_event(PEU_CSR_A_OE_ERR_RW1C_ALIAS_HW_ADDR, &oe_err_rw1c_alias_ev);
283 csr_port.set_notify_event(PEU_CSR_A_OE_ERR_RW1S_ALIAS_HW_ADDR, &oe_err_rw1s_alias_ev);
284 csr_port.set_notify_event(PEU_CSR_A_ROE_HDR1_HW_ADDR, &roe_hdr1_ev);
285 csr_port.set_notify_event(PEU_CSR_A_ROE_HDR2_HW_ADDR, &roe_hdr2_ev);
286 csr_port.set_notify_event(PEU_CSR_A_TOE_HDR1_HW_ADDR, &toe_hdr1_ev);
287 csr_port.set_notify_event(PEU_CSR_A_TOE_HDR2_HW_ADDR, &toe_hdr2_ev);
288 csr_port.set_notify_event(PEU_CSR_A_TLU_PRFC_HW_ADDR, &tlu_prfc_ev);
289 csr_port.set_notify_event(PEU_CSR_A_TLU_PRF0_HW_ADDR, &tlu_prf0_ev);
290 csr_port.set_notify_event(PEU_CSR_A_TLU_PRF1_HW_ADDR, &tlu_prf1_ev);
291 csr_port.set_notify_event(PEU_CSR_A_TLU_PRF2_HW_ADDR, &tlu_prf2_ev);
292 csr_port.set_notify_event(PEU_CSR_A_TLU_DBG_SEL_A_HW_ADDR, &tlu_dbg_sel_a_ev);
293 csr_port.set_notify_event(PEU_CSR_A_TLU_DBG_SEL_B_HW_ADDR, &tlu_dbg_sel_b_ev);
294 csr_port.set_notify_event(PEU_CSR_A_DEV_CAP_HW_ADDR, &dev_cap_ev);
295 csr_port.set_notify_event(PEU_CSR_A_DEV_CTL_HW_ADDR, &dev_ctl_ev);
296 csr_port.set_notify_event(PEU_CSR_A_DEV_STS_HW_ADDR, &dev_sts_ev);
297 csr_port.set_notify_event(PEU_CSR_A_LNK_CAP_HW_ADDR, &lnk_cap_ev);
298 csr_port.set_notify_event(PEU_CSR_A_LNK_CTL_HW_ADDR, &lnk_ctl_ev);
299 csr_port.set_notify_event(PEU_CSR_A_LNK_STS_HW_ADDR, &lnk_sts_ev);
300 csr_port.set_notify_event(PEU_CSR_A_SLT_CAP_HW_ADDR, &slt_cap_ev);
301 csr_port.set_notify_event(PEU_CSR_A_UE_LOG_HW_ADDR, &ue_log_ev);
302 csr_port.set_notify_event(PEU_CSR_A_UE_INT_EN_HW_ADDR, &ue_int_en_ev);
303 csr_port.set_notify_event(PEU_CSR_A_UE_EN_ERR_HW_ADDR, &ue_en_err_ev);
304 csr_port.set_notify_event(PEU_CSR_A_UE_ERR_RW1C_ALIAS_HW_ADDR, &ue_err_rw1c_alias_ev);
305 csr_port.set_notify_event(PEU_CSR_A_UE_ERR_RW1S_ALIAS_HW_ADDR, &ue_err_rw1s_alias_ev);
306 csr_port.set_notify_event(PEU_CSR_A_RUE_HDR1_HW_ADDR, &rue_hdr1_ev);
307 csr_port.set_notify_event(PEU_CSR_A_RUE_HDR2_HW_ADDR, &rue_hdr2_ev);
308 csr_port.set_notify_event(PEU_CSR_A_TUE_HDR1_HW_ADDR, &tue_hdr1_ev);
309 csr_port.set_notify_event(PEU_CSR_A_TUE_HDR2_HW_ADDR, &tue_hdr2_ev);
310 csr_port.set_notify_event(PEU_CSR_A_CE_LOG_HW_ADDR, &ce_log_ev);
311 csr_port.set_notify_event(PEU_CSR_A_CE_INT_EN_HW_ADDR, &ce_int_en_ev);
312 csr_port.set_notify_event(PEU_CSR_A_CE_EN_ERR_HW_ADDR, &ce_en_err_ev);
313 csr_port.set_notify_event(PEU_CSR_A_CE_ERR_RW1C_ALIAS_HW_ADDR, &ce_err_rw1c_alias_ev);
314 csr_port.set_notify_event(PEU_CSR_A_CE_ERR_RW1S_ALIAS_HW_ADDR, &ce_err_rw1s_alias_ev);
315 csr_port.set_notify_event(PEU_CSR_A_PEU_DLPL_SERDES_REV_HW_ADDR, &peu_dlpl_serdes_rev_ev);
316 csr_port.set_notify_event(PEU_CSR_A_ACKNAK_THRESH_HW_ADDR, &acknak_thresh_ev);
317 csr_port.set_notify_event(PEU_CSR_A_ACKNAK_TIMER_HW_ADDR, &acknak_timer_ev);
318 csr_port.set_notify_event(PEU_CSR_A_REPLAY_TIM_THRESH_HW_ADDR, &replay_tim_thresh_ev);
319 csr_port.set_notify_event(PEU_CSR_A_REPLAY_TIMER_HW_ADDR, &replay_timer_ev);
320 csr_port.set_notify_event(PEU_CSR_A_VEN_DLLP_MSG_HW_ADDR, &ven_dllp_msg_ev);
321 csr_port.set_notify_event(PEU_CSR_A_FORCE_LTSSM_HW_ADDR, &force_ltssm_ev);
322 csr_port.set_notify_event(PEU_CSR_A_LINK_CFG_HW_ADDR, &link_cfg_ev);
323 csr_port.set_notify_event(PEU_CSR_A_LINK_CTL_HW_ADDR, &link_ctl_ev);
324 csr_port.set_notify_event(PEU_CSR_A_LANE_SKEW_HW_ADDR, &lane_skew_ev);
325 csr_port.set_notify_event(PEU_CSR_A_SYMBOL_NUM_HW_ADDR, &symbol_num_ev);
326 csr_port.set_notify_event(PEU_CSR_A_SYMBOL_TIMER_HW_ADDR, &symbol_timer_ev);
327 csr_port.set_notify_event(PEU_CSR_A_CORE_STATUS_HW_ADDR, &core_status_ev);
328
329 csr_port.set_notify_event(PEU_CSR_A_EVENT_ERR_LOG_EN_HW_ADDR, &event_err_log_en_ev);
330 csr_port.set_notify_event(PEU_CSR_A_EVENT_ERR_INT_EN_HW_ADDR, &event_err_int_en_ev);
331 csr_port.set_notify_event(PEU_CSR_A_EVENT_ERR_INT_STS_HW_ADDR, &event_err_int_sts_ev);
332 csr_port.set_notify_event(PEU_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_HW_ADDR, &event_err_sts_clr_rw1c_alias_ev);
333 csr_port.set_notify_event(PEU_CSR_A_EVENT_ERR_STS_CLR_RW1S_ALIAS_HW_ADDR, &event_err_sts_clr_rw1s_alias_ev);
334 csr_port.set_notify_event(PEU_CSR_A_LNK_BIT_ERR_CNT_1_HW_ADDR, &lnk_bit_err_cnt_1_ev);
335 csr_port.set_notify_event(PEU_CSR_A_LNK_BIT_ERR_CNT_2_HW_ADDR, &lnk_bit_err_cnt_2_ev);
336 csr_port.set_notify_event(PEU_CSR_A_SERDES_PLL_HW_ADDR, &serdes_pll_ev);
337 csr_port.set_notify_event(PEU_CSR_A_SERDES_RECEIVER_LANE_CTL_HW_ADDR, &serdes_receiver_lane_ctl_ev);
338 csr_port.set_notify_event(PEU_CSR_A_SERDES_RECEIVER_LANE_STATUS_HW_ADDR, &serdes_receiver_lane_status_ev);
339 csr_port.set_notify_event(PEU_CSR_A_SERDES_XMITTER_LANE_CTL_HW_ADDR, &serdes_xmitter_lane_ctl_ev);
340 csr_port.set_notify_event(PEU_CSR_A_SERDES_XMITTER_LANE_STATUS_HW_ADDR, &serdes_xmitter_lane_status_ev);
341 csr_port.set_notify_event(PEU_CSR_A_SERDES_MACRO_TEST_CFG_HW_ADDR, &serdes_macro_test_cfg_ev);
342
343 }
344
345 void peu_csr_omni::read_acknak_thresh(void) {
346
347 sc_uint<64> acknak_thresh_csrbus_read_data_reg;
348
349 for ( ; ; ) {
350 csr_port_sem.wait();
351 LOG_DEBUG << "READ EVENT : Reading the CSR acknak_thresh ";
352 acknak_thresh_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_ACKNAK_THRESH_HW_ADDR);
353 csr_port_sem.post();
354 acknak_thresh_csrbus_read_data.write(acknak_thresh_csrbus_read_data_reg);
355 wait (acknak_thresh_ev);
356 }
357
358 }
359
360 void peu_csr_omni::write_acknak_thresh(void) {
361
362 while (true) {
363 wait (acknak_thresh_csrbus_omni_data.value_changed_event());
364 LOG_DEBUG << "WRITE EVENT : Writing the CSR acknak_thresh";
365 acknak_thresh_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_ACKNAK_THRESH_HW_ADDR, acknak_thresh_csrbus_omni_data.read().to_uint64());
366 }
367 }
368
369 void peu_csr_omni::read_tlu_ctl(void) {
370
371 sc_uint<64> tlu_ctl_csrbus_read_data_reg;
372
373 for ( ; ; ) {
374 csr_port_sem.wait();
375 LOG_DEBUG << "READ EVENT : Reading the CSR tlu_ctl ";
376 tlu_ctl_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TLU_CTL_HW_ADDR);
377 csr_port_sem.post();
378 tlu_ctl_csrbus_read_data.write(tlu_ctl_csrbus_read_data_reg);
379 wait (tlu_ctl_ev);
380 }
381
382 }
383
384 void peu_csr_omni::write_tlu_ctl(void) {
385
386 while (true) {
387 wait (tlu_ctl_csrbus_omni_data.value_changed_event());
388 LOG_DEBUG << "WRITE EVENT : Writing the CSR tlu_ctl";
389 tlu_ctl_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TLU_CTL_HW_ADDR, tlu_ctl_csrbus_omni_data.read().to_uint64());
390 }
391 }
392
393 void peu_csr_omni::read_ilu_err_rw1s_alias(void) {
394
395 sc_uint<64> ilu_err_rw1s_alias_csrbus_read_data_reg;
396
397 for ( ; ; ) {
398 csr_port_sem.wait();
399 LOG_DEBUG << "READ EVENT : Reading the CSR ilu_err_rw1s_alias ";
400 ilu_err_rw1s_alias_csrbus_read_data_reg = csr_port.read_csr(ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_ADDR);
401 csr_port_sem.post();
402 ilu_err_rw1s_alias_csrbus_read_data.write(ilu_err_rw1s_alias_csrbus_read_data_reg);
403 wait (ilu_err_rw1s_alias_ev);
404 }
405
406 }
407
408 void peu_csr_omni::write_ilu_err_rw1s_alias(void) {
409
410 while (true) {
411 wait (ilu_err_rw1s_alias_csrbus_omni_data.value_changed_event());
412 LOG_DEBUG << "WRITE EVENT : Writing the CSR ilu_err_rw1s_alias";
413 ilu_err_rw1s_alias_csrbus_read_data = csr_port.write_csr(ILU_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_ADDR, ilu_err_rw1s_alias_csrbus_omni_data.read().to_uint64());
414 }
415 }
416
417 void peu_csr_omni::read_tlu_sts(void) {
418
419 sc_uint<64> tlu_sts_csrbus_read_data_reg;
420
421 for ( ; ; ) {
422
423 csr_port_sem.wait();
424 LOG_DEBUG << "READ EVENT : Reading the CSR tlu_sts ";
425 tlu_sts_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TLU_STS_HW_ADDR);
426 csr_port_sem.post();
427 tlu_sts_csrbus_read_data.write(tlu_sts_csrbus_read_data_reg);
428 wait (tlu_sts_ev);
429 }
430
431 }
432
433 void peu_csr_omni::write_tlu_sts(void) {
434
435 while (true) {
436 wait (tlu_sts_csrbus_omni_data.value_changed_event());
437 LOG_DEBUG << "WRITE EVENT : Writing the CSR tlu_sts";
438 tlu_sts_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TLU_STS_HW_ADDR, tlu_sts_csrbus_omni_data.read().to_uint64());
439 }
440 }
441
442 void peu_csr_omni::read_trn_off(void) {
443
444 sc_uint<64> trn_off_csrbus_read_data_reg;
445
446 for ( ; ; ) {
447
448 csr_port_sem.wait();
449 LOG_DEBUG << "READ EVENT : Reading the CSR trn_off ";
450 trn_off_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TRN_OFF_HW_ADDR);
451 csr_port_sem.post();
452 trn_off_csrbus_read_data.write(trn_off_csrbus_read_data_reg);
453 wait (trn_off_ev);
454 }
455
456 }
457
458 void peu_csr_omni::write_trn_off(void) {
459
460 while (true) {
461 wait (trn_off_csrbus_omni_data.value_changed_event());
462 LOG_DEBUG << "WRITE EVENT : Writing the CSR trn_off";
463 trn_off_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TRN_OFF_HW_ADDR, trn_off_csrbus_omni_data.read().to_uint64());
464 }
465 }
466
467 void peu_csr_omni::read_tlu_ici(void) {
468
469 sc_uint<64> tlu_ici_csrbus_read_data_reg;
470
471 for ( ; ; ) {
472
473 csr_port_sem.wait();
474 LOG_DEBUG << "READ EVENT : Reading the CSR tlu_ici ";
475 tlu_ici_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TLU_ICI_HW_ADDR);
476 csr_port_sem.post();
477 tlu_ici_csrbus_read_data.write(tlu_ici_csrbus_read_data_reg);
478 wait (tlu_ici_ev);
479 }
480
481 }
482
483 void peu_csr_omni::write_tlu_ici(void) {
484
485 while (true) {
486 wait (tlu_ici_csrbus_omni_data.value_changed_event());
487 LOG_DEBUG << "WRITE EVENT : Writing the CSR tlu_ici ";
488 tlu_ici_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TLU_ICI_HW_ADDR,tlu_ici_csrbus_omni_data.read().to_uint64());
489 }
490 }
491
492 void peu_csr_omni::read_tlu_diag(void) {
493
494 sc_uint<64> tlu_diag_csrbus_read_data_reg;
495
496 for ( ; ; ) {
497
498 csr_port_sem.wait();
499 LOG_DEBUG << "READ EVENT : Reading the CSR tlu_diag ";
500 tlu_diag_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TLU_DIAG_HW_ADDR);
501 csr_port_sem.post();
502 tlu_diag_csrbus_read_data.write(tlu_diag_csrbus_read_data_reg);
503 wait (tlu_diag_ev);
504 }
505
506 }
507
508 void peu_csr_omni::write_tlu_diag(void) {
509
510 while (true) {
511 wait (tlu_diag_csrbus_omni_data.value_changed_event());
512 LOG_DEBUG << "WRITE EVENT : Writing the CSR tlu_diag";
513 tlu_diag_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TLU_DIAG_HW_ADDR, tlu_diag_csrbus_omni_data.read().to_uint64());
514 }
515 }
516
517 void peu_csr_omni::read_tlu_ecc(void) {
518
519 sc_uint<64> tlu_ecc_csrbus_read_data_reg;
520
521 for ( ; ; ) {
522
523 csr_port_sem.wait();
524 LOG_DEBUG << "READ EVENT : Reading the CSR tlu_ecc ";
525 tlu_ecc_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TLU_ECC_HW_ADDR);
526 csr_port_sem.post();
527 tlu_ecc_csrbus_read_data.write(tlu_ecc_csrbus_read_data_reg);
528 wait (tlu_ecc_ev);
529 }
530
531 }
532
533 void peu_csr_omni::write_tlu_ecc(void) {
534
535 while (true) {
536 wait (tlu_ecc_csrbus_omni_data.value_changed_event());
537 LOG_DEBUG << "WRITE EVENT : Writing the CSR tlu_ecc";
538 tlu_ecc_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TLU_ECC_HW_ADDR, tlu_ecc_csrbus_omni_data.read().to_uint64());
539 }
540 }
541
542 void peu_csr_omni::read_tlu_ecl(void) {
543
544 sc_uint<64> tlu_ecl_csrbus_read_data_reg;
545
546 for ( ; ; ) {
547
548 csr_port_sem.wait();
549 LOG_DEBUG << "READ EVENT : Reading the CSR tlu_ecl ";
550 tlu_ecl_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TLU_ECL_HW_ADDR);
551 csr_port_sem.post();
552 tlu_ecl_csrbus_read_data.write(tlu_ecl_csrbus_read_data_reg);
553 wait (tlu_ecl_ev);
554 }
555
556 }
557
558 void peu_csr_omni::write_tlu_ecl(void) {
559
560 while (true) {
561 wait (tlu_ecl_csrbus_omni_data.value_changed_event());
562 LOG_DEBUG << "WRITE EVENT : Writing the CSR tlu_ecl";
563 tlu_ecl_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TLU_ECL_HW_ADDR, tlu_ecl_csrbus_omni_data.read().to_uint64());
564 }
565 }
566
567 void peu_csr_omni::read_tlu_erb(void) {
568
569 sc_uint<64> tlu_erb_csrbus_read_data_reg;
570
571 for ( ; ; ) {
572
573 csr_port_sem.wait();
574 LOG_DEBUG << "READ EVENT : Reading the CSR tlu_erb ";
575 tlu_erb_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TLU_ERB_HW_ADDR);
576 csr_port_sem.post();
577 tlu_erb_csrbus_read_data.write(tlu_erb_csrbus_read_data_reg);
578 wait (tlu_erb_ev);
579 }
580
581 }
582
583 void peu_csr_omni::write_tlu_erb(void) {
584
585 while (true) {
586 wait (tlu_erb_csrbus_omni_data.value_changed_event());
587 LOG_DEBUG << "WRITE EVENT : Writing the CSR tlu_erb";
588 tlu_erb_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TLU_ERB_HW_ADDR, tlu_erb_csrbus_omni_data.read().to_uint64());
589 }
590 }
591
592 void peu_csr_omni::read_tlu_ica(void) {
593
594 sc_uint<64> tlu_ica_csrbus_read_data_reg;
595
596 for ( ; ; ) {
597
598 csr_port_sem.wait();
599 LOG_DEBUG << "READ EVENT : Reading the CSR tlu_ica ";
600 tlu_ica_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TLU_ICA_HW_ADDR);
601 csr_port_sem.post();
602 tlu_ica_csrbus_read_data.write(tlu_ica_csrbus_read_data_reg);
603 wait (tlu_ica_ev);
604 }
605
606 }
607
608 void peu_csr_omni::write_tlu_ica(void) {
609
610 while (true) {
611 wait (tlu_ica_csrbus_omni_data.value_changed_event());
612 LOG_DEBUG << "WRITE EVENT : Writing the CSR tlu_ica";
613 tlu_ica_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TLU_ICA_HW_ADDR, tlu_ica_csrbus_omni_data.read().to_uint64());
614 }
615 }
616
617 void peu_csr_omni::read_tlu_icr(void) {
618
619 sc_uint<64> tlu_icr_csrbus_read_data_reg;
620
621 for ( ; ; ) {
622
623 csr_port_sem.wait();
624 LOG_DEBUG << "READ EVENT : Reading the CSR tlu_icr ";
625 tlu_icr_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TLU_ICR_HW_ADDR);
626 csr_port_sem.post();
627 tlu_icr_csrbus_read_data.write(tlu_icr_csrbus_read_data_reg);
628 wait (tlu_icr_ev);
629 }
630
631 }
632
633 void peu_csr_omni::write_tlu_icr(void) {
634
635 while (true) {
636 wait (tlu_icr_csrbus_omni_data.value_changed_event());
637 LOG_DEBUG << "WRITE EVENT : Writing the CSR tlu_icr";
638 tlu_icr_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TLU_ICR_HW_ADDR, tlu_icr_csrbus_omni_data.read().to_uint64());
639 }
640 }
641
642 void peu_csr_omni::read_oe_log(void) {
643
644 sc_uint<64> oe_log_csrbus_read_data_reg;
645
646 for ( ; ; ) {
647
648 csr_port_sem.wait();
649 LOG_DEBUG << "READ EVENT : Reading the CSR oe_log ";
650 oe_log_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_OE_LOG_HW_ADDR);
651 csr_port_sem.post();
652 oe_log_csrbus_read_data.write(oe_log_csrbus_read_data_reg);
653 wait (oe_log_ev);
654 }
655
656 }
657
658 void peu_csr_omni::write_oe_log(void) {
659
660 while (true) {
661 wait (oe_log_csrbus_omni_data.value_changed_event());
662 LOG_DEBUG << "WRITE EVENT : Writing the CSR oe_log";
663 oe_log_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_OE_LOG_HW_ADDR, oe_log_csrbus_omni_data.read().to_uint64());
664 }
665 }
666
667 void peu_csr_omni::read_oe_int_en(void) {
668
669 sc_uint<64> oe_int_en_csrbus_read_data_reg;
670
671 for ( ; ; ) {
672
673 csr_port_sem.wait();
674 LOG_DEBUG << "READ EVENT : Reading the CSR oe_int_en ";
675 oe_int_en_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_OE_INT_EN_HW_ADDR);
676 csr_port_sem.post();
677 oe_int_en_csrbus_read_data.write(oe_int_en_csrbus_read_data_reg);
678 wait (oe_int_en_ev);
679 }
680
681 }
682
683 void peu_csr_omni::write_oe_int_en(void) {
684
685 while (true) {
686 wait (oe_int_en_csrbus_omni_data.value_changed_event());
687 LOG_DEBUG << "WRITE EVENT : Writing the CSR oe_int_en";
688 oe_int_en_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_OE_INT_EN_HW_ADDR, oe_int_en_csrbus_omni_data.read().to_uint64());
689 }
690 }
691
692
693 void peu_csr_omni::read_oe_en_err(void) {
694
695 sc_uint<64> oe_en_err_csrbus_read_data_reg;
696
697 for ( ; ; ) {
698
699 csr_port_sem.wait();
700 LOG_DEBUG << "READ EVENT : Reading the CSR oe_en_err ";
701 oe_en_err_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_OE_EN_ERR_HW_ADDR);
702 csr_port_sem.post();
703 oe_en_err_csrbus_read_data.write(oe_en_err_csrbus_read_data_reg);
704 wait (oe_en_err_ev);
705 }
706
707 }
708
709 void peu_csr_omni::write_oe_en_err(void) {
710
711 while (true) {
712 wait (oe_en_err_csrbus_omni_data.value_changed_event());
713 LOG_DEBUG << "WRITE EVENT : Writing the CSR oe_en_err";
714 oe_en_err_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_OE_EN_ERR_HW_ADDR, oe_en_err_csrbus_omni_data.read().to_uint64());
715 }
716 }
717
718 void peu_csr_omni::read_oe_err_rw1c_alias(void) {
719
720 sc_uint<64> oe_err_rw1c_alias_csrbus_read_data_reg;
721
722 for ( ; ; ) {
723
724 csr_port_sem.wait();
725 LOG_DEBUG << "READ EVENT : Reading the CSR oe_err_rw1c_alias ";
726 oe_err_rw1c_alias_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_OE_ERR_RW1C_ALIAS_HW_ADDR);
727 csr_port_sem.post();
728 oe_err_rw1c_alias_csrbus_read_data.write(oe_err_rw1c_alias_csrbus_read_data_reg);
729 wait (oe_err_rw1c_alias_ev);
730 }
731
732 }
733
734 void peu_csr_omni::write_oe_err_rw1c_alias(void) {
735
736 while (true) {
737 wait (oe_err_rw1c_alias_csrbus_omni_data.value_changed_event());
738 LOG_DEBUG << "WRITE EVENT : Writing the CSR oe_err_rw1c_alias";
739 oe_err_rw1c_alias_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_OE_ERR_RW1C_ALIAS_HW_ADDR, oe_err_rw1c_alias_csrbus_omni_data.read().to_uint64());
740 }
741 }
742
743 void peu_csr_omni::read_oe_err_rw1s_alias(void) {
744
745 sc_uint<64> oe_err_rw1s_alias_csrbus_read_data_reg;
746
747 for ( ; ; ) {
748
749 csr_port_sem.wait();
750 LOG_DEBUG << "READ EVENT : Reading the CSR oe_err_rw1s_alias ";
751 oe_err_rw1s_alias_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_OE_ERR_RW1S_ALIAS_HW_ADDR);
752 csr_port_sem.post();
753 oe_err_rw1s_alias_csrbus_read_data.write(oe_err_rw1s_alias_csrbus_read_data_reg);
754 wait (oe_err_rw1s_alias_ev);
755 }
756
757 }
758
759 void peu_csr_omni::write_oe_err_rw1s_alias(void) {
760
761 while (true) {
762 wait (oe_err_rw1s_alias_csrbus_omni_data.value_changed_event());
763 LOG_DEBUG << "WRITE EVENT : Writing the CSR oe_err_rw1s_alias";
764 oe_err_rw1s_alias_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_OE_ERR_RW1S_ALIAS_HW_ADDR, oe_err_rw1s_alias_csrbus_omni_data.read().to_uint64());
765 }
766 }
767
768 void peu_csr_omni::read_roe_hdr1(void) {
769
770 sc_uint<64> roe_hdr1_csrbus_read_data_reg;
771
772 for ( ; ; ) {
773
774 csr_port_sem.wait();
775 LOG_DEBUG << "READ EVENT : Reading the CSR roe_hdr1 ";
776 roe_hdr1_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_ROE_HDR1_HW_ADDR);
777 csr_port_sem.post();
778 roe_hdr1_csrbus_read_data.write(roe_hdr1_csrbus_read_data_reg);
779 wait (roe_hdr1_ev);
780 }
781
782 }
783
784 void peu_csr_omni::write_roe_hdr1(void) {
785
786 while (true) {
787 wait (roe_hdr1_csrbus_omni_data.value_changed_event());
788 LOG_DEBUG << "WRITE EVENT : Writing the CSR roe_hdr1";
789 roe_hdr1_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_ROE_HDR1_HW_ADDR, roe_hdr1_csrbus_omni_data.read().to_uint64());
790 }
791 }
792
793 void peu_csr_omni::read_roe_hdr2(void) {
794
795 sc_uint<64> roe_hdr2_csrbus_read_data_reg;
796
797 for ( ; ; ) {
798
799 csr_port_sem.wait();
800 LOG_DEBUG << "READ EVENT : Reading the CSR roe_hdr2 ";
801 roe_hdr2_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_ROE_HDR2_HW_ADDR);
802 csr_port_sem.post();
803 roe_hdr2_csrbus_read_data.write(roe_hdr2_csrbus_read_data_reg);
804 wait (roe_hdr2_ev);
805 }
806
807 }
808
809 void peu_csr_omni::write_roe_hdr2(void) {
810
811 while (true) {
812 wait (roe_hdr2_csrbus_omni_data.value_changed_event());
813 LOG_DEBUG << "WRITE EVENT : Writing the CSR roe_hdr2";
814 roe_hdr2_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_ROE_HDR2_HW_ADDR, roe_hdr2_csrbus_omni_data.read().to_uint64());
815 }
816 }
817
818 void peu_csr_omni::read_toe_hdr1(void) {
819
820 sc_uint<64> toe_hdr1_csrbus_read_data_reg;
821
822 for ( ; ; ) {
823
824 csr_port_sem.wait();
825 LOG_DEBUG << "READ EVENT : Reading the CSR toe_hdr1 ";
826 toe_hdr1_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TOE_HDR1_HW_ADDR);
827 csr_port_sem.post();
828 toe_hdr1_csrbus_read_data.write(toe_hdr1_csrbus_read_data_reg);
829 wait (toe_hdr1_ev);
830 }
831
832 }
833
834 void peu_csr_omni::write_toe_hdr1(void) {
835
836 while (true) {
837 wait (toe_hdr1_csrbus_omni_data.value_changed_event());
838 LOG_DEBUG << "WRITE EVENT : Writing the CSR toe_hdr1";
839 toe_hdr1_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TOE_HDR1_HW_ADDR, toe_hdr1_csrbus_omni_data.read().to_uint64());
840 }
841 }
842
843 void peu_csr_omni::read_toe_hdr2(void) {
844
845 sc_uint<64> toe_hdr2_csrbus_read_data_reg;
846
847 for ( ; ; ) {
848
849 csr_port_sem.wait();
850 LOG_DEBUG << "READ EVENT : Reading the CSR toe_hdr2 ";
851 toe_hdr2_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TOE_HDR2_HW_ADDR);
852 csr_port_sem.post();
853 toe_hdr2_csrbus_read_data.write(toe_hdr2_csrbus_read_data_reg);
854 wait (toe_hdr2_ev);
855 }
856
857 }
858
859 void peu_csr_omni::write_toe_hdr2(void) {
860
861 while (true) {
862 wait (toe_hdr2_csrbus_omni_data.value_changed_event());
863 LOG_DEBUG << "WRITE EVENT : Writing the CSR toe_hdr2";
864 toe_hdr2_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TOE_HDR2_HW_ADDR, toe_hdr2_csrbus_omni_data.read().to_uint64());
865 }
866 }
867
868 void peu_csr_omni::read_tlu_prfc(void) {
869
870 sc_uint<64> tlu_prfc_csrbus_read_data_reg;
871
872 for ( ; ; ) {
873
874 csr_port_sem.wait();
875 LOG_DEBUG << "READ EVENT : Reading the CSR tlu_prfc ";
876 tlu_prfc_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TLU_PRFC_HW_ADDR);
877 csr_port_sem.post();
878 tlu_prfc_csrbus_read_data.write(tlu_prfc_csrbus_read_data_reg);
879 wait (tlu_prfc_ev);
880 }
881
882 }
883
884 void peu_csr_omni::write_tlu_prfc(void) {
885
886 while (true) {
887 wait (tlu_prfc_csrbus_omni_data.value_changed_event());
888 LOG_DEBUG << "WRITE EVENT : Writing the CSR tlu_prfc";
889 tlu_prfc_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TLU_PRFC_HW_ADDR, tlu_prfc_csrbus_omni_data.read().to_uint64());
890 }
891 }
892
893 void peu_csr_omni::read_tlu_prf0(void) {
894
895 sc_uint<64> tlu_prf0_csrbus_read_data_reg;
896
897 for ( ; ; ) {
898
899 csr_port_sem.wait();
900 LOG_DEBUG << "READ EVENT : Reading the CSR tlu_prf0 ";
901 tlu_prf0_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TLU_PRF0_HW_ADDR);
902 csr_port_sem.post();
903 tlu_prf0_csrbus_read_data.write(tlu_prf0_csrbus_read_data_reg);
904 wait (tlu_prf0_ev);
905 }
906
907 }
908
909 void peu_csr_omni::write_tlu_prf0(void) {
910
911 while (true) {
912 wait (tlu_prf0_csrbus_omni_data.value_changed_event());
913 LOG_DEBUG << "WRITE EVENT : Writing the CSR tlu_prf0";
914 tlu_prf0_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TLU_PRF0_HW_ADDR, tlu_prf0_csrbus_omni_data.read().to_uint64());
915 }
916 }
917
918 void peu_csr_omni::read_tlu_prf1(void) {
919
920 sc_uint<64> tlu_prf1_csrbus_read_data_reg;
921
922 for ( ; ; ) {
923
924 csr_port_sem.wait();
925 LOG_DEBUG << "READ EVENT : Reading the CSR tlu_prf1 ";
926 tlu_prf1_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TLU_PRF1_HW_ADDR);
927 csr_port_sem.post();
928 tlu_prf1_csrbus_read_data.write(tlu_prf1_csrbus_read_data_reg);
929 wait (tlu_prf1_ev);
930 }
931
932 }
933
934 void peu_csr_omni::write_tlu_prf1(void) {
935
936 while (true) {
937 wait (tlu_prf1_csrbus_omni_data.value_changed_event());
938 LOG_DEBUG << "WRITE EVENT : Writing the CSR tlu_prf1";
939 tlu_prf1_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TLU_PRF1_HW_ADDR, tlu_prf1_csrbus_omni_data.read().to_uint64());
940 }
941 }
942
943 void peu_csr_omni::read_tlu_prf2(void) {
944
945 sc_uint<64> tlu_prf2_csrbus_read_data_reg;
946
947 for ( ; ; ) {
948
949 csr_port_sem.wait();
950 LOG_DEBUG << "READ EVENT : Reading the CSR tlu_prf2 ";
951 tlu_prf2_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TLU_PRF2_HW_ADDR);
952 csr_port_sem.post();
953 tlu_prf2_csrbus_read_data.write(tlu_prf2_csrbus_read_data_reg);
954 wait (tlu_prf2_ev);
955 }
956
957 }
958
959 void peu_csr_omni::write_tlu_prf2(void) {
960
961 while (true) {
962 wait (tlu_prf2_csrbus_omni_data.value_changed_event());
963 LOG_DEBUG << "WRITE EVENT : Writing the CSR tlu_prf2";
964 tlu_prf2_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TLU_PRF2_HW_ADDR, tlu_prf2_csrbus_omni_data.read().to_uint64());
965 }
966 }
967
968 void peu_csr_omni::read_tlu_dbg_sel_a(void) {
969
970 sc_uint<64> tlu_dbg_sel_a_csrbus_read_data_reg;
971
972 for ( ; ; ) {
973
974 csr_port_sem.wait();
975 LOG_DEBUG << "READ EVENT : Reading the CSR tlu_dbg_sel_a ";
976 tlu_dbg_sel_a_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TLU_DBG_SEL_A_HW_ADDR);
977 csr_port_sem.post();
978 tlu_dbg_sel_a_csrbus_read_data.write(tlu_dbg_sel_a_csrbus_read_data_reg);
979 wait (tlu_dbg_sel_a_ev);
980 }
981
982 }
983
984 void peu_csr_omni::write_tlu_dbg_sel_a(void) {
985
986 while (true) {
987 wait (tlu_dbg_sel_a_csrbus_omni_data.value_changed_event());
988 LOG_DEBUG << "WRITE EVENT : Writing the CSR tlu_dbg_sel_a";
989 tlu_dbg_sel_a_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TLU_DBG_SEL_A_HW_ADDR, tlu_dbg_sel_a_csrbus_omni_data.read().to_uint64());
990 }
991 }
992
993 void peu_csr_omni::read_tlu_dbg_sel_b(void) {
994
995 sc_uint<64> tlu_dbg_sel_b_csrbus_read_data_reg;
996
997 for ( ; ; ) {
998
999 csr_port_sem.wait();
1000 LOG_DEBUG << "READ EVENT : Reading the CSR tlu_dbg_sel_b ";
1001 tlu_dbg_sel_b_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TLU_DBG_SEL_B_HW_ADDR);
1002 csr_port_sem.post();
1003 tlu_dbg_sel_b_csrbus_read_data.write(tlu_dbg_sel_b_csrbus_read_data_reg);
1004 wait (tlu_dbg_sel_b_ev);
1005 }
1006
1007 }
1008
1009 void peu_csr_omni::write_tlu_dbg_sel_b(void) {
1010
1011 while (true) {
1012 wait (tlu_dbg_sel_b_csrbus_omni_data.value_changed_event());
1013 LOG_DEBUG << "WRITE EVENT : Writing the CSR tlu_dbg_sel_b";
1014 tlu_dbg_sel_b_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TLU_DBG_SEL_B_HW_ADDR, tlu_dbg_sel_b_csrbus_omni_data.read().to_uint64());
1015 }
1016 }
1017
1018 void peu_csr_omni::read_dev_cap(void) {
1019
1020 sc_uint<64> dev_cap_csrbus_read_data_reg;
1021
1022 for ( ; ; ) {
1023
1024 csr_port_sem.wait();
1025 LOG_DEBUG << "READ EVENT : Reading the CSR dev_cap ";
1026 dev_cap_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_DEV_CAP_HW_ADDR);
1027 csr_port_sem.post();
1028 dev_cap_csrbus_read_data.write(dev_cap_csrbus_read_data_reg);
1029 wait (dev_cap_ev);
1030 }
1031
1032 }
1033
1034 void peu_csr_omni::write_dev_cap(void) {
1035
1036 while (true) {
1037 wait (dev_cap_csrbus_omni_data.value_changed_event());
1038 LOG_DEBUG << "WRITE EVENT : Writing the CSR dev_cap";
1039 dev_cap_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_DEV_CAP_HW_ADDR, dev_cap_csrbus_omni_data.read().to_uint64());
1040 }
1041 }
1042
1043 void peu_csr_omni::read_dev_ctl(void) {
1044
1045 sc_uint<64> dev_ctl_csrbus_read_data_reg;
1046
1047 for ( ; ; ) {
1048
1049 csr_port_sem.wait();
1050 LOG_DEBUG << "READ EVENT : Reading the CSR dev_ctl ";
1051 dev_ctl_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_DEV_CTL_HW_ADDR);
1052 csr_port_sem.post();
1053 dev_ctl_csrbus_read_data.write(dev_ctl_csrbus_read_data_reg);
1054 wait (dev_ctl_ev);
1055 }
1056
1057 }
1058
1059 void peu_csr_omni::write_dev_ctl(void) {
1060
1061 while (true) {
1062 wait (dev_ctl_csrbus_omni_data.value_changed_event());
1063 LOG_DEBUG << "WRITE EVENT : Writing the CSR dev_ctl";
1064 dev_ctl_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_DEV_CTL_HW_ADDR, dev_ctl_csrbus_omni_data.read().to_uint64());
1065 }
1066 }
1067
1068 void peu_csr_omni::read_dev_sts(void) {
1069
1070 sc_uint<64> dev_sts_csrbus_read_data_reg;
1071
1072 for ( ; ; ) {
1073
1074 csr_port_sem.wait();
1075 LOG_DEBUG << "READ EVENT : Reading the CSR dev_sts ";
1076 dev_sts_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_DEV_STS_HW_ADDR);
1077 csr_port_sem.post();
1078 dev_sts_csrbus_read_data.write(dev_sts_csrbus_read_data_reg);
1079 wait (dev_sts_ev);
1080 }
1081
1082 }
1083
1084 void peu_csr_omni::write_dev_sts(void) {
1085
1086 while (true) {
1087 wait (dev_sts_csrbus_omni_data.value_changed_event());
1088 LOG_DEBUG << "WRITE EVENT : Writing the CSR dev_sts";
1089 dev_sts_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_DEV_STS_HW_ADDR, dev_sts_csrbus_omni_data.read().to_uint64());
1090 }
1091 }
1092
1093 void peu_csr_omni::read_lnk_cap(void) {
1094
1095 sc_uint<64> lnk_cap_csrbus_read_data_reg;
1096
1097 for ( ; ; ) {
1098
1099 csr_port_sem.wait();
1100 LOG_DEBUG << "READ EVENT : Reading the CSR lnk_cap ";
1101 lnk_cap_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_LNK_CAP_HW_ADDR);
1102 csr_port_sem.post();
1103 lnk_cap_csrbus_read_data.write(lnk_cap_csrbus_read_data_reg);
1104 wait (lnk_cap_ev);
1105 }
1106
1107 }
1108
1109 void peu_csr_omni::write_lnk_cap(void) {
1110
1111 while (true) {
1112 wait (lnk_cap_csrbus_omni_data.value_changed_event());
1113 LOG_DEBUG << "WRITE EVENT : Writing the CSR lnk_cap";
1114 lnk_cap_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_LNK_CAP_HW_ADDR, lnk_cap_csrbus_omni_data.read().to_uint64());
1115 }
1116 }
1117
1118 void peu_csr_omni::read_lnk_ctl(void) {
1119
1120 sc_uint<64> lnk_ctl_csrbus_read_data_reg;
1121
1122 for ( ; ; ) {
1123
1124 csr_port_sem.wait();
1125 LOG_DEBUG << "READ EVENT : Reading the CSR lnk_ctl ";
1126 lnk_ctl_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_LNK_CTL_HW_ADDR);
1127 csr_port_sem.post();
1128 lnk_ctl_csrbus_read_data.write(lnk_ctl_csrbus_read_data_reg);
1129 wait (lnk_ctl_ev);
1130 }
1131
1132 }
1133
1134 void peu_csr_omni::write_lnk_ctl(void) {
1135
1136 while (true) {
1137 wait (lnk_ctl_csrbus_omni_data.value_changed_event());
1138 LOG_DEBUG << "WRITE EVENT : Writing the CSR lnk_ctl";
1139 lnk_ctl_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_LNK_CTL_HW_ADDR, lnk_ctl_csrbus_omni_data.read().to_uint64());
1140 }
1141 }
1142
1143 void peu_csr_omni::read_lnk_sts(void) {
1144
1145 sc_uint<64> lnk_sts_csrbus_read_data_reg;
1146
1147 for ( ; ; ) {
1148
1149 csr_port_sem.wait();
1150 LOG_DEBUG << "READ EVENT : Reading the CSR lnk_sts ";
1151 lnk_sts_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_LNK_STS_HW_ADDR);
1152 csr_port_sem.post();
1153 lnk_sts_csrbus_read_data.write(lnk_sts_csrbus_read_data_reg);
1154 wait (lnk_sts_ev);
1155 }
1156
1157 }
1158
1159 void peu_csr_omni::write_lnk_sts(void) {
1160
1161 while (true) {
1162 wait (lnk_sts_csrbus_omni_data.value_changed_event());
1163 LOG_DEBUG << "WRITE EVENT : Writing the CSR lnk_sts";
1164 lnk_sts_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_LNK_STS_HW_ADDR, lnk_sts_csrbus_omni_data.read().to_uint64());
1165 }
1166 }
1167
1168 void peu_csr_omni::read_slt_cap(void) {
1169
1170 sc_uint<64> slt_cap_csrbus_read_data_reg;
1171
1172 for ( ; ; ) {
1173
1174 csr_port_sem.wait();
1175 LOG_DEBUG << "READ EVENT : Reading the CSR slt_cap ";
1176 slt_cap_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_SLT_CAP_HW_ADDR);
1177 csr_port_sem.post();
1178 slt_cap_csrbus_read_data.write(slt_cap_csrbus_read_data_reg);
1179 wait (slt_cap_ev);
1180 }
1181
1182 }
1183
1184 void peu_csr_omni::write_slt_cap(void) {
1185
1186 while (true) {
1187 wait (slt_cap_csrbus_omni_data.value_changed_event());
1188 LOG_DEBUG << "WRITE EVENT : Writing the CSR slt_cap";
1189 slt_cap_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_SLT_CAP_HW_ADDR, slt_cap_csrbus_omni_data.read().to_uint64());
1190 }
1191 }
1192
1193 void peu_csr_omni::read_ue_log(void) {
1194
1195 sc_uint<64> ue_log_csrbus_read_data_reg;
1196
1197 for ( ; ; ) {
1198
1199 csr_port_sem.wait();
1200 LOG_DEBUG << "READ EVENT : Reading the CSR ue_log ";
1201 ue_log_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_UE_LOG_HW_ADDR);
1202 csr_port_sem.post();
1203 ue_log_csrbus_read_data.write(ue_log_csrbus_read_data_reg);
1204 wait (ue_log_ev);
1205 }
1206
1207 }
1208
1209 void peu_csr_omni::write_ue_log(void) {
1210
1211 while (true) {
1212 wait (ue_log_csrbus_omni_data.value_changed_event());
1213 LOG_DEBUG << "WRITE EVENT : Writing the CSR ue_log";
1214 ue_log_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_UE_LOG_HW_ADDR, ue_log_csrbus_omni_data.read().to_uint64());
1215 }
1216 }
1217
1218 void peu_csr_omni::read_ue_int_en(void) {
1219
1220 sc_uint<64> ue_int_en_csrbus_read_data_reg;
1221
1222 for ( ; ; ) {
1223
1224 csr_port_sem.wait();
1225 LOG_DEBUG << "READ EVENT : Reading the CSR ue_int_en ";
1226 ue_int_en_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_UE_INT_EN_HW_ADDR);
1227 csr_port_sem.post();
1228 ue_int_en_csrbus_read_data.write(ue_int_en_csrbus_read_data_reg);
1229 wait (ue_int_en_ev);
1230 }
1231
1232 }
1233
1234 void peu_csr_omni::write_ue_int_en(void) {
1235
1236 while (true) {
1237 wait (ue_int_en_csrbus_omni_data.value_changed_event());
1238 LOG_DEBUG << "WRITE EVENT : Writing the CSR ue_int_en";
1239 ue_int_en_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_UE_INT_EN_HW_ADDR, ue_int_en_csrbus_omni_data.read().to_uint64());
1240 }
1241 }
1242
1243 void peu_csr_omni::read_ue_en_err(void) {
1244
1245 sc_uint<64> ue_en_err_csrbus_read_data_reg;
1246
1247 for ( ; ; ) {
1248
1249 csr_port_sem.wait();
1250 LOG_DEBUG << "READ EVENT : Reading the CSR ue_en_err ";
1251 ue_en_err_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_UE_EN_ERR_HW_ADDR);
1252 csr_port_sem.post();
1253 ue_en_err_csrbus_read_data.write(ue_en_err_csrbus_read_data_reg);
1254 wait (ue_en_err_ev);
1255 }
1256
1257 }
1258
1259 void peu_csr_omni::write_ue_en_err(void) {
1260
1261 while (true) {
1262 wait (ue_en_err_csrbus_omni_data.value_changed_event());
1263 LOG_DEBUG << "WRITE EVENT : Writing the CSR ue_en_err";
1264 ue_en_err_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_UE_EN_ERR_HW_ADDR, ue_en_err_csrbus_omni_data.read().to_uint64());
1265 }
1266 }
1267
1268 void peu_csr_omni::read_ue_err_rw1c_alias(void) {
1269
1270 sc_uint<64> ue_err_rw1c_alias_csrbus_read_data_reg;
1271
1272 for ( ; ; ) {
1273
1274 csr_port_sem.wait();
1275 LOG_DEBUG << "READ EVENT : Reading the CSR ue_err_rw1c_alias ";
1276 ue_err_rw1c_alias_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_UE_ERR_RW1C_ALIAS_HW_ADDR);
1277 csr_port_sem.post();
1278 ue_err_rw1c_alias_csrbus_read_data.write(ue_err_rw1c_alias_csrbus_read_data_reg);
1279 wait (ue_err_rw1c_alias_ev);
1280 }
1281
1282 }
1283
1284 void peu_csr_omni::write_ue_err_rw1c_alias(void) {
1285
1286 while (true) {
1287 wait (ue_err_rw1c_alias_csrbus_omni_data.value_changed_event());
1288 LOG_DEBUG << "WRITE EVENT : Writing the CSR ue_err_rw1c_alias";
1289 ue_err_rw1c_alias_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_UE_ERR_RW1C_ALIAS_HW_ADDR, ue_err_rw1c_alias_csrbus_omni_data.read().to_uint64());
1290 }
1291 }
1292
1293 void peu_csr_omni::read_ue_err_rw1s_alias(void) {
1294
1295 sc_uint<64> ue_err_rw1s_alias_csrbus_read_data_reg;
1296
1297 for ( ; ; ) {
1298
1299 csr_port_sem.wait();
1300 LOG_DEBUG << "READ EVENT : Reading the CSR ue_err_rw1s_alias ";
1301 ue_err_rw1s_alias_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_UE_ERR_RW1S_ALIAS_HW_ADDR);
1302 csr_port_sem.post();
1303 ue_err_rw1s_alias_csrbus_read_data.write(ue_err_rw1s_alias_csrbus_read_data_reg);
1304 wait (ue_err_rw1s_alias_ev);
1305 }
1306
1307 }
1308
1309 void peu_csr_omni::write_ue_err_rw1s_alias(void) {
1310
1311 while (true) {
1312 wait (ue_err_rw1s_alias_csrbus_omni_data.value_changed_event());
1313 LOG_DEBUG << "WRITE EVENT : Writing the CSR ue_err_rw1s_alias";
1314 ue_err_rw1s_alias_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_UE_ERR_RW1S_ALIAS_HW_ADDR, ue_err_rw1s_alias_csrbus_omni_data.read().to_uint64());
1315 }
1316 }
1317
1318 void peu_csr_omni::read_rue_hdr1(void) {
1319
1320 sc_uint<64> rue_hdr1_csrbus_read_data_reg;
1321
1322 for ( ; ; ) {
1323
1324 csr_port_sem.wait();
1325 LOG_DEBUG << "READ EVENT : Reading the CSR rue_hdr1 ";
1326 rue_hdr1_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_RUE_HDR1_HW_ADDR);
1327 csr_port_sem.post();
1328 rue_hdr1_csrbus_read_data.write(rue_hdr1_csrbus_read_data_reg);
1329 wait (rue_hdr1_ev);
1330 }
1331
1332 }
1333
1334 void peu_csr_omni::write_rue_hdr1(void) {
1335
1336 while (true) {
1337 wait (rue_hdr1_csrbus_omni_data.value_changed_event());
1338 LOG_DEBUG << "WRITE EVENT : Writing the CSR rue_hdr1";
1339 rue_hdr1_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_RUE_HDR1_HW_ADDR, rue_hdr1_csrbus_omni_data.read().to_uint64());
1340 }
1341 }
1342
1343 void peu_csr_omni::read_rue_hdr2(void) {
1344
1345 sc_uint<64> rue_hdr2_csrbus_read_data_reg;
1346
1347 for ( ; ; ) {
1348
1349 csr_port_sem.wait();
1350 LOG_DEBUG << "READ EVENT : Reading the CSR rue_hdr2 ";
1351 rue_hdr2_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_RUE_HDR2_HW_ADDR);
1352 csr_port_sem.post();
1353 rue_hdr2_csrbus_read_data.write(rue_hdr2_csrbus_read_data_reg);
1354 wait (rue_hdr2_ev);
1355 }
1356
1357 }
1358
1359 void peu_csr_omni::write_rue_hdr2(void) {
1360
1361 while (true) {
1362 wait (rue_hdr2_csrbus_omni_data.value_changed_event());
1363 LOG_DEBUG << "WRITE EVENT : Writing the CSR rue_hdr2";
1364 rue_hdr2_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_RUE_HDR2_HW_ADDR, rue_hdr2_csrbus_omni_data.read().to_uint64());
1365 }
1366 }
1367
1368 void peu_csr_omni::read_tue_hdr1(void) {
1369
1370 sc_uint<64> tue_hdr1_csrbus_read_data_reg;
1371
1372 for ( ; ; ) {
1373
1374 csr_port_sem.wait();
1375 LOG_DEBUG << "READ EVENT : Reading the CSR tue_hdr1 ";
1376 tue_hdr1_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TUE_HDR1_HW_ADDR);
1377 csr_port_sem.post();
1378 tue_hdr1_csrbus_read_data.write(tue_hdr1_csrbus_read_data_reg);
1379 wait (tue_hdr1_ev);
1380 }
1381
1382 }
1383
1384 void peu_csr_omni::write_tue_hdr1(void) {
1385
1386 while (true) {
1387 wait (tue_hdr1_csrbus_omni_data.value_changed_event());
1388 LOG_DEBUG << "WRITE EVENT : Writing the CSR tue_hdr1";
1389 tue_hdr1_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TUE_HDR1_HW_ADDR, tue_hdr1_csrbus_omni_data.read().to_uint64());
1390 }
1391 }
1392
1393 void peu_csr_omni::read_tue_hdr2(void) {
1394
1395 sc_uint<64> tue_hdr2_csrbus_read_data_reg;
1396
1397 for ( ; ; ) {
1398
1399 csr_port_sem.wait();
1400 LOG_DEBUG << "READ EVENT : Reading the CSR tue_hdr2 ";
1401 tue_hdr2_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_TUE_HDR2_HW_ADDR);
1402 csr_port_sem.post();
1403 tue_hdr2_csrbus_read_data.write(tue_hdr2_csrbus_read_data_reg);
1404 wait (tue_hdr2_ev);
1405 }
1406
1407 }
1408
1409 void peu_csr_omni::write_tue_hdr2(void) {
1410
1411 while (true) {
1412 wait (tue_hdr2_csrbus_omni_data.value_changed_event());
1413 LOG_DEBUG << "WRITE EVENT : Writing the CSR tue_hdr2";
1414 tue_hdr2_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_TUE_HDR2_HW_ADDR, tue_hdr2_csrbus_omni_data.read().to_uint64());
1415 }
1416 }
1417
1418 void peu_csr_omni::read_ce_log(void) {
1419
1420 sc_uint<64> ce_log_csrbus_read_data_reg;
1421
1422 for ( ; ; ) {
1423
1424 csr_port_sem.wait();
1425 LOG_DEBUG << "READ EVENT : Reading the CSR ce_log ";
1426 ce_log_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_CE_LOG_HW_ADDR);
1427 csr_port_sem.post();
1428 ce_log_csrbus_read_data.write(ce_log_csrbus_read_data_reg);
1429 wait (ce_log_ev);
1430 }
1431
1432 }
1433
1434 void peu_csr_omni::write_ce_log(void) {
1435
1436 while (true) {
1437 wait (ce_log_csrbus_omni_data.value_changed_event());
1438 LOG_DEBUG << "WRITE EVENT : Writing the CSR ce_log";
1439 ce_log_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_CE_LOG_HW_ADDR, ce_log_csrbus_omni_data.read().to_uint64());
1440 }
1441 }
1442
1443 void peu_csr_omni::read_ce_int_en(void) {
1444
1445 sc_uint<64> ce_int_en_csrbus_read_data_reg;
1446
1447 for ( ; ; ) {
1448
1449 csr_port_sem.wait();
1450 LOG_DEBUG << "READ EVENT : Reading the CSR ce_int_en ";
1451 ce_int_en_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_CE_INT_EN_HW_ADDR);
1452 csr_port_sem.post();
1453 ce_int_en_csrbus_read_data.write(ce_int_en_csrbus_read_data_reg);
1454 wait (ce_int_en_ev);
1455 }
1456
1457 }
1458
1459 void peu_csr_omni::write_ce_int_en(void) {
1460
1461 while (true) {
1462 wait (ce_int_en_csrbus_omni_data.value_changed_event());
1463 LOG_DEBUG << "WRITE EVENT : Writing the CSR ce_int_en";
1464 ce_int_en_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_CE_INT_EN_HW_ADDR, ce_int_en_csrbus_omni_data.read().to_uint64());
1465 }
1466 }
1467
1468 void peu_csr_omni::read_ce_en_err(void) {
1469
1470 sc_uint<64> ce_en_err_csrbus_read_data_reg;
1471
1472 for ( ; ; ) {
1473
1474 csr_port_sem.wait();
1475 LOG_DEBUG << "READ EVENT : Reading the CSR ce_en_err ";
1476 ce_en_err_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_CE_EN_ERR_HW_ADDR);
1477 csr_port_sem.post();
1478 ce_en_err_csrbus_read_data.write(ce_en_err_csrbus_read_data_reg);
1479 wait (ce_en_err_ev);
1480 }
1481
1482 }
1483
1484 void peu_csr_omni::write_ce_en_err(void) {
1485
1486 while (true) {
1487 wait (ce_en_err_csrbus_omni_data.value_changed_event());
1488 LOG_DEBUG << "WRITE EVENT : Writing the CSR ce_en_err";
1489 ce_en_err_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_CE_EN_ERR_HW_ADDR, ce_en_err_csrbus_omni_data.read().to_uint64());
1490 }
1491 }
1492
1493 void peu_csr_omni::read_ce_err_rw1c_alias(void) {
1494
1495 sc_uint<64> ce_err_rw1c_alias_csrbus_read_data_reg;
1496
1497 for ( ; ; ) {
1498
1499 csr_port_sem.wait();
1500 LOG_DEBUG << "READ EVENT : Reading the CSR ce_err_rw1c_alias ";
1501 ce_err_rw1c_alias_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_CE_ERR_RW1C_ALIAS_HW_ADDR);
1502 csr_port_sem.post();
1503 ce_err_rw1c_alias_csrbus_read_data.write(ce_err_rw1c_alias_csrbus_read_data_reg);
1504 wait (ce_err_rw1c_alias_ev);
1505 }
1506
1507 }
1508
1509 void peu_csr_omni::write_ce_err_rw1c_alias(void) {
1510
1511 while (true) {
1512 wait (ce_err_rw1c_alias_csrbus_omni_data.value_changed_event());
1513 LOG_DEBUG << "WRITE EVENT : Writing the CSR ce_err_rw1c_alias";
1514 ce_err_rw1c_alias_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_CE_ERR_RW1C_ALIAS_HW_ADDR, ce_err_rw1c_alias_csrbus_omni_data.read().to_uint64());
1515 }
1516 }
1517
1518 void peu_csr_omni::read_ce_err_rw1s_alias(void) {
1519
1520 sc_uint<64> ce_err_rw1s_alias_csrbus_read_data_reg;
1521
1522 for ( ; ; ) {
1523
1524 csr_port_sem.wait();
1525 LOG_DEBUG << "READ EVENT : Reading the CSR ce_err_rw1s_alias ";
1526 ce_err_rw1s_alias_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_CE_ERR_RW1S_ALIAS_HW_ADDR);
1527 csr_port_sem.post();
1528 ce_err_rw1s_alias_csrbus_read_data.write(ce_err_rw1s_alias_csrbus_read_data_reg);
1529 wait (ce_err_rw1s_alias_ev);
1530 }
1531
1532 }
1533
1534 void peu_csr_omni::write_ce_err_rw1s_alias(void) {
1535
1536 while (true) {
1537 wait (ce_err_rw1s_alias_csrbus_omni_data.value_changed_event());
1538 LOG_DEBUG << "WRITE EVENT : Writing the CSR ce_err_rw1s_alias";
1539 ce_err_rw1s_alias_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_CE_ERR_RW1S_ALIAS_HW_ADDR, ce_err_rw1s_alias_csrbus_omni_data.read().to_uint64());
1540 }
1541 }
1542
1543 void peu_csr_omni::read_peu_dlpl_serdes_rev(void) {
1544
1545 sc_uint<64> peu_dlpl_serdes_rev_csrbus_read_data_reg;
1546
1547 for ( ; ; ) {
1548
1549 csr_port_sem.wait();
1550 LOG_DEBUG << "READ EVENT : Reading the CSR peu_dlpl_serdes_rev ";
1551 peu_dlpl_serdes_rev_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_PEU_DLPL_SERDES_REV_HW_ADDR);
1552 csr_port_sem.post();
1553 peu_dlpl_serdes_rev_csrbus_read_data.write(peu_dlpl_serdes_rev_csrbus_read_data_reg);
1554 wait (peu_dlpl_serdes_rev_ev);
1555 }
1556
1557 }
1558
1559 void peu_csr_omni::write_peu_dlpl_serdes_rev(void) {
1560
1561 while (true) {
1562 wait (peu_dlpl_serdes_rev_csrbus_omni_data.value_changed_event());
1563 LOG_DEBUG << "WRITE EVENT : Writing the CSR peu_dlpl_serdes_rev";
1564 peu_dlpl_serdes_rev_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_PEU_DLPL_SERDES_REV_HW_ADDR, peu_dlpl_serdes_rev_csrbus_omni_data.read().to_uint64());
1565 }
1566 }
1567
1568 void peu_csr_omni::read_acknak_timer(void) {
1569
1570 sc_uint<64> acknak_timer_csrbus_read_data_reg;
1571
1572 for ( ; ; ) {
1573
1574 csr_port_sem.wait();
1575 LOG_DEBUG << "READ EVENT : Reading the CSR acknak_timer ";
1576 acknak_timer_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_ACKNAK_TIMER_HW_ADDR);
1577 csr_port_sem.post();
1578 acknak_timer_csrbus_read_data.write(acknak_timer_csrbus_read_data_reg);
1579 wait (acknak_timer_ev);
1580 }
1581
1582 }
1583
1584 void peu_csr_omni::write_acknak_timer(void) {
1585
1586 while (true) {
1587 wait (acknak_timer_csrbus_omni_data.value_changed_event());
1588 LOG_DEBUG << "WRITE EVENT : Writing the CSR acknak_timer";
1589 acknak_timer_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_ACKNAK_TIMER_HW_ADDR, acknak_timer_csrbus_omni_data.read().to_uint64());
1590 }
1591 }
1592
1593 void peu_csr_omni::read_replay_tim_thresh(void) {
1594
1595 sc_uint<64> replay_tim_thresh_csrbus_read_data_reg;
1596
1597 for ( ; ; ) {
1598
1599 csr_port_sem.wait();
1600 LOG_DEBUG << "READ EVENT : Reading the CSR replay_tim_thresh ";
1601 replay_tim_thresh_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_REPLAY_TIM_THRESH_HW_ADDR);
1602 csr_port_sem.post();
1603 replay_tim_thresh_csrbus_read_data.write(replay_tim_thresh_csrbus_read_data_reg);
1604 wait (replay_tim_thresh_ev);
1605 }
1606
1607 }
1608
1609 void peu_csr_omni::write_replay_tim_thresh(void) {
1610
1611 while (true) {
1612 wait (replay_tim_thresh_csrbus_omni_data.value_changed_event());
1613 LOG_DEBUG << "WRITE EVENT : Writing the CSR replay_tim_thresh";
1614 replay_tim_thresh_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_REPLAY_TIM_THRESH_HW_ADDR, replay_tim_thresh_csrbus_omni_data.read().to_uint64());
1615 }
1616 }
1617
1618 void peu_csr_omni::read_replay_timer(void) {
1619
1620 sc_uint<64> replay_timer_csrbus_read_data_reg;
1621
1622 for ( ; ; ) {
1623
1624 csr_port_sem.wait();
1625 LOG_DEBUG << "READ EVENT : Reading the CSR replay_timer ";
1626 replay_timer_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_REPLAY_TIMER_HW_ADDR);
1627 csr_port_sem.post();
1628 replay_timer_csrbus_read_data.write(replay_timer_csrbus_read_data_reg);
1629 wait (replay_timer_ev);
1630 }
1631
1632 }
1633
1634 void peu_csr_omni::write_replay_timer(void) {
1635
1636 while (true) {
1637 wait (replay_timer_csrbus_omni_data.value_changed_event());
1638 LOG_DEBUG << "WRITE EVENT : Writing the CSR replay_timer";
1639 replay_timer_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_REPLAY_TIMER_HW_ADDR, replay_timer_csrbus_omni_data.read().to_uint64());
1640 }
1641 }
1642
1643 void peu_csr_omni::read_ven_dllp_msg(void) {
1644
1645 sc_uint<64> ven_dllp_msg_csrbus_read_data_reg;
1646
1647 for ( ; ; ) {
1648
1649 csr_port_sem.wait();
1650 LOG_DEBUG << "READ EVENT : Reading the CSR ven_dllp_msg ";
1651 ven_dllp_msg_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_VEN_DLLP_MSG_HW_ADDR);
1652 csr_port_sem.post();
1653 ven_dllp_msg_csrbus_read_data.write(ven_dllp_msg_csrbus_read_data_reg);
1654 wait (ven_dllp_msg_ev);
1655 }
1656
1657 }
1658
1659 void peu_csr_omni::write_ven_dllp_msg(void) {
1660
1661 while (true) {
1662 wait (ven_dllp_msg_csrbus_omni_data.value_changed_event());
1663 LOG_DEBUG << "WRITE EVENT : Writing the CSR ven_dllp_msg";
1664 ven_dllp_msg_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_VEN_DLLP_MSG_HW_ADDR, ven_dllp_msg_csrbus_omni_data.read().to_uint64());
1665 }
1666 }
1667
1668 void peu_csr_omni::read_force_ltssm(void) {
1669
1670 sc_uint<64> force_ltssm_csrbus_read_data_reg;
1671
1672 for ( ; ; ) {
1673
1674 csr_port_sem.wait();
1675 LOG_DEBUG << "READ EVENT : Reading the CSR force_ltssm ";
1676 force_ltssm_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_FORCE_LTSSM_HW_ADDR);
1677 csr_port_sem.post();
1678 force_ltssm_csrbus_read_data.write(force_ltssm_csrbus_read_data_reg);
1679 wait (force_ltssm_ev);
1680 }
1681
1682 }
1683
1684 void peu_csr_omni::write_force_ltssm(void) {
1685
1686 while (true) {
1687 wait (force_ltssm_csrbus_omni_data.value_changed_event());
1688 LOG_DEBUG << "WRITE EVENT : Writing the CSR force_ltssm";
1689 force_ltssm_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_FORCE_LTSSM_HW_ADDR, force_ltssm_csrbus_omni_data.read().to_uint64());
1690 }
1691 }
1692
1693 void peu_csr_omni::read_link_cfg(void) {
1694
1695 sc_uint<64> link_cfg_csrbus_read_data_reg;
1696
1697 for ( ; ; ) {
1698
1699 csr_port_sem.wait();
1700 LOG_DEBUG << "READ EVENT : Reading the CSR link_cfg ";
1701 link_cfg_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_LINK_CFG_HW_ADDR);
1702 csr_port_sem.post();
1703 link_cfg_csrbus_read_data.write(link_cfg_csrbus_read_data_reg);
1704 wait (link_cfg_ev);
1705 }
1706
1707 }
1708
1709 void peu_csr_omni::write_link_cfg(void) {
1710
1711 while (true) {
1712 wait (link_cfg_csrbus_omni_data.value_changed_event());
1713 LOG_DEBUG << "WRITE EVENT : Writing the CSR link_cfg";
1714 link_cfg_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_LINK_CFG_HW_ADDR, link_cfg_csrbus_omni_data.read().to_uint64());
1715 }
1716 }
1717
1718 void peu_csr_omni::read_link_ctl(void) {
1719
1720 sc_uint<64> link_ctl_csrbus_read_data_reg;
1721
1722 for ( ; ; ) {
1723
1724 csr_port_sem.wait();
1725 LOG_DEBUG << "READ EVENT : Reading the CSR link_ctl ";
1726 link_ctl_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_LINK_CTL_HW_ADDR);
1727 csr_port_sem.post();
1728 link_ctl_csrbus_read_data.write(link_ctl_csrbus_read_data_reg);
1729 wait (link_ctl_ev);
1730 }
1731
1732 }
1733
1734 void peu_csr_omni::write_link_ctl(void) {
1735
1736 while (true) {
1737 wait (link_ctl_csrbus_omni_data.value_changed_event());
1738 LOG_DEBUG << "WRITE EVENT : Writing the CSR link_ctl";
1739 link_ctl_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_LINK_CTL_HW_ADDR, link_ctl_csrbus_omni_data.read().to_uint64());
1740 }
1741 }
1742
1743 void peu_csr_omni::read_lane_skew(void) {
1744
1745 sc_uint<64> lane_skew_csrbus_read_data_reg;
1746
1747 for ( ; ; ) {
1748
1749 csr_port_sem.wait();
1750 LOG_DEBUG << "READ EVENT : Reading the CSR lane_skew ";
1751 lane_skew_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_LANE_SKEW_HW_ADDR);
1752 csr_port_sem.post();
1753 lane_skew_csrbus_read_data.write(lane_skew_csrbus_read_data_reg);
1754 wait (lane_skew_ev);
1755 }
1756
1757 }
1758
1759 void peu_csr_omni::write_lane_skew(void) {
1760
1761 while (true) {
1762 wait (lane_skew_csrbus_omni_data.value_changed_event());
1763 LOG_DEBUG << "WRITE EVENT : Writing the CSR lane_skew";
1764 lane_skew_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_LANE_SKEW_HW_ADDR, lane_skew_csrbus_omni_data.read().to_uint64());
1765 }
1766 }
1767
1768 void peu_csr_omni::read_symbol_num(void) {
1769
1770 sc_uint<64> symbol_num_csrbus_read_data_reg;
1771
1772 for ( ; ; ) {
1773
1774 csr_port_sem.wait();
1775 LOG_DEBUG << "READ EVENT : Reading the CSR symbol_num ";
1776 symbol_num_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_SYMBOL_NUM_HW_ADDR);
1777 csr_port_sem.post();
1778 symbol_num_csrbus_read_data.write(symbol_num_csrbus_read_data_reg);
1779 wait (symbol_num_ev);
1780 }
1781
1782 }
1783
1784 void peu_csr_omni::write_symbol_num(void) {
1785
1786 while (true) {
1787 wait (symbol_num_csrbus_omni_data.value_changed_event());
1788 LOG_DEBUG << "WRITE EVENT : Writing the CSR symbol_num";
1789 symbol_num_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_SYMBOL_NUM_HW_ADDR, symbol_num_csrbus_omni_data.read().to_uint64());
1790 }
1791 }
1792
1793 void peu_csr_omni::read_symbol_timer(void) {
1794
1795 sc_uint<64> symbol_timer_csrbus_read_data_reg;
1796
1797 for ( ; ; ) {
1798
1799 csr_port_sem.wait();
1800 LOG_DEBUG << "READ EVENT : Reading the CSR symbol_timer ";
1801 symbol_timer_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_SYMBOL_TIMER_HW_ADDR);
1802 csr_port_sem.post();
1803 symbol_timer_csrbus_read_data.write(symbol_timer_csrbus_read_data_reg);
1804 wait (symbol_timer_ev);
1805 }
1806
1807 }
1808
1809 void peu_csr_omni::write_symbol_timer(void) {
1810
1811 while (true) {
1812 wait (symbol_timer_csrbus_omni_data.value_changed_event());
1813 LOG_DEBUG << "WRITE EVENT : Writing the CSR symbol_timer";
1814 symbol_timer_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_SYMBOL_TIMER_HW_ADDR, symbol_timer_csrbus_omni_data.read().to_uint64());
1815 }
1816 }
1817
1818 void peu_csr_omni::read_core_status(void) {
1819
1820 sc_uint<64> core_status_csrbus_read_data_reg;
1821
1822 for ( ; ; ) {
1823
1824 csr_port_sem.wait();
1825 LOG_DEBUG << "READ EVENT : Reading the CSR core_status ";
1826 core_status_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_CORE_STATUS_HW_ADDR);
1827 csr_port_sem.post();
1828 core_status_csrbus_read_data.write(core_status_csrbus_read_data_reg);
1829 wait (core_status_ev);
1830 }
1831
1832 }
1833
1834 void peu_csr_omni::write_core_status(void) {
1835
1836 while (true) {
1837 wait (core_status_csrbus_omni_data.value_changed_event());
1838 LOG_DEBUG << "WRITE EVENT : Writing the CSR core_status";
1839 core_status_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_CORE_STATUS_HW_ADDR, core_status_csrbus_omni_data.read().to_uint64());
1840 }
1841 }
1842
1843 void peu_csr_omni::read_event_err_log_en(void) {
1844
1845 sc_uint<64> event_err_log_en_csrbus_read_data_reg;
1846
1847 for ( ; ; ) {
1848
1849 csr_port_sem.wait();
1850 LOG_DEBUG << "READ EVENT : Reading the CSR event_err_log_en ";
1851 event_err_log_en_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_EVENT_ERR_LOG_EN_HW_ADDR);
1852 csr_port_sem.post();
1853 event_err_log_en_csrbus_read_data.write(event_err_log_en_csrbus_read_data_reg);
1854 wait (event_err_log_en_ev);
1855 }
1856
1857 }
1858
1859 void peu_csr_omni::write_event_err_log_en(void) {
1860
1861 while (true) {
1862 wait (event_err_log_en_csrbus_omni_data.value_changed_event());
1863 LOG_DEBUG << "WRITE EVENT : Writing the CSR event_err_log_en";
1864 event_err_log_en_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_EVENT_ERR_LOG_EN_HW_ADDR, event_err_log_en_csrbus_omni_data.read().to_uint64());
1865 }
1866 }
1867
1868 void peu_csr_omni::read_event_err_int_en(void) {
1869
1870 sc_uint<64> event_err_int_en_csrbus_read_data_reg;
1871
1872 for ( ; ; ) {
1873
1874 csr_port_sem.wait();
1875 LOG_DEBUG << "READ EVENT : Reading the CSR event_err_int_en ";
1876 event_err_int_en_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_EVENT_ERR_INT_EN_HW_ADDR);
1877 csr_port_sem.post();
1878 event_err_int_en_csrbus_read_data.write(event_err_int_en_csrbus_read_data_reg);
1879 wait (event_err_int_en_ev);
1880 }
1881
1882 }
1883
1884 void peu_csr_omni::write_event_err_int_en(void) {
1885
1886 while (true) {
1887 wait (event_err_int_en_csrbus_omni_data.value_changed_event());
1888 LOG_DEBUG << "WRITE EVENT : Writing the CSR event_err_int_en";
1889 event_err_int_en_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_EVENT_ERR_INT_EN_HW_ADDR, event_err_int_en_csrbus_omni_data.read().to_uint64());
1890 }
1891 }
1892
1893 void peu_csr_omni::read_event_err_int_sts(void) {
1894
1895 sc_uint<64> event_err_int_sts_csrbus_read_data_reg;
1896
1897 for ( ; ; ) {
1898
1899 csr_port_sem.wait();
1900 LOG_DEBUG << "READ EVENT : Reading the CSR event_err_int_sts ";
1901 event_err_int_sts_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_EVENT_ERR_INT_STS_HW_ADDR);
1902 csr_port_sem.post();
1903 event_err_int_sts_csrbus_read_data.write(event_err_int_sts_csrbus_read_data_reg);
1904 wait (event_err_int_sts_ev);
1905 }
1906
1907 }
1908
1909 void peu_csr_omni::write_event_err_int_sts(void) {
1910
1911 while (true) {
1912 wait (event_err_int_sts_csrbus_omni_data.value_changed_event());
1913 LOG_DEBUG << "WRITE EVENT : Writing the CSR event_err_int_sts";
1914 event_err_int_sts_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_EVENT_ERR_INT_STS_HW_ADDR, event_err_int_sts_csrbus_omni_data.read().to_uint64());
1915 }
1916 }
1917
1918 void peu_csr_omni::read_event_err_sts_clr_rw1c_alias(void) {
1919
1920 sc_uint<64> event_err_sts_clr_rw1c_alias_csrbus_read_data_reg;
1921
1922 for ( ; ; ) {
1923
1924 csr_port_sem.wait();
1925 LOG_DEBUG << "READ EVENT : Reading the CSR event_err_sts_clr_rw1c_alias ";
1926 event_err_sts_clr_rw1c_alias_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_HW_ADDR);
1927 csr_port_sem.post();
1928 event_err_sts_clr_rw1c_alias_csrbus_read_data.write(event_err_sts_clr_rw1c_alias_csrbus_read_data_reg);
1929 wait (event_err_sts_clr_rw1c_alias_ev);
1930 }
1931
1932 }
1933
1934 void peu_csr_omni::write_event_err_sts_clr_rw1c_alias(void) {
1935
1936 while (true) {
1937 wait (event_err_sts_clr_rw1c_alias_csrbus_omni_data.value_changed_event());
1938 LOG_DEBUG << "WRITE EVENT : Writing the CSR event_err_sts_clr_rw1c_alias";
1939 event_err_sts_clr_rw1c_alias_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_HW_ADDR, event_err_sts_clr_rw1c_alias_csrbus_omni_data.read().to_uint64());
1940 }
1941 }
1942
1943 void peu_csr_omni::read_event_err_sts_clr_rw1s_alias(void) {
1944
1945 sc_uint<64> event_err_sts_clr_rw1s_alias_csrbus_read_data_reg;
1946
1947 for ( ; ; ) {
1948
1949 csr_port_sem.wait();
1950 LOG_DEBUG << "READ EVENT : Reading the CSR event_err_sts_clr_rw1s_alias ";
1951 event_err_sts_clr_rw1s_alias_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_EVENT_ERR_STS_CLR_RW1S_ALIAS_HW_ADDR);
1952 csr_port_sem.post();
1953 event_err_sts_clr_rw1s_alias_csrbus_read_data.write(event_err_sts_clr_rw1s_alias_csrbus_read_data_reg);
1954 wait (event_err_sts_clr_rw1s_alias_ev);
1955 }
1956
1957 }
1958
1959 void peu_csr_omni::write_event_err_sts_clr_rw1s_alias(void) {
1960
1961 while (true) {
1962 wait (event_err_sts_clr_rw1s_alias_csrbus_omni_data.value_changed_event());
1963 LOG_DEBUG << "WRITE EVENT : Writing the CSR event_err_sts_clr_rw1s_alias";
1964 event_err_sts_clr_rw1s_alias_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_EVENT_ERR_STS_CLR_RW1S_ALIAS_HW_ADDR, event_err_sts_clr_rw1s_alias_csrbus_omni_data.read().to_uint64());
1965 }
1966 }
1967
1968 void peu_csr_omni::read_lnk_bit_err_cnt_1(void) {
1969
1970 sc_uint<64> lnk_bit_err_cnt_1_csrbus_read_data_reg;
1971
1972 for ( ; ; ) {
1973
1974 csr_port_sem.wait();
1975 LOG_DEBUG << "READ EVENT : Reading the CSR lnk_bit_err_cnt_1 ";
1976 lnk_bit_err_cnt_1_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_LNK_BIT_ERR_CNT_1_HW_ADDR);
1977 csr_port_sem.post();
1978 lnk_bit_err_cnt_1_csrbus_read_data.write(lnk_bit_err_cnt_1_csrbus_read_data_reg);
1979 wait (lnk_bit_err_cnt_1_ev);
1980 }
1981
1982 }
1983
1984 void peu_csr_omni::write_lnk_bit_err_cnt_1(void) {
1985
1986 while (true) {
1987 wait (lnk_bit_err_cnt_1_csrbus_omni_data.value_changed_event());
1988 LOG_DEBUG << "WRITE EVENT : Writing the CSR lnk_bit_err_cnt_1";
1989 lnk_bit_err_cnt_1_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_LNK_BIT_ERR_CNT_1_HW_ADDR, lnk_bit_err_cnt_1_csrbus_omni_data.read().to_uint64());
1990 }
1991 }
1992
1993 void peu_csr_omni::read_lnk_bit_err_cnt_2(void) {
1994
1995 sc_uint<64> lnk_bit_err_cnt_2_csrbus_read_data_reg;
1996
1997 for ( ; ; ) {
1998
1999 csr_port_sem.wait();
2000 LOG_DEBUG << "READ EVENT : Reading the CSR lnk_bit_err_cnt_2 ";
2001 lnk_bit_err_cnt_2_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_LNK_BIT_ERR_CNT_2_HW_ADDR);
2002 csr_port_sem.post();
2003 lnk_bit_err_cnt_2_csrbus_read_data.write(lnk_bit_err_cnt_2_csrbus_read_data_reg);
2004 wait (lnk_bit_err_cnt_2_ev);
2005 }
2006
2007 }
2008
2009 void peu_csr_omni::write_lnk_bit_err_cnt_2(void) {
2010
2011 while (true) {
2012 wait (lnk_bit_err_cnt_2_csrbus_omni_data.value_changed_event());
2013 LOG_DEBUG << "WRITE EVENT : Writing the CSR lnk_bit_err_cnt_2";
2014 lnk_bit_err_cnt_2_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_LNK_BIT_ERR_CNT_2_HW_ADDR, lnk_bit_err_cnt_2_csrbus_omni_data.read().to_uint64());
2015 }
2016 }
2017
2018 void peu_csr_omni::read_serdes_pll(void) {
2019
2020 sc_uint<64> serdes_pll_csrbus_read_data_reg;
2021
2022 for ( ; ; ) {
2023
2024 csr_port_sem.wait();
2025 LOG_DEBUG << "READ EVENT : Reading the CSR serdes_pll ";
2026 serdes_pll_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_SERDES_PLL_HW_ADDR);
2027 csr_port_sem.post();
2028 serdes_pll_csrbus_read_data.write(serdes_pll_csrbus_read_data_reg);
2029 wait (serdes_pll_ev);
2030 }
2031
2032 }
2033
2034 void peu_csr_omni::write_serdes_pll(void) {
2035
2036 while (true) {
2037 wait (serdes_pll_csrbus_omni_data.value_changed_event());
2038 LOG_DEBUG << "WRITE EVENT : Writing the CSR serdes_pll";
2039 serdes_pll_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_SERDES_PLL_HW_ADDR, serdes_pll_csrbus_omni_data.read().to_uint64());
2040 }
2041 }
2042
2043 void peu_csr_omni::read_serdes_receiver_lane_ctl(void) {
2044
2045 sc_uint<64> serdes_receiver_lane_ctl_csrbus_read_data_reg;
2046
2047 for ( ; ; ) {
2048
2049 csr_port_sem.wait();
2050 LOG_DEBUG << "READ EVENT : Reading the CSR serdes_receiver_lane_ctl ";
2051 serdes_receiver_lane_ctl_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_SERDES_RECEIVER_LANE_CTL_HW_ADDR);
2052 csr_port_sem.post();
2053 serdes_receiver_lane_ctl_csrbus_read_data.write(serdes_receiver_lane_ctl_csrbus_read_data_reg);
2054 wait (serdes_receiver_lane_ctl_ev);
2055 }
2056
2057 }
2058
2059 void peu_csr_omni::write_serdes_receiver_lane_ctl(void) {
2060
2061 while (true) {
2062 wait (serdes_receiver_lane_ctl_csrbus_omni_data.value_changed_event());
2063 LOG_DEBUG << "WRITE EVENT : Writing the CSR serdes_receiver_lane_ctl";
2064 serdes_receiver_lane_ctl_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_SERDES_RECEIVER_LANE_CTL_HW_ADDR, serdes_receiver_lane_ctl_csrbus_omni_data.read().to_uint64());
2065 }
2066 }
2067
2068 void peu_csr_omni::read_serdes_receiver_lane_status(void) {
2069
2070 sc_uint<64> serdes_receiver_lane_status_csrbus_read_data_reg;
2071
2072 for ( ; ; ) {
2073
2074 csr_port_sem.wait();
2075 LOG_DEBUG << "READ EVENT : Reading the CSR serdes_receiver_lane_status ";
2076 serdes_receiver_lane_status_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_SERDES_RECEIVER_LANE_STATUS_HW_ADDR);
2077 csr_port_sem.post();
2078 serdes_receiver_lane_status_csrbus_read_data.write(serdes_receiver_lane_status_csrbus_read_data_reg);
2079 wait (serdes_receiver_lane_status_ev);
2080 }
2081
2082 }
2083
2084 void peu_csr_omni::write_serdes_receiver_lane_status(void) {
2085
2086 while (true) {
2087 wait (serdes_receiver_lane_status_csrbus_omni_data.value_changed_event());
2088 LOG_DEBUG << "WRITE EVENT : Writing the CSR serdes_receiver_lane_status";
2089 serdes_receiver_lane_status_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_SERDES_RECEIVER_LANE_STATUS_HW_ADDR, serdes_receiver_lane_status_csrbus_omni_data.read().to_uint64());
2090 }
2091 }
2092
2093 void peu_csr_omni::read_serdes_xmitter_lane_ctl(void) {
2094
2095 sc_uint<64> serdes_xmitter_lane_ctl_csrbus_read_data_reg;
2096
2097 for ( ; ; ) {
2098
2099 csr_port_sem.wait();
2100 LOG_DEBUG << "READ EVENT : Reading the CSR serdes_xmitter_lane_ctl ";
2101 serdes_xmitter_lane_ctl_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_SERDES_XMITTER_LANE_CTL_HW_ADDR);
2102 csr_port_sem.post();
2103 serdes_xmitter_lane_ctl_csrbus_read_data.write(serdes_xmitter_lane_ctl_csrbus_read_data_reg);
2104 wait (serdes_xmitter_lane_ctl_ev);
2105 }
2106
2107 }
2108
2109 void peu_csr_omni::write_serdes_xmitter_lane_ctl(void) {
2110
2111 while (true) {
2112 wait (serdes_xmitter_lane_ctl_csrbus_omni_data.value_changed_event());
2113 LOG_DEBUG << "WRITE EVENT : Writing the CSR serdes_xmitter_lane_ctl";
2114 serdes_xmitter_lane_ctl_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_SERDES_XMITTER_LANE_CTL_HW_ADDR, serdes_xmitter_lane_ctl_csrbus_omni_data.read().to_uint64());
2115 }
2116 }
2117
2118 void peu_csr_omni::read_serdes_xmitter_lane_status(void) {
2119
2120 sc_uint<64> serdes_xmitter_lane_status_csrbus_read_data_reg;
2121
2122 for ( ; ; ) {
2123
2124 csr_port_sem.wait();
2125 LOG_DEBUG << "READ EVENT : Reading the CSR serdes_xmitter_lane_status ";
2126 serdes_xmitter_lane_status_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_SERDES_XMITTER_LANE_STATUS_HW_ADDR);
2127 csr_port_sem.post();
2128 serdes_xmitter_lane_status_csrbus_read_data.write(serdes_xmitter_lane_status_csrbus_read_data_reg);
2129 wait (serdes_xmitter_lane_status_ev);
2130 }
2131
2132 }
2133
2134 void peu_csr_omni::write_serdes_xmitter_lane_status(void) {
2135
2136 while (true) {
2137 wait (serdes_xmitter_lane_status_csrbus_omni_data.value_changed_event());
2138 LOG_DEBUG << "WRITE EVENT : Writing the CSR serdes_xmitter_lane_status";
2139 serdes_xmitter_lane_status_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_SERDES_XMITTER_LANE_STATUS_HW_ADDR, serdes_xmitter_lane_status_csrbus_omni_data.read().to_uint64());
2140 }
2141 }
2142
2143 void peu_csr_omni::read_serdes_macro_test_cfg(void) {
2144
2145 sc_uint<64> serdes_macro_test_cfg_csrbus_read_data_reg;
2146
2147 for ( ; ; ) {
2148
2149 csr_port_sem.wait();
2150 LOG_DEBUG << "READ EVENT : Reading the CSR serdes_macro_test_cfg ";
2151 serdes_macro_test_cfg_csrbus_read_data_reg = csr_port.read_csr(PEU_CSR_A_SERDES_MACRO_TEST_CFG_HW_ADDR);
2152 csr_port_sem.post();
2153 serdes_macro_test_cfg_csrbus_read_data.write(serdes_macro_test_cfg_csrbus_read_data_reg);
2154 wait (serdes_macro_test_cfg_ev);
2155 }
2156
2157 }
2158
2159 void peu_csr_omni::write_serdes_macro_test_cfg(void) {
2160
2161 while (true) {
2162 wait (serdes_macro_test_cfg_csrbus_omni_data.value_changed_event());
2163 LOG_DEBUG << "WRITE EVENT : Writing the CSR serdes_macro_test_cfg";
2164 serdes_macro_test_cfg_csrbus_read_data = csr_port.write_csr(PEU_CSR_A_SERDES_MACRO_TEST_CFG_HW_ADDR, serdes_macro_test_cfg_csrbus_omni_data.read().to_uint64());
2165 }
2166 }
2167
2168} // namespace pcie
2169
2170#endif // __EDG__
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