[OpenSPARC-T2-DV] / verif / model / pcie / peu / peu_defines.hpp

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: peu_defines.hpp
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#ifndef INC_peu_defines_hpp__
#define INC_peu_defines_hpp__

//-----------------------------------------------------------------------------
//****************************** GLOBAL CONSTANTS *****************************
//-----------------------------------------------------------------------------

#define PA_MSB  		42		// Physical address MSB

#define DEBUG_WDTH		8 		// Width of the Debug Ports
#define DBG_DATA_BITS	7,0 		// Debug data bits

#define PRF_ADDR_BITS	7,0
#define PRF_DATA_BITS	63,0

//-----------------------------------------------------------------------------
//******************************** CSR INTERFACE ******************************
//-----------------------------------------------------------------------------

#define CSR_ADDR_WDTH	27
#define CSR_ADDR_BITS	26,0
#define CSR_DATA_WDTH	64
#define CSR_DATA_BITS	63,0
#define CSR_RDMS_BITS	63,32
#define CSR_RDLS_BITS	31,0

#define CSR_CMND_WDTH	3
#define CSR_CMND_BITS	2,0
#define CSR_SRCB_WDTH	2
#define CSR_SRCB_BITS	1,0
#define CSR_STTS_BITS	2,0
#define CSR_TOUT_BITS	7,0

#define CSR_RING_WDTH	32
#define CSR_RING_BITS	CSR_RING_WDTH-1,0

#define CSR_PCKT_WDTH	96
#define CSR_PCKT_BITS	CSR_PCKT_WDTH-1,0

#define CSR_CMND_IDLE	0x0
#define CSR_CMND_RSET	0x1
#define CSR_CMND_RREQ	0x2
#define CSR_CMND_WREQ	0x3
#define CSR_CMND_RRSP	0x4
#define CSR_CMND_WRSP	0x5
#define CSR_CMND_RERR	0x6
#define CSR_CMND_WERR	0x7

#define CSR_PCKT_CMND_BITS	95,93
#define CSR_PCKT_ADDR_BITS	95,64
#define CSR_PCKT_RDMS_BITS	63,32
#define CSR_PCKT_RDLS_BITS	31,0

#define CSR_RING_CMND_BITS	31,29
#define CSR_RING_WRIT_BITS	29
#define CSR_RING_SRCB_BITS	28,27
#define CSR_RING_ADDR_BITS	CSR_ADDR_BITS

#define CSR_SRCB_JTAG	0
#define CSR_SRCB_SLOW	1
#define CSR_SRCB_MEDM	2
#define CSR_SRCB_FAST	3

//#######################################################
// Ingress Interface
//#######################################################

// ~~~~~~~~~~ Ingress IHB Interface ~~~~~~~~~~~~~~~~~

#define D2P_IHB_PTR_WDTH		7
#define D2P_IHB_PTR_BITS		D2P_IHB_PTR_WDTH-1,0

#define P2D_IHB_WPTR_WDTH		7
#define P2D_IHB_WPTR_BITS		P2D_IHB_WPTR_WDTH-1,0

#define D2P_IHB_ADDR_WDTH		6
#define D2P_IHB_ADDR_BITS		D2P_IHB_ADDR_WDTH-1,0
#define IHB_BUF_SIZE 			64	

#define P2D_IHB_DATA_WDTH		128
#define P2D_IHB_DATA_BITS		P2D_IHB_DATA_WDTH-1,0

#define P2D_IHB_DPAR_WDTH		4
#define P2D_IHB_DPAR_BITS		P2D_IHB_DPAR_WDTH-1,0

// ~~~~~~~~~~ Ingress IDB Interface ~~~~~~~~~~~~~~~~~

#define D2P_IDB_ADDR_WDTH        8                 // d2p_idb_addr
#define D2P_IDB_ADDR_BITS        D2P_IDB_ADDR_WDTH-1,0
#define IDB_BUF_SIZE			 256

#define P2D_IDB_DATA_WDTH        128               // p2d_idb_data
#define P2D_IDB_DATA_BITS        P2D_IDB_DATA_WDTH-1,0

#define P2D_IDB_DPAR_WDTH        4                 // p2d_idb_dpar
#define P2D_IDB_DPAR_BITS        P2D_IDB_DPAR_WDTH-1,0

// ~~~~~~~~~~ Ingress IBC Interface ~~~~~~~~~~~~~~~~~

#define D2P_IBC_DC_WDTH		12
#define D2P_IBC_DC_BITS		D2P_IBC_DC_WDTH-1,0

#define D2P_IBC_HC_WDTH		8
#define D2P_IBC_HC_BITS		D2P_IBC_HC_WDTH-1,0

#define D2P_IBC_NHC_WDTH         8                 // d2p_ibc_nhc
#define D2P_IBC_NHC_BITS         D2P_IBC_NHC_WDTH-1,0

#define D2P_IBC_PHC_WDTH         8                 // d2p_ibc_phc
#define D2P_IBC_PHC_BITS         D2P_IBC_PHC_WDTH-1,0

#define D2P_IBC_PDC_WDTH         12                // d2p_ibc_pdc
#define D2P_IBC_PDC_BITS         D2P_IBC_PDC_WDTH-1,0

// ~~~~~~~~~~ Ingress CTO Interface ~~~~~~~~~~~~~~~~~

#define P2D_CTO_TAG_WDTH         5                 // p2d_cto_tag
#define P2D_CTO_TAG_BITS         P2D_CTO_TAG_WDTH-1,0

//#######################################################
// Egress Interface
//#######################################################

// ~~~~~~~~~~ Egress EHB Interface ~~~~~~~~~~~~~~~~~

#define D2P_EHB_ADDR_WDTH        6                  // d2p_ehb_addr[5:0]
#define D2P_EHB_ADDR_BITS        D2P_EHB_ADDR_WDTH-1,0
#define EHB_BUF_SIZE			 64

#define D2P_EHB_DATA_WDTH        128                // d2p_ehb_data[127:0]
#define D2P_EHB_DATA_BITS        D2P_EHB_DATA_WDTH-1,0

#define D2P_EHB_DPAR_WDTH        4                  // d2p_ehb_dpar[3,0]
#define D2P_EHB_DPAR_BITS        D2P_EHB_DPAR_WDTH-1,0

// ~~~~~~~~~~ Egress EDB Interface ~~~~~~~~~~~~~~~~~

#define D2P_EDB_ADDR_WDTH        8                  // d2p_edb_addr[7:0]
#define D2P_EDB_ADDR_BITS        D2P_EDB_ADDR_WDTH-1,0
#define EDB_BUF_SIZE			 256

#define D2P_EDB_DATA_DW4_LSB     0 	
#define D2P_EDB_DATA_DW4_WDTH    32 	
#define D2P_EDB_DATA_DW4_MSB     D2P_EDB_DATA_DW4_LSB + D2P_EDB_DATA_DW4_WDTH - 1

#define D2P_EDB_DATA_DW3_LSB     D2P_EDB_DATA_DW4_LSB + D2P_EDB_DATA_DW4_WDTH 	
#define D2P_EDB_DATA_DW3_WDTH    32 	
#define D2P_EDB_DATA_DW3_MSB     D2P_EDB_DATA_DW3_LSB + D2P_EDB_DATA_DW3_WDTH - 1

#define D2P_EDB_DATA_DW2_LSB     D2P_EDB_DATA_DW3_LSB + D2P_EDB_DATA_DW3_WDTH 	
#define D2P_EDB_DATA_DW2_WDTH    32 	
#define D2P_EDB_DATA_DW2_MSB     D2P_EDB_DATA_DW2_LSB + D2P_EDB_DATA_DW2_WDTH - 1
 	
#define D2P_EDB_DATA_DW1_LSB     D2P_EDB_DATA_DW2_LSB + D2P_EDB_DATA_DW2_WDTH 	
#define D2P_EDB_DATA_DW1_WDTH    32 	
#define D2P_EDB_DATA_DW1_MSB     D2P_EDB_DATA_DW1_LSB + D2P_EDB_DATA_DW1_WDTH - 1
 
#define D2P_EDB_DATA_WDTH        D2P_EDB_DATA_DW1_LSB + D2P_EDB_DATA_DW1_WDTH
#define D2P_EDB_DATA_BITS        D2P_EDB_DATA_WDTH-1,0
		 			                 // d2p_edb_data[127:0]
#define D2P_EDB_DPAR_WDTH        4                  // d2p_edb_dpar[3:0]
#define D2P_EDB_DPAR_BITS        D2P_EDB_DPAR_WDTH-1,0

// ~~~~~~~~~~ Egress CREDIT Interface ~~~~~~~~~~~~~~~~~

#define P2D_EHB_ADDR_WDTH		 6

#define P2D_ECH_ADDR_WDTH		 6
#define P2D_ECH_RPTR_WDTH        6                  // p2d_ech_rptr[5:0]
#define P2D_ECH_RPTR_BITS        P2D_ECH_RPTR_WDTH-1,0

#define P2D_ERH_ADDR_WDTH		 6
#define P2D_ERH_RPTR_WDTH        6                  // p2d_erh_rptr[5:0]
#define P2D_ERH_RPTR_BITS        P2D_ERH_RPTR_WDTH-1,0

#define D2P_ECH_WPTR_WDTH        6                  // d2p_ech_wptr[5:0]
#define D2P_ECH_WPTR_BITS        D2P_ECH_WPTR_WDTH-1,0

#define D2P_ERH_WPTR_WDTH        6                  // d2p_erh_wptr[5:0]
#define D2P_ERH_WPTR_BITS        D2P_ERH_WPTR_WDTH-1,0

#define P2D_EDB_ADDR_WDTH		 7

#define P2D_ECD_ADDR_WDTH		 7
#define P2D_ECD_RPTR_WDTH        8                  // p2d_ecd_rptr[7:0]
#define P2D_ECD_RPTR_BITS        P2D_ECD_RPTR_WDTH-1,0

#define P2D_ERD_ADDR_WDTH		 7
#define P2D_ERD_RPTR_WDTH        8                  // p2d_erd_rptr[7:0]
#define P2D_ERD_RPTR_BITS        P2D_ERD_RPTR_WDTH-1,0


//#######################################################
// Ingress Interface
//#######################################################

//#######################################################
// CSR Interface
//#######################################################

#define P2D_MPS_WDTH             3                   // p2d_mps[2:0]
#define P2D_MPS_BITS             P2D_MPS_WDTH-1:0

#define D2P_CSR_RING_WDTH        96                 // d2p_csr_ring[99:0]
#define P2D_CSR_RING_WDTH        96                 // p2d_csr_ring[99:0]

//#######################################################
// DMC<->PEC (ILU<->TLU) spares
//#######################################################

#define D2P_SPARE_WDTH	5	// d2p_spare[4:0]
#define P2D_SPARE_WDTH	5	// p2d_spare[4:0]


//#######################################################
// PCI Express
//#######################################################

#define PCIE_HDR_FMT_BITS		126,125
#define PCIE_HDR_TYPE_BITS		124,120
#define PCIE_HDR_TC_BITS		118,116
#define PCIE_HDR_TD_BITS		111
#define PCIE_HDR_EP_BITS		110
#define PCIE_HDR_LEN_BITS		105,96
#define PCIE_HDR_MSG_BITS		71,64

#define PCIE_FMT_WDTH		2
#define PCIE_FMT_BITS		PCIE_FMT_WDTH-1,0

#define PCIE_TYPE_WDTH		5
#define PCIE_TYPE_BITS		PCIE_TYPE_WDTH-1,0

#define PCIE_TC_WDTH		3
#define PCIE_TC_BITS		PCIE_TC_WDTH-1,0

#define PCIE_LEN_WDTH		10
#define PCIE_LEN_BITS		PCIE_LEN_WDTH-1,0

#define PCIE_MSG_WDTH		8
#define PCIE_MSG_BITS		PCIE_MSG_WDTH-1,0

#define PCIE_BUS_NUM_WDTH		8
#define PCIE_BUS_NUM_BITS		PCIE_BUS_NUM_WDTH-1,0

#define PCIE_REQ_ID_WDTH		16
#define PCIE_REQ_ID_BITS		PCIE_REQ_ID_WDTH-1,0


#endif //INC_peu_defines_hpp__
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: peu_defines.hpp
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	#ifndef INC_peu_defines_hpp__
	36	#define INC_peu_defines_hpp__
	37
	38	//-----------------------------------------------------------------------------
	39	//**************************** GLOBAL CONSTANTS ***************************
	40	//-----------------------------------------------------------------------------
	41
	42	#define PA_MSB 42 // Physical address MSB
	43
	44	#define DEBUG_WDTH 8 // Width of the Debug Ports
	45	#define DBG_DATA_BITS 7,0 // Debug data bits
	46
	47	#define PRF_ADDR_BITS 7,0
	48	#define PRF_DATA_BITS 63,0
	49
	50	//-----------------------------------------------------------------------------
	51	//****************************** CSR INTERFACE ****************************
	52	//-----------------------------------------------------------------------------
	53
	54	#define CSR_ADDR_WDTH 27
	55	#define CSR_ADDR_BITS 26,0
	56	#define CSR_DATA_WDTH 64
	57	#define CSR_DATA_BITS 63,0
	58	#define CSR_RDMS_BITS 63,32
	59	#define CSR_RDLS_BITS 31,0
	60
	61	#define CSR_CMND_WDTH 3
	62	#define CSR_CMND_BITS 2,0
	63	#define CSR_SRCB_WDTH 2
	64	#define CSR_SRCB_BITS 1,0
65	#define CSR_STTS_BITS 2,0
66	#define CSR_TOUT_BITS 7,0
67
68	#define CSR_RING_WDTH 32
69	#define CSR_RING_BITS CSR_RING_WDTH-1,0
70
71	#define CSR_PCKT_WDTH 96
72	#define CSR_PCKT_BITS CSR_PCKT_WDTH-1,0
73
74	#define CSR_CMND_IDLE 0x0
75	#define CSR_CMND_RSET 0x1
76	#define CSR_CMND_RREQ 0x2
77	#define CSR_CMND_WREQ 0x3
78	#define CSR_CMND_RRSP 0x4
79	#define CSR_CMND_WRSP 0x5
80	#define CSR_CMND_RERR 0x6
81	#define CSR_CMND_WERR 0x7
82
83	#define CSR_PCKT_CMND_BITS 95,93
84	#define CSR_PCKT_ADDR_BITS 95,64
85	#define CSR_PCKT_RDMS_BITS 63,32
86	#define CSR_PCKT_RDLS_BITS 31,0
87
88	#define CSR_RING_CMND_BITS 31,29
89	#define CSR_RING_WRIT_BITS 29
90	#define CSR_RING_SRCB_BITS 28,27
91	#define CSR_RING_ADDR_BITS CSR_ADDR_BITS
92
93	#define CSR_SRCB_JTAG 0
94	#define CSR_SRCB_SLOW 1
95	#define CSR_SRCB_MEDM 2
96	#define CSR_SRCB_FAST 3
97
98	//#######################################################
99	// Ingress Interface
100	//#######################################################
101
102	// ~~~~~~~~~~ Ingress IHB Interface ~~~~~~~~~~~~~~~~~
103
104	#define D2P_IHB_PTR_WDTH 7
105	#define D2P_IHB_PTR_BITS D2P_IHB_PTR_WDTH-1,0
106
107	#define P2D_IHB_WPTR_WDTH 7
108	#define P2D_IHB_WPTR_BITS P2D_IHB_WPTR_WDTH-1,0
109
110	#define D2P_IHB_ADDR_WDTH 6
111	#define D2P_IHB_ADDR_BITS D2P_IHB_ADDR_WDTH-1,0
112	#define IHB_BUF_SIZE 64
113
114	#define P2D_IHB_DATA_WDTH 128
115	#define P2D_IHB_DATA_BITS P2D_IHB_DATA_WDTH-1,0
116
117	#define P2D_IHB_DPAR_WDTH 4
118	#define P2D_IHB_DPAR_BITS P2D_IHB_DPAR_WDTH-1,0
119
120	// ~~~~~~~~~~ Ingress IDB Interface ~~~~~~~~~~~~~~~~~
121
122	#define D2P_IDB_ADDR_WDTH 8 // d2p_idb_addr
123	#define D2P_IDB_ADDR_BITS D2P_IDB_ADDR_WDTH-1,0
124	#define IDB_BUF_SIZE 256
125
126	#define P2D_IDB_DATA_WDTH 128 // p2d_idb_data
127	#define P2D_IDB_DATA_BITS P2D_IDB_DATA_WDTH-1,0
128
129	#define P2D_IDB_DPAR_WDTH 4 // p2d_idb_dpar
130	#define P2D_IDB_DPAR_BITS P2D_IDB_DPAR_WDTH-1,0
131
132	// ~~~~~~~~~~ Ingress IBC Interface ~~~~~~~~~~~~~~~~~
133
134	#define D2P_IBC_DC_WDTH 12
135	#define D2P_IBC_DC_BITS D2P_IBC_DC_WDTH-1,0
136
137	#define D2P_IBC_HC_WDTH 8
138	#define D2P_IBC_HC_BITS D2P_IBC_HC_WDTH-1,0
139
140	#define D2P_IBC_NHC_WDTH 8 // d2p_ibc_nhc
141	#define D2P_IBC_NHC_BITS D2P_IBC_NHC_WDTH-1,0
142
143	#define D2P_IBC_PHC_WDTH 8 // d2p_ibc_phc
144	#define D2P_IBC_PHC_BITS D2P_IBC_PHC_WDTH-1,0
145
146	#define D2P_IBC_PDC_WDTH 12 // d2p_ibc_pdc
147	#define D2P_IBC_PDC_BITS D2P_IBC_PDC_WDTH-1,0
148
149	// ~~~~~~~~~~ Ingress CTO Interface ~~~~~~~~~~~~~~~~~
150
151	#define P2D_CTO_TAG_WDTH 5 // p2d_cto_tag
152	#define P2D_CTO_TAG_BITS P2D_CTO_TAG_WDTH-1,0
153
154	//#######################################################
155	// Egress Interface
156	//#######################################################
157
158	// ~~~~~~~~~~ Egress EHB Interface ~~~~~~~~~~~~~~~~~
159
160	#define D2P_EHB_ADDR_WDTH 6 // d2p_ehb_addr[5:0]
161	#define D2P_EHB_ADDR_BITS D2P_EHB_ADDR_WDTH-1,0
162	#define EHB_BUF_SIZE 64
163
164	#define D2P_EHB_DATA_WDTH 128 // d2p_ehb_data[127:0]
165	#define D2P_EHB_DATA_BITS D2P_EHB_DATA_WDTH-1,0
166
167	#define D2P_EHB_DPAR_WDTH 4 // d2p_ehb_dpar[3,0]
168	#define D2P_EHB_DPAR_BITS D2P_EHB_DPAR_WDTH-1,0
169
170	// ~~~~~~~~~~ Egress EDB Interface ~~~~~~~~~~~~~~~~~
171
172	#define D2P_EDB_ADDR_WDTH 8 // d2p_edb_addr[7:0]
173	#define D2P_EDB_ADDR_BITS D2P_EDB_ADDR_WDTH-1,0
174	#define EDB_BUF_SIZE 256
175
176	#define D2P_EDB_DATA_DW4_LSB 0
177	#define D2P_EDB_DATA_DW4_WDTH 32
178	#define D2P_EDB_DATA_DW4_MSB D2P_EDB_DATA_DW4_LSB + D2P_EDB_DATA_DW4_WDTH - 1
179
180	#define D2P_EDB_DATA_DW3_LSB D2P_EDB_DATA_DW4_LSB + D2P_EDB_DATA_DW4_WDTH
181	#define D2P_EDB_DATA_DW3_WDTH 32
182	#define D2P_EDB_DATA_DW3_MSB D2P_EDB_DATA_DW3_LSB + D2P_EDB_DATA_DW3_WDTH - 1
183
184	#define D2P_EDB_DATA_DW2_LSB D2P_EDB_DATA_DW3_LSB + D2P_EDB_DATA_DW3_WDTH
185	#define D2P_EDB_DATA_DW2_WDTH 32
186	#define D2P_EDB_DATA_DW2_MSB D2P_EDB_DATA_DW2_LSB + D2P_EDB_DATA_DW2_WDTH - 1
187
188	#define D2P_EDB_DATA_DW1_LSB D2P_EDB_DATA_DW2_LSB + D2P_EDB_DATA_DW2_WDTH
189	#define D2P_EDB_DATA_DW1_WDTH 32
190	#define D2P_EDB_DATA_DW1_MSB D2P_EDB_DATA_DW1_LSB + D2P_EDB_DATA_DW1_WDTH - 1
191
192	#define D2P_EDB_DATA_WDTH D2P_EDB_DATA_DW1_LSB + D2P_EDB_DATA_DW1_WDTH
193	#define D2P_EDB_DATA_BITS D2P_EDB_DATA_WDTH-1,0
194	// d2p_edb_data[127:0]
195	#define D2P_EDB_DPAR_WDTH 4 // d2p_edb_dpar[3:0]
196	#define D2P_EDB_DPAR_BITS D2P_EDB_DPAR_WDTH-1,0
197
198	// ~~~~~~~~~~ Egress CREDIT Interface ~~~~~~~~~~~~~~~~~
199
200	#define P2D_EHB_ADDR_WDTH 6
201
202	#define P2D_ECH_ADDR_WDTH 6
203	#define P2D_ECH_RPTR_WDTH 6 // p2d_ech_rptr[5:0]
204	#define P2D_ECH_RPTR_BITS P2D_ECH_RPTR_WDTH-1,0
205
206	#define P2D_ERH_ADDR_WDTH 6
207	#define P2D_ERH_RPTR_WDTH 6 // p2d_erh_rptr[5:0]
208	#define P2D_ERH_RPTR_BITS P2D_ERH_RPTR_WDTH-1,0
209
210	#define D2P_ECH_WPTR_WDTH 6 // d2p_ech_wptr[5:0]
211	#define D2P_ECH_WPTR_BITS D2P_ECH_WPTR_WDTH-1,0
212
213	#define D2P_ERH_WPTR_WDTH 6 // d2p_erh_wptr[5:0]
214	#define D2P_ERH_WPTR_BITS D2P_ERH_WPTR_WDTH-1,0
215
216	#define P2D_EDB_ADDR_WDTH 7
217
218	#define P2D_ECD_ADDR_WDTH 7
219	#define P2D_ECD_RPTR_WDTH 8 // p2d_ecd_rptr[7:0]
220	#define P2D_ECD_RPTR_BITS P2D_ECD_RPTR_WDTH-1,0
221
222	#define P2D_ERD_ADDR_WDTH 7
223	#define P2D_ERD_RPTR_WDTH 8 // p2d_erd_rptr[7:0]
224	#define P2D_ERD_RPTR_BITS P2D_ERD_RPTR_WDTH-1,0
225
226
227	//#######################################################
228	// Ingress Interface
229	//#######################################################
230
231	//#######################################################
232	// CSR Interface
233	//#######################################################
234
235	#define P2D_MPS_WDTH 3 // p2d_mps[2:0]
236	#define P2D_MPS_BITS P2D_MPS_WDTH-1:0
237
238	#define D2P_CSR_RING_WDTH 96 // d2p_csr_ring[99:0]
239	#define P2D_CSR_RING_WDTH 96 // p2d_csr_ring[99:0]
240
241	//#######################################################
242	// DMC<->PEC (ILU<->TLU) spares
243	//#######################################################
244
245	#define D2P_SPARE_WDTH 5 // d2p_spare[4:0]
246	#define P2D_SPARE_WDTH 5 // p2d_spare[4:0]
247
248
249
250	//#######################################################
251	// PCI Express
252	//#######################################################
253
254	#define PCIE_HDR_FMT_BITS 126,125
255	#define PCIE_HDR_TYPE_BITS 124,120
256	#define PCIE_HDR_TC_BITS 118,116
257	#define PCIE_HDR_TD_BITS 111
258	#define PCIE_HDR_EP_BITS 110
259	#define PCIE_HDR_LEN_BITS 105,96
260	#define PCIE_HDR_MSG_BITS 71,64
261
262	#define PCIE_FMT_WDTH 2
263	#define PCIE_FMT_BITS PCIE_FMT_WDTH-1,0
264
265	#define PCIE_TYPE_WDTH 5
266	#define PCIE_TYPE_BITS PCIE_TYPE_WDTH-1,0
267
268	#define PCIE_TC_WDTH 3
269	#define PCIE_TC_BITS PCIE_TC_WDTH-1,0
270
271	#define PCIE_LEN_WDTH 10
272	#define PCIE_LEN_BITS PCIE_LEN_WDTH-1,0
273
274	#define PCIE_MSG_WDTH 8
275	#define PCIE_MSG_BITS PCIE_MSG_WDTH-1,0
276
277	#define PCIE_BUS_NUM_WDTH 8
278	#define PCIE_BUS_NUM_BITS PCIE_BUS_NUM_WDTH-1,0
279
280	#define PCIE_REQ_ID_WDTH 16
281	#define PCIE_REQ_ID_BITS PCIE_REQ_ID_WDTH-1,0
282
283
284	#endif //INC_peu_defines_hpp__