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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / model / pcie / pl / ltssm.h
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AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: ltssm.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38// ========== Copyright Header Begin ==========================================
39//
40// OpenSPARC T2 Processor File: ltssm.h
41// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
42// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
43//
44// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
45//
46// This program is free software; you can redistribute it and/or modify
47// it under the terms of the GNU General Public License as published by
48// the Free Software Foundation; version 2 of the License.
49//
50// This program is distributed in the hope that it will be useful,
51// but WITHOUT ANY WARRANTY; without even the implied warranty of
52// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
53// GNU General Public License for more details.
54//
55// You should have received a copy of the GNU General Public License
56// along with this program; if not, write to the Free Software
57// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
58//
59// For the avoidance of doubt, and except that if any non-GPL license
60// choice is available it will apply instead, Sun elects to use only
61// the General Public License version 2 (GPLv2) at this time for any
62// software where a choice of GPL license versions is made
63// available with the language indicating that GPLv2 or any later version
64// may be used, or where a choice of which version of the GPL is applied is
65// otherwise unspecified.
66//
67// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
68// CA 95054 USA or visit www.sun.com if you need additional information or
69// have any questions.
70//
71// ========== Copyright Header End ============================================
72#ifndef INC_ltssm_h__
73#define INC_ltssm_h__
74#define IDLE 0
75#define ACTIVE 1
76#define DetectQuietDelay 10
77
78#ifdef LINK_1
79#define LINK_WIDTH 1
80#else
81#ifdef LINK_2
82#define LINK_WIDTH 2
83#else
84#ifdef LINK_4
85#define LINK_WIDTH 4
86#else
87#define LINK_WIDTH 8
88#endif
89#endif
90#endif
91
92#include "systemc.h"
93#include "pcie_common/csr_if_port.hpp"
94#include "pcie_common/peu_csr_defines.hpp"
95#include "pcie_common/symbol_encoding.hpp"
96#include "pcie_common/ilupeu_defines.h"
97#include "pcie_common/logger.hpp"
98#include "pl/encode_map.h"
99#include "pl/data_scrambler.h"
100#include "pl/running_disparity.h"
101
102#define curr_running_disp running_disparity::current_disparity()
103#define descrambler_i data_scrambler::descramble()
104#define scrambler_i data_scrambler::scramble()
105
106using namespace Logger;
107using namespace pcie;
108
109class ltssm : public sc_module
110{
111 public :
112 sc_in<sc_lv<LINK_WIDTH> > lane_in; // 10 bit lane
113 sc_in<sc_lv<LINK_WIDTH> > lane_in_bar;
114 sc_in<bool> link_clk;
115 sc_in<bool> reset_l;
116 sc_in<bool> reset_por_l;
117 sc_in<bool> q_not_empty;
118 sc_in<bool> start_reinit;
119 sc_out<bool> init_done;
120 sc_out<bool> init_done_rx;
121 sc_out<bool> frame_boundary_rx;
122 sc_out<bool> frame_boundary_tx;
123 sc_out <sc_lv<LINK_WIDTH> > lane_out;
124 sc_out <sc_lv<LINK_WIDTH> > lane_out_bar;
125 sc_out <bool> disable_scrambling;
126 sc_out <bool> last_idle_frame;
127 sc_out <bool> last_idle_frame_retraining;
128 sc_out <bool> ts1_pattern_received;
129 csr_if_port<CSR_ADDR_T, CSR_DATA_T> csr_port;
130
131 ltssm(sc_module_name _name) :
132 sc_module(_name),
133 csr_port("csr_port")
134 {
135 int i;
136 LOG_DEBUG << "LTSSM CTOR";
137 map_table = new encoder_map("map_table");
138 init_state = DETECT_QUIET; // Directly start from polling, by skipping detect state
139 init_state_rx = DETECT_QUIET;
140 write_init_done = false;
141 write_init_done_rx = false;
142 received_electrical_idle = false;
143 received_electrical_idle_constant_voltage = false;
144 constant_voltage_count = 0;
145 toRecovery = false;
146 received_skp_ordered_set = false;
147 received_2xts1_hot_reset = false;
148 ts1_hot_reset_count = 0;
149 from_cfg_lanenum_wait = false;
150 start_pattern_aligned = false;
151 first_retrain_idle_detection = true;
152 com_detected_tx = false;
153 frame_boundary_tx_counter = 0;
154 start_frame_boundary_tx = false;
155 stage_init_state_rx = false;
156 stage_init_state = false;
157 retraining = false;
158 this_is_retraining = false;
159 enter_drain_state = false;
160 disable_link_reg = false;
161 disable_scrambling_reg = false;
162 transmitted_16xts1_disabled = false;
163 transmitted_1xelec_idle = false;
164 lock_negedge_clock = false;
165 done_last_idle = 0;
166 done_last_idle_retrain = 0;
167 ireg = 0;
168 ts1_disabled_bit = 0;
169 frame_boundary_detected = 0;
170 frame_boundary_tx_detected = 0;
171 ts1_disabled_pattern_count = 0;
172 sym_counter = 0;
173 lock_counter = 0;
174 start_ordered_set = 0;
175 ts1_count = 0;
176 ts2_pattern_bit = 0;
177 elec_idle_pattern_bit = 0;
178 idle_pattern_bit = 0;
179 general_idle_pattern_bit = 0;
180 generated_pattern = 0;
181 ts1_non_pad_link_bit = 0;
182 ts1_non_pad_link_lane = 0;
183 ts1_non_pad_lane_bit = 0;
184 ts1_non_pad_diff_lane_bit = 0;
185 ts1_disable_link_count = 0;
186 ts1_disable_scrambling_count = 0;
187 this_ts1_2 = 0;
188 idl_count = 0;
189 ts1_2 = 0x0000000000000000000000000000000000000000;
190 electrical_idle_constant_voltage_set = 0x3ff;
191 symbol_count = 0;
192 come_next_time = 0;
193 transmit_ts1_count = 0;
194 transmit_ts2_count = 0;
195 transmit_idl_count = 0;
196 transmit_failover_ts2_count = 0;
197 transmitted_ts1_pattern = 0;
198 transmitted_ts2_pattern = 0;
199 transmitted_idl_pattern = 0;
200 link_field_is_non_PAD_ts1 = 0;
201 lane_field_is_non_PAD_ts1 = 0;
202 lane_field_is_non_PAD_ts2 = 0;
203 move_to_cfg_lanenum_wait = 0;
204 move_to_cfg_lanenum_accept = 0;
205 move_to_detect_quiet = 0;
206 symbol_num = 0;
207 ts1_pattern_received.initialize(false);
208
209 for(i=0;i<160;i++)
210 {
211 ts1_link_num_non_PAD[i] = 0x00000000;
212 ts1_lane_num_non_PAD[i] = 0x00000000;
213 ts1_link_lane_non_PAD[i] = 0x00000000;
214 }
215 for(i=0;i<LINK_WIDTH;i++)
216 first_packet[i] = true;
217
218 SC_THREAD(assign_block2);
219 SC_THREAD(rx_block);
220 SC_THREAD(init_state_machine);
221 SC_THREAD(counter_block0);
222 SC_THREAD(counter_block2);
223 SC_THREAD(counter_block4);
224 SC_THREAD(in_block);
225 SC_THREAD(frame_boundary_assign);
226 SC_THREAD(frame_boundary_assign_rx);
227 SC_THREAD(init_state_machine_rx);
228 SC_THREAD(read_csr_block);
229 SC_THREAD(read_csr1_block);
230 SC_THREAD(tx_block);
231 }
232
233 SC_HAS_PROCESS(ltssm);
234
235 sc_event csr_core_status_ev;
236 sc_event link_sts_csr_ev;
237 sc_event macl_pcs_ctl_ev;
238
239 private:
240 void set_delim_value(int set,int i);
241 void reset_var_detect_quiet();
242 encoder_map *map_table;
243 map<int,int>::iterator map_iter;
244 sc_bv<10> ireg_in[LINK_WIDTH];
245 sc_bv<10> ireg_in_bar[LINK_WIDTH];
246 sc_bv<10> ireg_in_p[LINK_WIDTH];
247 sc_bv<10> ireg_in_p_bar[LINK_WIDTH];
248 sc_bv<10> ireg_in_p_p[LINK_WIDTH];
249 sc_bv<10> ireg_in_p_p_bar[LINK_WIDTH];
250 sc_bv<10> ts1_lane_diff_non_PAD[LINK_WIDTH];
251 sc_bv<10> ts2_lane_diff_non_PAD[LINK_WIDTH];
252 sc_bv<10> ts1_lane_diff_non_PAD_tmp[LINK_WIDTH];
253 sc_bv<10> out_reg_ser;
254 sc_bv<10> out_reg_ser_bar;
255 sc_bv<LINK_WIDTH> out_reg;
256 sc_bv<LINK_WIDTH> out_reg_bar;
257 sc_bv<LINK_WIDTH> in_val;
258 sc_bv<LINK_WIDTH> in_val_bar;
259 sc_bv<LINK_WIDTH> ireg;
260 sc_bv<LINK_WIDTH> ireg_bar;
261 bool com_detected;
262 bool enter_drain_state;
263 bool negedge_skip_this;
264 bool come_next_time;
265 bool retraining;
266 bool this_is_retraining;
267 bool frame_boundary_detected;
268 bool frame_boundary_tx_detected;
269 bool first_packet[LINK_WIDTH];
270 bool first_retrain_idle_detection;
271 int done_last_idle;
272 int done_last_idle_retrain;
273
274 sc_bv<160> ts1_2;
275 sc_bv<160> disabled_set[LINK_WIDTH];
276 sc_bv<160> ts1_2_negedge;
277 sc_bv<160> ts1_2_serial[LINK_WIDTH];
278 sc_bv<160> ts1_2_serial_negedge[LINK_WIDTH];
279 sc_bv<160> ts1_set,ts2_set;
280 sc_bv<160> ts1_set_const[LINK_WIDTH],ts2_set_const[LINK_WIDTH];
281 sc_bv<10> ts1_2_N_FTS;
282 sc_bv<10> ts1_2_rate_ID;
283 sc_bv<8> ts1_trn_ctrl;
284 sc_bv<10> ts2_trn_ctrl;
285 sc_bv<10> ts1_2_TSID;
286 bool disable_scrambling_reg;
287 bool disable_link_reg;
288 bool write_init_done;
289 bool write_init_done_rx;
290 bool stage_init_state_rx;
291 bool stage_init_state;
292 bool start_pattern_aligned;
293 bool lock_negedge_clock;
294 sc_bv<10> idle_set[LINK_WIDTH];
295 sc_bv<10> idle_set_negedge[LINK_WIDTH];
296 sc_bv<40> fts_set;
297 sc_bv<40> fts_set_negedge;
298 sc_bv<40> skip_set;
299 sc_bv<40> skip_set_negedge;
300 sc_bv<10> training_ctl;
301 sc_bv<10> ts1_2_link_num[LINK_WIDTH];
302 sc_bv<10> ts1_2_lane_num[LINK_WIDTH];
303 sc_bv<LINK_WIDTH> transmit_link_num_non_PAD;
304 sc_bv<LINK_WIDTH> transmit_lane_num_non_PAD;
305 sc_bv<160> ts1_link_num_non_PAD[LINK_WIDTH];
306 sc_bv<160> ts1_lane_num_non_PAD[LINK_WIDTH];
307 sc_bv<160> ts1_link_lane_non_PAD[LINK_WIDTH];
308 sc_bv<160> ts2_link_lane_non_PAD[LINK_WIDTH];
309 sc_bv<40> idle_set_const[LINK_WIDTH];
310 sc_bv<40> elec_idle_set[LINK_WIDTH];
311 sc_bv<40> electrical_idle_set;
312 sc_bv<10> electrical_idle_constant_voltage_set;
313 sc_bv<40> electrical_idle_set_negedge;
314 sc_bv<10> encoded_value[256];
315 sc_bv<10> neg_encoded_value[256];
316 sc_bv<64> link_ctl_csr;
317 sc_bv<64> macl_pcs_ctl_csr;
318 sc_signal<bool> frame_boundary_reg;
319 sc_signal<bool> frame_boundary_reg_tx;
320 bool com_detected_tx;
321 bool start_frame_boundary_tx;
322 int frame_boundary_tx_counter;
323 int ts1_disabled_pattern_count;
324
325 bool start_ordered_set;
326 bool move_to_cfg_lanenum_wait,move_to_detect_quiet,move_to_cfg_lanenum_accept;
327 int generated_pattern ;
328 int elec_idle_pattern_bit;
329 int ts1_disabled_bit;
330 int init_state;
331 int prev_init_state;
332 int init_state_rx;
333 int lock_counter;
334 int sym_counter;
335 int ts1_count,ts1_hot_reset_count,ts2_count,transmit_ts1_count,transmit_ts2_count,transmit_idl_count,transmit_failover_ts2_count;
336 int lane_field_is_PAD_ts1,link_field_is_PAD_ts1,lane_field_is_PAD_ts2,link_field_is_PAD_ts2;
337 int link_field_PAD_ts1_ok,link_field_PAD_ts2_ok,lane_field_PAD_ts1_ok,lane_field_PAD_ts2_ok;
338 int link_field_non_PAD_ts1_ok,link_field_non_PAD_ts2_ok;
339 bool this_ts1_2;
340 int ts1_disable_link_count;
341 int ts1_disable_scrambling_count;
342 bool received_8xts2_sets,received_8xts1_sets,received_8xidl_sets,transmitted_16xts2_sets,transmitted_16xidl_sets,transmitted_1024xts1_2sets;
343 bool transmitted_1xelec_idle;
344 bool received_1xts2_sets,received_1xts1_sets,received_1xidl_sets;
345 bool received_electrical_idle,received_skp_ordered_set;
346 bool received_electrical_idle_constant_voltage;
347 bool received_2xts1_hot_reset;
348 int constant_voltage_count;
349 bool from_cfg_lanenum_wait;
350 bool toRecovery;
351 bool toHotReset1;
352 bool transmitted_16xts1_disabled;
353 int symbol_count;
354 int idl_count;
355 int ts2_pattern_bit,idle_pattern_bit,ts1_pattern_bit,ts1_non_pad_link_bit,ts1_non_pad_link_lane,ts1_non_pad_lane_bit,general_idle_pattern_bit;
356 int ts1_non_pad_diff_lane_bit;
357 int ts2_failover_pattern_bit;
358 int transmitted_ts1_pattern,transmitted_ts2_pattern,transmitted_idl_pattern;
359 int link_field_is_non_PAD_ts1,lane_field_is_non_PAD_ts1,link_field_is_non_PAD_ts2,lane_field_is_non_PAD_ts2;
360 int symbol_num;
361
362 CSR_DATA_T ltssm_control_reg; /** 006E2050 */
363 CSR_DATA_T core_status_reg; /** 006E2100 */
364
365
366 //Module threads and methods
367 void in_block();
368 void read_csr_block(); ///< Read LNK_CTL_HW CSR to look at disable link/scrambling etc
369 void read_csr1_block(); ///< This CSR Read is for HOT-RESET control
370 void assign_block2();
371 void frame_boundary_assign_rx();
372 void frame_boundary_assign();
373 void counter_block0(); ///< Counter block for receive side
374 void counter_block2(); ///< Counter block for receive side to check for COM_DETECTED
375 void counter_block4(); ///< Staged negedge_clk in data read
376 void reg_block1(); ///< Main block to receive/transmit data based on current LTSSM state
377 void tx_block();
378 void rx_block(); /// Function for teh receive port processing
379 void init_state_machine(); ///< always @(negedge frame_boundary)
380 void init_state_machine_rx();
381};
382
383#endif // INC_ltssm_h__
Full OpenSPARC design & verification tarball including full HDL.