[OpenSPARC-T2-DV] / verif / model / pcie / pl / pl_top.h

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: pl_top.h
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pl_top.h
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#ifndef INC_pl_top_h__
#define INC_pl_top_h__

#ifndef __EDG__

#include <systemc.h>
#include <math.h>
#include "pcie_common/config.hpp"
#include "pcie_common/pciePacket.hpp"
#include "pcie_common/logger.hpp"
#include "pcie_common/symbol_encoding.hpp"
#include "data_scrambler.h"
#include "encode_map.h"
#include "pl/running_disparity.h"
#include <map>

#include "pcie_common/data_port.hpp"

USING_NAMESPACE(pcie)
USING_NAMESPACE(Logger)

#ifdef LINK_1
#define LINK_WIDTH 1
#else
#ifdef LINK_2
#define LINK_WIDTH 2
#else
#ifdef LINK_4
#define LINK_WIDTH 4
#else
#define LINK_WIDTH 8
#endif
#endif
#endif

#define curr_running_disp running_disparity::current_disparity()
#define scrambler_i data_scrambler::scramble()
#define descrambler_i data_scrambler::descramble()

class pl_top : public sc_module
{
    public :
        /// Instance of read interface to fifo channel
        data_in_port<RefPciePacket> dll_pl_dllp_in;
        data_in_port<RefPciePacket> dll_pl_tlp_in;
        data_out_port<RefPciePacket> pl_dll_out;

        // Encoded data signals go into the serializer....
        sc_out<sc_lv<LINK_WIDTH> > encoded_data0;
        sc_out<sc_lv<LINK_WIDTH> > encoded_data1;
        sc_out<sc_lv<LINK_WIDTH> > encoded_data2;
        sc_out<sc_lv<LINK_WIDTH> > encoded_data3;
        sc_out<sc_lv<LINK_WIDTH> > encoded_data4;
        sc_out<sc_lv<LINK_WIDTH> > encoded_data5;
        sc_out<sc_lv<LINK_WIDTH> > encoded_data6;
        sc_out<sc_lv<LINK_WIDTH> > encoded_data7;
        sc_out<sc_lv<LINK_WIDTH> > encoded_data8;
        sc_out<sc_lv<LINK_WIDTH> > encoded_data9;
        sc_out <bool> sym_boundary;
        sc_out <bool> q_not_empty;
        sc_out <bool> start_reinit;
        sc_out <bool> stage_reinit;
        sc_out<bool > PhysicalLinkUp;

        /// These are the signals which are inputs from the deserializer
        sc_in<sc_lv<LINK_WIDTH> > deser_data0;
        sc_in<sc_lv<LINK_WIDTH> > deser_data1;
        sc_in<sc_lv<LINK_WIDTH> > deser_data2;
        sc_in<sc_lv<LINK_WIDTH> > deser_data3;
        sc_in<sc_lv<LINK_WIDTH> > deser_data4;
        sc_in<sc_lv<LINK_WIDTH> > deser_data5;
        sc_in<sc_lv<LINK_WIDTH> > deser_data6;
        sc_in<sc_lv<LINK_WIDTH> > deser_data7;
        sc_in<sc_lv<LINK_WIDTH> > deser_data8;
        sc_in<sc_lv<LINK_WIDTH> > deser_data9;
        sc_in<sc_lv<LINK_WIDTH> > deser_data0_b;
        sc_in<sc_lv<LINK_WIDTH> > deser_data1_b;
        sc_in<sc_lv<LINK_WIDTH> > deser_data2_b;
        sc_in<sc_lv<LINK_WIDTH> > deser_data3_b;
        sc_in<sc_lv<LINK_WIDTH> > deser_data4_b;
        sc_in<sc_lv<LINK_WIDTH> > deser_data5_b;
        sc_in<sc_lv<LINK_WIDTH> > deser_data6_b;
        sc_in<sc_lv<LINK_WIDTH> > deser_data7_b;
        sc_in<sc_lv<LINK_WIDTH> > deser_data8_b;
        sc_in<sc_lv<LINK_WIDTH> > deser_data9_b;
        sc_in<bool> frm_boundary_deser;
        sc_in<bool> disable_scrambling;
        sc_in<bool> link_clk;
        sc_in<bool> init_done;
        sc_in<bool> init_done_rx;
        sc_in<bool> frame_boundary_ltssm_tx;
        sc_in<bool> last_idle_frame;
        sc_in<bool> reset_l;
        sc_in<bool> reset_por_l;
        sc_in<bool> ts1_pattern_received;


        pl_top(sc_module_name _name) :
            sc_module(_name),
            dll_pl_tlp_in("dll_pl_tlp_in"),
            dll_pl_dllp_in("dll_pl_dllp_in"),
            pl_dll_out("pl_dll_out")
        {
            map_table = new encoder_map("encoder_map");
            finished_sending_pkt = false;
            SC_THREAD(ingress_process_packet);
            SC_THREAD(process_packet);
            SC_THREAD(check_reinit);
            SC_THREAD(check_stage_reinit);
            start_reinit.initialize(true);
            stage_reinit.initialize(true);
        }

        SC_HAS_PROCESS(pl_top);


    private :
        bool interleave_idle;
        bool xtracted_data_c[50000];
        bool finished_sending_pkt;
        bool initialization_done;

        unsigned int bitlane[10];
        sc_lv<10> encoded_data;
        sc_lv<LINK_WIDTH> ingr_xtracted_data[50000];
        sc_lv<LINK_WIDTH> ingr_xtracted_data_b[50000];
        sc_lv<10> ingr_decoded_data[50000];
        sc_lv<8> ingr_xtracted_byte[50000];
        bool ingr_xtracted_byte_c[50000];
        sc_lv<10> xtracted_data[50000];
        sc_int<10> ingress_data[50000];
        sc_uint<LINK_WIDTH> lane_data_bit[10];
        sc_lv <LINK_WIDTH> lane_data[10];
        sc_lv<10> ingr_lane_data[LINK_WIDTH];
        RefPciePacket global_packet;
        RefPciePacket global_ingress_packet;
        encoder_map *map_table;
        int this_pkt_size;


        void process_packet(); // Transmit port processing of packets
        void check_reinit(); // For recovery state control handover to LTSSM
        void check_stage_reinit(); // Recovery state transition staging
        void ingress_process_packet(); // Receiver/Ingress process packet

};

#endif // __EDG__

#endif // inc_pl_top_h__
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: pl_top.h
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	// ========== Copyright Header Begin ==========================================
	39	//
	40	// OpenSPARC T2 Processor File: pl_top.h
	41	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	42	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	43	//
	44	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	45	//
	46	// This program is free software; you can redistribute it and/or modify
	47	// it under the terms of the GNU General Public License as published by
	48	// the Free Software Foundation; version 2 of the License.
	49	//
	50	// This program is distributed in the hope that it will be useful,
	51	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	52	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	53	// GNU General Public License for more details.
	54	//
	55	// You should have received a copy of the GNU General Public License
	56	// along with this program; if not, write to the Free Software
	57	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	58	//
	59	// For the avoidance of doubt, and except that if any non-GPL license
	60	// choice is available it will apply instead, Sun elects to use only
	61	// the General Public License version 2 (GPLv2) at this time for any
	62	// software where a choice of GPL license versions is made
	63	// available with the language indicating that GPLv2 or any later version
	64	// may be used, or where a choice of which version of the GPL is applied is
65	// otherwise unspecified.
66	//
67	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
68	// CA 95054 USA or visit www.sun.com if you need additional information or
69	// have any questions.
70	//
71	// ========== Copyright Header End ============================================
72	#ifndef INC_pl_top_h__
73	#define INC_pl_top_h__
74
75	#ifndef __EDG__
76
77	#include <systemc.h>
78	#include <math.h>
79	#include "pcie_common/config.hpp"
80	#include "pcie_common/pciePacket.hpp"
81	#include "pcie_common/logger.hpp"
82	#include "pcie_common/symbol_encoding.hpp"
83	#include "data_scrambler.h"
84	#include "encode_map.h"
85	#include "pl/running_disparity.h"
86	#include <map>
87
88	#include "pcie_common/data_port.hpp"
89
90	USING_NAMESPACE(pcie)
91	USING_NAMESPACE(Logger)
92
93	#ifdef LINK_1
94	#define LINK_WIDTH 1
95	#else
96	#ifdef LINK_2
97	#define LINK_WIDTH 2
98	#else
99	#ifdef LINK_4
100	#define LINK_WIDTH 4
101	#else
102	#define LINK_WIDTH 8
103	#endif
104	#endif
105	#endif
106
107	#define curr_running_disp running_disparity::current_disparity()
108	#define scrambler_i data_scrambler::scramble()
109	#define descrambler_i data_scrambler::descramble()
110
111	class pl_top : public sc_module
112	{
113	public :
114	/// Instance of read interface to fifo channel
115	data_in_port<RefPciePacket> dll_pl_dllp_in;
116	data_in_port<RefPciePacket> dll_pl_tlp_in;
117	data_out_port<RefPciePacket> pl_dll_out;
118
119	// Encoded data signals go into the serializer....
120	sc_out<sc_lv<LINK_WIDTH> > encoded_data0;
121	sc_out<sc_lv<LINK_WIDTH> > encoded_data1;
122	sc_out<sc_lv<LINK_WIDTH> > encoded_data2;
123	sc_out<sc_lv<LINK_WIDTH> > encoded_data3;
124	sc_out<sc_lv<LINK_WIDTH> > encoded_data4;
125	sc_out<sc_lv<LINK_WIDTH> > encoded_data5;
126	sc_out<sc_lv<LINK_WIDTH> > encoded_data6;
127	sc_out<sc_lv<LINK_WIDTH> > encoded_data7;
128	sc_out<sc_lv<LINK_WIDTH> > encoded_data8;
129	sc_out<sc_lv<LINK_WIDTH> > encoded_data9;
130	sc_out <bool> sym_boundary;
131	sc_out <bool> q_not_empty;
132	sc_out <bool> start_reinit;
133	sc_out <bool> stage_reinit;
134	sc_out<bool > PhysicalLinkUp;
135
136	/// These are the signals which are inputs from the deserializer
137	sc_in<sc_lv<LINK_WIDTH> > deser_data0;
138	sc_in<sc_lv<LINK_WIDTH> > deser_data1;
139	sc_in<sc_lv<LINK_WIDTH> > deser_data2;
140	sc_in<sc_lv<LINK_WIDTH> > deser_data3;
141	sc_in<sc_lv<LINK_WIDTH> > deser_data4;
142	sc_in<sc_lv<LINK_WIDTH> > deser_data5;
143	sc_in<sc_lv<LINK_WIDTH> > deser_data6;
144	sc_in<sc_lv<LINK_WIDTH> > deser_data7;
145	sc_in<sc_lv<LINK_WIDTH> > deser_data8;
146	sc_in<sc_lv<LINK_WIDTH> > deser_data9;
147	sc_in<sc_lv<LINK_WIDTH> > deser_data0_b;
148	sc_in<sc_lv<LINK_WIDTH> > deser_data1_b;
149	sc_in<sc_lv<LINK_WIDTH> > deser_data2_b;
150	sc_in<sc_lv<LINK_WIDTH> > deser_data3_b;
151	sc_in<sc_lv<LINK_WIDTH> > deser_data4_b;
152	sc_in<sc_lv<LINK_WIDTH> > deser_data5_b;
153	sc_in<sc_lv<LINK_WIDTH> > deser_data6_b;
154	sc_in<sc_lv<LINK_WIDTH> > deser_data7_b;
155	sc_in<sc_lv<LINK_WIDTH> > deser_data8_b;
156	sc_in<sc_lv<LINK_WIDTH> > deser_data9_b;
157	sc_in<bool> frm_boundary_deser;
158	sc_in<bool> disable_scrambling;
159	sc_in<bool> link_clk;
160	sc_in<bool> init_done;
161	sc_in<bool> init_done_rx;
162	sc_in<bool> frame_boundary_ltssm_tx;
163	sc_in<bool> last_idle_frame;
164	sc_in<bool> reset_l;
165	sc_in<bool> reset_por_l;
166	sc_in<bool> ts1_pattern_received;
167
168
169	pl_top(sc_module_name _name) :
170	sc_module(_name),
171	dll_pl_tlp_in("dll_pl_tlp_in"),
172	dll_pl_dllp_in("dll_pl_dllp_in"),
173	pl_dll_out("pl_dll_out")
174	{
175	map_table = new encoder_map("encoder_map");
176	finished_sending_pkt = false;
177	SC_THREAD(ingress_process_packet);
178	SC_THREAD(process_packet);
179	SC_THREAD(check_reinit);
180	SC_THREAD(check_stage_reinit);
181	start_reinit.initialize(true);
182	stage_reinit.initialize(true);
183	}
184
185	SC_HAS_PROCESS(pl_top);
186
187
188
189
190	private :
191	bool interleave_idle;
192	bool xtracted_data_c[50000];
193	bool finished_sending_pkt;
194	bool initialization_done;
195
196	unsigned int bitlane[10];
197	sc_lv<10> encoded_data;
198	sc_lv<LINK_WIDTH> ingr_xtracted_data[50000];
199	sc_lv<LINK_WIDTH> ingr_xtracted_data_b[50000];
200	sc_lv<10> ingr_decoded_data[50000];
201	sc_lv<8> ingr_xtracted_byte[50000];
202	bool ingr_xtracted_byte_c[50000];
203	sc_lv<10> xtracted_data[50000];
204	sc_int<10> ingress_data[50000];
205	sc_uint<LINK_WIDTH> lane_data_bit[10];
206	sc_lv <LINK_WIDTH> lane_data[10];
207	sc_lv<10> ingr_lane_data[LINK_WIDTH];
208	RefPciePacket global_packet;
209	RefPciePacket global_ingress_packet;
210	encoder_map *map_table;
211	int this_pkt_size;
212
213
214	void process_packet(); // Transmit port processing of packets
215	void check_reinit(); // For recovery state control handover to LTSSM
216	void check_stage_reinit(); // Recovery state transition staging
217	void ingress_process_packet(); // Receiver/Ingress process packet
218
219	};
220
221	#endif // __EDG__
222
223	#endif // inc_pl_top_h__