projects / OpenSPARC-T2-DV / blame
| Commit | Line | Data |
|---|---|---|
| 86530b38 AT |
1 | #ifndef INC_rsb_hpp__ |
| 2 | #define INC_rsb_hpp__ | |
| 3 | ||
| 4 | #include <systemc.h> | |
| 5 | ||
| 6 | #include "pcie_common/config.hpp" | |
| 7 | #include "pcie_common/pciePacket.hpp" | |
| 8 | ||
| 9 | #include "pcie_common/data_port.hpp" | |
| 10 | #include "pcie_common/csr_if_port.hpp" | |
| 11 | #include "pcie_common/peu_csr_defines.hpp" | |
| 12 | #include "pcie_common/peu_defines.hpp" | |
| 13 | ||
| 14 | #include "tlm.h" | |
| 15 | ||
| 16 | using tlm::tlm_transport_if; | |
| 17 | using tlm::tlm_slave_if; | |
| 18 | ||
| 19 | #define NUM_RSB_ENTRIES 32 | |
| 20 | #define RSB_TAG_SIZE 4 | |
| 21 | #define CTO_TAG_SIZE 5 | |
| 22 | ||
| 23 | #include <queue> | |
| 24 | ||
| 25 | #define WAIT(__EV__) if(!POR_RESET) wait( __EV__ | reset_ev); \ | |
| 26 | if(POR_RESET) {LOG_WARNING<<"RSB: WAIT throwing an exception"; throw sc_exception();} | |
| 27 | ||
| 28 | namespace pcie { | |
| 29 | ||
| 30 | class rsb_data | |
| 31 | { | |
| 32 | public: | |
| 33 | sc_uint<CTO_TAG_SIZE> tlp_tag; ///< RSB index field | |
| 34 | sc_uint<16> req_id; ///< requester id | |
| 35 | vector < sc_uint < 8 > > raw_payload; | |
| 36 | bool vld; ///< Valid bit | |
| 37 | sc_uint<12> expect_bc; ///< expected byte count value | |
| 38 | sc_uint<7> expect_la; ///< expected last address bits | |
| 39 | sc_time timeout; ///< timeout value | |
| 40 | bool infTO; ///< Infinite timeout flag | |
| 41 | ||
| 42 | rsb_data(){ | |
| 43 | tlp_tag = 0; | |
| 44 | raw_payload.resize(1); | |
| 45 | raw_payload[0]=0; | |
| 46 | vld = false; | |
| 47 | expect_bc=0; | |
| 48 | infTO=false; | |
| 49 | } | |
| 50 | }; | |
| 51 | ||
| 52 | class rsb : public sc_module | |
| 53 | { | |
| 54 | public: | |
| 55 | rsb(sc_module_name module_name, sc_event *parent_global_ev, uint8 *global_event_type) : | |
| 56 | sc_module (module_name), | |
| 57 | ing_port("ing_itl_rsb_port"), | |
| 58 | csr_port("CSR_PORT"), | |
| 59 | eg_port("eg_etl_rsb_port"), | |
| 60 | rsb_clk("RSB_CLK",4,SC_NS,0.5), ///Assuming a 250MHz clock domain | |
| 61 | cto_req_port("cto_rsb_ilu_req_port") | |
| 62 | { | |
| 63 | this->parent_global_ev = parent_global_ev; | |
| 64 | this->global_event_type = global_event_type; | |
| 65 | SC_THREAD(ing_handler); | |
| 66 | SC_METHOD(init); | |
| 67 | SC_THREAD(reset_handler); | |
| 68 | } | |
| 69 | ||
| 70 | SC_HAS_PROCESS(rsb); | |
| 71 | ||
| 72 | sc_port< tlm_slave_if< RefPciePacket, bool > > ing_port; | |
| 73 | data_in_port<RefPciePacket> eg_port; | |
| 74 | csr_if_port< CSR_ADDR_T, CSR_DATA_T > csr_port; | |
| 75 | sc_port< tlm_put_if< sc_uint<CTO_TAG_SIZE> > > cto_req_port; | |
| 76 | ||
| 77 | sc_clock rsb_clk; ///< RSB clk | |
| 78 | ||
| 79 | private: | |
| 80 | //Module threads and methods | |
| 81 | void ing_handler(); | |
| 82 | void eg_handler(); | |
| 83 | void update_timer(); | |
| 84 | sc_time get_Cpl_TO(); | |
| 85 | void write_error_csr(uint8,uint8,uint8,char[]); | |
| 86 | void init(); | |
| 87 | void reset_handler(); | |
| 88 | ||
| 89 | sc_event reset_ev; ///< Reset event for threads in the module | |
| 90 | sc_event *parent_global_ev; ///< Global event to the module | |
| 91 | uint8 *global_event_type; ///< Global event type | |
| 92 | ||
| 93 | bool POR_RESET; ///< Power-on Reset flag | |
| 94 | bool STOP_TIMER; | |
| 95 | ||
| 96 | //Proc handles | |
| 97 | sc_process_handle eg_handler_ph; | |
| 98 | sc_process_handle update_timer_ph; | |
| 99 | ||
| 100 | USE_NAMESPACE(std)map<sc_uint<4>, rsb_data > rsb_db; ///< RSB look-up table | |
| 101 | ||
| 102 | enum {OE,UE,CE}; | |
| 103 | ||
| 104 | sc_uint<6> rs2it_err; ///< RSB error type local register | |
| 105 | }; | |
| 106 | } //namespace pcie | |
| 107 | #endif //INC_rsb_hpp |