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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / model / pcie / top / pcie_top.hpp
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: pcie_top.hpp
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
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28// otherwise unspecified.
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#ifndef INC_pcie_top_hpp__
36#define INC_pcie_top_hpp__
37
38#include <systemc.h>
39#ifdef LINK_8
40#define LINK_WIDTH 8 // This is a temporary arrangement
41#endif
42#ifdef LINK_1
43#define LINK_WIDTH 1
44#endif
45#ifdef LINK_2
46#define LINK_WIDTH 2
47#endif
48
49#ifdef LINK_4
50#define LINK_WIDTH 4
51#endif
52
53#ifdef LINK_12
54#define LINK_WIDTH 12
55#endif
56
57#ifdef LINK_16
58#define LINK_WIDTH 16
59#endif
60
61#ifdef LINK_24
62#define LINK_WIDTH 24
63#endif
64
65#ifdef LINK_32
66#define LINK_WIDTH 32
67#endif
68
69#include "pcie_common/config.hpp"
70
71#include "tl_top.hpp"
72#include "dll_top.hpp"
73#include "pl_top.h"
74#include "pcie_common/pciePacket.hpp"
75#include "pcie_common/tlm/tlm_data_channel.hpp"
76
77USING_NAMESPACE(pcie);
78
79class pcie_top : public sc_module
80{
81 public:
82 typedef tlm_data_channel< RefPciePacket > data_channel;
83
84 pcie_top(sc_module_name module_name, sc_event *parent_global_event, uint8 *parent_global_event_type) :
85 sc_module (module_name)
86 {
87 this->parent_global_event = parent_global_event;
88 this->parent_global_event_type = parent_global_event_type;
89
90 LOG_DEBUG << " < PCIE_TOP ()";
91 pl = new pl_top("PL_Top");
92 tl = new tl_top("TL_Top",parent_global_event,parent_global_event_type);
93 dll = new dll_top("DLL_Top",parent_global_event,parent_global_event_type);
94
95 tl_dl_data_chnl = new data_channel("TL_DL_Data_Chnl", parent_global_event,parent_global_event_type, 256);
96 dl_tl_data_chnl = new data_channel("DL_TL_Data_Chnl", parent_global_event,parent_global_event_type, 256);
97 pl_dl_data_chnl = new data_channel("PL_DL_Data_Chnl", parent_global_event,parent_global_event_type, 256);
98 dl_pl_dllp_data_chnl = new data_channel("DL_PL_DLLP_Data_Chnl", parent_global_event,parent_global_event_type, 256);
99 dl_pl_tlp_data_chnl = new data_channel("DL_PL_TLP_Data_Chnl", parent_global_event,parent_global_event_type, 256);
100
101 tl->etl_data_port(*tl_dl_data_chnl);
102 dll->tl_dll_in(*tl_dl_data_chnl);
103
104 tl->itl_data_port(*dl_tl_data_chnl);
105 dll->dll_tl_out(*dl_tl_data_chnl);
106
107 dll->dll_pl_dllp_out(*dl_pl_dllp_data_chnl);
108 pl->dll_pl_dllp_in(*dl_pl_dllp_data_chnl);
109
110 dll->dll_pl_tlp_out(*dl_pl_tlp_data_chnl);
111 pl->dll_pl_tlp_in(*dl_pl_tlp_data_chnl);
112
113 dll->pl_dll_in(*pl_dl_data_chnl);
114 pl->pl_dll_out(*pl_dl_data_chnl);
115
116 // Inputs from the deserializer
117 pl->deser_data0(deser_data0);
118 pl->deser_data1(deser_data1);
119 pl->deser_data2(deser_data2);
120 pl->deser_data3(deser_data3);
121 pl->deser_data4(deser_data4);
122 pl->deser_data5(deser_data5);
123 pl->deser_data6(deser_data6);
124 pl->deser_data7(deser_data7);
125 pl->deser_data8(deser_data8);
126 pl->deser_data9(deser_data9);
127 pl->deser_data0_b(deser_data0_b);
128 pl->deser_data1_b(deser_data1_b);
129 pl->deser_data2_b(deser_data2_b);
130 pl->deser_data3_b(deser_data3_b);
131 pl->deser_data4_b(deser_data4_b);
132 pl->deser_data5_b(deser_data5_b);
133 pl->deser_data6_b(deser_data6_b);
134 pl->deser_data7_b(deser_data7_b);
135 pl->deser_data8_b(deser_data8_b);
136 pl->deser_data9_b(deser_data9_b);
137 pl->frm_boundary_deser(frm_boundary_deser);
138 pl->disable_scrambling(disable_scrambling);
139 pl->link_clk(link_clk);
140 pl->init_done(init_done);
141 pl->init_done_rx(init_done_rx);
142
143 // Outputs to the serializer
144 pl->encoded_data0(encoded_data0);
145 pl->encoded_data1(encoded_data1);
146 pl->encoded_data2(encoded_data2);
147 pl->encoded_data3(encoded_data3);
148 pl->encoded_data4(encoded_data4);
149 pl->encoded_data5(encoded_data5);
150 pl->encoded_data6(encoded_data6);
151 pl->encoded_data7(encoded_data7);
152 pl->encoded_data8(encoded_data8);
153 pl->encoded_data9(encoded_data9);
154 pl->sym_boundary(sym_boundary);
155
156 dll->PhysicalLinkUp(link_up);
157 pl->PhysicalLinkUp(link_up);
158 LOG_DEBUG << " > PCIE_TOP ()";
159 }
160
161 ~pcie_top(){
162 delete pl;
163 delete tl;
164 delete dll;
165 delete tl_dl_data_chnl;
166 delete dl_tl_data_chnl;
167 delete dl_pl_dllp_data_chnl;
168 delete dl_pl_tlp_data_chnl;
169 delete pl_dl_data_chnl;
170 }
171
172 //private:
173 pl_top *pl;
174 tl_top *tl;
175 dll_top *dll;
176 data_channel *tl_dl_data_chnl;
177 data_channel *dl_tl_data_chnl;
178 data_channel *dl_pl_dllp_data_chnl;
179 data_channel *dl_pl_tlp_data_chnl;
180 data_channel *pl_dl_data_chnl;
181
182 sc_signal<bool> link_up;
183
184 sc_in<sc_lv<LINK_WIDTH> > deser_data0;
185 sc_in<sc_lv<LINK_WIDTH> > deser_data1;
186 sc_in<sc_lv<LINK_WIDTH> > deser_data2;
187 sc_in<sc_lv<LINK_WIDTH> > deser_data3;
188 sc_in<sc_lv<LINK_WIDTH> > deser_data4;
189 sc_in<sc_lv<LINK_WIDTH> > deser_data5;
190 sc_in<sc_lv<LINK_WIDTH> > deser_data6;
191 sc_in<sc_lv<LINK_WIDTH> > deser_data7;
192 sc_in<sc_lv<LINK_WIDTH> > deser_data8;
193 sc_in<sc_lv<LINK_WIDTH> > deser_data9;
194
195 sc_in<sc_lv<LINK_WIDTH> > deser_data0_b;
196 sc_in<sc_lv<LINK_WIDTH> > deser_data1_b;
197 sc_in<sc_lv<LINK_WIDTH> > deser_data2_b;
198 sc_in<sc_lv<LINK_WIDTH> > deser_data3_b;
199 sc_in<sc_lv<LINK_WIDTH> > deser_data4_b;
200 sc_in<sc_lv<LINK_WIDTH> > deser_data5_b;
201 sc_in<sc_lv<LINK_WIDTH> > deser_data6_b;
202 sc_in<sc_lv<LINK_WIDTH> > deser_data7_b;
203 sc_in<sc_lv<LINK_WIDTH> > deser_data8_b;
204 sc_in<sc_lv<LINK_WIDTH> > deser_data9_b;
205 sc_out<bool > sym_boundary;
206 sc_in<bool> disable_scrambling;
207 sc_in<bool> link_clk;
208 sc_in<bool> init_done;
209 sc_in<bool> init_done_rx;
210
211 sc_out<sc_lv<LINK_WIDTH> > encoded_data0;
212 sc_out<sc_lv<LINK_WIDTH> > encoded_data1;
213 sc_out<sc_lv<LINK_WIDTH> > encoded_data2;
214 sc_out<sc_lv<LINK_WIDTH> > encoded_data3;
215 sc_out<sc_lv<LINK_WIDTH> > encoded_data4;
216 sc_out<sc_lv<LINK_WIDTH> > encoded_data5;
217 sc_out<sc_lv<LINK_WIDTH> > encoded_data6;
218 sc_out<sc_lv<LINK_WIDTH> > encoded_data7;
219 sc_out<sc_lv<LINK_WIDTH> > encoded_data8;
220 sc_out<sc_lv<LINK_WIDTH> > encoded_data9;
221 sc_in<bool> frm_boundary_deser;
222
223 sc_event *parent_global_event;
224 uint8 *parent_global_event_type;
225};
226
227//} // namespace pcie
228
229#endif // INC_pcie_top_hpp__
Full OpenSPARC design & verification tarball including full HDL.