projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / model / verilog / mem / dram / axis_cmp_sat.v
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: axis_cmp_sat.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35 module cmp_sat (
36 //{{{
37 io_dram3_ecc_in, io_dram3_data_valid,
38 io_dram3_data_in, io_dram2_ecc_in, io_dram2_data_valid,
39 io_dram2_data_in, io_dram1_ecc_in, io_dram1_data_valid,
40 io_dram1_data_in, io_dram0_ecc_in, io_dram0_data_valid,
41 io_dram0_data_in,
42 dram3_io_write_en_l,
43 dram3_io_ras_l,
44 dram3_io_data_out, dram3_io_cs_l,
45 dram3_io_cas_l,
46 dram3_io_bank, dram3_io_addr, dram2_io_write_en_l, dram2_io_ras_l,
47 dram2_io_data_out,
48 dram2_io_cs_l,
49 dram2_io_cas_l, dram2_io_bank,
50 dram2_io_addr, dram1_io_write_en_l, dram1_io_ras_l,
51 dram1_io_data_out,
52 dram1_io_cs_l,
53 dram1_io_cas_l, dram1_io_bank,
54 dram1_io_addr,
55 dram0_io_write_en_l, dram0_io_ras_l,
56 dram0_io_data_out,
57 dram0_io_cs_l,
58 dram0_io_cas_l, dram0_io_bank,
59 dram0_io_addr,
60
61 jbi_io_ssi_mosi, io_jbi_ssi_miso,
62 //}}}
63 dramclk,
64 ssiclk,
65 reset
66 );
67
68 //{{{
69 input [14:0] dram0_io_addr; // From dram02 of dram.v
70 input [2:0] dram0_io_bank; // From dram02 of dram.v
71 input dram0_io_cas_l; // From dram02 of dram.v
72 input [3:0] dram0_io_cs_l; // From dram02 of dram.v
73 input [287:0] dram0_io_data_out; // From dram02 of dram.v
74 input dram0_io_ras_l; // From dram02 of dram.v
75 input dram0_io_write_en_l; // From dram02 of dram.v
76 input [14:0] dram1_io_addr; // From dram13 of dram.v
77 input [2:0] dram1_io_bank; // From dram13 of dram.v
78 input dram1_io_cas_l; // From dram13 of dram.v
79 input [3:0] dram1_io_cs_l; // From dram13 of dram.v
80 input [287:0] dram1_io_data_out; // From dram13 of dram.v
81 input dram1_io_ras_l; // From dram13 of dram.v
82 input dram1_io_write_en_l; // From dram13 of dram.v
83 input [14:0] dram2_io_addr; // From dram02 of dram.v
84 input [2:0] dram2_io_bank; // From dram02 of dram.v
85 input dram2_io_cas_l; // From dram02 of dram.v
86 input [3:0] dram2_io_cs_l; // From dram02 of dram.v
87 input [287:0] dram2_io_data_out; // From dram02 of dram.v
88 input dram2_io_ras_l; // From dram02 of dram.v
89 input dram2_io_write_en_l; // From dram02 of dram.v
90 input [14:0] dram3_io_addr; // From dram13 of dram.v
91 input [2:0] dram3_io_bank; // From dram13 of dram.v
92 input dram3_io_cas_l; // From dram13 of dram.v
93 input [3:0] dram3_io_cs_l; // From dram13 of dram.v
94 input [287:0] dram3_io_data_out; // From dram13 of dram.v
95 input dram3_io_ras_l; // From dram13 of dram.v
96 input dram3_io_write_en_l; // From dram13 of dram.v
97
98
99 input jbi_io_ssi_mosi; // Master out slave in to pad.
100 output io_jbi_ssi_miso; // Master in slave out from pad.
101
102 //}}}
103 //{{{
104
105 output [255:0] io_dram0_data_in; // To dram02 of dram.v
106 output io_dram0_data_valid; // To dram02 of dram.v
107 output [31:0] io_dram0_ecc_in; // To dram02 of dram.v
108 output [255:0] io_dram1_data_in; // To dram13 of dram.v
109 output io_dram1_data_valid; // To dram13 of dram.v
110 output [31:0] io_dram1_ecc_in; // To dram13 of dram.v
111 output [255:0] io_dram2_data_in; // To dram02 of dram.v
112 output io_dram2_data_valid; // To dram02 of dram.v
113 output [31:0] io_dram2_ecc_in; // To dram02 of dram.v
114 output [255:0] io_dram3_data_in; // To dram13 of dram.v
115 output io_dram3_data_valid; // To dram13 of dram.v
116 output [31:0] io_dram3_ecc_in; // To dram13 of dram.v
117 //}}}
118
119 input dramclk;
120 input ssiclk;
121 input reset;
122
123reg [7:0] TAP_STALL_CNT;
124reg [7:0] CLSP_STALL_CNT;
125 wire [127:0] dram_iob_final;
126
127//{{{ directory ram
128/**************************************************************************************************************
129* DIRECTORY RAM definitions
130**************************************************************************************************************/
131wire [26:8] iob_index, dram0_index, dram1_index, dram2_index, dram3_index;
132
133wire [31:0] iob_dir0_do, dram0_dir0_do, dram1_dir0_do, dram2_dir0_do, dram3_dir0_do;
134wire [31:0] iob_dir1_do, dram0_dir1_do, dram1_dir1_do, dram2_dir1_do, dram3_dir1_do;
135wire [31:0] iob_dir2_do, dram0_dir2_do, dram1_dir2_do, dram2_dir2_do, dram3_dir2_do;
136wire [31:0] iob_dir3_do, dram0_dir3_do, dram1_dir3_do, dram2_dir3_do, dram3_dir3_do;
137wire [31:0] iob_dir4_do, dram0_dir4_do, dram1_dir4_do, dram2_dir4_do, dram3_dir4_do;
138wire [31:0] iob_dir5_do, dram0_dir5_do, dram1_dir5_do, dram2_dir5_do, dram3_dir5_do;
139wire [31:0] iob_dir6_do, dram0_dir6_do, dram1_dir6_do, dram2_dir6_do, dram3_dir6_do;
140wire [31:0] iob_dir7_do, dram0_dir7_do, dram1_dir7_do, dram2_dir7_do, dram3_dir7_do;
141wire [31:0] iob_dir8_do, dram0_dir8_do, dram1_dir8_do, dram2_dir8_do, dram3_dir8_do;
142wire [31:0] iob_dir9_do, dram0_dir9_do, dram1_dir9_do, dram2_dir9_do, dram3_dir9_do;
143wire [31:0] iob_dira_do, dram0_dira_do, dram1_dira_do, dram2_dira_do, dram3_dira_do;
144wire [31:0] iob_dirb_do, dram0_dirb_do, dram1_dirb_do, dram2_dirb_do, dram3_dirb_do;
145wire [31:0] iob_dirc_do, dram0_dirc_do, dram1_dirc_do, dram2_dirc_do, dram3_dirc_do;
146wire [31:0] iob_dird_do, dram0_dird_do, dram1_dird_do, dram2_dird_do, dram3_dird_do;
147wire [31:0] iob_dire_do, dram0_dire_do, dram1_dire_do, dram2_dire_do, dram3_dire_do;
148wire [31:0] iob_dirf_do, dram0_dirf_do, dram1_dirf_do, dram2_dirf_do, dram3_dirf_do;
149wire [31:0] iob_dir10_do, dram0_dir10_do, dram1_dir10_do, dram2_dir10_do, dram3_dir10_do;
150wire [31:0] iob_dir11_do, dram0_dir11_do, dram1_dir11_do, dram2_dir11_do, dram3_dir11_do;
151wire [31:0] iob_dir12_do, dram0_dir12_do, dram1_dir12_do, dram2_dir12_do, dram3_dir12_do;
152wire [31:0] iob_dir13_do, dram0_dir13_do, dram1_dir13_do, dram2_dir13_do, dram3_dir13_do;
153wire [31:0] iob_dir14_do, dram0_dir14_do, dram1_dir14_do, dram2_dir14_do, dram3_dir14_do;
154wire [31:0] iob_dir15_do, dram0_dir15_do, dram1_dir15_do, dram2_dir15_do, dram3_dir15_do;
155wire [31:0] iob_dir16_do, dram0_dir16_do, dram1_dir16_do, dram2_dir16_do, dram3_dir16_do;
156wire [31:0] iob_dir17_do, dram0_dir17_do, dram1_dir17_do, dram2_dir17_do, dram3_dir17_do;
157wire [31:0] iob_dir18_do, dram0_dir18_do, dram1_dir18_do, dram2_dir18_do, dram3_dir18_do;
158wire [31:0] iob_dir19_do, dram0_dir19_do, dram1_dir19_do, dram2_dir19_do, dram3_dir19_do;
159wire [31:0] iob_dir1a_do, dram0_dir1a_do, dram1_dir1a_do, dram2_dir1a_do, dram3_dir1a_do;
160wire [31:0] iob_dir1b_do, dram0_dir1b_do, dram1_dir1b_do, dram2_dir1b_do, dram3_dir1b_do;
161wire [31:0] iob_dir1c_do, dram0_dir1c_do, dram1_dir1c_do, dram2_dir1c_do, dram3_dir1c_do;
162wire [31:0] iob_dir1d_do, dram0_dir1d_do, dram1_dir1d_do, dram2_dir1d_do, dram3_dir1d_do;
163wire [31:0] iob_dir1e_do, dram0_dir1e_do, dram1_dir1e_do, dram2_dir1e_do, dram3_dir1e_do;
164wire [31:0] iob_dir1f_do, dram0_dir1f_do, dram1_dir1f_do, dram2_dir1f_do, dram3_dir1f_do;
165wire [31:0] iob_dir20_do, dram0_dir20_do, dram1_dir20_do, dram2_dir20_do, dram3_dir20_do;
166wire [31:0] iob_dir21_do, dram0_dir21_do, dram1_dir21_do, dram2_dir21_do, dram3_dir21_do;
167wire [31:0] iob_dir22_do, dram0_dir22_do, dram1_dir22_do, dram2_dir22_do, dram3_dir22_do;
168wire [31:0] iob_dir23_do, dram0_dir23_do, dram1_dir23_do, dram2_dir23_do, dram3_dir23_do;
169wire [31:0] iob_dir24_do, dram0_dir24_do, dram1_dir24_do, dram2_dir24_do, dram3_dir24_do;
170wire [31:0] iob_dir25_do, dram0_dir25_do, dram1_dir25_do, dram2_dir25_do, dram3_dir25_do;
171wire [31:0] iob_dir26_do, dram0_dir26_do, dram1_dir26_do, dram2_dir26_do, dram3_dir26_do;
172wire [31:0] iob_dir27_do, dram0_dir27_do, dram1_dir27_do, dram2_dir27_do, dram3_dir27_do;
173wire [31:0] iob_dir28_do, dram0_dir28_do, dram1_dir28_do, dram2_dir28_do, dram3_dir28_do;
174wire [31:0] iob_dir29_do, dram0_dir29_do, dram1_dir29_do, dram2_dir29_do, dram3_dir29_do;
175wire [31:0] iob_dir2a_do, dram0_dir2a_do, dram1_dir2a_do, dram2_dir2a_do, dram3_dir2a_do;
176wire [31:0] iob_dir2b_do, dram0_dir2b_do, dram1_dir2b_do, dram2_dir2b_do, dram3_dir2b_do;
177wire [31:0] iob_dir2c_do, dram0_dir2c_do, dram1_dir2c_do, dram2_dir2c_do, dram3_dir2c_do;
178wire [31:0] iob_dir2d_do, dram0_dir2d_do, dram1_dir2d_do, dram2_dir2d_do, dram3_dir2d_do;
179wire [31:0] iob_dir2e_do, dram0_dir2e_do, dram1_dir2e_do, dram2_dir2e_do, dram3_dir2e_do;
180wire [31:0] iob_dir2f_do, dram0_dir2f_do, dram1_dir2f_do, dram2_dir2f_do, dram3_dir2f_do;
181wire [31:0] iob_dir30_do, dram0_dir30_do, dram1_dir30_do, dram2_dir30_do, dram3_dir30_do;
182wire [31:0] iob_dir31_do, dram0_dir31_do, dram1_dir31_do, dram2_dir31_do, dram3_dir31_do;
183wire [31:0] iob_dir32_do, dram0_dir32_do, dram1_dir32_do, dram2_dir32_do, dram3_dir32_do;
184wire [31:0] iob_dir33_do, dram0_dir33_do, dram1_dir33_do, dram2_dir33_do, dram3_dir33_do;
185wire [31:0] iob_dir34_do, dram0_dir34_do, dram1_dir34_do, dram2_dir34_do, dram3_dir34_do;
186wire [31:0] iob_dir35_do, dram0_dir35_do, dram1_dir35_do, dram2_dir35_do, dram3_dir35_do;
187wire [31:0] iob_dir36_do, dram0_dir36_do, dram1_dir36_do, dram2_dir36_do, dram3_dir36_do;
188wire [31:0] iob_dir37_do, dram0_dir37_do, dram1_dir37_do, dram2_dir37_do, dram3_dir37_do;
189wire [31:0] iob_dir38_do, dram0_dir38_do, dram1_dir38_do, dram2_dir38_do, dram3_dir38_do;
190wire [31:0] iob_dir39_do, dram0_dir39_do, dram1_dir39_do, dram2_dir39_do, dram3_dir39_do;
191wire [31:0] iob_dir3a_do, dram0_dir3a_do, dram1_dir3a_do, dram2_dir3a_do, dram3_dir3a_do;
192wire [31:0] iob_dir3b_do, dram0_dir3b_do, dram1_dir3b_do, dram2_dir3b_do, dram3_dir3b_do;
193wire [31:0] iob_dir3c_do, dram0_dir3c_do, dram1_dir3c_do, dram2_dir3c_do, dram3_dir3c_do;
194wire [31:0] iob_dir3d_do, dram0_dir3d_do, dram1_dir3d_do, dram2_dir3d_do, dram3_dir3d_do;
195wire [31:0] iob_dir3e_do, dram0_dir3e_do, dram1_dir3e_do, dram2_dir3e_do, dram3_dir3e_do;
196wire [31:0] iob_dir3f_do, dram0_dir3f_do, dram1_dir3f_do, dram2_dir3f_do, dram3_dir3f_do;
197
198dram_dir dir0 (.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
199 .data0(iob_dir0_do), .data1(dram0_dir0_do), .data2(dram1_dir0_do), .data3(dram2_dir0_do), .data4(dram3_dir0_do));
200dram_dir dir1 (.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
201 .data0(iob_dir1_do), .data1(dram0_dir1_do), .data2(dram1_dir1_do), .data3(dram2_dir1_do), .data4(dram3_dir1_do));
202dram_dir dir2 (.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
203 .data0(iob_dir2_do), .data1(dram0_dir2_do), .data2(dram1_dir2_do), .data3(dram2_dir2_do), .data4(dram3_dir2_do));
204dram_dir dir3 (.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
205 .data0(iob_dir3_do), .data1(dram0_dir3_do), .data2(dram1_dir3_do), .data3(dram2_dir3_do), .data4(dram3_dir3_do));
206dram_dir dir4 (.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
207 .data0(iob_dir4_do), .data1(dram0_dir4_do), .data2(dram1_dir4_do), .data3(dram2_dir4_do), .data4(dram3_dir4_do));
208dram_dir dir5 (.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
209 .data0(iob_dir5_do), .data1(dram0_dir5_do), .data2(dram1_dir5_do), .data3(dram2_dir5_do), .data4(dram3_dir5_do));
210dram_dir dir6 (.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
211 .data0(iob_dir6_do), .data1(dram0_dir6_do), .data2(dram1_dir6_do), .data3(dram2_dir6_do), .data4(dram3_dir6_do));
212dram_dir dir7 (.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
213 .data0(iob_dir7_do), .data1(dram0_dir7_do), .data2(dram1_dir7_do), .data3(dram2_dir7_do), .data4(dram3_dir7_do));
214dram_dir dir8 (.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
215 .data0(iob_dir8_do), .data1(dram0_dir8_do), .data2(dram1_dir8_do), .data3(dram2_dir8_do), .data4(dram3_dir8_do));
216dram_dir dir9 (.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
217 .data0(iob_dir9_do), .data1(dram0_dir9_do), .data2(dram1_dir9_do), .data3(dram2_dir9_do), .data4(dram3_dir9_do));
218dram_dir dira (.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
219 .data0(iob_dira_do), .data1(dram0_dira_do), .data2(dram1_dira_do), .data3(dram2_dira_do), .data4(dram3_dira_do));
220dram_dir dirb (.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
221 .data0(iob_dirb_do), .data1(dram0_dirb_do), .data2(dram1_dirb_do), .data3(dram2_dirb_do), .data4(dram3_dirb_do));
222dram_dir dirc (.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
223 .data0(iob_dirc_do), .data1(dram0_dirc_do), .data2(dram1_dirc_do), .data3(dram2_dirc_do), .data4(dram3_dirc_do));
224dram_dir dird (.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
225 .data0(iob_dird_do), .data1(dram0_dird_do), .data2(dram1_dird_do), .data3(dram2_dird_do), .data4(dram3_dird_do));
226dram_dir dire (.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
227 .data0(iob_dire_do), .data1(dram0_dire_do), .data2(dram1_dire_do), .data3(dram2_dire_do), .data4(dram3_dire_do));
228dram_dir dirf (.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
229 .data0(iob_dirf_do), .data1(dram0_dirf_do), .data2(dram1_dirf_do), .data3(dram2_dirf_do), .data4(dram3_dirf_do));
230dram_dir dir10(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
231 .data0(iob_dir10_do),.data1(dram0_dir10_do),.data2(dram1_dir10_do),.data3(dram2_dir10_do),.data4(dram3_dir10_do));
232dram_dir dir11(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
233 .data0(iob_dir11_do),.data1(dram0_dir11_do),.data2(dram1_dir11_do),.data3(dram2_dir11_do),.data4(dram3_dir11_do));
234dram_dir dir12(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
235 .data0(iob_dir12_do),.data1(dram0_dir12_do),.data2(dram1_dir12_do),.data3(dram2_dir12_do),.data4(dram3_dir12_do));
236dram_dir dir13(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
237 .data0(iob_dir13_do),.data1(dram0_dir13_do),.data2(dram1_dir13_do),.data3(dram2_dir13_do),.data4(dram3_dir13_do));
238dram_dir dir14(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
239 .data0(iob_dir14_do),.data1(dram0_dir14_do),.data2(dram1_dir14_do),.data3(dram2_dir14_do),.data4(dram3_dir14_do));
240dram_dir dir15(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
241 .data0(iob_dir15_do),.data1(dram0_dir15_do),.data2(dram1_dir15_do),.data3(dram2_dir15_do),.data4(dram3_dir15_do));
242dram_dir dir16(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
243 .data0(iob_dir16_do),.data1(dram0_dir16_do),.data2(dram1_dir16_do),.data3(dram2_dir16_do),.data4(dram3_dir16_do));
244dram_dir dir17(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
245 .data0(iob_dir17_do),.data1(dram0_dir17_do),.data2(dram1_dir17_do),.data3(dram2_dir17_do),.data4(dram3_dir17_do));
246dram_dir dir18(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
247 .data0(iob_dir18_do),.data1(dram0_dir18_do),.data2(dram1_dir18_do),.data3(dram2_dir18_do),.data4(dram3_dir18_do));
248dram_dir dir19(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
249 .data0(iob_dir19_do),.data1(dram0_dir19_do),.data2(dram1_dir19_do),.data3(dram2_dir19_do),.data4(dram3_dir19_do));
250dram_dir dir1a(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
251 .data0(iob_dir1a_do),.data1(dram0_dir1a_do),.data2(dram1_dir1a_do),.data3(dram2_dir1a_do),.data4(dram3_dir1a_do));
252dram_dir dir1b(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
253 .data0(iob_dir1b_do),.data1(dram0_dir1b_do),.data2(dram1_dir1b_do),.data3(dram2_dir1b_do),.data4(dram3_dir1b_do));
254dram_dir dir1c(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
255 .data0(iob_dir1c_do),.data1(dram0_dir1c_do),.data2(dram1_dir1c_do),.data3(dram2_dir1c_do),.data4(dram3_dir1c_do));
256dram_dir dir1d(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
257 .data0(iob_dir1d_do),.data1(dram0_dir1d_do),.data2(dram1_dir1d_do),.data3(dram2_dir1d_do),.data4(dram3_dir1d_do));
258dram_dir dir1e(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
259 .data0(iob_dir1e_do),.data1(dram0_dir1e_do),.data2(dram1_dir1e_do),.data3(dram2_dir1e_do),.data4(dram3_dir1e_do));
260dram_dir dir1f(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
261 .data0(iob_dir1f_do),.data1(dram0_dir1f_do),.data2(dram1_dir1f_do),.data3(dram2_dir1f_do),.data4(dram3_dir1f_do));
262dram_dir dir20(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
263 .data0(iob_dir20_do),.data1(dram0_dir20_do),.data2(dram1_dir20_do),.data3(dram2_dir20_do),.data4(dram3_dir20_do));
264dram_dir dir21(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
265 .data0(iob_dir21_do),.data1(dram0_dir21_do),.data2(dram1_dir21_do),.data3(dram2_dir21_do),.data4(dram3_dir21_do));
266dram_dir dir22(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
267 .data0(iob_dir22_do),.data1(dram0_dir22_do),.data2(dram1_dir22_do),.data3(dram2_dir22_do),.data4(dram3_dir22_do));
268dram_dir dir23(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
269 .data0(iob_dir23_do),.data1(dram0_dir23_do),.data2(dram1_dir23_do),.data3(dram2_dir23_do),.data4(dram3_dir23_do));
270dram_dir dir24(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
271 .data0(iob_dir24_do),.data1(dram0_dir24_do),.data2(dram1_dir24_do),.data3(dram2_dir24_do),.data4(dram3_dir24_do));
272dram_dir dir25(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
273 .data0(iob_dir25_do),.data1(dram0_dir25_do),.data2(dram1_dir25_do),.data3(dram2_dir25_do),.data4(dram3_dir25_do));
274dram_dir dir26(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
275 .data0(iob_dir26_do),.data1(dram0_dir26_do),.data2(dram1_dir26_do),.data3(dram2_dir26_do),.data4(dram3_dir26_do));
276dram_dir dir27(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
277 .data0(iob_dir27_do),.data1(dram0_dir27_do),.data2(dram1_dir27_do),.data3(dram2_dir27_do),.data4(dram3_dir27_do));
278dram_dir dir28(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
279 .data0(iob_dir28_do),.data1(dram0_dir28_do),.data2(dram1_dir28_do),.data3(dram2_dir28_do),.data4(dram3_dir28_do));
280dram_dir dir29(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
281 .data0(iob_dir29_do),.data1(dram0_dir29_do),.data2(dram1_dir29_do),.data3(dram2_dir29_do),.data4(dram3_dir29_do));
282dram_dir dir2a(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
283 .data0(iob_dir2a_do),.data1(dram0_dir2a_do),.data2(dram1_dir2a_do),.data3(dram2_dir2a_do),.data4(dram3_dir2a_do));
284dram_dir dir2b(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
285 .data0(iob_dir2b_do),.data1(dram0_dir2b_do),.data2(dram1_dir2b_do),.data3(dram2_dir2b_do),.data4(dram3_dir2b_do));
286dram_dir dir2c(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
287 .data0(iob_dir2c_do),.data1(dram0_dir2c_do),.data2(dram1_dir2c_do),.data3(dram2_dir2c_do),.data4(dram3_dir2c_do));
288dram_dir dir2d(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
289 .data0(iob_dir2d_do),.data1(dram0_dir2d_do),.data2(dram1_dir2d_do),.data3(dram2_dir2d_do),.data4(dram3_dir2d_do));
290dram_dir dir2e(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
291 .data0(iob_dir2e_do),.data1(dram0_dir2e_do),.data2(dram1_dir2e_do),.data3(dram2_dir2e_do),.data4(dram3_dir2e_do));
292dram_dir dir2f(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
293 .data0(iob_dir2f_do),.data1(dram0_dir2f_do),.data2(dram1_dir2f_do),.data3(dram2_dir2f_do),.data4(dram3_dir2f_do));
294dram_dir dir30(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
295 .data0(iob_dir30_do),.data1(dram0_dir30_do),.data2(dram1_dir30_do),.data3(dram2_dir30_do),.data4(dram3_dir30_do));
296dram_dir dir31(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
297 .data0(iob_dir31_do),.data1(dram0_dir31_do),.data2(dram1_dir31_do),.data3(dram2_dir31_do),.data4(dram3_dir31_do));
298dram_dir dir32(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
299 .data0(iob_dir32_do),.data1(dram0_dir32_do),.data2(dram1_dir32_do),.data3(dram2_dir32_do),.data4(dram3_dir32_do));
300dram_dir dir33(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
301 .data0(iob_dir33_do),.data1(dram0_dir33_do),.data2(dram1_dir33_do),.data3(dram2_dir33_do),.data4(dram3_dir33_do));
302dram_dir dir34(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
303 .data0(iob_dir34_do),.data1(dram0_dir34_do),.data2(dram1_dir34_do),.data3(dram2_dir34_do),.data4(dram3_dir34_do));
304dram_dir dir35(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
305 .data0(iob_dir35_do),.data1(dram0_dir35_do),.data2(dram1_dir35_do),.data3(dram2_dir35_do),.data4(dram3_dir35_do));
306dram_dir dir36(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
307 .data0(iob_dir36_do),.data1(dram0_dir36_do),.data2(dram1_dir36_do),.data3(dram2_dir36_do),.data4(dram3_dir36_do));
308dram_dir dir37(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
309 .data0(iob_dir37_do),.data1(dram0_dir37_do),.data2(dram1_dir37_do),.data3(dram2_dir37_do),.data4(dram3_dir37_do));
310dram_dir dir38(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
311 .data0(iob_dir38_do),.data1(dram0_dir38_do),.data2(dram1_dir38_do),.data3(dram2_dir38_do),.data4(dram3_dir38_do));
312dram_dir dir39(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
313 .data0(iob_dir39_do),.data1(dram0_dir39_do),.data2(dram1_dir39_do),.data3(dram2_dir39_do),.data4(dram3_dir39_do));
314dram_dir dir3a(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
315 .data0(iob_dir3a_do),.data1(dram0_dir3a_do),.data2(dram1_dir3a_do),.data3(dram2_dir3a_do),.data4(dram3_dir3a_do));
316dram_dir dir3b(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
317 .data0(iob_dir3b_do),.data1(dram0_dir3b_do),.data2(dram1_dir3b_do),.data3(dram2_dir3b_do),.data4(dram3_dir3b_do));
318dram_dir dir3c(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
319 .data0(iob_dir3c_do),.data1(dram0_dir3c_do),.data2(dram1_dir3c_do),.data3(dram2_dir3c_do),.data4(dram3_dir3c_do));
320dram_dir dir3d(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
321 .data0(iob_dir3d_do),.data1(dram0_dir3d_do),.data2(dram1_dir3d_do),.data3(dram2_dir3d_do),.data4(dram3_dir3d_do));
322dram_dir dir3e(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
323 .data0(iob_dir3e_do),.data1(dram0_dir3e_do),.data2(dram1_dir3e_do),.data3(dram2_dir3e_do),.data4(dram3_dir3e_do));
324dram_dir dir3f(.adr0(iob_index), .adr1(dram0_index ), .adr2(dram1_index), .adr3(dram2_index ), .adr4(dram3_index),
325 .data0(iob_dir3f_do),.data1(dram0_dir3f_do),.data2(dram1_dir3f_do),.data3(dram2_dir3f_do),.data4(dram3_dir3f_do));
326
327//}}}
328//{{{ ssi
329wire [127:0] iob_do0, iob_do1, iob_do2, iob_do3, iob_do4, iob_do5, iob_do6, iob_do7;
330wire [127:0] iob_do8, iob_do9, iob_doa, iob_dob, iob_doc, iob_dod, iob_doe, iob_dof;
331
332//{{{ misc ssi signals
333reg [40:0] FAST_CLK_CNT; // CYCLE NUMBER
334reg [39:0] CLK_CNT ; // CYCLE NUMBER
335reg [39:0] CLK_CNT_RUST; // CYCLE COUNT OF RUST KERNAL
336reg [ 3:0] IOB_VLD ; // IOB IFILL RESPONSE SEQUENCE
337reg [32:0] IOB_ADR0 ; // IOB FILL ADDRESS
338reg [32:0] IOB_ADR1 ;
339reg [2:0] REQ_GNT_CNT; // REQUESTS vs. GRANTS
340reg [5:0] POWERON_CNT; // WAKE UP 32 THREADS
341reg [1:0] POWERON_VEC; // POWERON SEQ
342reg [7:0] IO_CPX_REQ_CQ_VEC; // iob_cpx_req_cq register
343reg [31:0] RESTART_COUNT; // Count off to next restart
344reg [31:0] RESUME_COUNT ; // Count off to next resume
345reg [31:0] HALT_COUNT ; // Count off to next halt
346reg [ 4:0] INT_COUNT; // INT THREAD POINTER
347reg [ 1:0] INT_TYPE0; // Interrupt type field
348reg [ 1:0] INT_TYPE1; // Interrupt type field staged
349reg [ 1:0] INT_VEC; // valid interrupt staged staged
350reg [31:0] STALL_ON_CNT; // iob_pcx_stall_pq enable counter
351reg [31:0] STALL_OFF_CNT; // iob_pcx_stall_pq disable counter
352reg [10:0] WDOG_FWD; // Forward request must complete in < 2K cycles
353reg FWD_ACTIVE; // Forward request is currently being processed
354reg [ 1:0] FWD_REQ; // Forward request being issued
355reg [11:0] FWD_ADR; // Forward page address bits
356reg [63:0] FWD_DATA; // Forward data
357reg [ 4:0] FWD_SEQ; // RRWRR sequence
358reg [31:0] FINISHED; // Which threads have completed
359//}}}
360
361/**************************************************************************************************************
362* BOOT ROM LOGIC
363* This logic operates in a divide by 4 relative to the Jbus clock.
364**************************************************************************************************************/
365`ifdef CMP_IOBDG
366reg [31:0] SSI_CMD_SEQ;
367reg SSI_CMD_RW;
368reg [ 1:0] SSI_CMD_LNGT;
369reg [27:0] SSI_CMD_ADR;
370reg [65:0] SSI_RTN_SEQ;
371reg [65:0] SSI_SND_SEQ;
372reg [ 1:0] SSI_WR_RSPN;
373reg [63:0] SSI_RTN_DATA;
374reg [63:0] SSI_SND_DATA;
375reg SSI_RTN_PAR;
376reg [15:0] SSI_DELAY;
377reg [13:0] CONSOLE_RD_TIMER;
378
379wire [15:0] ssi_fix_delay;
380
381
382wire [31:0] console_out;
383
384wire [7:0] console_status = console_out[7:0];
385wire [7:0] console_data = console_out[15:8];
386
387//assign console_status[7:0] = (CTL_RAM[12] & 8'hff);
388//assign console_data [7:0] = ((CTL_RAM[12] >> 8) & 8'hff);
389
390wire [31:0] ssi_cmd_seqP = ((SSI_CMD_SEQ == 32'h0) & jbi_io_ssi_mosi &
391 ~(|SSI_SND_SEQ) & ~(|SSI_WR_RSPN)) ? 32'h80000000 :
392 ( SSI_CMD_SEQ[1] & ~SSI_CMD_RW) ? 32'h00000000 :
393 {1'b0, SSI_CMD_SEQ[31:1]};
394
395wire ssi_cmd_rwP = SSI_CMD_SEQ[31] ? jbi_io_ssi_mosi : SSI_CMD_RW;
396
397wire [ 1:0] ssi_cmd_lngtP = (|SSI_CMD_SEQ[30:29]) ? {SSI_CMD_LNGT[0], jbi_io_ssi_mosi} : SSI_CMD_LNGT[1:0];
398
399wire [27:0] ssi_cmd_adrP = (|SSI_CMD_SEQ[28:1]) ? {SSI_CMD_ADR[26:0], jbi_io_ssi_mosi} : SSI_CMD_ADR[27:0];
400
401wire [39:0] jbi_rom_adr = {12'hfff, SSI_CMD_ADR[27:0]};
402
403//wire pcx_iob_fill_ld = SSI_CMD_SEQ[0] & SSI_CMD_RW;
404 wire pcx_iob_fill_ld = (ssi_fix_delay == SSI_DELAY) & SSI_CMD_RW;
405
406 wire [15:0] ssi_delayP = (SSI_CMD_SEQ[0] & SSI_CMD_RW) ? 16'h0001 :
407 (ssi_fix_delay == SSI_DELAY) ? 16'h0000 :
408 (SSI_DELAY == 16'h0000) ? 16'h0000 : ((SSI_DELAY + 1) & 16'hffff);
409
410//wire [ 31:0] rom_read_4byte = ~IOB_ADR1[3] ? (~IOB_ADR1[2] ? dram_iob_final[127: 96] : dram_iob_final[95:64]) :
411// (~IOB_ADR1[2] ? dram_iob_final[ 63: 32] : dram_iob_final[31: 0]);
412
413wire [ 63:0] rom_read_8byte = ~IOB_ADR1[3] ? dram_iob_final[127:64] : dram_iob_final[63:0];
414wire [ 31:0] rom_read_4byte = ~IOB_ADR1[2] ? rom_read_8byte[63:32] : rom_read_8byte[31:0];
415wire [ 15:0] rom_read_2byte = ~IOB_ADR1[1] ? rom_read_4byte[31:16] : rom_read_4byte[15:0];
416wire [ 7:0] rom_read_1byte = ~IOB_ADR1[0] ? rom_read_2byte[15: 8] : rom_read_2byte[ 7:0];
417
418wire [ 63:0] rom_read = (SSI_CMD_LNGT[1:0] == 2'b11) ? rom_read_8byte :
419 (SSI_CMD_LNGT[1:0] == 2'b10) ? {rom_read_4byte, 32'h0} :
420 (SSI_CMD_LNGT[1:0] == 2'b01) ? {rom_read_2byte, 48'h0} : {rom_read_1byte, 56'h0};
421
422wire ssi_rtn_last = ((SSI_CMD_LNGT[1:0] == 2'b11) & SSI_RTN_SEQ[65]) |
423 ((SSI_CMD_LNGT[1:0] == 2'b10) & SSI_RTN_SEQ[33]) |
424 ((SSI_CMD_LNGT[1:0] == 2'b01) & SSI_RTN_SEQ[17]) |
425 ((SSI_CMD_LNGT[1:0] == 2'b00) & SSI_RTN_SEQ[ 9]);
426
427wire ssi_snd_last = ((SSI_CMD_LNGT[1:0] == 2'b11) & SSI_SND_SEQ[64]) |
428 ((SSI_CMD_LNGT[1:0] == 2'b10) & SSI_SND_SEQ[32]) |
429 ((SSI_CMD_LNGT[1:0] == 2'b01) & SSI_SND_SEQ[16]) |
430 ((SSI_CMD_LNGT[1:0] == 2'b00) & SSI_SND_SEQ[ 8]);
431
432wire [65:0] ssi_rtn_seqP = IOB_VLD[3] ? 66'h1 :
433 ssi_rtn_last ? 66'h0 : {SSI_RTN_SEQ[64:0], 1'b0};
434
435wire [65:0] ssi_snd_seqP = (SSI_CMD_SEQ[1] & ~SSI_CMD_RW) ? 66'h1 :
436 ssi_snd_last ? 66'h0 : {SSI_SND_SEQ[64:0], 1'b0};
437
438wire [1:0] ssi_wr_rspnP = ssi_snd_last ? 2'b01 : {SSI_WR_RSPN[0], 1'b0};
439
440wire [63:0] ssi_rtn_dataP = IOB_VLD[3] ?
441 ((SSI_CMD_ADR == 28'h0c2c005) ? {console_status, 56'h0} :
442 (SSI_CMD_ADR == 28'h0c2c000) ? {console_data , 56'h0} : rom_read[63:0]) :
443 (|SSI_RTN_SEQ[64:1]) ? {SSI_RTN_DATA[62:0], 1'b0} : SSI_RTN_DATA[63:0];
444
445wire [63:0] ssi_snd_dataP = ((|SSI_SND_SEQ[63:0]) & ~ssi_snd_last) ? {SSI_SND_DATA[62:0], jbi_io_ssi_mosi} :
446 SSI_SND_DATA[63:0];
447
448wire ssi_rtn_parP = SSI_RTN_SEQ[ 0] ? 1 : (io_jbi_ssi_miso ^ SSI_RTN_PAR);
449
450assign io_jbi_ssi_miso = SSI_RTN_SEQ[ 0] ? 1'b1 :
451 (|SSI_WR_RSPN[1:0]) ? 1'b1 :
452 ssi_rtn_last ? SSI_RTN_PAR :
453 (|SSI_RTN_SEQ[64:1]) ? SSI_RTN_DATA[63] : 1'b0;
454
455
456wire console_rd_v = (ssi_rtn_last & (SSI_CMD_ADR == 28'h0c2c005)) & (&CONSOLE_RD_TIMER);
457
458`ifdef AXIS
459wire [13:0] console_rd_timerP = console_rd_v ? 14'h03 :
460 (&CONSOLE_RD_TIMER) ? CONSOLE_RD_TIMER :
461 CONSOLE_RD_TIMER + 4;
462`else
463wire [13:0] console_rd_timerP = console_rd_v ? 14'h7f :
464 (&CONSOLE_RD_TIMER) ? CONSOLE_RD_TIMER :
465 CONSOLE_RD_TIMER + 128;
466`endif
467
468wire console_mask = (ssi_rtn_last & (SSI_CMD_ADR == 28'h0c2c000)) |
469 (ssi_snd_last & (SSI_CMD_ADR == 28'h0c2c005));
470
471wire [31:0] console_in = console_mask ? (console_out & 32'hffffffee) : CLK_CNT[39:8];
472
473rf2x32 rf2x32 ( .rclk (ssiclk),
474 .radr (1'b1),
475 .wadr (console_mask),
476 .ren (1'b1),
477 .we (1'b1),
478 .wm (32'hffffffff),
479 .din (console_in),
480 .dout (console_out) );
481
482always @(posedge ssiclk) begin
483 if (ssi_snd_last)
484 begin // axis tbcall_region
485 $display("SSI CONSOLE WRITE %h %h %h", SSI_CMD_ADR, SSI_CMD_LNGT, SSI_SND_DATA);
486 end
487 if (ssi_rtn_last & (SSI_CMD_ADR == 28'h0c2c000)) // Data Byte rd
488 begin // axis tbcall_region
489 $display("Writing cmp_mask [dbyte read] %x", CONSOLE_RD_TIMER);
490$writememh("include/CONSOLE_RAM", rf2x32.REGF2X32);
491 end
492//if (ssi_rtn_last & (SSI_CMD_ADR == 28'h0c2c000)) // Data Byte rd
493// begin // axis tbcall_region
494// CTL_RAM[12] <= (CTL_RAM[12] & 32'hffffffee);
495// end
496 if (ssi_snd_last & (SSI_CMD_ADR == 28'h0c2c005)) // Status Byte wr
497 begin // axis tbcall_region
498 $display("Writing cmp_mask [sbyte write] %x", CONSOLE_RD_TIMER);
499$writememh("include/CONSOLE_RAM", rf2x32.REGF2X32);
500 end
501//if (ssi_snd_last & (SSI_CMD_ADR == 28'h0c2c005)) // Status Byte wr
502// begin // axis tbcall_region
503// CTL_RAM[12] <= (CTL_RAM[12] & 32'hffffffee);
504// end
505 if (console_rd_v) // Status Byte rd
506 begin // axis tbcall_region
507 $display("Reading cmp_mask [sbyte read] %x", CONSOLE_RD_TIMER);
508$readmemh("include/CONSOLE_RAM", rf2x32.REGF2X32);
509 end
510
511`ifdef AXIS
512 CONSOLE_RD_TIMER <= (reset) ? 14'h03 : console_rd_timerP;
513`else
514 CONSOLE_RD_TIMER <= (reset) ? 14'hff : console_rd_timerP;
515`endif
516
517 SSI_CMD_SEQ <= (reset) ? 32'h0 : ssi_cmd_seqP;
518 SSI_CMD_RW <= (reset) ? 1'h0 : ssi_cmd_rwP;
519 SSI_CMD_LNGT <= (reset) ? 2'h0 : ssi_cmd_lngtP;
520 SSI_CMD_ADR <= (reset) ? 28'h0 : ssi_cmd_adrP;
521 SSI_RTN_SEQ <= (reset) ? 66'h0 : ssi_rtn_seqP;
522 SSI_SND_SEQ <= (reset) ? 66'h0 : ssi_snd_seqP;
523 SSI_WR_RSPN <= (reset) ? 2'b0 : ssi_wr_rspnP;
524 SSI_RTN_DATA <= (reset) ? 64'h0 : ssi_rtn_dataP;
525 SSI_SND_DATA <= (reset) ? 64'h0 : ssi_snd_dataP;
526 SSI_RTN_PAR <= (reset) ? 1'h0 : ssi_rtn_parP;
527 SSI_DELAY <= (reset) ? 16'h0 : ssi_delayP;
528end
529`else
530assign io_jbi_ssi_miso = 1'b0;
531`endif
532
533
534wire [ 7:0] iob_line = jbi_rom_adr[ 7: 0];
535// assign iob_index[26:8] = ({jbi_rom_adr[ 39: 9],jbi_rom_adr[6]} + jbi_rom_adr[ 39:15]) & 19'h7FFFF;
536assign iob_index[26:8] = ({jbi_rom_adr[ 39: 9],jbi_rom_adr[6]}) & 19'h7FFFF;
537wire [39:8] iob_match = jbi_rom_adr[ 39: 8];
538
539
540//}}}
541//{{{ misc iob/ccx stuff
542/**************************************************************************************************************
543* This logic responds to IFILL requests from the cmp. Whenever a request pcx_iob_data_px2[123:0] is received,
544* iob_cpx_req_cq is asserted the next cycle with a one-hot version of the Cpu_id field of pcx_iob_data_px2.
545* Then, on the next cycle, iob_cpx_data_ca[144:0] is asserted.
546* This sequence has priority over the poweron interrupts being sent to wake up the threads. Thus there
547* needs to be no queuing and grant can be ignored.
548**************************************************************************************************************/
549
550
551
552wire [ 5:0] iob_way = ~pcx_iob_fill_ld ? 6'b000000 :
553 (iob_dir0_do == iob_match) ? 6'b000000 :
554 (iob_dir1_do == iob_match) ? 6'b000001 :
555 (iob_dir2_do == iob_match) ? 6'b000010 :
556 (iob_dir3_do == iob_match) ? 6'b000011 :
557 (iob_dir4_do == iob_match) ? 6'b000100 :
558 (iob_dir5_do == iob_match) ? 6'b000101 :
559 (iob_dir6_do == iob_match) ? 6'b000110 :
560 (iob_dir7_do == iob_match) ? 6'b000111 :
561 (iob_dir8_do == iob_match) ? 6'b001000 :
562 (iob_dir9_do == iob_match) ? 6'b001001 :
563 (iob_dira_do == iob_match) ? 6'b001010 :
564 (iob_dirb_do == iob_match) ? 6'b001011 :
565 (iob_dirc_do == iob_match) ? 6'b001100 :
566 (iob_dird_do == iob_match) ? 6'b001101 :
567 (iob_dire_do == iob_match) ? 6'b001110 :
568 (iob_dirf_do == iob_match) ? 6'b001111 :
569 (iob_dir10_do == iob_match) ? 6'b010000 :
570 (iob_dir11_do == iob_match) ? 6'b010001 :
571 (iob_dir12_do == iob_match) ? 6'b010010 :
572 (iob_dir13_do == iob_match) ? 6'b010011 :
573 (iob_dir14_do == iob_match) ? 6'b010100 :
574 (iob_dir15_do == iob_match) ? 6'b010101 :
575 (iob_dir16_do == iob_match) ? 6'b010110 :
576 (iob_dir17_do == iob_match) ? 6'b010111 :
577 (iob_dir18_do == iob_match) ? 6'b011000 :
578 (iob_dir19_do == iob_match) ? 6'b011001 :
579 (iob_dir1a_do == iob_match) ? 6'b011010 :
580 (iob_dir1b_do == iob_match) ? 6'b011011 :
581 (iob_dir1c_do == iob_match) ? 6'b011100 :
582 (iob_dir1d_do == iob_match) ? 6'b011101 :
583 (iob_dir1e_do == iob_match) ? 6'b011110 :
584 (iob_dir1f_do == iob_match) ? 6'b011111 :
585 (iob_dir20_do == iob_match) ? 6'b100000 :
586 (iob_dir21_do == iob_match) ? 6'b100001 :
587 (iob_dir22_do == iob_match) ? 6'b100010 :
588 (iob_dir23_do == iob_match) ? 6'b100011 :
589 (iob_dir24_do == iob_match) ? 6'b100100 :
590 (iob_dir25_do == iob_match) ? 6'b100101 :
591 (iob_dir26_do == iob_match) ? 6'b100110 :
592 (iob_dir27_do == iob_match) ? 6'b100111 :
593 (iob_dir28_do == iob_match) ? 6'b101000 :
594 (iob_dir29_do == iob_match) ? 6'b101001 :
595 (iob_dir2a_do == iob_match) ? 6'b101010 :
596 (iob_dir2b_do == iob_match) ? 6'b101011 :
597 (iob_dir2c_do == iob_match) ? 6'b101100 :
598 (iob_dir2d_do == iob_match) ? 6'b101101 :
599 (iob_dir2e_do == iob_match) ? 6'b101110 :
600 (iob_dir2f_do == iob_match) ? 6'b101111 :
601 (iob_dir30_do == iob_match) ? 6'b110000 :
602 (iob_dir31_do == iob_match) ? 6'b110001 :
603 (iob_dir32_do == iob_match) ? 6'b110010 :
604 (iob_dir33_do == iob_match) ? 6'b110011 :
605 (iob_dir34_do == iob_match) ? 6'b110100 :
606 (iob_dir35_do == iob_match) ? 6'b110101 :
607 (iob_dir36_do == iob_match) ? 6'b110110 :
608 (iob_dir37_do == iob_match) ? 6'b110111 :
609 (iob_dir38_do == iob_match) ? 6'b111000 :
610 (iob_dir39_do == iob_match) ? 6'b111001 :
611 (iob_dir3a_do == iob_match) ? 6'b111010 :
612 (iob_dir3b_do == iob_match) ? 6'b111011 :
613 (iob_dir3c_do == iob_match) ? 6'b111100 :
614 (iob_dir3d_do == iob_match) ? 6'b111101 :
615 (iob_dir3e_do == iob_match) ? 6'b111110 :
616 (iob_dir3f_do == iob_match) ? 6'b111111 :
617 6'b111111;
618
619// wire refresh_max =
620// (|(cmp.dram02.dramctl0.dram_dctl.dram_que.rfc_cnt)) |
621// (|(cmp.dram02.dramctl1.dram_dctl.dram_que.rfc_cnt)) |
622// (|(cmp.dram13.dramctl0.dram_dctl.dram_que.rfc_cnt)) |
623// (|(cmp.dram13.dramctl1.dram_dctl.dram_que.rfc_cnt));
624
625wire [3:0] boot_data_way = {jbi_rom_adr[8:7],jbi_rom_adr[5:4]};
626
627 assign dram_iob_final[127:0] = (boot_data_way == 4'h0) ? iob_do0 :
628 (boot_data_way == 4'h1) ? iob_do1 :
629 (boot_data_way == 4'h2) ? iob_do2 :
630 (boot_data_way == 4'h3) ? iob_do3 :
631 (boot_data_way == 4'h4) ? iob_do4 :
632 (boot_data_way == 4'h5) ? iob_do5 :
633 (boot_data_way == 4'h6) ? iob_do6 :
634 (boot_data_way == 4'h7) ? iob_do7 :
635 (boot_data_way == 4'h8) ? iob_do8 :
636 (boot_data_way == 4'h9) ? iob_do9 :
637 (boot_data_way == 4'ha) ? iob_doa :
638 (boot_data_way == 4'hb) ? iob_dob :
639 (boot_data_way == 4'hc) ? iob_doc :
640 (boot_data_way == 4'hd) ? iob_dod :
641 (boot_data_way == 4'he) ? iob_doe : iob_dof;
642
643/**************************************************************************************************************
644* Global clock domain registers clocked and initialized
645**************************************************************************************************************/
646reg [5:0] iob_way_d;
647always @(posedge ssiclk) begin
648 IOB_VLD <= (reset) ? 4'b0 : {IOB_VLD[2],IOB_VLD[1], IOB_VLD[0], pcx_iob_fill_ld};
649 IOB_ADR0 <= (reset) ? 33'h0 : { iob_way_d[5:0], iob_index[26:8], iob_line[7:0]};
650 IOB_ADR1 <= (reset) ? 33'h0 : IOB_ADR0[32:0];
651// FINISHED <= (reset) ? 32'h0 : finishedP[31:0];
652 iob_way_d <= (reset) ? 6'b0 :iob_way[5:0];
653 if (IOB_VLD[2])
654 begin // axis tbcall_region
655 $display("SSI PROM READ %h %h %h", jbi_rom_adr, IOB_ADR0, rom_read[63:0]);
656 end
657end
658
659//}}}
660`define DUMP_DRAM1
661`ifdef DUMP_DRAM
662//{{{ dram dump
663//always @(posedge clk) begin
664initial begin
665// if (sim_done[0] & ~sim_done[1] & write_mem)
666
667#4500000 ;
668 begin // axis tbcall_region
669 $display("DUMPING MEMORY");
670$writememh("dram_init/dump0", dram0.DRAM);
671$writememh("dram_init/dump1", dram1.DRAM);
672$writememh("dram_init/dump2", dram2.DRAM);
673$writememh("dram_init/dump3", dram3.DRAM);
674$writememh("dram_init/dump4", dram4.DRAM);
675$writememh("dram_init/dump5", dram5.DRAM);
676$writememh("dram_init/dump6", dram6.DRAM);
677$writememh("dram_init/dump7", dram7.DRAM);
678$writememh("dram_init/dump8", dram8.DRAM);
679$writememh("dram_init/dump9", dram9.DRAM);
680$writememh("dram_init/dumpa", drama.DRAM);
681$writememh("dram_init/dumpb", dramb.DRAM);
682$writememh("dram_init/dumpc", dramc.DRAM);
683$writememh("dram_init/dumpd", dramd.DRAM);
684$writememh("dram_init/dumpe", drame.DRAM);
685$writememh("dram_init/dumpf", dramf.DRAM);
686 end
687end
688//}}}
689`endif
690reg [31:0] CTL_RAM [31:0];
691`define DRAM_SLAM
692//`define DRAM_PLUSARGS
693
694//{{{ dram setup
695`ifdef DRAM_SLAM
696wire [2:0] que_data_del_cnt = (CTL_RAM[15] & 7); // Delay for DRAM reads
697wire [2:0] que_data_del_cnt0 = (CTL_RAM[15] & 7); // Delay for DRAM reads
698wire [2:0] que_data_del_cnt1 = (CTL_RAM[15] & 7); // Delay for DRAM reads
699wire [2:0] que_data_del_cnt2 = (CTL_RAM[15] & 7); // Delay for DRAM reads
700wire [2:0] que_data_del_cnt3 = (CTL_RAM[15] & 7); // Delay for DRAM reads
701wire que_eight_bank_mode = ((CTL_RAM[15] >> 4) & 1); // Eight Bank Mode
702wire que_eight_bank_mode0 = ((CTL_RAM[15] >> 4) & 1); // Eight Bank Mode
703wire que_eight_bank_mode1 = ((CTL_RAM[15] >> 4) & 1); // Eight Bank Mode
704wire que_eight_bank_mode2 = ((CTL_RAM[15] >> 4) & 1); // Eight Bank Mode
705wire que_eight_bank_mode3 = ((CTL_RAM[15] >> 4) & 1); // Eight Bank Mode
706wire [3:0] ras_addr_width = ((CTL_RAM[15] >> 8) & 15); // RAS address width
707wire [3:0] ras_addr_width0 = ((CTL_RAM[15] >> 8) & 15); // RAS address width
708wire [3:0] ras_addr_width1 = ((CTL_RAM[15] >> 8) & 15); // RAS address width
709wire [3:0] ras_addr_width2 = ((CTL_RAM[15] >> 8) & 15); // RAS address width
710wire [3:0] ras_addr_width3 = ((CTL_RAM[15] >> 8) & 15); // RAS address width
711wire stacked_dimm = ((CTL_RAM[15] >>12) & 1); // Stacked DIMM DRAM
712wire stacked_dimm0 = ((CTL_RAM[15] >>12) & 1); // Stacked DIMM DRAM
713wire stacked_dimm1 = ((CTL_RAM[15] >>12) & 1); // Stacked DIMM DRAM
714wire stacked_dimm2 = ((CTL_RAM[15] >>12) & 1); // Stacked DIMM DRAM
715wire stacked_dimm3 = ((CTL_RAM[15] >>12) & 1); // Stacked DIMM DRAM
716wire que_rank1_present = ((CTL_RAM[15] >>16) & 1); // DRAM rank1
717wire que_rank1_present0 = ((CTL_RAM[15] >>16) & 1); // DRAM rank1
718wire que_rank1_present1 = ((CTL_RAM[15] >>16) & 1); // DRAM rank1
719wire que_rank1_present2 = ((CTL_RAM[15] >>16) & 1); // DRAM rank1
720wire que_rank1_present3 = ((CTL_RAM[15] >>16) & 1); // DRAM rank1
721wire [2:0] que_tot_ranks = ((CTL_RAM[15] >>20) & 7); // DRAM total ranks. Derivitive
722
723
724`elsif DRAM_PLUSARGS
725reg [2:0] que_data_del_cnt ;
726reg [2:0] que_data_del_cnt0 ;
727reg [2:0] que_data_del_cnt1 ;
728reg [2:0] que_data_del_cnt2 ;
729reg [2:0] que_data_del_cnt3 ;
730reg que_eight_bank_mode ;
731reg que_eight_bank_mode0 ;
732reg que_eight_bank_mode1 ;
733reg que_eight_bank_mode2 ;
734reg que_eight_bank_mode3 ;
735reg [3:0] ras_addr_width ;
736reg [3:0] ras_addr_width0 ;
737reg [3:0] ras_addr_width1 ;
738reg [3:0] ras_addr_width2 ;
739reg [3:0] ras_addr_width3 ;
740reg stacked_dimm ;
741reg stacked_dimm0 ;
742reg stacked_dimm1 ;
743reg stacked_dimm2 ;
744reg stacked_dimm3 ;
745reg que_rank1_present ;
746reg que_rank1_present0 ;
747reg que_rank1_present1 ;
748reg que_rank1_present2 ;
749reg que_rank1_present3 ;
750reg [2:0] que_tot_ranks ;
751
752`ifdef PALLADIUM
753initial
754begin
755 CTL_RAM[0] <= 'h00000a71;
756 CTL_RAM[1] <= 'h00000001;
757 CTL_RAM[2] <= 'h00000000;
758 CTL_RAM[3] <= 'h00080c1c;
759 CTL_RAM[4] <= 'h00000000;
760 CTL_RAM[5] <= 'h00000100;
761 CTL_RAM[6] <= 'h040E0C02;
762 CTL_RAM[7] <= 'h300E0150;
763 CTL_RAM[8] <= 'h41410506;
764 CTL_RAM[9] <= 'h00000041;
765 CTL_RAM[10] <= 'h42420405;
766 CTL_RAM[11] <= 'h00000042;
767 CTL_RAM[12] <= 'h00000060;
768 CTL_RAM[13] <= 'h00000002;
769 CTL_RAM[14] <= 'h00000000;
770 CTL_RAM[15] <= 'h00411f11;
771 CTL_RAM[16] <= 'h00000191;
772 CTL_RAM[17] <= 'h00000000;
773 CTL_RAM[18] <= 'h00000000;
774 CTL_RAM[19] <= 'h00000000;
775 CTL_RAM[20] <= 'h00000200;
776 CTL_RAM[21] <= 'h00000000;
777 CTL_RAM[22] <= 'h00000000;
778 CTL_RAM[23] <= 'h00000000;
779 CTL_RAM[24] <= 'h00000000;
780 CTL_RAM[25] <= 'h00000000;
781 CTL_RAM[26] <= 'h00000000;
782 CTL_RAM[27] <= 'h00000001;
783 CTL_RAM[28] <= 'h00000001;
784 CTL_RAM[29] <= 'h00000001;
785 CTL_RAM[30] <= 'h00000001;
786 CTL_RAM[31] <= 'h10000000;
787end // initial begin
788`endif // `ifdef PALLADIUM
789
790initial
791begin
792 $display("Setting DRAM using cmd line plusargs\n");
793
794 if ( $value$plusargs("que_tot_ranks=%h",que_tot_ranks))
795 begin
796 $display("que_tot_ranks=%b\n",que_tot_ranks);
797 que_data_del_cnt0 = que_data_del_cnt; // Making it non-blocking
798 que_data_del_cnt1 = que_data_del_cnt; // to break the race bw
799 que_data_del_cnt2 = que_data_del_cnt; // assign and initial
800 que_data_del_cnt3 = que_data_del_cnt;
801 end
802 if ( $value$plusargs("que_data_del_cnt=%h",que_data_del_cnt))
803 begin
804 $display("que_data_del_cnt=%b\n",que_data_del_cnt);
805 que_eight_bank_mode0 = que_eight_bank_mode;
806 que_eight_bank_mode1 = que_eight_bank_mode;
807 que_eight_bank_mode2 = que_eight_bank_mode;
808 que_eight_bank_mode3 = que_eight_bank_mode;
809 end
810 else
811 begin
812 $display("que_data_del_cnt=%b\n",que_data_del_cnt);
813 que_eight_bank_mode0 = que_eight_bank_mode;
814 que_eight_bank_mode1 = que_eight_bank_mode;
815 que_eight_bank_mode2 = que_eight_bank_mode;
816 que_eight_bank_mode3 = que_eight_bank_mode;
817 end
818 if ( $value$plusargs("ras_addr_width=%h",ras_addr_width))
819 begin
820 $display("ras_addr_width=%b\n",ras_addr_width);
821 end
822 if ( $value$plusargs("stacked_dimm=%h",stacked_dimm))
823 begin
824 $display("stacked_dimm=%b\n",stacked_dimm);
825 stacked_dimm0 = stacked_dimm;
826 stacked_dimm1 = stacked_dimm;
827 stacked_dimm2 = stacked_dimm;
828 stacked_dimm3 = stacked_dimm;
829 end
830 if ( $value$plusargs("que_eight_bank_mode=%h",que_eight_bank_mode))
831 begin
832 $display("que_eight_bank_mode=%b\n",que_eight_bank_mode);
833 end
834 if ( $value$plusargs("que_rank1_present=%h",que_rank1_present))
835 begin
836 $display("que_rank1_present=%b\n",que_rank1_present);
837 que_rank1_present0 = que_rank1_present;
838 que_rank1_present1 = que_rank1_present;
839 que_rank1_present2 = que_rank1_present;
840 que_rank1_present3 = que_rank1_present;
841 end
842
843end
844
845`else
846wire [2:0] que_data_del_cnt0 = cmp.dram02.dramctl0.dram_dctl.dram_que.que_data_del_cnt;
847wire [2:0] que_data_del_cnt1 = cmp.dram13.dramctl0.dram_dctl.dram_que.que_data_del_cnt;
848wire [2:0] que_data_del_cnt2 = cmp.dram02.dramctl1.dram_dctl.dram_que.que_data_del_cnt;
849wire [2:0] que_data_del_cnt3 = cmp.dram13.dramctl1.dram_dctl.dram_que.que_data_del_cnt;
850wire que_eight_bank_mode0 = cmp.dram02.dramctl0.dram_dctl.dram_que.que_eight_bank_mode;
851wire que_eight_bank_mode1 = cmp.dram13.dramctl0.dram_dctl.dram_que.que_eight_bank_mode;
852wire que_eight_bank_mode2 = cmp.dram02.dramctl1.dram_dctl.dram_que.que_eight_bank_mode;
853wire que_eight_bank_mode3 = cmp.dram13.dramctl1.dram_dctl.dram_que.que_eight_bank_mode;
854wire [3:0] ras_addr_width0 = cmp.dram02.dramctl0.dram_dctl.dram_que.chip_config_reg[8:5];
855wire [3:0] ras_addr_width1 = cmp.dram13.dramctl0.dram_dctl.dram_que.chip_config_reg[8:5];
856wire [3:0] ras_addr_width2 = cmp.dram02.dramctl1.dram_dctl.dram_que.chip_config_reg[8:5];
857wire [3:0] ras_addr_width3 = cmp.dram13.dramctl1.dram_dctl.dram_que.chip_config_reg[8:5];
858wire stacked_dimm0 = cmp.dram02.dramctl0.dram_dctl.dram_que.chip_config_reg[0];
859wire stacked_dimm1 = cmp.dram13.dramctl0.dram_dctl.dram_que.chip_config_reg[0];
860wire stacked_dimm2 = cmp.dram02.dramctl1.dram_dctl.dram_que.chip_config_reg[0];
861wire stacked_dimm3 = cmp.dram13.dramctl1.dram_dctl.dram_que.chip_config_reg[0];
862wire que_rank1_present0 = cmp.dram02.dramctl0.dram_dctl.dram_que.que_rank1_present;
863wire que_rank1_present1 = cmp.dram13.dramctl0.dram_dctl.dram_que.que_rank1_present;
864wire que_rank1_present2 = cmp.dram02.dramctl1.dram_dctl.dram_que.que_rank1_present;
865wire que_rank1_present3 = cmp.dram13.dramctl1.dram_dctl.dram_que.que_rank1_present;
866`endif
867wire dram_dump = ((CTL_RAM[29] <= CLK_CNT[39:8]) & (|CTL_RAM[29])); // DRAM write and read data
868//}}}
869//{{{ dram
870/**************************************************************************************************************
871* DRAM clock domain registers
872**************************************************************************************************************/
873reg [ 6: 0] DRAM0_WRITV_P ; // WRITE SEQUENCE FROM CAS
874reg [ 6: 0] DRAM0_READV_P ; // READ SEQUENCE FROM CAS
875reg [ 5: 0] DRAM0_CQWF_P ; // POSITIVE CLOCK DOMAIN CRITICAL QUADWORD FIRST ADDRESS BIT STAGED
876reg [ 6: 0] DRAM0_PARITY_P; // POSITIVE CLOCK DOMAIN ADDRESS PARITY
877reg [36: 4] DRAM0_ADR_HOLD; // PA FROM CAS CYCLE
878reg [33: 8] DRAM0_ADR0_P ; // POSITIVE CLOCK DOMAIN STAGED ADDRESS (0-5 clocks from CAS)
879reg [33: 8] DRAM0_ADR1_P ;
880reg [33: 8] DRAM0_ADR2_P ;
881reg [33: 8] DRAM0_ADR3_P ;
882reg [33: 8] DRAM0_ADR4_P ;
883reg [33: 8] DRAM0_ADR5_P ;
884reg [127:0] DRAM0_DATA_02_6; // STAGED DRAM DATA 02
885reg [ 15:0] DRAM0_ECC_02_6; // STAGED DRAM ECC 02
886reg DRAM0_READV5_N; // NEGATIVE CLOCK DOMAIN READ VALID SEQUENCE
887reg DRAM0_CQWF5_N ; // NEGATIVE CLOCK DOMAIN CRITICAL QUADWORD FIRST ADDRESS BIT STAGED
888reg DRAM0_PARITY5_N; // NEGATIVE CLOCK DOMAIN ADDRESS PARITY
889reg DRAM0_PARITY6_N; // NEGATIVE CLOCK DOMAIN ADDRESS PARITY
890reg [33: 8] DRAM0_ADR5_N ; // NEGATIVE CLOCK DOMAIN STAGED ADDRESS (5 clocks from CAS)
891reg [127:0] DRAM0_DATA_13_6; // STAGED DRAM DATA 13
892reg [ 15:0] DRAM0_ECC_13_6; // STAGED DRAM ECC 13
893
894reg [ 6: 0] DRAM1_WRITV_P ; // WRITE SEQUENCE FROM CAS
895reg [ 6: 0] DRAM1_READV_P ; // READ SEQUENCE FROM CAS
896reg [ 5: 0] DRAM1_CQWF_P ; // POSITIVE CLOCK DOMAIN CRITICAL QUADWORD FIRST ADDRESS BIT STAGED
897reg [ 6: 0] DRAM1_PARITY_P; // POSITIVE CLOCK DOMAIN ADDRESS PARITY
898reg [36: 4] DRAM1_ADR_HOLD; // PA FROM CAS CYCLE
899reg [33: 8] DRAM1_ADR0_P ; // POSITIVE CLOCK DOMAIN STAGED ADDRESS (0-5 clocks from CAS)
900reg [33: 8] DRAM1_ADR1_P ;
901reg [33: 8] DRAM1_ADR2_P ;
902reg [33: 8] DRAM1_ADR3_P ;
903reg [33: 8] DRAM1_ADR4_P ;
904reg [33: 8] DRAM1_ADR5_P ;
905reg [127:0] DRAM1_DATA_02_6; // STAGED DRAM DATA 02
906reg DRAM1_READV5_N; // NEGATIVE CLOCK DOMAIN READ VALID SEQUENCE
907reg DRAM1_CQWF5_N ; // NEGATIVE CLOCK DOMAIN CRITICAL QUADWORD FIRST ADDRESS BIT STAGED
908reg DRAM1_PARITY5_N; // NEGATIVE CLOCK DOMAIN ADDRESS PARITY
909reg DRAM1_PARITY6_N; // NEGATIVE CLOCK DOMAIN ADDRESS PARITY
910reg [33: 8] DRAM1_ADR5_N ; // NEGATIVE CLOCK DOMAIN STAGED ADDRESS (5 clocks from CAS)
911reg [127:0] DRAM1_DATA_13_6; // STAGED DRAM DATA 13
912reg [ 15:0] DRAM1_ECC_02_6; // STAGED DRAM ECC 02
913reg [ 15:0] DRAM1_ECC_13_6; // STAGED DRAM ECC 13
914
915reg [ 6: 0] DRAM2_WRITV_P ; // WRITE SEQUENCE FROM CAS
916reg [ 6: 0] DRAM2_READV_P ; // READ SEQUENCE FROM CAS
917reg [ 5: 0] DRAM2_CQWF_P ; // POSITIVE CLOCK DOMAIN CRITICAL QUADWORD FIRST ADDRESS BIT STAGED
918reg [ 6: 0] DRAM2_PARITY_P; // POSITIVE CLOCK DOMAIN ADDRESS PARITY
919reg [36: 4] DRAM2_ADR_HOLD; // PA FROM CAS CYCLE
920reg [33: 8] DRAM2_ADR0_P ; // POSITIVE CLOCK DOMAIN STAGED ADDRESS (0-5 clocks from CAS)
921reg [33: 8] DRAM2_ADR1_P ;
922reg [33: 8] DRAM2_ADR2_P ;
923reg [33: 8] DRAM2_ADR3_P ;
924reg [33: 8] DRAM2_ADR4_P ;
925reg [33: 8] DRAM2_ADR5_P ;
926reg [127:0] DRAM2_DATA_02_6; // STAGED DRAM DATA 02
927reg DRAM2_READV5_N; // NEGATIVE CLOCK DOMAIN READ VALID SEQUENCE
928reg DRAM2_CQWF5_N ; // NEGATIVE CLOCK DOMAIN CRITICAL QUADWORD FIRST ADDRESS BIT STAGED
929reg DRAM2_PARITY5_N; // NEGATIVE CLOCK DOMAIN ADDRESS PARITY
930reg DRAM2_PARITY6_N; // NEGATIVE CLOCK DOMAIN ADDRESS PARITY
931reg [33: 8] DRAM2_ADR5_N ; // NEGATIVE CLOCK DOMAIN STAGED ADDRESS (5 clocks from CAS)
932reg [127:0] DRAM2_DATA_13_6; // STAGED DRAM DATA 13
933reg [ 15:0] DRAM2_ECC_02_6; // STAGED DRAM ECC 02
934reg [ 15:0] DRAM2_ECC_13_6; // STAGED DRAM ECC 13
935
936reg [ 6: 0] DRAM3_WRITV_P ; // WRITE SEQUENCE FROM CAS
937reg [ 6: 0] DRAM3_READV_P ; // READ SEQUENCE FROM CAS
938reg [ 5: 0] DRAM3_CQWF_P ; // POSITIVE CLOCK DOMAIN CRITICAL QUADWORD FIRST ADDRESS BIT STAGED
939reg [ 6: 0] DRAM3_PARITY_P; // POSITIVE CLOCK DOMAIN ADDRESS PARITY
940reg [36: 4] DRAM3_ADR_HOLD; // PA FROM CAS CYCLE
941reg [33: 8] DRAM3_ADR0_P ; // POSITIVE CLOCK DOMAIN STAGED ADDRESS (0-5 clocks from CAS)
942reg [33: 8] DRAM3_ADR1_P ;
943reg [33: 8] DRAM3_ADR2_P ;
944reg [33: 8] DRAM3_ADR3_P ;
945reg [33: 8] DRAM3_ADR4_P ;
946reg [33: 8] DRAM3_ADR5_P ;
947reg [127:0] DRAM3_DATA_02_6; // STAGED DRAM DATA 02
948reg DRAM3_READV5_N; // NEGATIVE CLOCK DOMAIN READ VALID SEQUENCE
949reg DRAM3_CQWF5_N ; // NEGATIVE CLOCK DOMAIN CRITICAL QUADWORD FIRST ADDRESS BIT STAGED
950reg DRAM3_PARITY5_N; // NEGATIVE CLOCK DOMAIN ADDRESS PARITY
951reg DRAM3_PARITY6_N; // NEGATIVE CLOCK DOMAIN ADDRESS PARITY
952reg [33: 8] DRAM3_ADR5_N ; // NEGATIVE CLOCK DOMAIN STAGED ADDRESS (5 clocks from CAS)
953reg [127:0] DRAM3_DATA_13_6; // STAGED DRAM DATA 13
954reg [ 15:0] DRAM3_ECC_02_6; // STAGED DRAM ECC 02
955reg [ 15:0] DRAM3_ECC_13_6; // STAGED DRAM ECC 13
956reg IO_DRAM0_DATA_VALID_NXT;
957reg IO_DRAM1_DATA_VALID_NXT;
958reg IO_DRAM2_DATA_VALID_NXT;
959reg IO_DRAM3_DATA_VALID_NXT;
960
961/**************************************************************************************************************
962* DIRECTORY RAM definitions
963**************************************************************************************************************/
964wire [127:0] dram0_data_read0, dram0_data_read1, dram0_data_read2, dram0_data_read3;
965wire [127:0] dram1_data_read0, dram1_data_read1, dram1_data_read2, dram1_data_read3;
966wire [127:0] dram2_data_read0, dram2_data_read1, dram2_data_read2, dram2_data_read3;
967wire [127:0] dram3_data_read0, dram3_data_read1, dram3_data_read2, dram3_data_read3;
968wire [ 15:0] dram0_ecc_read0, dram0_ecc_read1, dram0_ecc_read2, dram0_ecc_read3;
969wire [ 15:0] dram1_ecc_read0, dram1_ecc_read1, dram1_ecc_read2, dram1_ecc_read3;
970wire [ 15:0] dram2_ecc_read0, dram2_ecc_read1, dram2_ecc_read2, dram2_ecc_read3;
971wire [ 15:0] dram3_ecc_read0, dram3_ecc_read1, dram3_ecc_read2, dram3_ecc_read3;
972
973dram_data dram0 (.clk(dramclk), .rd_adr0(IOB_ADR1[32:8]), .rd_adr1(DRAM0_ADR5_P),
974 .dout0 (iob_do0[127:0]), .dout1 (dram0_data_read0), .eout1(dram0_ecc_read0),
975 .wr_adr0(DRAM0_ADR5_P), .we_0(DRAM0_WRITV_P[5]),
976 .din_0(dram0_io_data_out[143: 0]), .dram_dump(dram_dump));
977dram_data dram1 (.clk(dramclk), .rd_adr0(IOB_ADR1[32:8]), .rd_adr1(DRAM0_ADR5_N),
978 .dout0 (iob_do1[127:0]), .dout1 (dram0_data_read1), .eout1(dram0_ecc_read1),
979 .wr_adr0(DRAM0_ADR5_P), .we_0(DRAM0_WRITV_P[5]),
980 .din_0(dram0_io_data_out[287:144]), .dram_dump(dram_dump));
981dram_data dram2 (.clk(dramclk), .rd_adr0(IOB_ADR1[32:8]), .rd_adr1(DRAM0_ADR5_P),
982 .dout0 (iob_do2[127:0]), .dout1 (dram0_data_read2), .eout1(dram0_ecc_read2),
983 .wr_adr0(DRAM0_ADR5_P), .we_0(DRAM0_WRITV_P[6]),
984 .din_0(dram0_io_data_out[143: 0]), .dram_dump(dram_dump));
985dram_data dram3 (.clk(dramclk), .rd_adr0(IOB_ADR1[32:8]), .rd_adr1(DRAM0_ADR5_N),
986 .dout0 (iob_do3[127:0]), .dout1 (dram0_data_read3), .eout1(dram0_ecc_read3),
987 .wr_adr0(DRAM0_ADR5_P), .we_0(DRAM0_WRITV_P[6]),
988 .din_0(dram0_io_data_out[287:144]), .dram_dump(dram_dump));
989
990dram_data dram4 (.clk(dramclk), .rd_adr0(IOB_ADR1[32:8]), .rd_adr1(DRAM1_ADR5_P),
991 .dout0 (iob_do4[127:0]), .dout1 (dram1_data_read0), .eout1(dram1_ecc_read0),
992 .wr_adr0(DRAM1_ADR5_P), .we_0(DRAM1_WRITV_P[5]),
993 .din_0(dram1_io_data_out[143: 0]), .dram_dump(dram_dump));
994dram_data dram5 (.clk(dramclk), .rd_adr0(IOB_ADR1[32:8]), .rd_adr1(DRAM1_ADR5_N),
995 .dout0 (iob_do5[127:0]), .dout1 (dram1_data_read1), .eout1(dram1_ecc_read1),
996 .wr_adr0(DRAM1_ADR5_P), .we_0(DRAM1_WRITV_P[5]),
997 .din_0(dram1_io_data_out[287:144]), .dram_dump(dram_dump));
998dram_data dram6 (.clk(dramclk), .rd_adr0(IOB_ADR1[32:8]), .rd_adr1(DRAM1_ADR5_P),
999 .dout0 (iob_do6[127:0]), .dout1 (dram1_data_read2), .eout1(dram1_ecc_read2),
1000 .wr_adr0(DRAM1_ADR5_P), .we_0(DRAM1_WRITV_P[6]),
1001 .din_0(dram1_io_data_out[143: 0]), .dram_dump(dram_dump));
1002dram_data dram7 (.clk(dramclk), .rd_adr0(IOB_ADR1[32:8]), .rd_adr1(DRAM1_ADR5_N),
1003 .dout0 (iob_do7[127:0]), .dout1 (dram1_data_read3), .eout1(dram1_ecc_read3),
1004 .wr_adr0(DRAM1_ADR5_P), .we_0(DRAM1_WRITV_P[6]),
1005 .din_0(dram1_io_data_out[287:144]), .dram_dump(dram_dump));
1006
1007dram_data dram8 (.clk(dramclk), .rd_adr0(IOB_ADR1[32:8]), .rd_adr1(DRAM2_ADR5_P),
1008 .dout0 (iob_do8[127:0]), .dout1 (dram2_data_read0), .eout1(dram2_ecc_read0),
1009 .wr_adr0(DRAM2_ADR5_P), .we_0(DRAM2_WRITV_P[5]),
1010 .din_0(dram2_io_data_out[143: 0]), .dram_dump(dram_dump));
1011dram_data dram9 (.clk(dramclk), .rd_adr0(IOB_ADR1[32:8]), .rd_adr1(DRAM2_ADR5_N),
1012 .dout0 (iob_do9[127:0]), .dout1 (dram2_data_read1), .eout1(dram2_ecc_read1),
1013 .wr_adr0(DRAM2_ADR5_P), .we_0(DRAM2_WRITV_P[5]),
1014 .din_0(dram2_io_data_out[287:144]), .dram_dump(dram_dump));
1015dram_data drama (.clk(dramclk), .rd_adr0(IOB_ADR1[32:8]), .rd_adr1(DRAM2_ADR5_P),
1016 .dout0 (iob_doa[127:0]), .dout1 (dram2_data_read2), .eout1(dram2_ecc_read2),
1017 .wr_adr0(DRAM2_ADR5_P), .we_0(DRAM2_WRITV_P[6]),
1018 .din_0(dram2_io_data_out[143: 0]), .dram_dump(dram_dump));
1019dram_data dramb (.clk(dramclk), .rd_adr0(IOB_ADR1[32:8]), .rd_adr1(DRAM2_ADR5_N),
1020 .dout0 (iob_dob[127:0]), .dout1 (dram2_data_read3), .eout1(dram2_ecc_read3),
1021 .wr_adr0(DRAM2_ADR5_P), .we_0(DRAM2_WRITV_P[6]),
1022 .din_0(dram2_io_data_out[287:144]), .dram_dump(dram_dump));
1023
1024dram_data dramc (.clk(dramclk), .rd_adr0(IOB_ADR1[32:8]), .rd_adr1(DRAM3_ADR5_P),
1025 .dout0 (iob_doc[127:0]), .dout1 (dram3_data_read0), .eout1(dram3_ecc_read0),
1026 .wr_adr0(DRAM3_ADR5_P), .we_0(DRAM3_WRITV_P[5]),
1027 .din_0(dram3_io_data_out[143: 0]), .dram_dump(dram_dump));
1028dram_data dramd (.clk(dramclk), .rd_adr0(IOB_ADR1[32:8]), .rd_adr1(DRAM3_ADR5_N),
1029 .dout0 (iob_dod[127:0]), .dout1 (dram3_data_read1), .eout1(dram3_ecc_read1),
1030 .wr_adr0(DRAM3_ADR5_P), .we_0(DRAM3_WRITV_P[5]),
1031 .din_0(dram3_io_data_out[287:144]), .dram_dump(dram_dump));
1032dram_data drame (.clk(dramclk), .rd_adr0(IOB_ADR1[32:8]), .rd_adr1(DRAM3_ADR5_P),
1033 .dout0 (iob_doe[127:0]), .dout1 (dram3_data_read2), .eout1(dram3_ecc_read2),
1034 .wr_adr0(DRAM3_ADR5_P), .we_0(DRAM3_WRITV_P[6]),
1035 .din_0(dram3_io_data_out[143: 0]), .dram_dump(dram_dump));
1036dram_data dramf (.clk(dramclk), .rd_adr0(IOB_ADR1[32:8]), .rd_adr1(DRAM3_ADR5_N),
1037 .dout0 (iob_dof[127:0]), .dout1 (dram3_data_read3), .eout1(dram3_ecc_read3),
1038 .wr_adr0(DRAM3_ADR5_P), .we_0(DRAM3_WRITV_P[6]),
1039 .din_0(dram3_io_data_out[287:144]), .dram_dump(dram_dump));
1040
1041
1042reg [34:20] RAS [127:0];
1043
1044/**************************************************************************************************************
1045* This logic cobbles together the physical address from the ras/cas and dram control signals.
1046* The code below is from Sunil V @ /home/svemul/addr.enc
1047*
1048if(8bank_mode){
1049 if(ras_addr_width == 14){
1050 if(rank & stack) {
1051 assign dram2_adr_cas[35:34] = {((dram2_io_cs_l == 4'h7) | (dram2_io_cs_l == 4'hb)),
1052 ((dram2_io_cs_l == 4'h7) | (dram2_io_cs_l == 4'hd))};
1053 }else if(rank | stack) {
1054 assign dram2_adr_cas[34] = {(dram2_io_cs_l == 4'hb) | (dram2_io_cs_l == 4'hd)};
1055 }
1056 assign dram2_adr_cas[33:20] = RAS[dram2_io_addr[13:0]];
1057 }
1058 if(ras_addr_width == 15){
1059 if(rank & stack) {
1060 assign dram2_adr_cas[36:35] = {((dram2_io_cs_l == 4'h7) | (dram2_io_cs_l == 4'hb)),
1061 ((dram2_io_cs_l == 4'h7) | (dram2_io_cs_l == 4'hd))};
1062 }else if(rank | stack){
1063 assign dram2_adr_cas[35] = {(dram2_io_cs_l == 4'hb) | (dram2_io_cs_l == 4'hd)};
1064 }
1065 assign dram2_adr_cas[34:20] = RAS[dram2_io_addr[14:0]];
1066 }
1067else{
1068 if(ras_addr_width == 13){
1069 if(rank & stack){
1070 assign dram2_adr_cas[33:32] = {((dram2_io_cs_l == 4'h7) | (dram2_io_cs_l == 4'hb)),
1071 ((dram2_io_cs_l == 4'h7) | (dram2_io_cs_l == 4'hd))};
1072 }else if(rank | stack) {
1073 assign dram2_adr_cas[32] = {(dram2_io_cs_l == 4'hb) | (dram2_io_cs_l == 4'hd)};
1074
1075 }
1076 assign dram2_adr_cas[31:19] = RAS[dram2_io_addr[12:0]];
1077 }
1078 if(ras_addr_width == 14){
1079 if(rank & stack){
1080 assign dram2_adr_cas[34:33] = {((dram2_io_cs_l == 4'h7) | (dram2_io_cs_l == 4'hb)),
1081 ((dram2_io_cs_l == 4'h7) | (dram2_io_cs_l == 4'hd))};
1082 }else if(rank | stack) {
1083 assign dram2_adr_cas[33] = {(dram2_io_cs_l == 4'hb) | (dram2_io_cs_l == 4'hd)};
1084 }
1085 assign dram2_adr_cas[32:19] = RAS[dram2_io_addr[13:0]];
1086 }
1087}
1088
1089if(8bank_mode){
1090 assign dram2_adr_cas[ 19] = dram2_io_addr[11];
1091 assign dram2_adr_cas[18:11] = dram2_io_addr[9:2];
1092 assign dram2_adr_cas[10: 8] = dram2_io_bank[2:0] ^ dram2_adr_cas[20:18] ^ dram2_adr_cas[30:28];
1093}else{
1094 assign dram2_adr_cas[ 18] = dram2_io_addr[11];
1095 assign dram2_adr_cas[17:10] = dram2_io_addr[9:2];
1096 assign dram2_adr_cas[9: 8] = dram2_io_bank[1:0] ^ dram2_adr_cas[19:18] ^ dram2_adr_cas[29:28];
1097}
1098
1099assign dram2_adr_cas[ 7: 6] = 2'b10;
1100assign dram2_adr_cas[ 5: 4] = dram2_io_addr[1:0]
1101******************************** ******************************************************************************/
1102`ifdef N1_addr_decode
1103//{{{ addr decode stuff n1 setup
1104wire [36:4] dram0_adr_cas;
1105wire [36:4] dram1_adr_cas;
1106wire [36:4] dram2_adr_cas;
1107wire [36:4] dram3_adr_cas;
1108
1109// BANK0
1110wire rank_and_stack0 = stacked_dimm0 & que_rank1_present0;
1111wire rank_xor_stack0 = stacked_dimm0 ^ que_rank1_present0;
1112
1113wire [2:0] dram0_cs_adr = {((dram0_io_cs_l == 4'hb) | (dram0_io_cs_l == 4'hd)),
1114 ((dram0_io_cs_l == 4'h7) | (dram0_io_cs_l == 4'hb)),
1115 ((dram0_io_cs_l == 4'h7) | (dram0_io_cs_l == 4'hd))};
1116
1117assign dram0_adr_cas[36] = que_eight_bank_mode0 &
1118 ((ras_addr_width0 == 15) & rank_and_stack0 & dram0_cs_adr[1]);
1119assign dram0_adr_cas[35] = que_eight_bank_mode0 &
1120 (((ras_addr_width0 == 14) & rank_and_stack0 & dram0_cs_adr[1]) |
1121 ((ras_addr_width0 == 15) & rank_and_stack0 & dram0_cs_adr[0]) |
1122 ((ras_addr_width0 == 15) & rank_xor_stack0 & dram0_cs_adr[2]));
1123
1124wire [ 6:0] dram0_ras_adr = que_eight_bank_mode0 ? {2'b00, dram0_adr_cas[36:35], dram0_io_bank[2:0]} :
1125 {2'b00, 2'b00, 1'b0, dram0_io_bank[1:0]};
1126wire [14:0] dram0_ras_data = RAS[dram0_ras_adr];
1127
1128assign dram0_adr_cas[34 ] = que_eight_bank_mode0 ?
1129 (((ras_addr_width0 == 14) & rank_and_stack0 & dram0_cs_adr[0]) |
1130 ((ras_addr_width0 == 14) & rank_xor_stack0 & dram0_cs_adr[2]) |
1131 ((ras_addr_width0 == 15) & dram0_ras_data[14])) :
1132 ((ras_addr_width0 == 14) & rank_and_stack0 & dram0_cs_adr[1]);
1133assign dram0_adr_cas[33 ] = que_eight_bank_mode0 ? dram0_ras_data[13] :
1134 (((ras_addr_width0 == 13) & rank_and_stack0 & dram0_cs_adr[1]) |
1135 ((ras_addr_width0 == 14) & rank_and_stack0 & dram0_cs_adr[0]) |
1136 ((ras_addr_width0 == 14) & rank_xor_stack0 & dram0_cs_adr[2]));
1137assign dram0_adr_cas[32 ] = que_eight_bank_mode0 ? dram0_ras_data[12] :
1138 (((ras_addr_width0 == 13) & rank_and_stack0 & dram0_cs_adr[0]) |
1139 ((ras_addr_width0 == 13) & rank_xor_stack0 & dram0_cs_adr[2]) |
1140 ((ras_addr_width0 == 14) & dram0_ras_data[13]));
1141assign dram0_adr_cas[31:20] = que_eight_bank_mode0 ? dram0_ras_data[11:0] : dram0_ras_data[12:1];
1142assign dram0_adr_cas[ 19] = que_eight_bank_mode0 ? dram0_io_addr[11] : dram0_ras_data[0];
1143assign dram0_adr_cas[ 18] = que_eight_bank_mode0 ? dram0_io_addr[9] : dram0_io_addr[11];
1144assign dram0_adr_cas[17:11] = que_eight_bank_mode0 ? dram0_io_addr[8:2] : dram0_io_addr[9:3];
1145assign dram0_adr_cas[10 ] = que_eight_bank_mode0 ? (dram0_io_bank[2] ^ dram0_adr_cas[20] ^ dram0_adr_cas[30]) :
1146 dram0_io_addr[2];
1147assign dram0_adr_cas[ 9: 8] = (dram0_io_bank[1:0] ^ dram0_adr_cas[19:18] ^ dram0_adr_cas[29:28]);
1148assign dram0_adr_cas[ 7: 6] = 2'b00;
1149assign dram0_adr_cas[ 5: 4] = dram0_io_addr[1:0];
1150
1151// BANK1
1152wire rank_and_stack1 = stacked_dimm1 & que_rank1_present1;
1153wire rank_xor_stack1 = stacked_dimm1 ^ que_rank1_present1;
1154
1155wire [2:0] dram1_cs_adr = {((dram1_io_cs_l == 4'hb) | (dram1_io_cs_l == 4'hd)),
1156 ((dram1_io_cs_l == 4'h7) | (dram1_io_cs_l == 4'hb)),
1157 ((dram1_io_cs_l == 4'h7) | (dram1_io_cs_l == 4'hd))};
1158
1159assign dram1_adr_cas[36] = que_eight_bank_mode1 &
1160 ((ras_addr_width1 == 15) & rank_and_stack1 & dram1_cs_adr[1]);
1161assign dram1_adr_cas[35] = que_eight_bank_mode1 &
1162 (((ras_addr_width1 == 14) & rank_and_stack1 & dram1_cs_adr[1]) |
1163 ((ras_addr_width1 == 15) & rank_and_stack1 & dram1_cs_adr[0]) |
1164 ((ras_addr_width1 == 15) & rank_xor_stack1 & dram1_cs_adr[2]));
1165
1166wire [ 6:0] dram1_ras_adr = que_eight_bank_mode1 ? {2'b01, dram1_adr_cas[36:35], dram1_io_bank[2:0]} :
1167 {2'b01, 2'b00, 1'b0, dram1_io_bank[1:0]};
1168wire [14:0] dram1_ras_data = RAS[dram1_ras_adr];
1169
1170assign dram1_adr_cas[34 ] = que_eight_bank_mode1 ?
1171 (((ras_addr_width1 == 14) & rank_and_stack1 & dram1_cs_adr[0]) |
1172 ((ras_addr_width1 == 14) & rank_xor_stack1 & dram1_cs_adr[2]) |
1173 ((ras_addr_width1 == 15) & dram1_ras_data[14])) :
1174 ((ras_addr_width1 == 14) & rank_and_stack1 & dram1_cs_adr[1]);
1175assign dram1_adr_cas[33 ] = que_eight_bank_mode1 ? dram1_ras_data[13] :
1176 (((ras_addr_width1 == 13) & rank_and_stack1 & dram1_cs_adr[1]) |
1177 ((ras_addr_width1 == 14) & rank_and_stack1 & dram1_cs_adr[0]) |
1178 ((ras_addr_width1 == 14) & rank_xor_stack1 & dram1_cs_adr[2]));
1179assign dram1_adr_cas[32 ] = que_eight_bank_mode1 ? dram1_ras_data[12] :
1180 (((ras_addr_width1 == 13) & rank_and_stack1 & dram1_cs_adr[0]) |
1181 ((ras_addr_width1 == 13) & rank_xor_stack1 & dram1_cs_adr[2]) |
1182 ((ras_addr_width1 == 14) & dram1_ras_data[13]));
1183assign dram1_adr_cas[31:20] = que_eight_bank_mode1 ? dram1_ras_data[11:0] : dram1_ras_data[12:1];
1184assign dram1_adr_cas[ 19] = que_eight_bank_mode1 ? dram1_io_addr[11] : dram1_ras_data[0];
1185assign dram1_adr_cas[ 18] = que_eight_bank_mode1 ? dram1_io_addr[ 9] : dram1_io_addr[11];
1186assign dram1_adr_cas[17:11] = que_eight_bank_mode1 ? dram1_io_addr[8:2] : dram1_io_addr[9:3];
1187assign dram1_adr_cas[10 ] = que_eight_bank_mode1 ? (dram1_io_bank[2] ^ dram1_adr_cas[20] ^ dram1_adr_cas[30]) :
1188 dram1_io_addr[2];
1189assign dram1_adr_cas[ 9: 8] = (dram1_io_bank[1:0] ^ dram1_adr_cas[19:18] ^ dram1_adr_cas[29:28]);
1190assign dram1_adr_cas[ 7: 6] = 2'b01;
1191assign dram1_adr_cas[ 5: 4] = dram1_io_addr[1:0];
1192
1193// BANK2
1194wire rank_and_stack2 = stacked_dimm2 & que_rank1_present2;
1195wire rank_xor_stack2 = stacked_dimm2 ^ que_rank1_present2;
1196
1197wire [2:0] dram2_cs_adr = {((dram2_io_cs_l == 4'hb) | (dram2_io_cs_l == 4'hd)),
1198 ((dram2_io_cs_l == 4'h7) | (dram2_io_cs_l == 4'hb)),
1199 ((dram2_io_cs_l == 4'h7) | (dram2_io_cs_l == 4'hd))};
1200
1201assign dram2_adr_cas[36] = que_eight_bank_mode2 &
1202 ((ras_addr_width2 == 15) & rank_and_stack2 & dram2_cs_adr[1]);
1203assign dram2_adr_cas[35] = que_eight_bank_mode2 &
1204 (((ras_addr_width2 == 14) & rank_and_stack2 & dram2_cs_adr[1]) |
1205 ((ras_addr_width2 == 15) & rank_and_stack2 & dram2_cs_adr[0]) |
1206 ((ras_addr_width2 == 15) & rank_xor_stack2 & dram2_cs_adr[2]));
1207
1208wire [ 6:0] dram2_ras_adr = que_eight_bank_mode2 ? {2'b10, dram2_adr_cas[36:35], dram2_io_bank[2:0]} :
1209 {2'b10, 2'b00, 1'b0, dram2_io_bank[1:0]};
1210wire [14:0] dram2_ras_data = RAS[dram2_ras_adr];
1211
1212assign dram2_adr_cas[34 ] = que_eight_bank_mode2 ?
1213 (((ras_addr_width2 == 14) & rank_and_stack2 & dram2_cs_adr[0]) |
1214 ((ras_addr_width2 == 14) & rank_xor_stack2 & dram2_cs_adr[2]) |
1215 ((ras_addr_width2 == 15) & dram2_ras_data[14])) :
1216 ((ras_addr_width2 == 14) & rank_and_stack2 & dram2_cs_adr[1]);
1217assign dram2_adr_cas[33 ] = que_eight_bank_mode2 ? dram2_ras_data[13] :
1218 (((ras_addr_width2 == 13) & rank_and_stack2 & dram2_cs_adr[1]) |
1219 ((ras_addr_width2 == 14) & rank_and_stack2 & dram2_cs_adr[0]) |
1220 ((ras_addr_width2 == 14) & rank_xor_stack2 & dram2_cs_adr[2]));
1221assign dram2_adr_cas[32 ] = que_eight_bank_mode2 ? dram2_ras_data[12] :
1222 (((ras_addr_width2 == 13) & rank_and_stack2 & dram2_cs_adr[0]) |
1223 ((ras_addr_width2 == 13) & rank_xor_stack2 & dram2_cs_adr[2]) |
1224 ((ras_addr_width2 == 14) & dram2_ras_data[13]));
1225assign dram2_adr_cas[31:20] = que_eight_bank_mode2 ? dram2_ras_data[11:0] : dram2_ras_data[12:1];
1226assign dram2_adr_cas[ 19] = que_eight_bank_mode2 ? dram2_io_addr[11] : dram2_ras_data[0];
1227assign dram2_adr_cas[ 18] = que_eight_bank_mode2 ? dram2_io_addr[ 9] : dram2_io_addr[11];
1228assign dram2_adr_cas[17:11] = que_eight_bank_mode2 ? dram2_io_addr[8:2] : dram2_io_addr[9:3];
1229assign dram2_adr_cas[10 ] = que_eight_bank_mode2 ? (dram2_io_bank[2] ^ dram2_adr_cas[20] ^ dram2_adr_cas[30]) :
1230 dram2_io_addr[2];
1231assign dram2_adr_cas[ 9: 8] = (dram2_io_bank[1:0] ^ dram2_adr_cas[19:18] ^ dram2_adr_cas[29:28]);
1232assign dram2_adr_cas[ 7: 6] = 2'b10;
1233assign dram2_adr_cas[ 5: 4] = dram2_io_addr[1:0];
1234
1235// BANK3
1236wire rank_and_stack3 = stacked_dimm3 & que_rank1_present3;
1237wire rank_xor_stack3 = stacked_dimm3 ^ que_rank1_present3;
1238
1239wire [2:0] dram3_cs_adr = {((dram3_io_cs_l == 4'hb) | (dram3_io_cs_l == 4'hd)),
1240 ((dram3_io_cs_l == 4'h7) | (dram3_io_cs_l == 4'hb)),
1241 ((dram3_io_cs_l == 4'h7) | (dram3_io_cs_l == 4'hd))};
1242
1243assign dram3_adr_cas[36] = que_eight_bank_mode3 &
1244 ((ras_addr_width3 == 15) & rank_and_stack3 & dram3_cs_adr[1]);
1245assign dram3_adr_cas[35] = que_eight_bank_mode3 &
1246 (((ras_addr_width3 == 14) & rank_and_stack3 & dram3_cs_adr[1]) |
1247 ((ras_addr_width3 == 15) & rank_and_stack3 & dram3_cs_adr[0]) |
1248 ((ras_addr_width3 == 15) & rank_xor_stack3 & dram3_cs_adr[2]));
1249
1250wire [ 6:0] dram3_ras_adr = que_eight_bank_mode3 ? {2'b11, dram3_adr_cas[36:35], dram3_io_bank[2:0]} :
1251 {2'b11, 2'b00, 1'b0, dram3_io_bank[1:0]};
1252wire [14:0] dram3_ras_data = RAS[dram3_ras_adr];
1253
1254assign dram3_adr_cas[34 ] = que_eight_bank_mode3 ?
1255 (((ras_addr_width3 == 14) & rank_and_stack3 & dram3_cs_adr[0]) |
1256 ((ras_addr_width3 == 14) & rank_xor_stack3 & dram3_cs_adr[2]) |
1257 ((ras_addr_width3 == 15) & dram3_ras_data[14])) :
1258 ((ras_addr_width3 == 14) & rank_and_stack3 & dram3_cs_adr[1]);
1259assign dram3_adr_cas[33 ] = que_eight_bank_mode3 ? dram3_ras_data[13] :
1260 (((ras_addr_width3 == 13) & rank_and_stack3 & dram3_cs_adr[1]) |
1261 ((ras_addr_width3 == 14) & rank_and_stack3 & dram3_cs_adr[0]) |
1262 ((ras_addr_width3 == 14) & rank_xor_stack3 & dram3_cs_adr[2]));
1263assign dram3_adr_cas[32 ] = que_eight_bank_mode3 ? dram3_ras_data[12] :
1264 (((ras_addr_width3 == 13) & rank_and_stack3 & dram3_cs_adr[0]) |
1265 ((ras_addr_width3 == 13) & rank_xor_stack3 & dram3_cs_adr[2]) |
1266 ((ras_addr_width3 == 14) & dram3_ras_data[13]));
1267assign dram3_adr_cas[31:20] = que_eight_bank_mode3 ? dram3_ras_data[11:0] : dram3_ras_data[12:1];
1268assign dram3_adr_cas[ 19] = que_eight_bank_mode3 ? dram3_io_addr[11] : dram3_ras_data[0];
1269assign dram3_adr_cas[ 18] = que_eight_bank_mode3 ? dram3_io_addr[ 9] : dram3_io_addr[11];
1270assign dram3_adr_cas[17:11] = que_eight_bank_mode3 ? dram3_io_addr[8:2] : dram3_io_addr[9:3];
1271assign dram3_adr_cas[10 ] = que_eight_bank_mode3 ? (dram3_io_bank[2] ^ dram3_adr_cas[20] ^ dram3_adr_cas[30]) :
1272 dram3_io_addr[2];
1273assign dram3_adr_cas[ 9: 8] = (dram3_io_bank[1:0] ^ dram3_adr_cas[19:18] ^ dram3_adr_cas[29:28]);
1274assign dram3_adr_cas[ 7: 6] = 2'b11;
1275assign dram3_adr_cas[ 5: 4] = dram3_io_addr[1:0];
1276//}}}
1277`endif
1278
1279//{{{ addr decode stuff
1280//{{{ bank0 addr
1281wire [36:4] dram0_adr_cas;
1282
1283wire [ 6:0] dram0_ras_adr = que_eight_bank_mode0 ? {2'b00, dram0_adr_cas[36:35], dram0_io_bank[2:0]} :
1284 {2'b00, 2'b00, 1'b0, dram0_io_bank[1:0]};
1285wire [14:0] dram0_ras_data = RAS[dram0_ras_adr];
1286
1287assign dram0_adr_cas[36:34] = 3'b0;
1288assign dram0_adr_cas[33] = dram0_io_addr[12];
1289assign dram0_adr_cas[32:19] = dram0_ras_data[14:0];
1290assign dram0_adr_cas[18:11] = {dram0_io_addr[11],dram0_io_addr[9:3]};
1291assign dram0_adr_cas[10:9] = dram0_io_bank[2:1];
1292assign dram0_adr_cas[8:7] = 2'b00;
1293assign dram0_adr_cas[6] = dram0_io_bank[0];
1294assign dram0_adr_cas[5:4] = dram0_io_addr[1:0];
1295
1296
1297//}}}
1298//{{{ bank1 addr
1299wire [36:4] dram1_adr_cas;
1300
1301wire [ 6:0] dram1_ras_adr = que_eight_bank_mode1 ? {2'b01, dram1_adr_cas[36:35], dram1_io_bank[2:0]} :
1302 {2'b01, 2'b00, 1'b0, dram1_io_bank[1:0]};
1303wire [14:0] dram1_ras_data = RAS[dram1_ras_adr];
1304
1305assign dram1_adr_cas[36:34] = 3'b0;
1306assign dram1_adr_cas[33] = dram1_io_addr[12];
1307assign dram1_adr_cas[32:19] = dram1_ras_data[14:0];
1308assign dram1_adr_cas[18:11] = {dram1_io_addr[11],dram1_io_addr[9:3]};
1309assign dram1_adr_cas[10:9] = dram1_io_bank[2:1];
1310assign dram1_adr_cas[8:7] = 2'b01;
1311assign dram1_adr_cas[6] = dram1_io_bank[0];
1312assign dram1_adr_cas[5:4] = dram1_io_addr[1:0];
1313
1314
1315//}}}
1316//{{{ bank2 addr
1317wire [36:4] dram2_adr_cas;
1318
1319wire [ 6:0] dram2_ras_adr = que_eight_bank_mode2 ? {2'b10, dram2_adr_cas[36:35], dram2_io_bank[2:0]} :
1320 {2'b10, 2'b00, 1'b0, dram2_io_bank[1:0]};
1321wire [14:0] dram2_ras_data = RAS[dram2_ras_adr];
1322
1323assign dram2_adr_cas[36:34] = 3'b0;
1324assign dram2_adr_cas[33] = dram2_io_addr[12];
1325assign dram2_adr_cas[32:19] = dram2_ras_data[14:0];
1326assign dram2_adr_cas[18:11] = {dram2_io_addr[11],dram2_io_addr[9:3]};
1327assign dram2_adr_cas[10:9] = dram2_io_bank[2:1];
1328assign dram2_adr_cas[8:7] = 2'b10;
1329assign dram2_adr_cas[6] = dram2_io_bank[0];
1330assign dram2_adr_cas[5:4] = dram2_io_addr[1:0];
1331
1332
1333//}}}
1334//{{{ bank3 addr
1335wire [36:4] dram3_adr_cas;
1336
1337wire [ 6:0] dram3_ras_adr = que_eight_bank_mode3 ? {2'b11, dram3_adr_cas[36:35], dram3_io_bank[2:0]} :
1338 {2'b11, 2'b00, 1'b0, dram3_io_bank[1:0]};
1339wire [14:0] dram3_ras_data = RAS[dram3_ras_adr];
1340
1341assign dram3_adr_cas[36:34] = 3'b0;
1342assign dram3_adr_cas[33] = dram3_io_addr[12];
1343assign dram3_adr_cas[32:19] = dram3_ras_data[14:0];
1344assign dram3_adr_cas[18:11] = {dram3_io_addr[11],dram3_io_addr[9:3]};
1345assign dram3_adr_cas[10:9] = dram3_io_bank[2:1];
1346assign dram3_adr_cas[8:7] = 2'b11;
1347assign dram3_adr_cas[6] = dram3_io_bank[0];
1348assign dram3_adr_cas[5:4] = dram3_io_addr[1:0];
1349
1350
1351//}}}
1352//}}}
1353
1354//assign dram3_adr_cas[36:35] = {((dram3_io_cs_l == 4'h7) | (dram3_io_cs_l == 4'hb)),
1355// ((dram3_io_cs_l == 4'h7) | (dram3_io_cs_l == 4'hd))};
1356//assign dram3_adr_cas[34:20] = RAS[{2'b11, dram3_adr_cas[36:35], dram3_io_bank[2:0]}];
1357//assign dram3_adr_cas[ 19] = dram3_io_addr[11];
1358//assign dram3_adr_cas[18:11] = dram3_io_addr[9:2];
1359//assign dram3_adr_cas[10: 8] = dram3_io_bank[2:0] ^ dram3_adr_cas[20:18] ^ dram3_adr_cas[30:28];
1360//assign dram3_adr_cas[ 7: 6] = 2'b11;
1361//assign dram3_adr_cas[ 5: 4] = dram3_io_addr[1:0];
1362
1363wire dram0_ras_cy = ~dram0_io_ras_l & dram0_io_cas_l;
1364wire dram0_cas_cy = dram0_io_ras_l & ~dram0_io_cas_l;
1365wire dram0_rd_cas = dram0_io_ras_l & ~dram0_io_cas_l & dram0_io_write_en_l;
1366wire dram0_wr_cas = dram0_io_ras_l & ~dram0_io_cas_l & ~dram0_io_write_en_l;
1367
1368wire dram1_ras_cy = ~dram1_io_ras_l & dram1_io_cas_l;
1369wire dram1_cas_cy = dram1_io_ras_l & ~dram1_io_cas_l;
1370wire dram1_rd_cas = dram1_io_ras_l & ~dram1_io_cas_l & dram1_io_write_en_l;
1371wire dram1_wr_cas = dram1_io_ras_l & ~dram1_io_cas_l & ~dram1_io_write_en_l;
1372
1373wire dram2_ras_cy = ~dram2_io_ras_l & dram2_io_cas_l;
1374wire dram2_cas_cy = dram2_io_ras_l & ~dram2_io_cas_l;
1375wire dram2_rd_cas = dram2_io_ras_l & ~dram2_io_cas_l & dram2_io_write_en_l;
1376wire dram2_wr_cas = dram2_io_ras_l & ~dram2_io_cas_l & ~dram2_io_write_en_l;
1377
1378wire dram3_ras_cy = ~dram3_io_ras_l & dram3_io_cas_l;
1379wire dram3_cas_cy = dram3_io_ras_l & ~dram3_io_cas_l;
1380wire dram3_rd_cas = dram3_io_ras_l & ~dram3_io_cas_l & dram3_io_write_en_l;
1381wire dram3_wr_cas = dram3_io_ras_l & ~dram3_io_cas_l & ~dram3_io_write_en_l;
1382
1383wire [36:4] dram0_adr = dram0_cas_cy ? dram0_adr_cas : DRAM0_ADR_HOLD;
1384wire [36:4] dram1_adr = dram1_cas_cy ? dram1_adr_cas : DRAM1_ADR_HOLD;
1385wire [36:4] dram2_adr = dram2_cas_cy ? dram2_adr_cas : DRAM2_ADR_HOLD;
1386wire [36:4] dram3_adr = dram3_cas_cy ? dram3_adr_cas : DRAM3_ADR_HOLD;
1387
1388wire dram0_adr_parity = ^({dram0_adr[36:9],dram0_adr[6]});
1389wire dram1_adr_parity = ^({dram1_adr[36:9],dram1_adr[6]});
1390wire dram2_adr_parity = ^({dram2_adr[36:9],dram2_adr[6]});
1391wire dram3_adr_parity = ^({dram3_adr[36:9],dram3_adr[6]});
1392
1393/**************************************************************************************************************
1394* The DRAM is modeled as a multi set associative cache. Here the way is calculated. It is assumed
1395* that the mem.image initializes all memory used by the program. Thus no provision need be made here
1396* for cache misses and the resulting problems with X's.
1397**************************************************************************************************************/
1398wire [ 7:4] dram0_line = dram0_adr[7:4];
1399assign dram0_index[26:8] = ({dram0_adr[36:9],dram0_adr[6]}/* + dram0_adr[36:15]*/ ) & 19'h7FFFF;
1400wire [39: 8] dram0_match = {3'b0, dram0_adr[36: 9],dram0_adr[6]};
1401wire [ 7:4] dram1_line = dram1_adr[7:4];
1402assign dram1_index[26:8] = ({dram1_adr[36:9],dram1_adr[6]}/* + dram1_adr[36:15] */) & 19'h7FFFF;
1403wire [39: 8] dram1_match = {3'b0, dram1_adr[36: 9],dram1_adr[6]};
1404wire [ 7:4] dram2_line = dram2_adr[7:4];
1405assign dram2_index[26:8] = ({dram2_adr[36:9],dram2_adr[6]}/* + dram2_adr[36:15] */) & 19'h7FFFF;
1406wire [39: 8] dram2_match = {3'b0, dram2_adr[36: 9],dram2_adr[6]};
1407wire [ 7:4] dram3_line = dram3_adr[7:4];
1408assign dram3_index[26:8] = ({dram3_adr[36:9],dram3_adr[6]}/* + dram3_adr[36:15] */) & 19'h7FFFF;
1409wire [39: 8] dram3_match = {3'b0, dram3_adr[36: 9],dram3_adr[6]};
1410wire [ 5:0] dram0_way = (dram0_dir0_do == dram0_match) ? 6'b000000 :
1411 (dram0_dir1_do == dram0_match) ? 6'b000001 :
1412 (dram0_dir2_do == dram0_match) ? 6'b000010 :
1413 (dram0_dir3_do == dram0_match) ? 6'b000011 :
1414 (dram0_dir4_do == dram0_match) ? 6'b000100 :
1415 (dram0_dir5_do == dram0_match) ? 6'b000101 :
1416 (dram0_dir6_do == dram0_match) ? 6'b000110 :
1417 (dram0_dir7_do == dram0_match) ? 6'b000111 :
1418 (dram0_dir8_do == dram0_match) ? 6'b001000 :
1419 (dram0_dir9_do == dram0_match) ? 6'b001001 :
1420 (dram0_dira_do == dram0_match) ? 6'b001010 :
1421 (dram0_dirb_do == dram0_match) ? 6'b001011 :
1422 (dram0_dirc_do == dram0_match) ? 6'b001100 :
1423 (dram0_dird_do == dram0_match) ? 6'b001101 :
1424 (dram0_dire_do == dram0_match) ? 6'b001110 :
1425 (dram0_dirf_do == dram0_match) ? 6'b001111 :
1426 (dram0_dir10_do == dram0_match) ? 6'b010000 :
1427 (dram0_dir11_do == dram0_match) ? 6'b010001 :
1428 (dram0_dir12_do == dram0_match) ? 6'b010010 :
1429 (dram0_dir13_do == dram0_match) ? 6'b010011 :
1430 (dram0_dir14_do == dram0_match) ? 6'b010100 :
1431 (dram0_dir15_do == dram0_match) ? 6'b010101 :
1432 (dram0_dir16_do == dram0_match) ? 6'b010110 :
1433 (dram0_dir17_do == dram0_match) ? 6'b010111 :
1434 (dram0_dir18_do == dram0_match) ? 6'b011000 :
1435 (dram0_dir19_do == dram0_match) ? 6'b011001 :
1436 (dram0_dir1a_do == dram0_match) ? 6'b011010 :
1437 (dram0_dir1b_do == dram0_match) ? 6'b011011 :
1438 (dram0_dir1c_do == dram0_match) ? 6'b011100 :
1439 (dram0_dir1d_do == dram0_match) ? 6'b011101 :
1440 (dram0_dir1e_do == dram0_match) ? 6'b011110 :
1441 (dram0_dir1f_do == dram0_match) ? 6'b011111 :
1442 (dram0_dir20_do == dram0_match) ? 6'b100000 :
1443 (dram0_dir21_do == dram0_match) ? 6'b100001 :
1444 (dram0_dir22_do == dram0_match) ? 6'b100010 :
1445 (dram0_dir23_do == dram0_match) ? 6'b100011 :
1446 (dram0_dir24_do == dram0_match) ? 6'b100100 :
1447 (dram0_dir25_do == dram0_match) ? 6'b100101 :
1448 (dram0_dir26_do == dram0_match) ? 6'b100110 :
1449 (dram0_dir27_do == dram0_match) ? 6'b100111 :
1450 (dram0_dir28_do == dram0_match) ? 6'b101000 :
1451 (dram0_dir29_do == dram0_match) ? 6'b101001 :
1452 (dram0_dir2a_do == dram0_match) ? 6'b101010 :
1453 (dram0_dir2b_do == dram0_match) ? 6'b101011 :
1454 (dram0_dir2c_do == dram0_match) ? 6'b101100 :
1455 (dram0_dir2d_do == dram0_match) ? 6'b101101 :
1456 (dram0_dir2e_do == dram0_match) ? 6'b101110 :
1457 (dram0_dir2f_do == dram0_match) ? 6'b101111 :
1458 (dram0_dir30_do == dram0_match) ? 6'b110000 :
1459 (dram0_dir31_do == dram0_match) ? 6'b110001 :
1460 (dram0_dir32_do == dram0_match) ? 6'b110010 :
1461 (dram0_dir33_do == dram0_match) ? 6'b110011 :
1462 (dram0_dir34_do == dram0_match) ? 6'b110100 :
1463 (dram0_dir35_do == dram0_match) ? 6'b110101 :
1464 (dram0_dir36_do == dram0_match) ? 6'b110110 :
1465 (dram0_dir37_do == dram0_match) ? 6'b110111 :
1466 (dram0_dir38_do == dram0_match) ? 6'b111000 :
1467 (dram0_dir39_do == dram0_match) ? 6'b111001 :
1468 (dram0_dir3a_do == dram0_match) ? 6'b111010 :
1469 (dram0_dir3b_do == dram0_match) ? 6'b111011 :
1470 (dram0_dir3c_do == dram0_match) ? 6'b111100 :
1471 (dram0_dir3d_do == dram0_match) ? 6'b111101 :
1472 (dram0_dir3e_do == dram0_match) ? 6'b111110 :
1473 (dram0_dir3f_do == dram0_match) ? 6'b111111 :
1474 6'b111111;
1475wire [ 5:0] dram1_way = (dram1_dir0_do == dram1_match) ? 6'b000000 :
1476 (dram1_dir1_do == dram1_match) ? 6'b000001 :
1477 (dram1_dir2_do == dram1_match) ? 6'b000010 :
1478 (dram1_dir3_do == dram1_match) ? 6'b000011 :
1479 (dram1_dir4_do == dram1_match) ? 6'b000100 :
1480 (dram1_dir5_do == dram1_match) ? 6'b000101 :
1481 (dram1_dir6_do == dram1_match) ? 6'b000110 :
1482 (dram1_dir7_do == dram1_match) ? 6'b000111 :
1483 (dram1_dir8_do == dram1_match) ? 6'b001000 :
1484 (dram1_dir9_do == dram1_match) ? 6'b001001 :
1485 (dram1_dira_do == dram1_match) ? 6'b001010 :
1486 (dram1_dirb_do == dram1_match) ? 6'b001011 :
1487 (dram1_dirc_do == dram1_match) ? 6'b001100 :
1488 (dram1_dird_do == dram1_match) ? 6'b001101 :
1489 (dram1_dire_do == dram1_match) ? 6'b001110 :
1490 (dram1_dirf_do == dram1_match) ? 6'b001111 :
1491 (dram1_dir10_do == dram1_match) ? 6'b010000 :
1492 (dram1_dir11_do == dram1_match) ? 6'b010001 :
1493 (dram1_dir12_do == dram1_match) ? 6'b010010 :
1494 (dram1_dir13_do == dram1_match) ? 6'b010011 :
1495 (dram1_dir14_do == dram1_match) ? 6'b010100 :
1496 (dram1_dir15_do == dram1_match) ? 6'b010101 :
1497 (dram1_dir16_do == dram1_match) ? 6'b010110 :
1498 (dram1_dir17_do == dram1_match) ? 6'b010111 :
1499 (dram1_dir18_do == dram1_match) ? 6'b011000 :
1500 (dram1_dir19_do == dram1_match) ? 6'b011001 :
1501 (dram1_dir1a_do == dram1_match) ? 6'b011010 :
1502 (dram1_dir1b_do == dram1_match) ? 6'b011011 :
1503 (dram1_dir1c_do == dram1_match) ? 6'b011100 :
1504 (dram1_dir1d_do == dram1_match) ? 6'b011101 :
1505 (dram1_dir1e_do == dram1_match) ? 6'b011110 :
1506 (dram1_dir1f_do == dram1_match) ? 6'b011111 :
1507 (dram1_dir20_do == dram1_match) ? 6'b100000 :
1508 (dram1_dir21_do == dram1_match) ? 6'b100001 :
1509 (dram1_dir22_do == dram1_match) ? 6'b100010 :
1510 (dram1_dir23_do == dram1_match) ? 6'b100011 :
1511 (dram1_dir24_do == dram1_match) ? 6'b100100 :
1512 (dram1_dir25_do == dram1_match) ? 6'b100101 :
1513 (dram1_dir26_do == dram1_match) ? 6'b100110 :
1514 (dram1_dir27_do == dram1_match) ? 6'b100111 :
1515 (dram1_dir28_do == dram1_match) ? 6'b101000 :
1516 (dram1_dir29_do == dram1_match) ? 6'b101001 :
1517 (dram1_dir2a_do == dram1_match) ? 6'b101010 :
1518 (dram1_dir2b_do == dram1_match) ? 6'b101011 :
1519 (dram1_dir2c_do == dram1_match) ? 6'b101100 :
1520 (dram1_dir2d_do == dram1_match) ? 6'b101101 :
1521 (dram1_dir2e_do == dram1_match) ? 6'b101110 :
1522 (dram1_dir2f_do == dram1_match) ? 6'b101111 :
1523 (dram1_dir30_do == dram1_match) ? 6'b110000 :
1524 (dram1_dir31_do == dram1_match) ? 6'b110001 :
1525 (dram1_dir32_do == dram1_match) ? 6'b110010 :
1526 (dram1_dir33_do == dram1_match) ? 6'b110011 :
1527 (dram1_dir34_do == dram1_match) ? 6'b110100 :
1528 (dram1_dir35_do == dram1_match) ? 6'b110101 :
1529 (dram1_dir36_do == dram1_match) ? 6'b110110 :
1530 (dram1_dir37_do == dram1_match) ? 6'b110111 :
1531 (dram1_dir38_do == dram1_match) ? 6'b111000 :
1532 (dram1_dir39_do == dram1_match) ? 6'b111001 :
1533 (dram1_dir3a_do == dram1_match) ? 6'b111010 :
1534 (dram1_dir3b_do == dram1_match) ? 6'b111011 :
1535 (dram1_dir3c_do == dram1_match) ? 6'b111100 :
1536 (dram1_dir3d_do == dram1_match) ? 6'b111101 :
1537 (dram1_dir3e_do == dram1_match) ? 6'b111110 :
1538 (dram1_dir3f_do == dram1_match) ? 6'b111111 :
1539 6'b111111;
1540
1541wire [ 5:0] dram2_way = (dram2_dir0_do == dram2_match) ? 6'b000000 :
1542 (dram2_dir1_do == dram2_match) ? 6'b000001 :
1543 (dram2_dir2_do == dram2_match) ? 6'b000010 :
1544 (dram2_dir3_do == dram2_match) ? 6'b000011 :
1545 (dram2_dir4_do == dram2_match) ? 6'b000100 :
1546 (dram2_dir5_do == dram2_match) ? 6'b000101 :
1547 (dram2_dir6_do == dram2_match) ? 6'b000110 :
1548 (dram2_dir7_do == dram2_match) ? 6'b000111 :
1549 (dram2_dir8_do == dram2_match) ? 6'b001000 :
1550 (dram2_dir9_do == dram2_match) ? 6'b001001 :
1551 (dram2_dira_do == dram2_match) ? 6'b001010 :
1552 (dram2_dirb_do == dram2_match) ? 6'b001011 :
1553 (dram2_dirc_do == dram2_match) ? 6'b001100 :
1554 (dram2_dird_do == dram2_match) ? 6'b001101 :
1555 (dram2_dire_do == dram2_match) ? 6'b001110 :
1556 (dram2_dirf_do == dram2_match) ? 6'b001111 :
1557 (dram2_dir10_do == dram2_match) ? 6'b010000 :
1558 (dram2_dir11_do == dram2_match) ? 6'b010001 :
1559 (dram2_dir12_do == dram2_match) ? 6'b010010 :
1560 (dram2_dir13_do == dram2_match) ? 6'b010011 :
1561 (dram2_dir14_do == dram2_match) ? 6'b010100 :
1562 (dram2_dir15_do == dram2_match) ? 6'b010101 :
1563 (dram2_dir16_do == dram2_match) ? 6'b010110 :
1564 (dram2_dir17_do == dram2_match) ? 6'b010111 :
1565 (dram2_dir18_do == dram2_match) ? 6'b011000 :
1566 (dram2_dir19_do == dram2_match) ? 6'b011001 :
1567 (dram2_dir1a_do == dram2_match) ? 6'b011010 :
1568 (dram2_dir1b_do == dram2_match) ? 6'b011011 :
1569 (dram2_dir1c_do == dram2_match) ? 6'b011100 :
1570 (dram2_dir1d_do == dram2_match) ? 6'b011101 :
1571 (dram2_dir1e_do == dram2_match) ? 6'b011110 :
1572 (dram2_dir1f_do == dram2_match) ? 6'b011111 :
1573 (dram2_dir20_do == dram2_match) ? 6'b100000 :
1574 (dram2_dir21_do == dram2_match) ? 6'b100001 :
1575 (dram2_dir22_do == dram2_match) ? 6'b100010 :
1576 (dram2_dir23_do == dram2_match) ? 6'b100011 :
1577 (dram2_dir24_do == dram2_match) ? 6'b100100 :
1578 (dram2_dir25_do == dram2_match) ? 6'b100101 :
1579 (dram2_dir26_do == dram2_match) ? 6'b100110 :
1580 (dram2_dir27_do == dram2_match) ? 6'b100111 :
1581 (dram2_dir28_do == dram2_match) ? 6'b101000 :
1582 (dram2_dir29_do == dram2_match) ? 6'b101001 :
1583 (dram2_dir2a_do == dram2_match) ? 6'b101010 :
1584 (dram2_dir2b_do == dram2_match) ? 6'b101011 :
1585 (dram2_dir2c_do == dram2_match) ? 6'b101100 :
1586 (dram2_dir2d_do == dram2_match) ? 6'b101101 :
1587 (dram2_dir2e_do == dram2_match) ? 6'b101110 :
1588 (dram2_dir2f_do == dram2_match) ? 6'b101111 :
1589 (dram2_dir30_do == dram2_match) ? 6'b110000 :
1590 (dram2_dir31_do == dram2_match) ? 6'b110001 :
1591 (dram2_dir32_do == dram2_match) ? 6'b110010 :
1592 (dram2_dir33_do == dram2_match) ? 6'b110011 :
1593 (dram2_dir34_do == dram2_match) ? 6'b110100 :
1594 (dram2_dir35_do == dram2_match) ? 6'b110101 :
1595 (dram2_dir36_do == dram2_match) ? 6'b110110 :
1596 (dram2_dir37_do == dram2_match) ? 6'b110111 :
1597 (dram2_dir38_do == dram2_match) ? 6'b111000 :
1598 (dram2_dir39_do == dram2_match) ? 6'b111001 :
1599 (dram2_dir3a_do == dram2_match) ? 6'b111010 :
1600 (dram2_dir3b_do == dram2_match) ? 6'b111011 :
1601 (dram2_dir3c_do == dram2_match) ? 6'b111100 :
1602 (dram2_dir3d_do == dram2_match) ? 6'b111101 :
1603 (dram2_dir3e_do == dram2_match) ? 6'b111110 :
1604 (dram2_dir3f_do == dram2_match) ? 6'b111111 :
1605 6'b111111;
1606wire [ 5:0] dram3_way = (dram3_dir0_do == dram3_match) ? 6'b000000 :
1607 (dram3_dir1_do == dram3_match) ? 6'b000001 :
1608 (dram3_dir2_do == dram3_match) ? 6'b000010 :
1609 (dram3_dir3_do == dram3_match) ? 6'b000011 :
1610 (dram3_dir4_do == dram3_match) ? 6'b000100 :
1611 (dram3_dir5_do == dram3_match) ? 6'b000101 :
1612 (dram3_dir6_do == dram3_match) ? 6'b000110 :
1613 (dram3_dir7_do == dram3_match) ? 6'b000111 :
1614 (dram3_dir8_do == dram3_match) ? 6'b001000 :
1615 (dram3_dir9_do == dram3_match) ? 6'b001001 :
1616 (dram3_dira_do == dram3_match) ? 6'b001010 :
1617 (dram3_dirb_do == dram3_match) ? 6'b001011 :
1618 (dram3_dirc_do == dram3_match) ? 6'b001100 :
1619 (dram3_dird_do == dram3_match) ? 6'b001101 :
1620 (dram3_dire_do == dram3_match) ? 6'b001110 :
1621 (dram3_dirf_do == dram3_match) ? 6'b001111 :
1622 (dram3_dir10_do == dram3_match) ? 6'b010000 :
1623 (dram3_dir11_do == dram3_match) ? 6'b010001 :
1624 (dram3_dir12_do == dram3_match) ? 6'b010010 :
1625 (dram3_dir13_do == dram3_match) ? 6'b010011 :
1626 (dram3_dir14_do == dram3_match) ? 6'b010100 :
1627 (dram3_dir15_do == dram3_match) ? 6'b010101 :
1628 (dram3_dir16_do == dram3_match) ? 6'b010110 :
1629 (dram3_dir17_do == dram3_match) ? 6'b010111 :
1630 (dram3_dir18_do == dram3_match) ? 6'b011000 :
1631 (dram3_dir19_do == dram3_match) ? 6'b011001 :
1632 (dram3_dir1a_do == dram3_match) ? 6'b011010 :
1633 (dram3_dir1b_do == dram3_match) ? 6'b011011 :
1634 (dram3_dir1c_do == dram3_match) ? 6'b011100 :
1635 (dram3_dir1d_do == dram3_match) ? 6'b011101 :
1636 (dram3_dir1e_do == dram3_match) ? 6'b011110 :
1637 (dram3_dir1f_do == dram3_match) ? 6'b011111 :
1638 (dram3_dir20_do == dram3_match) ? 6'b100000 :
1639 (dram3_dir21_do == dram3_match) ? 6'b100001 :
1640 (dram3_dir22_do == dram3_match) ? 6'b100010 :
1641 (dram3_dir23_do == dram3_match) ? 6'b100011 :
1642 (dram3_dir24_do == dram3_match) ? 6'b100100 :
1643 (dram3_dir25_do == dram3_match) ? 6'b100101 :
1644 (dram3_dir26_do == dram3_match) ? 6'b100110 :
1645 (dram3_dir27_do == dram3_match) ? 6'b100111 :
1646 (dram3_dir28_do == dram3_match) ? 6'b101000 :
1647 (dram3_dir29_do == dram3_match) ? 6'b101001 :
1648 (dram3_dir2a_do == dram3_match) ? 6'b101010 :
1649 (dram3_dir2b_do == dram3_match) ? 6'b101011 :
1650 (dram3_dir2c_do == dram3_match) ? 6'b101100 :
1651 (dram3_dir2d_do == dram3_match) ? 6'b101101 :
1652 (dram3_dir2e_do == dram3_match) ? 6'b101110 :
1653 (dram3_dir2f_do == dram3_match) ? 6'b101111 :
1654 (dram3_dir30_do == dram3_match) ? 6'b110000 :
1655 (dram3_dir31_do == dram3_match) ? 6'b110001 :
1656 (dram3_dir32_do == dram3_match) ? 6'b110010 :
1657 (dram3_dir33_do == dram3_match) ? 6'b110011 :
1658 (dram3_dir34_do == dram3_match) ? 6'b110100 :
1659 (dram3_dir35_do == dram3_match) ? 6'b110101 :
1660 (dram3_dir36_do == dram3_match) ? 6'b110110 :
1661 (dram3_dir37_do == dram3_match) ? 6'b110111 :
1662 (dram3_dir38_do == dram3_match) ? 6'b111000 :
1663 (dram3_dir39_do == dram3_match) ? 6'b111001 :
1664 (dram3_dir3a_do == dram3_match) ? 6'b111010 :
1665 (dram3_dir3b_do == dram3_match) ? 6'b111011 :
1666 (dram3_dir3c_do == dram3_match) ? 6'b111100 :
1667 (dram3_dir3d_do == dram3_match) ? 6'b111101 :
1668 (dram3_dir3e_do == dram3_match) ? 6'b111110 :
1669 (dram3_dir3f_do == dram3_match) ? 6'b111111 :
1670 6'b111111;
1671
1672/**************************************************************************************************************
1673* MEMORY ACCESS NOT DEFINED IN MEM.IMAGE FILE
1674**************************************************************************************************************/
1675reg way_err_enable;
1676reg way_warn_enable;
1677initial begin
1678 if ($value$plusargs("ddr2_way_err_enable=%d", way_err_enable)) begin
1679 end else begin
1680 way_err_enable=1;
1681 end
1682 if ($value$plusargs("ddr2_way_warn_enable=%d", way_warn_enable)) begin
1683 end else begin
1684 way_warn_enable=0;
1685 end
1686end
1687wire iob_way_err = 1'b0; // ~(iob_dir3f_do == iob_match ) & (&iob_way);
1688wire dram0_way_err = ~(dram0_dir3f_do == dram0_match) & (&dram0_way) & dram0_cas_cy & way_err_enable;
1689wire dram1_way_err = ~(dram1_dir3f_do == dram1_match) & (&dram1_way) & dram1_cas_cy & way_err_enable;
1690wire dram2_way_err = ~(dram2_dir3f_do == dram2_match) & (&dram2_way) & dram2_cas_cy & way_err_enable;
1691wire dram3_way_err = ~(dram3_dir3f_do == dram3_match) & (&dram3_way) & dram3_cas_cy & way_err_enable;
1692
1693wire dram0_way_warn = ~(dram0_dir3f_do == dram0_match) & (&dram0_way) & dram0_cas_cy & way_warn_enable;
1694wire dram1_way_warn = ~(dram1_dir3f_do == dram1_match) & (&dram1_way) & dram1_cas_cy & way_warn_enable;
1695wire dram2_way_warn = ~(dram2_dir3f_do == dram2_match) & (&dram2_way) & dram2_cas_cy & way_warn_enable;
1696wire dram3_way_warn = ~(dram3_dir3f_do == dram3_match) & (&dram3_way) & dram3_cas_cy & way_warn_enable;
1697
1698`ifdef EMUL
1699always @(posedge ssiclk) begin
1700 if (iob_way_err)
1701 begin // axis tbcall_region
1702 $display(" ERROR: IOB ADR BOUNDS. CY = %d. ADR= %h",CLK_CNT, jbi_rom_adr);
1703 end
1704end
1705reg [36:4] dram0_adr_r;
1706reg [36:4] dram1_adr_r;
1707reg [36:4] dram2_adr_r;
1708reg [36:4] dram3_adr_r;
1709reg dram_addr_dump;
1710initial dram_addr_dump=1'b1;
1711always @(posedge dramclk) begin
1712 dram0_adr_r <= dram0_adr;
1713 dram1_adr_r <= dram1_adr;
1714 dram2_adr_r <= dram2_adr;
1715 dram3_adr_r <= dram3_adr;
1716
1717 if (dram0_way_err)
1718 begin // axis tbcall_region
1719 $display(" ERROR: DRAM ADR BOUNDS. CY = %d. ADR= %h",CLK_CNT, {DRAM0_ADR_HOLD, 4'h0});
1720 end
1721 if (dram1_way_err)
1722 begin // axis tbcall_region
1723 $display(" ERROR: DRAM1 ADR BOUNDS. CY = %d. ADR= %h",CLK_CNT, {DRAM1_ADR_HOLD, 4'h0});
1724 end
1725 if (dram2_way_err)
1726 begin // axis tbcall_region
1727 $display(" ERROR: DRAM2 ADR BOUNDS. CY = %d. ADR= %h",CLK_CNT, {DRAM2_ADR_HOLD, 4'h0});
1728 end
1729 if (dram3_way_err)
1730 begin // axis tbcall_region
1731 $display(" ERROR: DRAM3 ADR BOUNDS. CY = %d. ADR= %h",CLK_CNT, {DRAM3_ADR_HOLD, 4'h0});
1732 end
1733
1734 if (dram0_way_warn)
1735 begin // axis tbcall_region
1736 $display(" DRAM ADR BOUNDS. CY = %d. ADR= %h",CLK_CNT, {DRAM0_ADR_HOLD, 4'h0});
1737 end
1738 if (dram1_way_warn)
1739 begin // axis tbcall_region
1740 $display(" DRAM1 ADR BOUNDS. CY = %d. ADR= %h",CLK_CNT, {DRAM1_ADR_HOLD, 4'h0});
1741 end
1742 if (dram2_way_warn)
1743 begin // axis tbcall_region
1744 $display(" DRAM2 ADR BOUNDS. CY = %d. ADR= %h",CLK_CNT, {DRAM2_ADR_HOLD, 4'h0});
1745 end
1746 if (dram3_way_warn)
1747 begin // axis tbcall_region
1748 $display(" DRAM3 ADR BOUNDS. CY = %d. ADR= %h",CLK_CNT, {DRAM3_ADR_HOLD, 4'h0});
1749 end
1750 if (dram0_rd_cas & dram_addr_dump)
1751 begin // axis tbcall_region
1752 $display(" DRAM0 %d RD=%h0", CLK_CNT, dram0_adr_r);
1753 end
1754 if (dram1_rd_cas & dram_addr_dump)
1755 begin // axis tbcall_region
1756 $display(" DRAM1 %d RD=%h0", CLK_CNT, dram1_adr_r);
1757 end
1758 if (dram2_rd_cas & dram_addr_dump)
1759 begin // axis tbcall_region
1760 $display(" DRAM2 %d RD=%h0", CLK_CNT, dram2_adr_r);
1761 end
1762 if (dram3_rd_cas& dram_addr_dump)
1763 begin // axis tbcall_region
1764 $display(" DRAM3 %d RD=%h0", CLK_CNT, dram3_adr_r);
1765 end
1766 if (dram0_wr_cas& dram_addr_dump)
1767 begin // axis tbcall_region
1768 $display(" DRAM0 %d WR=%h0", CLK_CNT, dram0_adr_r);
1769 end
1770 if (dram1_wr_cas & dram_addr_dump)
1771 begin // axis tbcall_region
1772 $display(" DRAM1 %d WR=%h0", CLK_CNT, dram1_adr_r);
1773 end
1774 if (dram2_wr_cas & dram_addr_dump)
1775 begin // axis tbcall_region
1776 $display(" DRAM2 %d WR=%h0", CLK_CNT, dram2_adr_r);
1777 end
1778 if (dram3_wr_cas & dram_addr_dump)
1779 begin // axis tbcall_region
1780 $display(" DRAM3 %d WR=%h0", CLK_CNT, dram3_adr_r);
1781 end
1782end
1783`else
1784always @(posedge ssiclk) begin
1785 if (iob_way_err)
1786 $display(" ERROR: IOB ADDRESS OUT OF BOUNDS ON CYCLE = %d. ADR= %h",CLK_CNT, jbi_rom_adr);
1787end
1788always @(posedge dramclk) begin
1789 if (dram0_way_err)
1790 $display(" ERROR: DRAM0 ADDRESS OUT OF BOUNDS ON CYCLE = %d. ADR= %h",CLK_CNT, {dram0_adr, 4'h0});
1791 if (dram1_way_err)
1792 $display(" ERROR: DRAM1 ADDRESS OUT OF BOUNDS ON CYCLE = %d. ADR= %h",CLK_CNT, {dram1_adr, 4'h0});
1793 if (dram2_way_err)
1794 $display(" ERROR: DRAM2 ADDRESS OUT OF BOUNDS ON CYCLE = %d. ADR= %h",CLK_CNT, {dram2_adr, 4'h0});
1795 if (dram3_way_err)
1796 $display(" ERROR: DRAM3 ADDRESS OUT OF BOUNDS ON CYCLE = %d. ADR= %h",CLK_CNT, {dram3_adr, 4'h0});
1797 if (dram0_rd_cas) $display(" DRAM0 %d RD=%h0", CLK_CNT, dram0_adr);
1798 if (dram1_rd_cas) $display(" DRAM1 %d RD=%h0", CLK_CNT, dram1_adr);
1799 if (dram2_rd_cas) $display(" DRAM2 %d RD=%h0", CLK_CNT, dram2_adr);
1800 if (dram3_rd_cas) $display(" DRAM3 %d RD=%h0", CLK_CNT, dram3_adr);
1801 if (dram0_wr_cas) $display(" DRAM0 %d WR=%h0", CLK_CNT, dram0_adr);
1802 if (dram1_wr_cas) $display(" DRAM1 %d WR=%h0", CLK_CNT, dram1_adr);
1803 if (dram2_wr_cas) $display(" DRAM2 %d WR=%h0", CLK_CNT, dram2_adr);
1804 if (dram3_wr_cas) $display(" DRAM3 %d WR=%h0", CLK_CNT, dram3_adr);
1805end
1806`endif
1807
1808/**************************************************************************************************************
1809* If we read the following line out of the mem.image file
1810* it should be placed in the the address order 0, 1, 2, 3 as shown below:
1811*
1812* 8f902001050060d0 8190800083908000 050000058410a200 8590800081f00000
1813* 0 1 2 3
1814*
1815* When the data is returned from the DRAM it is received in the
1816* following order assuming the critical QW is 0. The C's represent the
1817* dram cycle io_dram2_data_valid is asserted (DRAM2_READV[5]). Thus 0 and 2 are written
1818* on the positive edge of the dram clock, and 1 and 3 on the negative.
1819*
1820* 0 0 2 2 io_dram2_data_in[255:128]
1821* 1 1 3 3 io_dram2_data_in[127: 0]
1822* CCCCCCCC io_dram2_data_valid
1823*
1824* The ECC is generated when the data is read from the DRAM. The XOR of the address bits [36:8] is
1825* XORed with the final ECC for address protection.
1826**************************************************************************************************************/
1827wire [127:0] io_dram0_data_02_5 = DRAM0_CQWF_P[5] ? dram0_data_read2[127:0] : dram0_data_read0[127:0]; // Posedge
1828wire [127:0] io_dram0_data_02_6p = DRAM0_CQWF_P[5] ? dram0_data_read0[127:0] : dram0_data_read2[127:0]; // Posedge
1829wire [127:0] io_dram0_data_13_5 = DRAM0_CQWF5_N ? dram0_data_read3[127:0] : dram0_data_read1[127:0]; // Negedge
1830wire [127:0] io_dram0_data_13_6p = DRAM0_CQWF5_N ? dram0_data_read1[127:0] : dram0_data_read3[127:0]; // Negedge
1831wire [ 15:0] io_dram0_ecc_02_5 = DRAM0_CQWF_P[5] ? dram0_ecc_read2[ 15:0] : dram0_ecc_read0[ 15:0]; // Posedge
1832wire [ 15:0] io_dram0_ecc_02_6p = DRAM0_CQWF_P[5] ? dram0_ecc_read0[ 15:0] : dram0_ecc_read2[ 15:0]; // Posedge
1833wire [ 15:0] io_dram0_ecc_13_5 = DRAM0_CQWF5_N ? dram0_ecc_read3[ 15:0] : dram0_ecc_read1[ 15:0]; // Negedge
1834wire [ 15:0] io_dram0_ecc_13_6p = DRAM0_CQWF5_N ? dram0_ecc_read1[ 15:0] : dram0_ecc_read3[ 15:0]; // Negedge
1835
1836wire [127:0] io_dram1_data_02_5 = DRAM1_CQWF_P[5] ? dram1_data_read2[127:0] : dram1_data_read0[127:0]; // Posedge
1837wire [127:0] io_dram1_data_02_6p = DRAM1_CQWF_P[5] ? dram1_data_read0[127:0] : dram1_data_read2[127:0]; // Posedge
1838wire [127:0] io_dram1_data_13_5 = DRAM1_CQWF5_N ? dram1_data_read3[127:0] : dram1_data_read1[127:0]; // Negedge
1839wire [127:0] io_dram1_data_13_6p = DRAM1_CQWF5_N ? dram1_data_read1[127:0] : dram1_data_read3[127:0]; // Negedge
1840wire [ 15:0] io_dram1_ecc_02_5 = DRAM1_CQWF_P[5] ? dram1_ecc_read2[ 15:0] : dram1_ecc_read0[ 15:0]; // Posedge
1841wire [ 15:0] io_dram1_ecc_02_6p = DRAM1_CQWF_P[5] ? dram1_ecc_read0[ 15:0] : dram1_ecc_read2[ 15:0]; // Posedge
1842wire [ 15:0] io_dram1_ecc_13_5 = DRAM1_CQWF5_N ? dram1_ecc_read3[ 15:0] : dram1_ecc_read1[ 15:0]; // Negedge
1843wire [ 15:0] io_dram1_ecc_13_6p = DRAM1_CQWF5_N ? dram1_ecc_read1[ 15:0] : dram1_ecc_read3[ 15:0]; // Negedge
1844
1845wire [127:0] io_dram2_data_02_5 = DRAM2_CQWF_P[5] ? dram2_data_read2[127:0] : dram2_data_read0[127:0]; // Posedge
1846wire [127:0] io_dram2_data_02_6p = DRAM2_CQWF_P[5] ? dram2_data_read0[127:0] : dram2_data_read2[127:0]; // Posedge
1847wire [127:0] io_dram2_data_13_5 = DRAM2_CQWF5_N ? dram2_data_read3[127:0] : dram2_data_read1[127:0]; // Negedge
1848wire [127:0] io_dram2_data_13_6p = DRAM2_CQWF5_N ? dram2_data_read1[127:0] : dram2_data_read3[127:0]; // Negedge
1849wire [ 15:0] io_dram2_ecc_02_5 = DRAM2_CQWF_P[5] ? dram2_ecc_read2[ 15:0] : dram2_ecc_read0[ 15:0]; // Posedge
1850wire [ 15:0] io_dram2_ecc_02_6p = DRAM2_CQWF_P[5] ? dram2_ecc_read0[ 15:0] : dram2_ecc_read2[ 15:0]; // Posedge
1851wire [ 15:0] io_dram2_ecc_13_5 = DRAM2_CQWF5_N ? dram2_ecc_read3[ 15:0] : dram2_ecc_read1[ 15:0]; // Negedge
1852wire [ 15:0] io_dram2_ecc_13_6p = DRAM2_CQWF5_N ? dram2_ecc_read1[ 15:0] : dram2_ecc_read3[ 15:0]; // Negedge
1853
1854wire [127:0] io_dram3_data_02_5 = DRAM3_CQWF_P[5] ? dram3_data_read2[127:0] : dram3_data_read0[127:0]; // Posedge
1855wire [127:0] io_dram3_data_02_6p = DRAM3_CQWF_P[5] ? dram3_data_read0[127:0] : dram3_data_read2[127:0]; // Posedge
1856wire [127:0] io_dram3_data_13_5 = DRAM3_CQWF5_N ? dram3_data_read3[127:0] : dram3_data_read1[127:0]; // Negedge
1857wire [127:0] io_dram3_data_13_6p = DRAM3_CQWF5_N ? dram3_data_read1[127:0] : dram3_data_read3[127:0]; // Negedge
1858wire [ 15:0] io_dram3_ecc_02_5 = DRAM3_CQWF_P[5] ? dram3_ecc_read2[ 15:0] : dram3_ecc_read0[ 15:0]; // Posedge
1859wire [ 15:0] io_dram3_ecc_02_6p = DRAM3_CQWF_P[5] ? dram3_ecc_read0[ 15:0] : dram3_ecc_read2[ 15:0]; // Posedge
1860wire [ 15:0] io_dram3_ecc_13_5 = DRAM3_CQWF5_N ? dram3_ecc_read3[ 15:0] : dram3_ecc_read1[ 15:0]; // Negedge
1861wire [ 15:0] io_dram3_ecc_13_6p = DRAM3_CQWF5_N ? dram3_ecc_read1[ 15:0] : dram3_ecc_read3[ 15:0]; // Negedge
1862
1863/****
1864assign io_dram0_data_in[255:128] = DRAM0_READV_P[5] ? io_dram0_data_02_5 : DRAM0_DATA_02_6;
1865assign io_dram0_data_in[127: 0] = DRAM0_READV5_N ? io_dram0_data_13_5 : DRAM0_DATA_13_6;
1866assign io_dram1_data_in[255:128] = DRAM1_READV_P[5] ? io_dram1_data_02_5 : DRAM1_DATA_02_6;
1867assign io_dram1_data_in[127: 0] = DRAM1_READV5_N ? io_dram1_data_13_5 : DRAM1_DATA_13_6;
1868assign io_dram2_data_in[255:128] = DRAM2_READV_P[5] ? io_dram2_data_02_5 : DRAM2_DATA_02_6;
1869assign io_dram2_data_in[127: 0] = DRAM2_READV5_N ? io_dram2_data_13_5 : DRAM2_DATA_13_6;
1870assign io_dram3_data_in[255:128] = DRAM3_READV_P[5] ? io_dram3_data_02_5 : DRAM3_DATA_02_6;
1871assign io_dram3_data_in[127: 0] = DRAM3_READV5_N ? io_dram3_data_13_5 : DRAM3_DATA_13_6;
1872****/
1873reg [255:128] io_dram0_data_inPR;
1874reg [255:128] io_dram1_data_inPR;
1875reg [255:128] io_dram2_data_inPR;
1876reg [255:128] io_dram3_data_inPR;
1877reg [127: 0] io_dram0_data_inNR;
1878reg [127: 0] io_dram1_data_inNR;
1879reg [127: 0] io_dram2_data_inNR;
1880reg [127: 0] io_dram3_data_inNR;
1881reg [ 31: 16] io_dram0_ecc_inPR;
1882reg [ 31: 16] io_dram1_ecc_inPR;
1883reg [ 31: 16] io_dram2_ecc_inPR;
1884reg [ 31: 16] io_dram3_ecc_inPR;
1885reg [ 15: 0] io_dram0_ecc_inNR;
1886reg [ 15: 0] io_dram1_ecc_inNR;
1887reg [ 15: 0] io_dram2_ecc_inNR;
1888reg [ 15: 0] io_dram3_ecc_inNR;
1889
1890wire [255:128] io_dram0_data_inP = DRAM0_READV_P[5] ? io_dram0_data_02_5 : DRAM0_DATA_02_6;
1891wire [127: 0] io_dram0_data_inN = DRAM0_READV5_N ? io_dram0_data_13_5 : DRAM0_DATA_13_6;
1892wire [255:128] io_dram1_data_inP = DRAM1_READV_P[5] ? io_dram1_data_02_5 : DRAM1_DATA_02_6;
1893wire [127: 0] io_dram1_data_inN = DRAM1_READV5_N ? io_dram1_data_13_5 : DRAM1_DATA_13_6;
1894wire [255:128] io_dram2_data_inP = DRAM2_READV_P[5] ? io_dram2_data_02_5 : DRAM2_DATA_02_6;
1895wire [127: 0] io_dram2_data_inN = DRAM2_READV5_N ? io_dram2_data_13_5 : DRAM2_DATA_13_6;
1896wire [255:128] io_dram3_data_inP = DRAM3_READV_P[5] ? io_dram3_data_02_5 : DRAM3_DATA_02_6;
1897wire [127: 0] io_dram3_data_inN = DRAM3_READV5_N ? io_dram3_data_13_5 : DRAM3_DATA_13_6;
1898wire [ 31: 16] io_dram0_ecc_inP = DRAM0_READV_P[5] ? io_dram0_ecc_02_5 : DRAM0_ECC_02_6;
1899wire [ 15: 0] io_dram0_ecc_inN = DRAM0_READV5_N ? io_dram0_ecc_13_5 : DRAM0_ECC_13_6;
1900wire [ 31: 16] io_dram1_ecc_inP = DRAM1_READV_P[5] ? io_dram1_ecc_02_5 : DRAM1_ECC_02_6;
1901wire [ 15: 0] io_dram1_ecc_inN = DRAM1_READV5_N ? io_dram1_ecc_13_5 : DRAM1_ECC_13_6;
1902wire [ 31: 16] io_dram2_ecc_inP = DRAM2_READV_P[5] ? io_dram2_ecc_02_5 : DRAM2_ECC_02_6;
1903wire [ 15: 0] io_dram2_ecc_inN = DRAM2_READV5_N ? io_dram2_ecc_13_5 : DRAM2_ECC_13_6;
1904wire [ 31: 16] io_dram3_ecc_inP = DRAM3_READV_P[5] ? io_dram3_ecc_02_5 : DRAM3_ECC_02_6;
1905wire [ 15: 0] io_dram3_ecc_inN = DRAM3_READV5_N ? io_dram3_ecc_13_5 : DRAM3_ECC_13_6;
1906
1907assign io_dram0_data_in[255:128] = (que_data_del_cnt0 == 3'b001) ? io_dram0_data_inP : io_dram0_data_inPR;
1908assign io_dram1_data_in[255:128] = (que_data_del_cnt1 == 3'b001) ? io_dram1_data_inP : io_dram1_data_inPR;
1909assign io_dram2_data_in[255:128] = (que_data_del_cnt2 == 3'b001) ? io_dram2_data_inP : io_dram2_data_inPR;
1910assign io_dram3_data_in[255:128] = (que_data_del_cnt3 == 3'b001) ? io_dram3_data_inP : io_dram3_data_inPR;
1911assign io_dram0_data_in[127: 0] = (que_data_del_cnt0 == 3'b001) ? io_dram0_data_inN : io_dram0_data_inNR;
1912assign io_dram1_data_in[127: 0] = (que_data_del_cnt1 == 3'b001) ? io_dram1_data_inN : io_dram1_data_inNR;
1913assign io_dram2_data_in[127: 0] = (que_data_del_cnt2 == 3'b001) ? io_dram2_data_inN : io_dram2_data_inNR;
1914assign io_dram3_data_in[127: 0] = (que_data_del_cnt3 == 3'b001) ? io_dram3_data_inN : io_dram3_data_inNR;
1915assign io_dram0_ecc_in[ 31: 16] = (que_data_del_cnt0 == 3'b001) ? io_dram0_ecc_inP : io_dram0_ecc_inPR;
1916assign io_dram1_ecc_in[ 31: 16] = (que_data_del_cnt1 == 3'b001) ? io_dram1_ecc_inP : io_dram1_ecc_inPR;
1917assign io_dram2_ecc_in[ 31: 16] = (que_data_del_cnt2 == 3'b001) ? io_dram2_ecc_inP : io_dram2_ecc_inPR;
1918assign io_dram3_ecc_in[ 31: 16] = (que_data_del_cnt3 == 3'b001) ? io_dram3_ecc_inP : io_dram3_ecc_inPR;
1919assign io_dram0_ecc_in[ 15: 0] = (que_data_del_cnt0 == 3'b001) ? io_dram0_ecc_inN : io_dram0_ecc_inNR;
1920assign io_dram1_ecc_in[ 15: 0] = (que_data_del_cnt1 == 3'b001) ? io_dram1_ecc_inN : io_dram1_ecc_inNR;
1921assign io_dram2_ecc_in[ 15: 0] = (que_data_del_cnt2 == 3'b001) ? io_dram2_ecc_inN : io_dram2_ecc_inNR;
1922assign io_dram3_ecc_in[ 15: 0] = (que_data_del_cnt3 == 3'b001) ? io_dram3_ecc_inN : io_dram3_ecc_inNR;
1923/****
1924
1925wire [15:0] dram0_ecc_read02, dram0_ecc_read13;
1926wire [15:0] dram1_ecc_read02, dram1_ecc_read13;
1927wire [15:0] dram2_ecc_read02, dram2_ecc_read13;
1928wire [15:0] dram3_ecc_read02, dram3_ecc_read13;
1929
1930dram_ecc_gen ecc0_02 ( .data(io_dram0_data_in[255:128]), .ecc(dram0_ecc_read02[15:0]) );
1931dram_ecc_gen ecc0_13 ( .data(io_dram0_data_in[127: 0]), .ecc(dram0_ecc_read13[15:0]) );
1932dram_ecc_gen ecc1_02 ( .data(io_dram1_data_in[255:128]), .ecc(dram1_ecc_read02[15:0]) );
1933dram_ecc_gen ecc1_13 ( .data(io_dram1_data_in[127: 0]), .ecc(dram1_ecc_read13[15:0]) );
1934dram_ecc_gen ecc2_02 ( .data(io_dram2_data_in[255:128]), .ecc(dram2_ecc_read02[15:0]) );
1935dram_ecc_gen ecc2_13 ( .data(io_dram2_data_in[127: 0]), .ecc(dram2_ecc_read13[15:0]) );
1936dram_ecc_gen ecc3_02 ( .data(io_dram3_data_in[255:128]), .ecc(dram3_ecc_read02[15:0]) );
1937dram_ecc_gen ecc3_13 ( .data(io_dram3_data_in[127: 0]), .ecc(dram3_ecc_read13[15:0]) );
1938
1939assign io_dram0_ecc_in[31:0] = (que_data_del_cnt0 == 3'b001) ?
1940 {(dram0_ecc_read02[15 :0] ^ {16{DRAM0_PARITY_P[5]}}),
1941 (dram0_ecc_read13[15 :0] ^ {16{DRAM0_PARITY5_N }})} :
1942 {(dram0_ecc_read02[15 :0] ^ {16{DRAM0_PARITY_P[6]}}),
1943 (dram0_ecc_read13[15 :0] ^ {16{DRAM0_PARITY6_N }})};
1944assign io_dram1_ecc_in[31:0] = (que_data_del_cnt1 == 3'b001) ?
1945 {(dram1_ecc_read02[15 :0] ^ {16{DRAM1_PARITY_P[5]}}),
1946 (dram1_ecc_read13[15 :0] ^ {16{DRAM1_PARITY5_N }})} :
1947 {(dram1_ecc_read02[15 :0] ^ {16{DRAM1_PARITY_P[6]}}),
1948 (dram1_ecc_read13[15 :0] ^ {16{DRAM1_PARITY6_N }})};
1949assign io_dram2_ecc_in[31:0] = (que_data_del_cnt2 == 3'b001) ?
1950 {(dram2_ecc_read02[15 :0] ^ {16{DRAM2_PARITY_P[5]}}),
1951 (dram2_ecc_read13[15 :0] ^ {16{DRAM2_PARITY5_N }})} :
1952 {(dram2_ecc_read02[15 :0] ^ {16{DRAM2_PARITY_P[6]}}),
1953 (dram2_ecc_read13[15 :0] ^ {16{DRAM2_PARITY6_N }})};
1954assign io_dram3_ecc_in[31:0] = (que_data_del_cnt3 == 3'b001) ?
1955 {(dram3_ecc_read02[15 :0] ^ {16{DRAM3_PARITY_P[5]}}),
1956 (dram3_ecc_read13[15 :0] ^ {16{DRAM3_PARITY5_N }})} :
1957 {(dram3_ecc_read02[15 :0] ^ {16{DRAM3_PARITY_P[6]}}),
1958 (dram3_ecc_read13[15 :0] ^ {16{DRAM3_PARITY6_N }})};
1959***/
1960assign io_dram0_data_valid = (que_data_del_cnt0 == 3'b001) ? DRAM0_READV_P[5] : DRAM0_READV_P[6];
1961assign io_dram1_data_valid = (que_data_del_cnt1 == 3'b001) ? DRAM1_READV_P[5] : DRAM1_READV_P[6];
1962assign io_dram2_data_valid = (que_data_del_cnt2 == 3'b001) ? DRAM2_READV_P[5] : DRAM2_READV_P[6];
1963assign io_dram3_data_valid = (que_data_del_cnt3 == 3'b001) ? DRAM3_READV_P[5] : DRAM3_READV_P[6];
1964
1965/**************************************************************************************************************
1966* DRAM clock domain registers and RAM are clocked and initialized
1967**************************************************************************************************************/
1968`ifdef EMUL
1969reg [255:0] io_dram0_data_in_r, io_dram1_data_in_r, io_dram2_data_in_r, io_dram3_data_in_r;
1970
1971always @(posedge dramclk) begin
1972 io_dram0_data_in_r <= io_dram0_data_in;
1973 io_dram1_data_in_r <= io_dram1_data_in;
1974 io_dram2_data_in_r <= io_dram2_data_in;
1975 io_dram3_data_in_r <= io_dram3_data_in;
1976
1977 if ((io_dram0_data_valid | IO_DRAM0_DATA_VALID_NXT) & dram_dump)
1978 begin // axis tbcall_region
1979 $display ("DRAM0 RD= %h", io_dram0_data_in_r);
1980 end
1981 if ((io_dram1_data_valid | IO_DRAM1_DATA_VALID_NXT) & dram_dump)
1982 begin // axis tbcall_region
1983 $display ("DRAM1 RD= %h", io_dram1_data_in_r);
1984 end
1985 if ((io_dram2_data_valid | IO_DRAM2_DATA_VALID_NXT) & dram_dump)
1986 begin // axis tbcall_region
1987 $display ("DRAM2 RD= %h", io_dram2_data_in_r);
1988 end
1989 if ((io_dram3_data_valid | IO_DRAM3_DATA_VALID_NXT) & dram_dump)
1990 begin // axis tbcall_region
1991 $display ("DRAM3 RD= %h", io_dram3_data_in_r);
1992 end
1993end
1994`else
1995always @(posedge dramclk) begin
1996 if ((io_dram0_data_valid | IO_DRAM0_DATA_VALID_NXT) & dram_dump) $display ("DRAM0 RD= %h", io_dram0_data_in);
1997 if ((io_dram1_data_valid | IO_DRAM1_DATA_VALID_NXT) & dram_dump) $display ("DRAM1 RD= %h", io_dram1_data_in);
1998 if ((io_dram2_data_valid | IO_DRAM2_DATA_VALID_NXT) & dram_dump) $display ("DRAM2 RD= %h", io_dram2_data_in);
1999 if ((io_dram3_data_valid | IO_DRAM3_DATA_VALID_NXT) & dram_dump) $display ("DRAM3 RD= %h", io_dram3_data_in);
2000end
2001`endif
2002
2003initial begin
2004 CLK_CNT <= 40'h0;
2005end
2006always @(posedge dramclk) begin
2007 CLK_CNT <= CLK_CNT + 40'b1;
2008 io_dram0_data_inPR <= io_dram0_data_inP;
2009 io_dram1_data_inPR <= io_dram1_data_inP;
2010 io_dram2_data_inPR <= io_dram2_data_inP;
2011 io_dram3_data_inPR <= io_dram3_data_inP;
2012 io_dram0_ecc_inPR <= io_dram0_ecc_inP;
2013 io_dram1_ecc_inPR <= io_dram1_ecc_inP;
2014 io_dram2_ecc_inPR <= io_dram2_ecc_inP;
2015 io_dram3_ecc_inPR <= io_dram3_ecc_inP;
2016
2017 IO_DRAM0_DATA_VALID_NXT <= io_dram0_data_valid;
2018 IO_DRAM1_DATA_VALID_NXT <= io_dram1_data_valid;
2019 IO_DRAM2_DATA_VALID_NXT <= io_dram2_data_valid;
2020 IO_DRAM3_DATA_VALID_NXT <= io_dram3_data_valid;
2021
2022 if (dram0_ras_cy) RAS[dram0_ras_adr] <= dram0_io_addr[14:0];
2023 if (dram1_ras_cy) RAS[dram1_ras_adr] <= dram1_io_addr[14:0];
2024 if (dram2_ras_cy) RAS[dram2_ras_adr] <= dram2_io_addr[14:0];
2025 if (dram3_ras_cy) RAS[dram3_ras_adr] <= dram3_io_addr[14:0];
2026
2027 DRAM0_WRITV_P <= {DRAM0_WRITV_P[5:0], dram0_wr_cas};
2028 DRAM0_READV_P <= {DRAM0_READV_P[5:0], dram0_rd_cas};
2029 DRAM0_CQWF_P <= {DRAM0_CQWF_P[4:0], dram0_line[5]};
2030 DRAM0_PARITY_P<= {DRAM0_PARITY_P[5:0], dram0_adr_parity};
2031 DRAM0_ADR_HOLD<= dram0_adr;
2032//DRAM0_ADR0_P <= (|dram0_blk_hit[4:3]) ? {dram0_blk_hit[4:0], dram0_adr [29:8]} :
2033// {dram0_blk_hit[4:0], dram0_way[5:0], dram0_index[23:8]};
2034// DRAM0_ADR0_P <= { dram0_way[5:0], dram0_index[26:8]};
2035 DRAM0_ADR0_P <= {(^{dram0_adr[36:9],dram0_adr[6]}), dram0_way[5:0], dram0_index[26:8]};
2036 DRAM0_ADR1_P <= DRAM0_ADR0_P[33:8];
2037 DRAM0_ADR2_P <= DRAM0_ADR1_P[33:8];
2038 DRAM0_ADR3_P <= DRAM0_ADR2_P[33:8];
2039 DRAM0_ADR4_P <= DRAM0_ADR3_P[33:8];
2040 DRAM0_ADR5_P <= DRAM0_ADR4_P[33:8];
2041 DRAM0_DATA_02_6 <= io_dram0_data_02_6p[127:0];
2042 DRAM0_ECC_02_6 <= io_dram0_ecc_02_6p[15:0];
2043 DRAM1_WRITV_P <= {DRAM1_WRITV_P[5:0], dram1_wr_cas};
2044
2045 DRAM1_READV_P <= {DRAM1_READV_P[5:0], dram1_rd_cas};
2046 DRAM1_CQWF_P <= {DRAM1_CQWF_P[4:0], dram1_line[5]};
2047 DRAM1_PARITY_P<= {DRAM1_PARITY_P[5:0], dram1_adr_parity};
2048 DRAM1_ADR_HOLD<= dram1_adr;
2049//DRAM1_ADR0_P <= (|dram1_blk_hit[4:3]) ? {dram1_blk_hit[4:0], dram1_adr [29:8]} :
2050// {dram1_blk_hit[4:0], dram1_way[5:0], dram1_index[23:8]};
2051// DRAM1_ADR0_P <= { dram1_way[5:0], dram1_index[26:8]};
2052 DRAM1_ADR0_P <= {(^{dram1_adr[36:9],dram1_adr[6]}), dram1_way[5:0], dram1_index[26:8]};
2053 DRAM1_ADR1_P <= DRAM1_ADR0_P[33:8];
2054 DRAM1_ADR2_P <= DRAM1_ADR1_P[33:8];
2055 DRAM1_ADR3_P <= DRAM1_ADR2_P[33:8];
2056 DRAM1_ADR4_P <= DRAM1_ADR3_P[33:8];
2057 DRAM1_ADR5_P <= DRAM1_ADR4_P[33:8];
2058 DRAM1_DATA_02_6 <= io_dram1_data_02_6p[127:0];
2059 DRAM1_ECC_02_6 <= io_dram1_ecc_02_6p[15:0];
2060 DRAM2_WRITV_P <= {DRAM2_WRITV_P[5:0], dram2_wr_cas};
2061 DRAM2_READV_P <= {DRAM2_READV_P[5:0], dram2_rd_cas};
2062 DRAM2_CQWF_P <= {DRAM2_CQWF_P[4:0], dram2_line[5]};
2063 DRAM2_PARITY_P<= {DRAM2_PARITY_P[5:0], dram2_adr_parity};
2064 DRAM2_ADR_HOLD<= dram2_adr;
2065//DRAM2_ADR0_P <= (|dram2_blk_hit[4:3]) ? {dram2_blk_hit[4:0], dram2_adr [29:8]} :
2066// {dram2_blk_hit[4:0], dram2_way[5:0], dram2_index[23:8]};
2067// DRAM2_ADR0_P <= { dram2_way[5:0], dram2_index[26:8]};
2068 DRAM2_ADR0_P <= {(^{dram2_adr[36:9],dram2_adr[6]}), dram2_way[5:0], dram2_index[26:8]};
2069 DRAM2_ADR1_P <= DRAM2_ADR0_P[33:8];
2070 DRAM2_ADR2_P <= DRAM2_ADR1_P[33:8];
2071 DRAM2_ADR3_P <= DRAM2_ADR2_P[33:8];
2072 DRAM2_ADR4_P <= DRAM2_ADR3_P[33:8];
2073 DRAM2_ADR5_P <= DRAM2_ADR4_P[33:8];
2074 DRAM2_DATA_02_6 <= io_dram2_data_02_6p[127:0];
2075 DRAM2_ECC_02_6 <= io_dram2_ecc_02_6p[15:0];
2076 DRAM3_WRITV_P <= {DRAM3_WRITV_P[5:0], dram3_wr_cas};
2077 DRAM3_READV_P <= {DRAM3_READV_P[5:0], dram3_rd_cas};
2078 DRAM3_CQWF_P <= {DRAM3_CQWF_P[4:0], dram3_line[5]};
2079 DRAM3_PARITY_P<= {DRAM3_PARITY_P[5:0], dram3_adr_parity};
2080 DRAM3_ADR_HOLD<= dram3_adr;
2081//DRAM3_ADR0_P <= (|dram3_blk_hit[4:3]) ? {dram3_blk_hit[4:0], dram3_adr [29:8]} :
2082// {dram3_blk_hit[4:0], dram3_way[5:0], dram3_index[23:8]};
2083// DRAM3_ADR0_P <= { dram3_way[5:0], dram3_index[26:8]};
2084 DRAM3_ADR0_P <= {(^{dram3_adr[36:9],dram3_adr[6]}), dram3_way[5:0], dram3_index[26:8]};
2085 DRAM3_ADR1_P <= DRAM3_ADR0_P[33:8];
2086 DRAM3_ADR2_P <= DRAM3_ADR1_P[33:8];
2087 DRAM3_ADR3_P <= DRAM3_ADR2_P[33:8];
2088 DRAM3_ADR4_P <= DRAM3_ADR3_P[33:8];
2089 DRAM3_ADR5_P <= DRAM3_ADR4_P[33:8];
2090 DRAM3_DATA_02_6 <= io_dram3_data_02_6p[127:0];
2091 DRAM3_ECC_02_6 <= io_dram3_ecc_02_6p[15:0];
2092end
2093
2094always @(negedge dramclk) begin
2095 io_dram0_data_inNR <= io_dram0_data_inN;
2096 io_dram1_data_inNR <= io_dram1_data_inN;
2097 io_dram2_data_inNR <= io_dram2_data_inN;
2098 io_dram3_data_inNR <= io_dram3_data_inN;
2099 io_dram0_ecc_inNR <= io_dram0_ecc_inN;
2100 io_dram1_ecc_inNR <= io_dram1_ecc_inN;
2101 io_dram2_ecc_inNR <= io_dram2_ecc_inN;
2102 io_dram3_ecc_inNR <= io_dram3_ecc_inN;
2103
2104 DRAM0_READV5_N <= DRAM0_READV_P[5];
2105 DRAM0_CQWF5_N <= DRAM0_CQWF_P[5];
2106 DRAM0_PARITY5_N <= DRAM0_PARITY_P[5];
2107 DRAM0_PARITY6_N <= DRAM0_PARITY_P[6];
2108 DRAM0_ADR5_N <= {(DRAM0_ADR5_P[33]),DRAM0_ADR5_P[32:8]};
2109 DRAM0_DATA_13_6 <= io_dram0_data_13_6p[127:0];
2110 DRAM0_ECC_13_6 <= io_dram0_ecc_13_6p[ 15:0];
2111 DRAM1_READV5_N <= DRAM1_READV_P[5];
2112 DRAM1_CQWF5_N <= DRAM1_CQWF_P[5];
2113 DRAM1_PARITY5_N <= DRAM1_PARITY_P[5];
2114 DRAM1_PARITY6_N <= DRAM1_PARITY_P[6];
2115 DRAM1_ADR5_N <= {(DRAM1_ADR5_P[33]),DRAM1_ADR5_P[32:8]};
2116 DRAM1_DATA_13_6 <= io_dram1_data_13_6p[127:0];
2117 DRAM1_ECC_13_6 <= io_dram1_ecc_13_6p[ 15:0];
2118 DRAM2_READV5_N <= DRAM2_READV_P[5];
2119 DRAM2_CQWF5_N <= DRAM2_CQWF_P[5];
2120 DRAM2_PARITY5_N <= DRAM2_PARITY_P[5];
2121 DRAM2_PARITY6_N <= DRAM2_PARITY_P[6];
2122 DRAM2_ADR5_N <= {(DRAM2_ADR5_P[33]),DRAM2_ADR5_P[32:8]};
2123 DRAM2_DATA_13_6 <= io_dram2_data_13_6p[127:0];
2124 DRAM2_ECC_13_6 <= io_dram2_ecc_13_6p[ 15:0];
2125 DRAM3_READV5_N <= DRAM3_READV_P[5];
2126 DRAM3_CQWF5_N <= DRAM3_CQWF_P[5];
2127 DRAM3_PARITY5_N <= DRAM3_PARITY_P[5];
2128 DRAM3_PARITY6_N <= DRAM3_PARITY_P[6];
2129 DRAM3_ADR5_N <= {(DRAM3_ADR5_P[33]),DRAM3_ADR5_P[32:8]};
2130 DRAM3_DATA_13_6 <= io_dram3_data_13_6p[127:0];
2131 DRAM3_ECC_13_6 <= io_dram3_ecc_13_6p[ 15:0];
2132end
2133
2134initial begin
2135 DRAM0_WRITV_P <= 7'h0;
2136 DRAM0_READV_P <= 6'h0;
2137 DRAM0_CQWF_P <= 6'h0;
2138 DRAM0_PARITY_P<= 6'h0;
2139 DRAM0_PARITY_P<= 7'h0;
2140 DRAM0_ADR_HOLD<= 33'h0;
2141 DRAM0_ADR0_P <= 25'h0;
2142 DRAM0_ADR1_P <= 25'h0;
2143 DRAM0_ADR2_P <= 25'h0;
2144 DRAM0_ADR3_P <= 25'h0;
2145 DRAM0_ADR4_P <= 25'h0;
2146 DRAM0_ADR5_P <= 25'h0;
2147 DRAM0_DATA_02_6 <= 128'h0;
2148 DRAM0_READV5_N <= 1'b0;
2149 DRAM0_CQWF5_N <= 1'b0;
2150 DRAM0_PARITY5_N <= 1'b0;
2151 DRAM0_PARITY6_N <= 1'b0;
2152 DRAM0_ADR5_N <= 26'h0;
2153 DRAM0_DATA_13_6 <= 128'h0;
2154 DRAM0_ECC_13_6 <= 16'h0;
2155 DRAM1_WRITV_P <= 7'h0;
2156 DRAM1_READV_P <= 6'h0;
2157 DRAM1_CQWF_P <= 6'h0;
2158 DRAM1_PARITY_P<= 6'h0;
2159 DRAM1_ADR_HOLD<= 33'h0;
2160 DRAM1_ADR0_P <= 26'h0;
2161 DRAM1_ADR1_P <= 26'h0;
2162 DRAM1_ADR2_P <= 26'h0;
2163 DRAM1_ADR3_P <= 26'h0;
2164 DRAM1_ADR4_P <= 26'h0;
2165 DRAM1_ADR5_P <= 26'h0;
2166 DRAM1_DATA_02_6 <= 128'h0;
2167 DRAM1_READV5_N <= 1'b0;
2168 DRAM1_CQWF5_N <= 1'b0;
2169 DRAM1_PARITY5_N <= 1'b0;
2170 DRAM1_PARITY6_N <= 1'b0;
2171 DRAM1_ADR5_N <= 26'h0;
2172 DRAM1_DATA_13_6 <= 128'h0;
2173 DRAM1_ECC_13_6 <= 16'h0;
2174 DRAM2_WRITV_P <= 7'h0;
2175 DRAM2_READV_P <= 6'h0;
2176 DRAM2_CQWF_P <= 6'h0;
2177 DRAM2_PARITY_P<= 6'h0;
2178 DRAM2_ADR_HOLD<= 33'h0;
2179 DRAM2_ADR0_P <= 26'h0;
2180 DRAM2_ADR1_P <= 26'h0;
2181 DRAM2_ADR2_P <= 26'h0;
2182 DRAM2_ADR3_P <= 26'h0;
2183 DRAM2_ADR4_P <= 26'h0;
2184 DRAM2_ADR5_P <= 26'h0;
2185 DRAM2_DATA_02_6 <= 128'h0;
2186 DRAM2_READV5_N <= 1'b0;
2187 DRAM2_CQWF5_N <= 1'b0;
2188 DRAM2_PARITY5_N <= 1'b0;
2189 DRAM2_PARITY6_N <= 1'b0;
2190 DRAM2_ADR5_N <= 26'h0;
2191 DRAM2_DATA_13_6 <= 128'h0;
2192 DRAM2_ECC_13_6 <= 16'h0;
2193 DRAM3_WRITV_P <= 7'h0;
2194 DRAM3_READV_P <= 6'h0;
2195 DRAM3_CQWF_P <= 6'h0;
2196 DRAM3_PARITY_P<= 6'h0;
2197 DRAM3_ADR_HOLD<= 33'h0;
2198 DRAM3_ADR0_P <= 26'h0;
2199 DRAM3_ADR1_P <= 26'h0;
2200 DRAM3_ADR2_P <= 26'h0;
2201 DRAM3_ADR3_P <= 26'h0;
2202 DRAM3_ADR4_P <= 26'h0;
2203 DRAM3_ADR5_P <= 26'h0;
2204 DRAM3_DATA_02_6 <= 128'h0;
2205 DRAM3_READV5_N <= 1'b0;
2206 DRAM3_CQWF5_N <= 1'b0;
2207 DRAM3_PARITY5_N <= 1'b0;
2208 DRAM3_PARITY6_N <= 1'b0;
2209 DRAM3_ADR5_N <= 26'h0;
2210 DRAM3_DATA_13_6 <= 128'h0;
2211 DRAM3_ECC_13_6 <= 16'h0;
2212 IO_DRAM0_DATA_VALID_NXT <= 1'b0;
2213 IO_DRAM1_DATA_VALID_NXT <= 1'b0;
2214 IO_DRAM2_DATA_VALID_NXT <= 1'b0;
2215 IO_DRAM3_DATA_VALID_NXT <= 1'b0;
2216end
2217//}}}
2218assign ssi_fix_delay[15:0] = (CTL_RAM[13] & 16'hffff); // Data Return delay on SSI bus
2219
2220
2221 endmodule
2222
2223
Full OpenSPARC design & verification tarball including full HDL.