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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: axis_dimm.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module n2_dimm ( | |
36 | CK0, bCK0, bCS0, bRAS0, bCAS0, bWE0, | |
37 | BA0, Addr0, DQ0,DQS0, | |
38 | CK1, bCK1, bCS1, bRAS1, bCAS1, bWE1, | |
39 | BA1, Addr1, DQ1,DQS1, | |
40 | CK2, bCK2, bCS2, bRAS2, bCAS2, bWE2, | |
41 | BA2, Addr2, DQ2,DQS2, | |
42 | CK3, bCK3, bCS3, bRAS3, bCAS3, bWE3, | |
43 | BA3, Addr3, DQ3, DQS3 | |
44 | ||
45 | ); | |
46 | /*{{{ */ | |
47 | `ifdef DRAM_SAT | |
48 | parameter addr_bits=15; | |
49 | `else | |
50 | parameter addr_bits=17; | |
51 | `endif | |
52 | ||
53 | `ifdef DRAM_BANK_BITS2 | |
54 | parameter bank_bits=2; | |
55 | `else | |
56 | parameter bank_bits=3; | |
57 | `endif | |
58 | parameter data_bits=144; | |
59 | /*}}} */ | |
60 | ||
61 | input CK0,bCK0; // Clock Signals | |
62 | input [17:0] bCS0; // Rank/Chip Selects | |
63 | input [17:0] bRAS0, bCAS0, bWE0; // Command Inputs | |
64 | input [(bank_bits-1):0] BA0; // Address Inputs (Bank sel) | |
65 | input [(addr_bits-1):0] Addr0; // Address Inputs | |
66 | inout [(data_bits-1):0] DQ0; // Data Bus | |
67 | output DQS0; // strobe | |
68 | ||
69 | ||
70 | input CK1,bCK1; // Clock Signals | |
71 | input [17:0] bCS1; // Rank/Chip Selects | |
72 | input [17:0] bRAS1, bCAS1, bWE1; // Command Inputs | |
73 | input [(bank_bits-1):0] BA1; // Address Inputs (Bank sel) | |
74 | input [(addr_bits-1):0] Addr1; // Address Inputs | |
75 | inout [(data_bits-1):0] DQ1; // Data Bus | |
76 | output DQS1; // strobe | |
77 | ||
78 | input CK2,bCK2; // Clock Signals | |
79 | input [17:0] bCS2; // Rank/Chip Selects | |
80 | input [17:0] bRAS2, bCAS2, bWE2; // Command Inputs | |
81 | input [(bank_bits-1):0] BA2; // Address Inputs (Bank sel) | |
82 | input [(addr_bits-1):0] Addr2; // Address Inputs | |
83 | inout [(data_bits-1):0] DQ2; // Data Bus | |
84 | output DQS2; // strobe | |
85 | ||
86 | input CK3,bCK3; // Clock Signals | |
87 | input [17:0] bCS3; // Rank/Chip Selects | |
88 | input [17:0] bRAS3, bCAS3, bWE3; // Command Inputs | |
89 | input [(bank_bits-1):0] BA3; // Address Inputs (Bank sel) | |
90 | input [(addr_bits-1):0] Addr3; // Address Inputs | |
91 | inout [(data_bits-1):0] DQ3; // Data Bus | |
92 | output DQS3; // strobe | |
93 | ||
94 | ||
95 | ||
96 | ||
97 | ||
98 | wire [14:0] dram0_io_addr; // From dram02 of dram.v | |
99 | wire [2:0] dram0_io_bank; // From dram02 of dram.v | |
100 | wire dram0_io_cas_l; // From dram02 of dram.v | |
101 | wire [3:0] dram0_io_cs_l; // From dram02 of dram.v | |
102 | wire [287:0] dram0_io_data_out; // From dram02 of dram.v | |
103 | wire dram0_io_ras_l; // From dram02 of dram.v | |
104 | wire dram0_io_write_en_l; // From dram02 of dram.v | |
105 | ||
106 | wire [14:0] dram1_io_addr; // From dram13 of dram.v | |
107 | wire [2:0] dram1_io_bank; // From dram13 of dram.v | |
108 | wire dram1_io_cas_l; // From dram13 of dram.v | |
109 | wire [3:0] dram1_io_cs_l; // From dram13 of dram.v | |
110 | wire [287:0] dram1_io_data_out; // From dram13 of dram.v | |
111 | wire dram1_io_ras_l; // From dram13 of dram.v | |
112 | wire dram1_io_write_en_l; // From dram13 of dram.v | |
113 | ||
114 | wire [14:0] dram2_io_addr; // From dram02 of dram.v | |
115 | wire [2:0] dram2_io_bank; // From dram02 of dram.v | |
116 | wire dram2_io_cas_l; // From dram02 of dram.v | |
117 | wire [3:0] dram2_io_cs_l; // From dram02 of dram.v | |
118 | wire [287:0] dram2_io_data_out; // From dram02 of dram.v | |
119 | wire dram2_io_ras_l; // From dram02 of dram.v | |
120 | wire dram2_io_write_en_l; // From dram02 of dram.v | |
121 | ||
122 | wire [14:0] dram3_io_addr; // From dram13 of dram.v | |
123 | wire [2:0] dram3_io_bank; // From dram13 of dram.v | |
124 | wire dram3_io_cas_l; // From dram13 of dram.v | |
125 | wire [3:0] dram3_io_cs_l; // From dram13 of dram.v | |
126 | wire [287:0] dram3_io_data_out; // From dram13 of dram.v | |
127 | wire dram3_io_ras_l; // From dram13 of dram.v | |
128 | wire dram3_io_write_en_l; // From dram13 of dram.v | |
129 | wire dramclk; | |
130 | ||
131 | wire jbi_io_ssi_mosi; // Master out slave in to pad. | |
132 | wire reset; | |
133 | wire ssiclk; | |
134 | ||
135 | ||
136 | assign dram0_io_addr = Addr0; | |
137 | assign dram1_io_addr = Addr1; | |
138 | assign dram2_io_addr = Addr2; | |
139 | assign dram3_io_addr = Addr3; | |
140 | ||
141 | assign dram0_io_bank = BA0; | |
142 | assign dram1_io_bank = BA1; | |
143 | assign dram2_io_bank = BA2; | |
144 | assign dram3_io_bank = BA3; | |
145 | ||
146 | assign dram0_io_cas_l = bCAS0; | |
147 | assign dram1_io_cas_l = bCAS1; | |
148 | assign dram2_io_cas_l = bCAS2; | |
149 | assign dram3_io_cas_l = bCAS3; | |
150 | ||
151 | assign dram0_io_ras_l = bRAS0; | |
152 | assign dram1_io_ras_l = bRAS1; | |
153 | assign dram2_io_ras_l = bRAS2; | |
154 | assign dram3_io_ras_l = bRAS3; | |
155 | ||
156 | assign dram0_io_cs_l = bCS0; | |
157 | assign dram2_io_cs_l = bCS1; | |
158 | assign dram3_io_cs_l = bCS2; | |
159 | assign dram3_io_cs_l = bCS3; | |
160 | ||
161 | assign dram0_io_write_en_l = bWE0; | |
162 | assign dram1_io_write_en_l = bWE1; | |
163 | assign dram2_io_write_en_l = bWE2; | |
164 | assign dram3_io_write_en_l = bWE3; | |
165 | ||
166 | ||
167 | reg data_delay; | |
168 | wire [255:0] io_dram0_data_in; // To dram02 of dram.v | |
169 | wire io_dram0_data_valid; // To dram02 of dram.v | |
170 | wire [31:0] io_dram0_ecc_in; // To dram02 of dram.v | |
171 | wire [255:0] io_dram1_data_in; // To dram13 of dram.v | |
172 | wire io_dram1_data_valid; // To dram13 of dram.v | |
173 | wire [31:0] io_dram1_ecc_in; // To dram13 of dram.v | |
174 | wire [255:0] io_dram2_data_in; // To dram02 of dram.v | |
175 | wire io_dram2_data_valid; // To dram02 of dram.v | |
176 | wire [31:0] io_dram2_ecc_in; // To dram02 of dram.v | |
177 | wire [255:0] io_dram3_data_in; // To dram13 of dram.v | |
178 | wire io_dram3_data_valid; // To dram13 of dram.v | |
179 | wire [31:0] io_dram3_ecc_in; // To dram13 of dram.v | |
180 | wire io_jbi_ssi_miso; // Master in slave out from pad. | |
181 | ||
182 | reg [(data_bits-1):0] ddr_data0; | |
183 | reg [(data_bits-1):0] ddr_data1; | |
184 | reg [(data_bits-1):0] ddr_data2; | |
185 | reg [(data_bits-1):0] ddr_data3; | |
186 | reg dram0_data_valid_d; | |
187 | reg dram1_data_valid_d; | |
188 | reg dram2_data_valid_d; | |
189 | reg dram3_data_valid_d; | |
190 | wire dram0_data_valid = dram0_data_valid_d | io_dram0_data_valid; | |
191 | wire dram1_data_valid = dram1_data_valid_d | io_dram1_data_valid; | |
192 | wire dram2_data_valid = dram2_data_valid_d | io_dram2_data_valid; | |
193 | wire dram3_data_valid = dram3_data_valid_d | io_dram3_data_valid; | |
194 | ||
195 | reg dram0_data_valid_e; | |
196 | reg dram1_data_valid_e; | |
197 | reg dram2_data_valid_e; | |
198 | reg dram3_data_valid_e; | |
199 | `ifdef AXIS_EMUL_COSIM_old_code | |
200 | /*{{{ works for targetless*/ | |
201 | always @(negedge dramclk) begin | |
202 | dram0_data_valid_e = dimm.DRAM0_READV_P[5] | io_dram0_data_valid; | |
203 | dram1_data_valid_e = dimm.DRAM1_READV_P[5] | io_dram1_data_valid; | |
204 | dram2_data_valid_e = dimm.DRAM2_READV_P[5] | io_dram2_data_valid; | |
205 | dram3_data_valid_e = dimm.DRAM3_READV_P[5] | io_dram3_data_valid; | |
206 | end | |
207 | assign DQS0 = dram0_data_valid_e ? ~dramclk : 1'bz; | |
208 | assign DQS1 = dram1_data_valid_e ? ~dramclk : 1'bz; | |
209 | assign DQS2 = dram2_data_valid_e ? ~dramclk : 1'bz; | |
210 | assign DQS3 = dram3_data_valid_e ? ~dramclk : 1'bz; | |
211 | /*}}} */ | |
212 | `else | |
213 | /*{{{ works for software*/ | |
214 | /* | |
215 | wire DQS0_e = (io_dram0_data_valid | dram0_data_valid_d) ? dramclk : 1'bz; | |
216 | wire DQS1_e = (io_dram1_data_valid | dram1_data_valid_d) ? dramclk : 1'bz; | |
217 | wire DQS2_e = (io_dram2_data_valid | dram2_data_valid_d) ? dramclk : 1'bz; | |
218 | wire DQS3_e = (io_dram3_data_valid | dram3_data_valid_d) ? dramclk : 1'bz; | |
219 | */ | |
220 | reg DQS0_d; | |
221 | reg DQS1_d; | |
222 | reg DQS2_d; | |
223 | reg DQS3_d; | |
224 | reg DQS0_dd; | |
225 | reg DQS1_dd; | |
226 | reg DQS2_dd; | |
227 | reg DQS3_dd; | |
228 | reg dqs0_vl; | |
229 | reg dqs1_vl; | |
230 | reg dqs2_vl; | |
231 | reg dqs3_vl; | |
232 | reg dqs0_vl_d; | |
233 | reg dqs1_vl_d; | |
234 | reg dqs2_vl_d; | |
235 | reg dqs3_vl_d; | |
236 | ||
237 | always @ (posedge tb_top.mcusat_fbdimm.fbdimm_mem0.fbdimm0.dram_2x_clk) begin | |
238 | DQS0_dd <= DQS0_d; | |
239 | DQS1_dd <= DQS1_d; | |
240 | DQS2_dd <= DQS2_d; | |
241 | DQS3_dd <= DQS3_d; | |
242 | dqs0_vl_d = dqs0_vl|io_dram0_data_valid; | |
243 | dqs1_vl_d = dqs1_vl|io_dram1_data_valid; | |
244 | dqs2_vl_d = dqs2_vl|io_dram2_data_valid; | |
245 | dqs3_vl_d = dqs3_vl|io_dram3_data_valid; | |
246 | end | |
247 | always @ (CK0) begin | |
248 | dqs0_vl <= (io_dram0_data_valid | dram0_data_valid_d); | |
249 | dqs1_vl <= (io_dram1_data_valid | dram1_data_valid_d); | |
250 | dqs2_vl <= (io_dram2_data_valid | dram2_data_valid_d); | |
251 | dqs3_vl <= (io_dram3_data_valid | dram3_data_valid_d); | |
252 | DQS0_d <= ~CK0 & (io_dram0_data_valid | dram0_data_valid_d); | |
253 | DQS1_d <= ~CK1 & (io_dram1_data_valid | dram1_data_valid_d); | |
254 | DQS2_d <= ~CK2 & (io_dram2_data_valid | dram2_data_valid_d); | |
255 | DQS3_d <= ~CK3 & (io_dram3_data_valid | dram3_data_valid_d); | |
256 | end | |
257 | assign DQS0=dqs0_vl_d ? DQS0_dd:1'bz; | |
258 | assign DQS1=dqs1_vl_d ? DQS1_dd:1'bz; | |
259 | assign DQS2=dqs2_vl_d ? DQS2_dd:1'bz; | |
260 | assign DQS3=dqs3_vl_d ? DQS3_dd:1'bz; | |
261 | /*}}} */ | |
262 | `endif | |
263 | always @(posedge dramclk) begin | |
264 | dram0_data_valid_d = io_dram0_data_valid; | |
265 | dram1_data_valid_d = io_dram1_data_valid; | |
266 | dram2_data_valid_d = io_dram2_data_valid; | |
267 | dram3_data_valid_d = io_dram3_data_valid; | |
268 | end | |
269 | always @(negedge dramclk) begin | |
270 | ddr_data0=DQ0; | |
271 | ddr_data1=DQ1; | |
272 | ddr_data2=DQ2; | |
273 | ddr_data3=DQ3; | |
274 | end | |
275 | assign dramclk=CK0; | |
276 | ||
277 | /*ecc,ecc,data,data,ecc,ecc,data,data*/ | |
278 | /*{{{ */ | |
279 | assign dram0_io_data_out= { | |
280 | DQ0[71:56], | |
281 | DQ0[55:0], | |
282 | DQ0[143:72], | |
283 | ||
284 | ddr_data0[71:56], | |
285 | ddr_data0[55:0], | |
286 | ddr_data0[143:72] | |
287 | }; | |
288 | /*}}} */ | |
289 | /*{{{ */ | |
290 | assign dram1_io_data_out= { | |
291 | DQ1[71:56], | |
292 | DQ1[55:0], | |
293 | DQ1[143:72], | |
294 | ddr_data1[71:56], | |
295 | ddr_data1[55:0], | |
296 | ddr_data1[143:72] | |
297 | }; | |
298 | /*}}} */ | |
299 | /*{{{ */ | |
300 | assign dram2_io_data_out= { | |
301 | DQ2[71:56], | |
302 | DQ2[55:0], | |
303 | DQ2[143:72], | |
304 | ddr_data2[71:56], | |
305 | ddr_data2[55:0], | |
306 | ddr_data2[143:72] | |
307 | }; | |
308 | /*}}} */ | |
309 | /*{{{ */ | |
310 | assign dram3_io_data_out= { | |
311 | DQ3[71:56], | |
312 | DQ3[55:0], | |
313 | DQ3[143:72], | |
314 | ddr_data3[71:56], | |
315 | ddr_data3[55:0], | |
316 | ddr_data3[143:72] | |
317 | }; | |
318 | /*}}} */ | |
319 | ||
320 | /*{{{ old*/ | |
321 | /* | |
322 | assign DQ0_t = (dram0_data_valid & bCK0) ? {io_dram0_data_in[63+8:0] , io_dram0_ecc_in[15:0 ], io_dram0_data_in[127:64+8] } : 144'hzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz; | |
323 | assign DQ0_t = (dram0_data_valid & CK0) ? {io_dram0_data_in[191+8:128], io_dram0_ecc_in[31:16], io_dram0_data_in[255:192+8]} : 144'hzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz; | |
324 | ||
325 | assign DQ1_t = (dram1_data_valid & bCK1) ? {io_dram1_data_in[63+8:0] , io_dram1_ecc_in[15:0 ], io_dram1_data_in[127:64+8] } : 144'hzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz; | |
326 | assign DQ1_t = (dram1_data_valid & CK1) ? {io_dram1_data_in[191+8:128], io_dram1_ecc_in[31:16], io_dram1_data_in[255:192+8]} : 144'hzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz; | |
327 | ||
328 | assign DQ2_t = (dram2_data_valid & bCK2) ? {io_dram2_data_in[63+8:0] , io_dram2_ecc_in[15:0 ], io_dram2_data_in[127:64+8] } : 144'hzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz; | |
329 | assign DQ2_t = (dram2_data_valid & CK2) ? {io_dram2_data_in[191+8:128], io_dram2_ecc_in[31:16], io_dram2_data_in[255:192+8]} : 144'hzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz; | |
330 | ||
331 | assign DQ3_t = (dram3_data_valid & bCK3) ? {io_dram3_data_in[63+8:0] , io_dram3_ecc_in[15:0 ], io_dram3_data_in[127:64+8] } : 144'hzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz; | |
332 | assign DQ3_t = (dram3_data_valid & CK3) ? { io_dram3_data_in[191+8:128], io_dram3_ecc_in[31:16], io_dram3_data_in[255:192+8] } : 144'hzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz; | |
333 | */ | |
334 | /*}}} */ | |
335 | /*{{{ */ | |
336 | ||
337 | wire [(data_bits-1):0] DQ0_th = {io_dram0_data_in[63+8:0] , io_dram0_ecc_in[15:0 ], io_dram0_data_in[127:64+8] } ; | |
338 | wire [(data_bits-1):0] DQ0_tl = {io_dram0_data_in[191+8:128], io_dram0_ecc_in[31:16], io_dram0_data_in[255:192+8]} ; | |
339 | ||
340 | wire [(data_bits-1):0] DQ1_th = {io_dram1_data_in[63+8:0] , io_dram1_ecc_in[15:0 ], io_dram1_data_in[127:64+8] } ; | |
341 | wire [(data_bits-1):0] DQ1_tl = {io_dram1_data_in[191+8:128], io_dram1_ecc_in[31:16], io_dram1_data_in[255:192+8]} ; | |
342 | ||
343 | wire [(data_bits-1):0] DQ2_th = {io_dram2_data_in[63+8:0] , io_dram2_ecc_in[15:0 ], io_dram2_data_in[127:64+8] } ; | |
344 | wire [(data_bits-1):0] DQ2_tl = {io_dram2_data_in[191+8:128], io_dram2_ecc_in[31:16], io_dram2_data_in[255:192+8]} ; | |
345 | ||
346 | wire [(data_bits-1):0] DQ3_th = {io_dram3_data_in[63+8:0] , io_dram3_ecc_in[15:0 ], io_dram3_data_in[127:64+8] } ; | |
347 | wire [(data_bits-1):0] DQ3_tl = { io_dram3_data_in[191+8:128], io_dram3_ecc_in[31:16], io_dram3_data_in[255:192+8] } ; | |
348 | /*}}} */ | |
349 | /*{{{ */ | |
350 | reg [(data_bits-1):0] DQ0_r; | |
351 | reg dq0_vl; | |
352 | reg dq0_vlr; | |
353 | assign DQ0=dq0_vlr ? DQ0_r : 144'hzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz; | |
354 | reg [(data_bits-1):0] DQ1_r; | |
355 | reg dq1_vl; | |
356 | reg dq1_vlr; | |
357 | assign DQ1=dq1_vlr ? DQ1_r : 144'hzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz; | |
358 | reg [(data_bits-1):0] DQ2_r; | |
359 | reg dq2_vl; | |
360 | reg dq2_vlr; | |
361 | assign DQ2=dq2_vlr ? DQ2_r : 144'hzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz; | |
362 | reg [(data_bits-1):0] DQ3_r; | |
363 | reg dq3_vl; | |
364 | reg dq3_vlr; | |
365 | assign DQ3=dq3_vlr ? DQ3_r : 144'hzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz; | |
366 | always @ (negedge tb_top.mcusat_fbdimm.fbdimm_mem0.fbdimm0.dram_2x_clk) begin | |
367 | dq0_vlr=dq0_vl; | |
368 | dq0_vl=dram0_data_valid; | |
369 | if (CK0) DQ0_r=DQ0_th; else DQ0_r=DQ0_tl; | |
370 | end | |
371 | always @ (negedge tb_top.mcusat_fbdimm.fbdimm_mem2.fbdimm0.dram_2x_clk) begin | |
372 | dq1_vlr=dq1_vl; | |
373 | dq1_vl=dram1_data_valid; | |
374 | if (CK1) DQ1_r=DQ1_th; else DQ1_r=DQ1_tl; | |
375 | end | |
376 | always @ (negedge tb_top.mcusat_fbdimm.fbdimm_mem4.fbdimm0.dram_2x_clk) begin | |
377 | dq2_vlr=dq2_vl; | |
378 | dq2_vl=dram2_data_valid; | |
379 | if (CK2) DQ2_r=DQ2_th; else DQ2_r=DQ2_tl; | |
380 | end | |
381 | always @ (negedge tb_top.mcusat_fbdimm.fbdimm_mem6.fbdimm0.dram_2x_clk) begin | |
382 | dq3_vlr=dq3_vl; | |
383 | dq3_vl=dram3_data_valid; | |
384 | if (CK3) DQ3_r=DQ3_th; else DQ3_r=DQ3_tl; | |
385 | end | |
386 | ||
387 | ||
388 | ||
389 | /*}}} */ | |
390 | ||
391 | cmp_sat dimm ( | |
392 | .dram0_io_addr (dram0_io_addr[14:0]), // wire (dimm) <= () | |
393 | .dram0_io_bank (dram0_io_bank[2:0]), // wire (dimm) <= () | |
394 | .dram0_io_cas_l (dram0_io_cas_l), // wire (dimm) <= () | |
395 | .dram0_io_cs_l (dram0_io_cs_l[3:0]), // wire (dimm) <= () | |
396 | .dram0_io_data_out (dram0_io_data_out[287:0]), // wire (dimm) <= () | |
397 | .dram0_io_ras_l (dram0_io_ras_l), // wire (dimm) <= () | |
398 | .dram0_io_write_en_l (dram0_io_write_en_l), // wire (dimm) <= () | |
399 | .dram1_io_addr (dram1_io_addr[14:0]), // wire (dimm) <= () | |
400 | .dram1_io_bank (dram1_io_bank[2:0]), // wire (dimm) <= () | |
401 | .dram1_io_cas_l (dram1_io_cas_l), // wire (dimm) <= () | |
402 | .dram1_io_cs_l (dram1_io_cs_l[3:0]), // wire (dimm) <= () | |
403 | .dram1_io_data_out (dram1_io_data_out[287:0]), // wire (dimm) <= () | |
404 | .dram1_io_ras_l (dram1_io_ras_l), // wire (dimm) <= () | |
405 | .dram1_io_write_en_l (dram1_io_write_en_l), // wire (dimm) <= () | |
406 | .dram2_io_addr (dram2_io_addr[14:0]), // wire (dimm) <= () | |
407 | .dram2_io_bank (dram2_io_bank[2:0]), // wire (dimm) <= () | |
408 | .dram2_io_cas_l (dram2_io_cas_l), // wire (dimm) <= () | |
409 | .dram2_io_cs_l (dram2_io_cs_l[3:0]), // wire (dimm) <= () | |
410 | .dram2_io_data_out (dram2_io_data_out[287:0]), // wire (dimm) <= () | |
411 | .dram2_io_ras_l (dram2_io_ras_l), // wire (dimm) <= () | |
412 | .dram2_io_write_en_l (dram2_io_write_en_l), // wire (dimm) <= () | |
413 | .dram3_io_addr (dram3_io_addr[14:0]), // wire (dimm) <= () | |
414 | .dram3_io_bank (dram3_io_bank[2:0]), // wire (dimm) <= () | |
415 | .dram3_io_cas_l (dram3_io_cas_l), // wire (dimm) <= () | |
416 | .dram3_io_cs_l (dram3_io_cs_l[3:0]), // wire (dimm) <= () | |
417 | .dram3_io_data_out (dram3_io_data_out[287:0]), // wire (dimm) <= () | |
418 | .dram3_io_ras_l (dram3_io_ras_l), // wire (dimm) <= () | |
419 | .dram3_io_write_en_l (dram3_io_write_en_l), // wire (dimm) <= () | |
420 | .jbi_io_ssi_mosi (jbi_io_ssi_mosi), // wire (dimm) <= () | |
421 | .io_jbi_ssi_miso (io_jbi_ssi_miso), // output (dimm) => () | |
422 | .io_dram0_data_in (io_dram0_data_in[255:0]), // output (dimm) => () | |
423 | .io_dram0_data_valid (io_dram0_data_valid), // output (dimm) => () | |
424 | .io_dram0_ecc_in (io_dram0_ecc_in[31:0]), // output (dimm) => () | |
425 | .io_dram1_data_in (io_dram1_data_in[255:0]), // output (dimm) => () | |
426 | .io_dram1_data_valid (io_dram1_data_valid), // output (dimm) => () | |
427 | .io_dram1_ecc_in (io_dram1_ecc_in[31:0]), // output (dimm) => () | |
428 | .io_dram2_data_in (io_dram2_data_in[255:0]), // output (dimm) => () | |
429 | .io_dram2_data_valid (io_dram2_data_valid), // output (dimm) => () | |
430 | .io_dram2_ecc_in (io_dram2_ecc_in[31:0]), // output (dimm) => () | |
431 | .io_dram3_data_in (io_dram3_data_in[255:0]), // output (dimm) => () | |
432 | .io_dram3_data_valid (io_dram3_data_valid), // output (dimm) => () | |
433 | .io_dram3_ecc_in (io_dram3_ecc_in[31:0]), // output (dimm) => () | |
434 | .dramclk (dramclk), // wire (dimm) <= () | |
435 | .ssiclk (ssiclk), // wire (dimm) <= () | |
436 | .reset (reset) // wire (dimm) <= () | |
437 | ); | |
438 | `ifdef MCUSAT | |
439 | assign jbi_io_ssi_mosi = 1'b0; | |
440 | assign ssiclk = dramclk; | |
441 | `else | |
442 | assign tb_top.cpu.SSI_MISO = io_jbi_ssi_miso; | |
443 | assign jbi_io_ssi_mosi = tb_top.cpu.SSI_MOSI; | |
444 | assign ssiclk = cpu.ncu.ncu_mio_ssi_sck; | |
445 | `endif | |
446 | reg reset_reg; | |
447 | reg reset_reg_d; | |
448 | reg dram_init_done; | |
449 | initial reset_reg=1'b1; | |
450 | initial reset_reg_d=1'b1; | |
451 | initial dram_init_done=1'b0; | |
452 | always @ (posedge dramclk) | |
453 | dram_init_done = 1'b1; | |
454 | ||
455 | `ifdef MCUSAT | |
456 | always @ (posedge cpu.mcu.gclk) begin | |
457 | reset_reg_d <= reset_reg; | |
458 | reset_reg <= cpu.mcu.tcu_aclk; | |
459 | `else | |
460 | always @ (posedge ssiclk) begin | |
461 | reset_reg_d <= reset_reg; | |
462 | reset_reg <= ~ tb_top.flush_reset_complete; | |
463 | `endif | |
464 | end | |
465 | assign reset = reset_reg_d; | |
466 | reg loaded; | |
467 | initial loaded=1'b0; | |
468 | initial begin | |
469 | data_delay=1'b0; | |
470 | `ifdef PALLADIUM | |
471 | `else | |
472 | #3 ; | |
473 | `endif | |
474 | ||
475 | $readmemh("include/cmp_mask", dimm.CTL_RAM); | |
476 | //end | |
477 | //always@ (posedge tb_top.SYSCLK) begin | |
478 | // if (tb_top.PWRON_RST_L == 1'b0) | |
479 | // loaded<=1'b0; | |
480 | // else if (tb_top.PWRON_RST_L == 1'b1 && !loaded) begin | |
481 | // loaded <=1'b1; | |
482 | // begin // axis tbcall_region // | |
483 | /*{{{ load dir*/ | |
484 | $readmemh("dram_init/dir0", dimm.dir0.DRAM_DIR); | |
485 | $readmemh("dram_init/dir1", dimm.dir1.DRAM_DIR); | |
486 | $readmemh("dram_init/dir2", dimm.dir2.DRAM_DIR); | |
487 | $readmemh("dram_init/dir3", dimm.dir3.DRAM_DIR); | |
488 | $readmemh("dram_init/dir4", dimm.dir4.DRAM_DIR); | |
489 | $readmemh("dram_init/dir5", dimm.dir5.DRAM_DIR); | |
490 | $readmemh("dram_init/dir6", dimm.dir6.DRAM_DIR); | |
491 | $readmemh("dram_init/dir7", dimm.dir7.DRAM_DIR); | |
492 | $readmemh("dram_init/dir8", dimm.dir8.DRAM_DIR); | |
493 | $readmemh("dram_init/dir9", dimm.dir9.DRAM_DIR); | |
494 | $readmemh("dram_init/dira", dimm.dira.DRAM_DIR); | |
495 | $readmemh("dram_init/dirb", dimm.dirb.DRAM_DIR); | |
496 | $readmemh("dram_init/dirc", dimm.dirc.DRAM_DIR); | |
497 | $readmemh("dram_init/dird", dimm.dird.DRAM_DIR); | |
498 | $readmemh("dram_init/dire", dimm.dire.DRAM_DIR); | |
499 | $readmemh("dram_init/dirf", dimm.dirf.DRAM_DIR); | |
500 | $readmemh("dram_init/dir10", dimm.dir10.DRAM_DIR); | |
501 | $readmemh("dram_init/dir11", dimm.dir11.DRAM_DIR); | |
502 | $readmemh("dram_init/dir12", dimm.dir12.DRAM_DIR); | |
503 | $readmemh("dram_init/dir13", dimm.dir13.DRAM_DIR); | |
504 | $readmemh("dram_init/dir14", dimm.dir14.DRAM_DIR); | |
505 | $readmemh("dram_init/dir15", dimm.dir15.DRAM_DIR); | |
506 | $readmemh("dram_init/dir16", dimm.dir16.DRAM_DIR); | |
507 | $readmemh("dram_init/dir17", dimm.dir17.DRAM_DIR); | |
508 | $readmemh("dram_init/dir18", dimm.dir18.DRAM_DIR); | |
509 | $readmemh("dram_init/dir19", dimm.dir19.DRAM_DIR); | |
510 | $readmemh("dram_init/dir1a", dimm.dir1a.DRAM_DIR); | |
511 | $readmemh("dram_init/dir1b", dimm.dir1b.DRAM_DIR); | |
512 | $readmemh("dram_init/dir1c", dimm.dir1c.DRAM_DIR); | |
513 | $readmemh("dram_init/dir1d", dimm.dir1d.DRAM_DIR); | |
514 | $readmemh("dram_init/dir1e", dimm.dir1e.DRAM_DIR); | |
515 | $readmemh("dram_init/dir1f", dimm.dir1f.DRAM_DIR); | |
516 | $readmemh("dram_init/dir20", dimm.dir20.DRAM_DIR); | |
517 | $readmemh("dram_init/dir21", dimm.dir21.DRAM_DIR); | |
518 | $readmemh("dram_init/dir22", dimm.dir22.DRAM_DIR); | |
519 | $readmemh("dram_init/dir23", dimm.dir23.DRAM_DIR); | |
520 | $readmemh("dram_init/dir24", dimm.dir24.DRAM_DIR); | |
521 | $readmemh("dram_init/dir25", dimm.dir25.DRAM_DIR); | |
522 | $readmemh("dram_init/dir26", dimm.dir26.DRAM_DIR); | |
523 | $readmemh("dram_init/dir27", dimm.dir27.DRAM_DIR); | |
524 | $readmemh("dram_init/dir28", dimm.dir28.DRAM_DIR); | |
525 | $readmemh("dram_init/dir29", dimm.dir29.DRAM_DIR); | |
526 | $readmemh("dram_init/dir2a", dimm.dir2a.DRAM_DIR); | |
527 | $readmemh("dram_init/dir2b", dimm.dir2b.DRAM_DIR); | |
528 | $readmemh("dram_init/dir2c", dimm.dir2c.DRAM_DIR); | |
529 | $readmemh("dram_init/dir2d", dimm.dir2d.DRAM_DIR); | |
530 | $readmemh("dram_init/dir2e", dimm.dir2e.DRAM_DIR); | |
531 | $readmemh("dram_init/dir2f", dimm.dir2f.DRAM_DIR); | |
532 | $readmemh("dram_init/dir30", dimm.dir30.DRAM_DIR); | |
533 | $readmemh("dram_init/dir31", dimm.dir31.DRAM_DIR); | |
534 | $readmemh("dram_init/dir32", dimm.dir32.DRAM_DIR); | |
535 | $readmemh("dram_init/dir33", dimm.dir33.DRAM_DIR); | |
536 | $readmemh("dram_init/dir34", dimm.dir34.DRAM_DIR); | |
537 | $readmemh("dram_init/dir35", dimm.dir35.DRAM_DIR); | |
538 | $readmemh("dram_init/dir36", dimm.dir36.DRAM_DIR); | |
539 | $readmemh("dram_init/dir37", dimm.dir37.DRAM_DIR); | |
540 | $readmemh("dram_init/dir38", dimm.dir38.DRAM_DIR); | |
541 | $readmemh("dram_init/dir39", dimm.dir39.DRAM_DIR); | |
542 | $readmemh("dram_init/dir3a", dimm.dir3a.DRAM_DIR); | |
543 | $readmemh("dram_init/dir3b", dimm.dir3b.DRAM_DIR); | |
544 | $readmemh("dram_init/dir3c", dimm.dir3c.DRAM_DIR); | |
545 | $readmemh("dram_init/dir3d", dimm.dir3d.DRAM_DIR); | |
546 | $readmemh("dram_init/dir3e", dimm.dir3e.DRAM_DIR); | |
547 | $readmemh("dram_init/dir3f", dimm.dir3f.DRAM_DIR); | |
548 | /*}}} */ | |
549 | /*{{{ load data*/ | |
550 | // $readmemh("include/CONSOLE_RAM", dimm.rf2x32.REGF2X32); | |
551 | $display("loading axis memories now"); $fflush(1); | |
552 | `ifdef BLK_4GIG | |
553 | /*{{{ load drams*/ | |
554 | $readmemh("dram_init/dram0_1",dimm.dram0.DRAM); | |
555 | $readmemh("dram_init/dram1_1",dimm.dram1.DRAM); | |
556 | $readmemh("dram_init/dram2_1",dimm.dram2.DRAM); | |
557 | $readmemh("dram_init/dram3_1",dimm.dram3.DRAM); | |
558 | $readmemh("dram_init/dram4_1",dimm.dram4.DRAM); | |
559 | $readmemh("dram_init/dram5_1",dimm.dram5.DRAM); | |
560 | $readmemh("dram_init/dram6_1",dimm.dram6.DRAM); | |
561 | $readmemh("dram_init/dram7_1",dimm.dram7.DRAM); | |
562 | $readmemh("dram_init/dram8_1",dimm.dram8.DRAM); | |
563 | $readmemh("dram_init/dram9_1",dimm.dram9.DRAM); | |
564 | $readmemh("dram_init/drama_1",dimm.drama.DRAM); | |
565 | $readmemh("dram_init/dramb_1",dimm.dramb.DRAM); | |
566 | $readmemh("dram_init/dramc_1",dimm.dramc.DRAM); | |
567 | $readmemh("dram_init/dramd_1",dimm.dramd.DRAM); | |
568 | $readmemh("dram_init/drame_1",dimm.drame.DRAM); | |
569 | $readmemh("dram_init/dramf_1",dimm.dramf.DRAM); | |
570 | /*}}} */ | |
571 | /*{{{ load drams*/ | |
572 | $readmemh("dram_init/dram0",dimm.dram0.DRAM1); | |
573 | $readmemh("dram_init/dram1",dimm.dram1.DRAM1); | |
574 | $readmemh("dram_init/dram2",dimm.dram2.DRAM1); | |
575 | $readmemh("dram_init/dram3",dimm.dram3.DRAM1); | |
576 | $readmemh("dram_init/dram4",dimm.dram4.DRAM1); | |
577 | $readmemh("dram_init/dram5",dimm.dram5.DRAM1); | |
578 | $readmemh("dram_init/dram6",dimm.dram6.DRAM1); | |
579 | $readmemh("dram_init/dram7",dimm.dram7.DRAM1); | |
580 | $readmemh("dram_init/dram8",dimm.dram8.DRAM1); | |
581 | $readmemh("dram_init/dram9",dimm.dram9.DRAM1); | |
582 | $readmemh("dram_init/drama",dimm.drama.DRAM1); | |
583 | $readmemh("dram_init/dramb",dimm.dramb.DRAM1); | |
584 | $readmemh("dram_init/dramc",dimm.dramc.DRAM1); | |
585 | $readmemh("dram_init/dramd",dimm.dramd.DRAM1); | |
586 | $readmemh("dram_init/drame",dimm.drame.DRAM1); | |
587 | $readmemh("dram_init/dramf",dimm.dramf.DRAM1); | |
588 | /*}}} */ | |
589 | `else | |
590 | $readmemh("dram_init/dram0", dimm.dram0.DRAM); | |
591 | $readmemh("dram_init/dram1", dimm.dram1.DRAM); | |
592 | $readmemh("dram_init/dram2", dimm.dram2.DRAM); | |
593 | $readmemh("dram_init/dram3", dimm.dram3.DRAM); | |
594 | $readmemh("dram_init/dram4", dimm.dram4.DRAM); | |
595 | $readmemh("dram_init/dram5", dimm.dram5.DRAM); | |
596 | $readmemh("dram_init/dram6", dimm.dram6.DRAM); | |
597 | $readmemh("dram_init/dram7", dimm.dram7.DRAM); | |
598 | $readmemh("dram_init/dram8", dimm.dram8.DRAM); | |
599 | $readmemh("dram_init/dram9", dimm.dram9.DRAM); | |
600 | $readmemh("dram_init/drama", dimm.drama.DRAM); | |
601 | $readmemh("dram_init/dramb", dimm.dramb.DRAM); | |
602 | $readmemh("dram_init/dramc", dimm.dramc.DRAM); | |
603 | $readmemh("dram_init/dramd", dimm.dramd.DRAM); | |
604 | $readmemh("dram_init/drame", dimm.drame.DRAM); | |
605 | $readmemh("dram_init/dramf", dimm.dramf.DRAM); | |
606 | `endif | |
607 | $display("done loading axis memories"); $fflush(1); | |
608 | /*}}} */ | |
609 | // end | |
610 | // end | |
611 | end | |
612 | endmodule | |
613 | // VPERL: GENERATED_END |