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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: alert_lfsr.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module alert_lfsr(enable,reset,lfsr_output,clk); | |
36 | // interface signals | |
37 | input enable; | |
38 | input reset; | |
39 | input clk; | |
40 | output [13:0] lfsr_output; | |
41 | // internal registers/wires | |
42 | reg [13:0] lfsr_reg; | |
43 | reg [11:0] Xo; | |
44 | reg [4:0] transfer_count; | |
45 | reg [13:0] Xo_tmp; | |
46 | reg [3:0] curr_state; | |
47 | reg X12,X13; | |
48 | reg next_idle_state; | |
49 | reg start_lfsr; | |
50 | reg [3:0] reset_cnt; | |
51 | wire reset_ff=(reset_cnt == 4'hf); | |
52 | wire Xo_tmp12; | |
53 | ||
54 | initial start_lfsr=0; | |
55 | ||
56 | always@(posedge clk) | |
57 | if ( reset ) | |
58 | start_lfsr=1; | |
59 | ||
60 | wire [13:0] lfsr_output_tmp; | |
61 | assign Xo_tmp12 = next_idle_state ? Xo_tmp[0] : ~Xo_tmp[0]; | |
62 | assign lfsr_output_tmp= (start_lfsr & ~reset_ff) ? {Xo_tmp[0],Xo_tmp12,Xo_tmp[11:0]} : 1'b0 ; | |
63 | ||
64 | assign lfsr_output = ~ lfsr_output_tmp; | |
65 | ||
66 | wire lfsr_clk = next_idle_state; | |
67 | always@(posedge lfsr_clk) if ( enable) | |
68 | begin | |
69 | if (reset_cnt) | |
70 | reset_cnt=reset_cnt-1; | |
71 | end | |
72 | ||
73 | always @(posedge lfsr_clk) begin if ( enable ) | |
74 | Xo_tmp[11:0] <= Xo[11:0]; | |
75 | end | |
76 | ||
77 | ||
78 | ||
79 | ||
80 | always@(posedge clk) if ( start_lfsr & enable ) | |
81 | begin | |
82 | case(curr_state) | |
83 | 4'h0: begin curr_state <= 1; end | |
84 | 4'h1: begin curr_state <= 2; end | |
85 | 4'h2: begin curr_state <= 3; end | |
86 | 4'h3: begin curr_state <= 4; end | |
87 | 4'h4: begin curr_state <= 5; end | |
88 | 4'h5: begin curr_state <= 6; next_idle_state <= ~next_idle_state; end | |
89 | 4'h6: begin curr_state <= 7; end | |
90 | 4'h7: begin curr_state <= 8; end | |
91 | 4'h8: begin curr_state <= 9; end | |
92 | 4'h9: begin curr_state <= 4'ha; end | |
93 | 4'ha: begin curr_state <= 4'hb; end | |
94 | 4'hb: begin curr_state <= 0; next_idle_state <= ~next_idle_state; end | |
95 | endcase | |
96 | end | |
97 | ||
98 | ||
99 | always @(posedge lfsr_clk) begin | |
100 | if (reset_ff) | |
101 | Xo <= 12'b1; | |
102 | else begin | |
103 | Xo[11] <= Xo[0] ^ Xo[3] ^ Xo[4] ^ Xo[7]; | |
104 | Xo[10] <= Xo[11]; | |
105 | Xo[9] <= Xo[10]; | |
106 | Xo[8] <= Xo[9]; | |
107 | Xo[7] <= Xo[8]; | |
108 | Xo[6] <= Xo[7]; | |
109 | Xo[5] <= Xo[6]; | |
110 | Xo[4] <= Xo[5]; | |
111 | Xo[3] <= Xo[4]; | |
112 | Xo[2] <= Xo[3]; | |
113 | Xo[1] <= Xo[2]; | |
114 | Xo[0] <= Xo[1]; | |
115 | end | |
116 | end | |
117 | ||
118 | ||
119 | ||
120 | ||
121 | // Initialization | |
122 | initial begin | |
123 | curr_state=0; | |
124 | Xo_tmp=12'b000000000001; | |
125 | next_idle_state=1; | |
126 | reset_cnt=4'hf; | |
127 | end | |
128 | ||
129 | endmodule |