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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / model / verilog / mem / fbdimm / design / amb_init.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: amb_init.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module amb_init(init, // init singal going to other modules
36 drc, // drc register value
37 rst, // reset
38 pn, // primary northbound
39 ps, // primary soutbound
40 ps_bar, // primary soutbound complement
41 ps_fsr,
42 pn_bar,
43 ps0_in, // primary southbound link0
44 ps0_in_bar, // primary southbound link0 complement
45 ps1_in, // primary southbound link1
46 ps1_in_bar, // primary southbound link1
47 ps2_in, // primary southbound link2
48 ps2_in_bar, // primary southbound link2
49 ps3_in, // primary southbound link3
50 ps4_in, // primary southbound link4
51 ps5_in, // primary southbound link5
52 ps6_in, // primary southbound link6
53 ps7_in, // primary southbound link7
54 ps8_in, // primary southbound link8
55 ps9_in, // primary southbound link9
56 ps10_in, // primary southbound link10
57 ps11_in, // primary southbound link11
58 pn0_out, // primary northbound link0
59 pn1_out, // primary northbound link1
60 pn2_out, // primary northbound link2
61 pn3_out, // primary northbound link3
62 pn4_out, // primary northbound link4
63 pn5_out, // primary northbound link5
64 pn6_out, // primary northbound link6
65 pn7_out, // primary northbound link7
66 pn8_out, // primary northbound link8
67 pn9_out, // primary northbound link9
68 pn10_out, // primary northbound link10
69 pn11_out, // primary northbound link11
70 pn12_out, // primary northbound link11
71 pn13_out, // primary northbound link11
72 enter_recalibrate,// enter recalibrate state signal
73 enter_los, // enter L0S state signal
74 l0sdur_reg,
75 recalibdur_reg,
76 clk_int, // internal clock
77 frm_begin, // signal that is asserted twice in a frame
78 frm_begin_dtm, // signal that is asserted twice in a frame
79 frm_boundary, // marking of frame boundaries
80 frm_boundary_fast, // marking of frame boundaries
81 frm_boundary_dtm, // marking of frame boundaries
82 sb_config, // soutbound configuration
83 nb_config, // northbound configuration
84 init_seq_started,
85 disable_state,
86 frm_start,
87 link_clk, // link clock
88 dram_clk, // dram clock
89 dtm_tr_complete,
90 ch_state,
91 sclk);
92
93parameter NB_LINK=14;
94parameter SB_LINK=10;
95parameter DS=0;
96
97// Inputs / Outputs
98
99input [SB_LINK-1:0] ps,ps_bar;
100output [NB_LINK-1:0] pn,pn_bar;
101input [SB_LINK-1:0] ps0_in,ps1_in,ps2_in,ps3_in,ps4_in,ps5_in;
102input [SB_LINK-1:0] ps6_in,ps7_in,ps8_in,ps9_in,ps10_in,ps11_in;
103output [NB_LINK-1:0] pn0_out,pn1_out,pn2_out,pn3_out,pn4_out,pn5_out;
104output [NB_LINK-1:0] pn6_out,pn7_out,pn8_out,pn9_out,pn10_out,pn11_out,pn12_out,pn13_out;
105input [SB_LINK-1:0] ps0_in_bar,ps1_in_bar,ps2_in_bar;
106input [31:0] drc,l0sdur_reg,recalibdur_reg;
107input [11:0] ps_fsr;
108output [3:0] sb_config,nb_config;
109input link_clk,sclk,clk_int,dram_clk;
110input rst;
111input init_seq_started;
112output init;
113output frm_begin,frm_begin_dtm;
114output frm_boundary,frm_boundary_dtm;
115output disable_state;
116input frm_boundary_fast;
117output frm_start;
118output [3:0] ch_state;
119input enter_recalibrate, enter_los;
120input dtm_tr_complete;
121
122// Internal registers
123reg [143:0] ts0_reg0,ts0_reg1,ts0_reg2,ts0_reg3,ts0_reg4,ts0_reg5,ts0_reg6;
124reg [143:0] ts0_reg7,ts0_reg8,ts0_reg9;
125reg [47:0] ireg_l0;
126reg [47:0] ireg_l1;
127reg [47:0] ireg_l2;
128reg [47:0] ireg_l3;
129reg [47:0] ireg_l4;
130reg [47:0] ireg_l5;
131reg [47:0] ireg_l6;
132reg [47:0] ireg_l7;
133reg [47:0] ireg_l8;
134reg [47:0] ireg_l9;
135reg [11:0] ts0_clk_training;
136reg [11:0] ts0_grp1;
137reg [11:0] ts0_grp2;
138reg [11:0] ts0_grp3;
139reg [10:0] test_header_reg;
140reg [13:0] ts2_start_reg,ts2_end_reg;
141reg [13:0] ts3_start_reg,ts3_end_reg;
142reg [10:0] calibrate_state_counter;
143reg [13:0] ts1_start_reg,ts1_end_reg;
144reg [6:0] nop_cnt;
145reg [3:0] curr_state;
146
147reg [3:0] next_state;
148reg [3:0] sb_config_reg;
149reg [3:0] nb_config_reg;
150reg [7:0] fsm_added_delay_reg;
151reg [8:0] LOs_Timer,Recalibrate_Timer;
152reg [3:0] fsr_counter,lock_counter,prev_counter;
153reg [3:0] fsr_counter2,lock_counter2,prev_counter2;
154reg [3:0] fsr_counter_dtm,lock_counter_dtm,prev_counter_dtm;
155reg [3:0] fsr_counter2_dtm,lock_counter2_dtm,prev_counter2_dtm;
156reg [4:0] training_counter;
157reg [3:0] LastAMB_ID;
158reg [4:0] nb_width_capability;
159reg [3:0] tsid;
160reg header_detected,enable_fsm,header_detected_dtm;
161reg dtm_enabled;
162reg fsm_reenable;
163reg init_reg;
164reg nb_tr_reg;
165reg training_sequence_start_reg;
166reg bypass_init;
167reg enter_calibrate_state;
168reg entered_LO;
169reg dummy;
170reg [3:0] sb2nbmap_reg;
171reg testing_delimeter_end_detected;
172
173wire [NB_LINK-1:0] pn0_out_tmp,pn1_out_tmp,pn2_out_tmp,pn3_out_tmp,pn4_out_tmp,pn5_out_tmp;
174wire [NB_LINK-1:0] pn6_out_tmp,pn7_out_tmp,pn8_out_tmp,pn9_out_tmp,pn10_out_tmp,pn11_out_tmp,pn12_out_tmp,pn13_out_tmp;
175wire [9:0] delay_reg;
176wire [SB_LINK-1:0] ps_in;
177wire [SB_LINK-1:0] ps_in_bar;
178wire [NB_LINK-1:0] pn_reg;
179wire [NB_LINK-1:0] pn_sb2nbmap;
180wire [NB_LINK-1:0] pn_init;
181wire [13:0] ts0_ready;
182wire [13:0] tr_amb_id_ok,ts_amb_id_ok,cf_amb_id_ok,po_amb_id_ok;
183wire [13:0] frm_align,ts1_start,ts1_end,ts2_start,ts2_end,ts3_start,ts3_end;
184wire [3:0] amb_id0,amb_id1,amb_id2,amb_id3;
185wire [3:0] amb_id4,amb_id5,amb_id6,amb_id7;
186wire [3:0] amb_id8,amb_id9,amb_id10,amb_id11;
187wire [3:0] amb_id12,amb_id13;
188wire [9:0] mcu_sb_dummy;
189wire [2:0] dummy_sb2nbmap;
190wire training_sequence_start;
191wire nb_tr_en;
192wire link_clk_en;
193wire link_clk_int,dtm_link_clk_int;
194wire ts1_complete,ts2_complete,ts3_complete;
195wire tr_complete;
196wire dtm_rst;
197wire put_ts0_data;
198wire detect_test_hdr_2of3;
199wire detect_cfg_hdr_2of3;
200wire detect_poll_hdr_2of3;
201
202// assignments
203
204 assign delay_reg =(drc[7:4]+drc[3:0])+fsm_added_delay_reg[7:0];
205
206
207`ifdef AXIS_FBDIMM_NO_FSR
208`else
209assign link_clk_int = link_clk & link_clk_en;
210assign dtm_link_clk_int = link_clk & nb_tr_en;
211assign link_clk_en = (ps_in === ps_in_bar ) | ( fsm_reenable ) ? 1'b1 : ( ~init_reg ) ? 1'b0 : 1'b1;
212`endif
213
214assign nb_tr_en = (ps_in === ps_in_bar ) | ( fsm_reenable ) ? 1'b1 : ( ~nb_tr_reg ) ? 1'b0: 1'b1;
215assign put_ts0_data = init_reg & ( ( tr_amb_id_ok == 14'h3fff ) | ( ts_amb_id_ok == 14'h3fff ) | ( cf_amb_id_ok == 14'h3fff ) | ( po_amb_id_ok == 14'h3fff ));
216assign mcu_sb_dummy = ps;
217assign training_sequence_start = training_sequence_start_reg;
218assign ts2_start = ts2_start_reg;
219assign ts3_start = ts3_start_reg;
220assign ts1_start = ts1_start_reg[11:0];
221assign init = bypass_init ? rst : init_reg;
222assign sb_config = sb_config_reg;
223assign nb_config = nb_config_reg;
224assign disable_state = ( curr_state == `AMB_INIT_DISABLE );
225assign ch_state = curr_state;
226
227reg [7:0] fbd_poll_add_latency;
228
229// Initialization
230
231initial begin
232 sb2nbmap_reg=0;
233 tsid = 4'h0;
234 nop_cnt = 0;
235 curr_state = `AMB_INIT_DISABLE;
236 fsr_counter = 4'h7;
237 fsr_counter2 = 4'hd;
238 sb_config_reg = 4'hf;
239 nb_config_reg = 4'hf;
240 ts1_start_reg = 14'h0;
241 entered_LO = 0;
242 init_reg = 1;
243 nb_tr_reg = 1;
244 fsm_added_delay_reg = 8'h0;
245 calibrate_state_counter = 0;
246
247 `ifdef DTM_ENABLED
248 dtm_enabled = 1;
249 `else
250 dtm_enabled = 0;
251 `endif
252
253`ifdef AXIS_FBDIMM_NO_FSR
254 fbd_poll_add_latency = 8'h4;
255`else
256 if ( !$value$plusargs("fbd_poll_add_latency=%h", fbd_poll_add_latency))
257 fbd_poll_add_latency = 8'h4;
258`endif
259
260 if ($test$plusargs("1_FBDIMM")) LastAMB_ID=0;
261 else if ($test$plusargs("2_FBDIMMS")) LastAMB_ID=1;
262 else if ($test$plusargs("3_FBDIMMS")) LastAMB_ID=2;
263 else if ($test$plusargs("4_FBDIMMS")) LastAMB_ID=3;
264 else if ($test$plusargs("5_FBDIMMS")) LastAMB_ID=4;
265 else if ($test$plusargs("6_FBDIMMS")) LastAMB_ID=5;
266 else if ($test$plusargs("7_FBDIMMS")) LastAMB_ID=6;
267 else if ($test$plusargs("8_FBDIMMS")) LastAMB_ID=7;
268 else LastAMB_ID=0;
269
270 if ($test$plusargs("DTM_ENABLED")) dtm_enabled=1;
271 else dtm_enabled=0;
272
273 if ( $test$plusargs("bypass_init")) begin
274 bypass_init = 1;
275 lock_counter = 4'h1;
276 lock_counter_dtm = 4'h1;
277 init_reg = 0;
278 end
279 else begin
280 bypass_init=0;
281 end
282
283 nb_width_capability=5'h1f;
284
285`ifdef AXIS_FBDIMM_HW
286`else
287 dummy=$value$plusargs("fbdimm_nb_witdh_capability=%h",nb_width_capability);
288
289 if ( $test$plusargs("fbdimm_dbg")) $ch_dispmon("amb_init",`DBG_0,1);
290 if ( $test$plusargs("fbdimm_dbg_1")) $ch_dispmon("amb_init",`DBG_1,1);
291 if ( $test$plusargs("fbdimm_dbg_2")) $ch_dispmon("amb_init",`DBG_2,1);
292 if ( $test$plusargs("fbdimm_dbg_3")) $ch_dispmon("amb_init",`DBG_3,1);
293 if ( $test$plusargs("fbdimm_dbg_4")) $ch_dispmon("amb_init",`DBG_4,1);
294
295 if ( $test$plusargs("mapout_sb9")) sb_config_reg = 4'b1001;
296 if ( $test$plusargs("mapout_sb8")) sb_config_reg = 4'b1000;
297 if ( $test$plusargs("mapout_sb7")) sb_config_reg = 4'b0111;
298 if ( $test$plusargs("mapout_sb6")) sb_config_reg = 4'b0110;
299 if ( $test$plusargs("mapout_sb5")) sb_config_reg = 4'b0101;
300 if ( $test$plusargs("mapout_sb4")) sb_config_reg = 4'b0100;
301 if ( $test$plusargs("mapout_sb3")) sb_config_reg = 4'b0011;
302 if ( $test$plusargs("mapout_sb2")) sb_config_reg = 4'b0010;
303 if ( $test$plusargs("mapout_sb1")) sb_config_reg = 4'b0001;
304 if ( $test$plusargs("mapout_sb0")) sb_config_reg = 4'b0000;
305
306 if ( $test$plusargs("mapout_nb13")) nb_config_reg = 4'b1101;
307 if ( $test$plusargs("mapout_nb12")) nb_config_reg = 4'b1100;
308 if ( $test$plusargs("mapout_nb11")) nb_config_reg = 4'b1011;
309 if ( $test$plusargs("mapout_nb10")) nb_config_reg = 4'b1010;
310 if ( $test$plusargs("mapout_nb9")) nb_config_reg = 4'b1001;
311 if ( $test$plusargs("mapout_nb8")) nb_config_reg = 4'b1000;
312 if ( $test$plusargs("mapout_nb7")) nb_config_reg = 4'b0111;
313 if ( $test$plusargs("mapout_nb6")) nb_config_reg = 4'b0110;
314 if ( $test$plusargs("mapout_nb5")) nb_config_reg = 4'b0101;
315 if ( $test$plusargs("mapout_nb4")) nb_config_reg = 4'b0100;
316 if ( $test$plusargs("mapout_nb3")) nb_config_reg = 4'b0011;
317 if ( $test$plusargs("mapout_nb2")) nb_config_reg = 4'b0010;
318 if ( $test$plusargs("mapout_nb1")) nb_config_reg = 4'b0001;
319 if ( $test$plusargs("mapout_nb0")) nb_config_reg = 4'b0000;
320
321`endif
322
323end // initialization
324
325
326`ifdef FBDIMM_BUG_107438
327 always@(posedge link_clk)
328 dtm_enabled <= tb_top.start_mcu_dtm_training;
329`endif
330
331
332// MAIN AMB INIT FSM
333
334always@(negedge clk_int)
335begin
336 if ( !enter_calibrate_state )
337 begin
338
339 if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ||
340 ( ps1_in[1] !== ps1_in[0] ) && ( ps1_in[1] == ps1_in[2]) ||
341 ( ps2_in[1] !== ps2_in[0] ) && ( ps2_in[1] == ps2_in[2]) ||
342 ( ps3_in[1] !== ps3_in[0] ) && ( ps3_in[1] == ps3_in[2]) ||
343 ( ps4_in[1] !== ps4_in[0] ) && ( ps4_in[1] == ps4_in[2]) ||
344 ( ps5_in[1] !== ps5_in[0] ) && ( ps5_in[1] == ps5_in[2]) ||
345 ( ps6_in[1] !== ps6_in[0] ) && ( ps6_in[1] == ps6_in[2]) ||
346 ( ps7_in[1] !== ps7_in[0] ) && ( ps7_in[1] == ps7_in[2]) ||
347 ( ps8_in[1] !== ps8_in[0] ) && ( ps8_in[1] == ps8_in[2]) ||
348 ( ps9_in[1] !== ps9_in[0] ) && ( ps9_in[1] == ps9_in[2]) ||
349 ( ps10_in[1] !== ps10_in[0] ) && ( ps10_in[1] == ps10_in[2]) ||
350 ( ps11_in[1] !== ps11_in[0] ) && ( ps11_in[1] == ps11_in[2])
351 ) // failed lane is 0
352 begin
353 if ( {ps0_in[1],ps1_in[1],ps2_in[1],ps3_in[1],ps4_in[1],ps5_in[1],ps6_in[1],ps7_in[1],ps8_in[1],ps9_in[1]} == 10'h3ff )
354 calibrate_state_counter <= calibrate_state_counter +1 ;
355 else
356 calibrate_state_counter <= 0;
357
358 end else begin
359 if ( {ps0_in[0],ps1_in[0],ps2_in[0],ps3_in[0],ps4_in[0],ps5_in[0],ps6_in[0],ps7_in[0],ps8_in[0],ps9_in[0]} == 10'h3ff )
360 calibrate_state_counter <= calibrate_state_counter +1 ;
361 else
362 calibrate_state_counter <= 0;
363
364
365 end
366
367 end
368 else
369 calibrate_state_counter <= calibrate_state_counter +1 ;
370
371 if ( !disable_state )
372 begin
373 if ( (calibrate_state_counter > (`tClkTrain * 2 * 3 )) && (( curr_state == `AMB_INIT_TRAIN) || ( curr_state == `AMB_INIT_CALIB) ) )
374 enter_calibrate_state <= 1;
375 else
376 enter_calibrate_state <= 0;
377 end
378 else
379 enter_calibrate_state <= 0;
380
381
382end
383
384always@(posedge clk_int)
385begin
386 if ( enter_los | enter_recalibrate )
387 fsm_reenable <= 1;
388 else if ( curr_state == `AMB_INIT_LO )
389 fsm_reenable <=0;
390
391end
392
393reg [2:0] testing_delimeter_end_detect_state;
394reg ts1_in_progress;
395
396initial begin
397ts1_in_progress=0;
398testing_delimeter_end_detect_state=0;
399end
400
401always@(negedge frm_boundary)
402begin
403 case ( testing_delimeter_end_detect_state)
404 3'h0: begin
405 testing_delimeter_end_detected<=0;
406 // if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ) // failed lane is 0
407 if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ||
408 ( ps1_in[1] !== ps1_in[0] ) && ( ps1_in[1] == ps1_in[2]) ||
409 ( ps2_in[1] !== ps2_in[0] ) && ( ps2_in[1] == ps2_in[2]) ||
410 ( ps3_in[1] !== ps3_in[0] ) && ( ps3_in[1] == ps3_in[2]) ||
411 ( ps4_in[1] !== ps4_in[0] ) && ( ps4_in[1] == ps4_in[2]) ||
412 ( ps5_in[1] !== ps5_in[0] ) && ( ps5_in[1] == ps5_in[2]) ||
413 ( ps6_in[1] !== ps6_in[0] ) && ( ps6_in[1] == ps6_in[2]) ||
414 ( ps7_in[1] !== ps7_in[0] ) && ( ps7_in[1] == ps7_in[2]) ||
415 ( ps8_in[1] !== ps8_in[0] ) && ( ps8_in[1] == ps8_in[2]) ||
416 ( ps9_in[1] !== ps9_in[0] ) && ( ps9_in[1] == ps9_in[2]) ||
417 ( ps10_in[1] !== ps10_in[0] ) && ( ps10_in[1] == ps10_in[2]) ||
418 ( ps11_in[1] !== ps11_in[0] ) && ( ps11_in[1] == ps11_in[2])
419 ) // failed lane is 0
420
421 begin
422 if ( ({ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1]} == 12'hffe) )
423 ts1_in_progress <= 1'b1;
424 end else begin
425 if ( ({ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0]} == 12'hffe) )
426 ts1_in_progress <= 1'b1;
427 end
428
429 if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ||
430 ( ps1_in[1] !== ps1_in[0] ) && ( ps1_in[1] == ps1_in[2]) ||
431 ( ps2_in[1] !== ps2_in[0] ) && ( ps2_in[1] == ps2_in[2]) ||
432 ( ps3_in[1] !== ps3_in[0] ) && ( ps3_in[1] == ps3_in[2]) ||
433 ( ps4_in[1] !== ps4_in[0] ) && ( ps4_in[1] == ps4_in[2]) ||
434 ( ps5_in[1] !== ps5_in[0] ) && ( ps5_in[1] == ps5_in[2]) ||
435 ( ps6_in[1] !== ps6_in[0] ) && ( ps6_in[1] == ps6_in[2]) ||
436 ( ps7_in[1] !== ps7_in[0] ) && ( ps7_in[1] == ps7_in[2]) ||
437 ( ps8_in[1] !== ps8_in[0] ) && ( ps8_in[1] == ps8_in[2]) ||
438 ( ps9_in[1] !== ps9_in[0] ) && ( ps9_in[1] == ps9_in[2]) ||
439 ( ps10_in[1] !== ps10_in[0] ) && ( ps10_in[1] == ps10_in[2]) ||
440 ( ps11_in[1] !== ps11_in[0] ) && ( ps11_in[1] == ps11_in[2])
441 ) // failed lane is 0
442 // if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ) // failed lane is 0
443 begin
444 if ( ({ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1]} == 12'h678) )
445 testing_delimeter_end_detect_state <= 3'h1;
446 end else begin
447 if ( ({ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0]} == 12'h678) )
448 testing_delimeter_end_detect_state <= 3'h1;
449 end
450
451 end
452 3'h1: begin
453 if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ||
454 ( ps1_in[1] !== ps1_in[0] ) && ( ps1_in[1] == ps1_in[2]) ||
455 ( ps2_in[1] !== ps2_in[0] ) && ( ps2_in[1] == ps2_in[2]) ||
456 ( ps3_in[1] !== ps3_in[0] ) && ( ps3_in[1] == ps3_in[2]) ||
457 ( ps4_in[1] !== ps4_in[0] ) && ( ps4_in[1] == ps4_in[2]) ||
458 ( ps5_in[1] !== ps5_in[0] ) && ( ps5_in[1] == ps5_in[2]) ||
459 ( ps6_in[1] !== ps6_in[0] ) && ( ps6_in[1] == ps6_in[2]) ||
460 ( ps7_in[1] !== ps7_in[0] ) && ( ps7_in[1] == ps7_in[2]) ||
461 ( ps8_in[1] !== ps8_in[0] ) && ( ps8_in[1] == ps8_in[2]) ||
462 ( ps9_in[1] !== ps9_in[0] ) && ( ps9_in[1] == ps9_in[2]) ||
463 ( ps10_in[1] !== ps10_in[0] ) && ( ps10_in[1] == ps10_in[2]) ||
464 ( ps11_in[1] !== ps11_in[0] ) && ( ps11_in[1] == ps11_in[2])
465 ) // failed lane is 0
466 //if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ) // failed lane is 0
467 begin
468
469 if ( ({ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1]} == 12'h345) )
470 testing_delimeter_end_detect_state <= 3'h2;
471 else if ( ({ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1]} !== 12'h678) )
472 testing_delimeter_end_detect_state <= 3'h0;
473
474 end else begin
475 if ( ({ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0]} == 12'h345) )
476 testing_delimeter_end_detect_state <= 3'h2;
477 else if ( ({ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0]} !== 12'h678) )
478 testing_delimeter_end_detect_state <= 3'h0;
479 end
480
481 end
482 3'h2: begin
483 //if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ) // failed lane is 0
484 if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ||
485 ( ps1_in[1] !== ps1_in[0] ) && ( ps1_in[1] == ps1_in[2]) ||
486 ( ps2_in[1] !== ps2_in[0] ) && ( ps2_in[1] == ps2_in[2]) ||
487 ( ps3_in[1] !== ps3_in[0] ) && ( ps3_in[1] == ps3_in[2]) ||
488 ( ps4_in[1] !== ps4_in[0] ) && ( ps4_in[1] == ps4_in[2]) ||
489 ( ps5_in[1] !== ps5_in[0] ) && ( ps5_in[1] == ps5_in[2]) ||
490 ( ps6_in[1] !== ps6_in[0] ) && ( ps6_in[1] == ps6_in[2]) ||
491 ( ps7_in[1] !== ps7_in[0] ) && ( ps7_in[1] == ps7_in[2]) ||
492 ( ps8_in[1] !== ps8_in[0] ) && ( ps8_in[1] == ps8_in[2]) ||
493 ( ps9_in[1] !== ps9_in[0] ) && ( ps9_in[1] == ps9_in[2]) ||
494 ( ps10_in[1] !== ps10_in[0] ) && ( ps10_in[1] == ps10_in[2]) ||
495 ( ps11_in[1] !== ps11_in[0] ) && ( ps11_in[1] == ps11_in[2])
496 ) // failed lane is 0
497 begin
498 if ( ({ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1]} == 12'h678) )
499 testing_delimeter_end_detect_state <= 3'h3;
500 else
501 testing_delimeter_end_detect_state <= 3'h0;
502 end else begin
503 if ( ({ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0]} == 12'h678) )
504 testing_delimeter_end_detect_state <= 3'h3;
505 else
506 testing_delimeter_end_detect_state <= 3'h0;
507 end
508
509 end
510 3'h3: begin
511
512 //if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ) // failed lane is 0
513 if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ||
514 ( ps1_in[1] !== ps1_in[0] ) && ( ps1_in[1] == ps1_in[2]) ||
515 ( ps2_in[1] !== ps2_in[0] ) && ( ps2_in[1] == ps2_in[2]) ||
516 ( ps3_in[1] !== ps3_in[0] ) && ( ps3_in[1] == ps3_in[2]) ||
517 ( ps4_in[1] !== ps4_in[0] ) && ( ps4_in[1] == ps4_in[2]) ||
518 ( ps5_in[1] !== ps5_in[0] ) && ( ps5_in[1] == ps5_in[2]) ||
519 ( ps6_in[1] !== ps6_in[0] ) && ( ps6_in[1] == ps6_in[2]) ||
520 ( ps7_in[1] !== ps7_in[0] ) && ( ps7_in[1] == ps7_in[2]) ||
521 ( ps8_in[1] !== ps8_in[0] ) && ( ps8_in[1] == ps8_in[2]) ||
522 ( ps9_in[1] !== ps9_in[0] ) && ( ps9_in[1] == ps9_in[2]) ||
523 ( ps10_in[1] !== ps10_in[0] ) && ( ps10_in[1] == ps10_in[2]) ||
524 ( ps11_in[1] !== ps11_in[0] ) && ( ps11_in[1] == ps11_in[2])
525 ) // failed lane is 0
526 begin
527 if ( ({ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1]} == 12'h345) )
528 testing_delimeter_end_detected<=1;
529 else
530 testing_delimeter_end_detect_state <= 3'h0;
531 end else begin
532 if ( ({ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0]} == 12'h345) )
533 testing_delimeter_end_detected<=1;
534 else
535 testing_delimeter_end_detect_state <= 3'h0;
536 end
537
538 testing_delimeter_end_detect_state <= 3'h0;
539 ts1_in_progress <= 1'b0;
540
541 end
542
543 endcase
544
545
546end
547
548wire detected_2of3_exit_ei;
549wire detected_2of3_enter_ei;
550
551voting_logic test_exit_disable (.a ( ps0_in[0] != ps0_in_bar[0] ),
552 .b ( ps0_in[1] != ps0_in_bar[1] ),
553 .c ( ps0_in[2] != ps0_in_bar[2] ),
554 .out (detected_2of3_exit_ei ));
555
556voting_logic test_enter_disable (.a ( ps0_in[0] == ps0_in_bar[0] ),
557 .b ( ps0_in[1] == ps0_in_bar[1] ),
558 .c ( ps0_in[2] == ps0_in_bar[2] ),
559 .out (detected_2of3_enter_ei ));
560
561
562wire detected_2of3_ts2_hdr;
563
564voting_logic test_ts2_header(.a (({ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0]} == 12'hffe)),
565 .b (({ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1]} == 12'hffe)),
566 .c (({ps11_in[2],ps10_in[2],ps9_in[2],ps8_in[2],ps7_in[2],ps6_in[2],ps5_in[2],ps4_in[2],ps3_in[2],ps2_in[2],ps1_in[2],ps0_in[2]} == 12'hffe)),
567 .out ( detected_2of3_ts2_hdr ));
568
569always@(negedge clk_int) if ( ~bypass_init) begin
570
571 if ( rst ) begin
572 curr_state = `AMB_INIT_DISABLE;
573 init_reg=1;
574 end
575 else
576 case(curr_state)
577 `AMB_INIT_DISABLE: begin
578 nop_cnt=0;
579 init_reg=1;
580 if ( detected_2of3_exit_ei )
581 begin
582 curr_state=`AMB_INIT_TRAIN;
583 entered_LO = 0;
584 //init_reg=1;
585 training_sequence_start_reg=1;
586 end
587 else begin
588 //init_reg=0;
589 training_sequence_start_reg=0;
590 end
591 end
592 `AMB_INIT_TRAIN : begin
593
594 if ( enter_calibrate_state ) begin
595 training_sequence_start_reg=0;
596 curr_state=`AMB_INIT_CALIB;
597 end
598
599 if ( detected_2of3_enter_ei ) begin
600 training_sequence_start_reg=0;
601 curr_state=`AMB_INIT_DISABLE;
602 end
603
604 if ( (detected_2of3_ts2_hdr && dtm_enabled == 0 )
605 ||
606 (dtm_tr_complete && dtm_enabled == 1))
607 begin
608 training_counter = training_counter + 1;
609 training_sequence_start_reg=0;
610 if(dtm_enabled == 1 )
611 begin
612 curr_state = `AMB_INIT_LO;
613 entered_LO = 1;
614 end
615 else if(dtm_enabled == 0)
616 begin
617 curr_state=`AMB_INIT_TEST;
618 entered_LO = 0;
619 end
620 end
621 else begin
622 ts0_reg0[143:0] = {ts0_reg0[142:0],ps_in[0]};
623 ts0_reg1[143:0] = {ts0_reg1[142:0],ps_in[1]};
624 ts0_reg2[143:0] = {ts0_reg2[142:0],ps_in[2]};
625 ts0_reg3[143:0] = {ts0_reg3[142:0],ps_in[3]};
626 ts0_reg4[143:0] = {ts0_reg4[142:0],ps_in[4]};
627 ts0_reg5[143:0] = {ts0_reg5[142:0],ps_in[5]};
628 ts0_reg6[143:0] = {ts0_reg6[142:0],ps_in[6]};
629 ts0_reg7[143:0] = {ts0_reg7[142:0],ps_in[7]};
630 ts0_reg8[143:0] = {ts0_reg8[142:0],ps_in[8]};
631 ts0_reg9[143:0] = {ts0_reg9[142:0],ps_in[9]};
632
633 end
634 end
635
636 `AMB_INIT_CALIB : begin
637
638 if ( detected_2of3_enter_ei )
639 curr_state=`AMB_INIT_DISABLE;
640
641 end
642
643 `AMB_INIT_TEST : begin
644 ts1_start_reg[11:0]=12'hfff; // start testing sequence
645 test_header_reg[10:0] = {ps_in[0], test_header_reg[10:1]};
646
647
648
649 //if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ) // failed lane is 0
650 if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ||
651 ( ps1_in[1] !== ps1_in[0] ) && ( ps1_in[1] == ps1_in[2]) ||
652 ( ps2_in[1] !== ps2_in[0] ) && ( ps2_in[1] == ps2_in[2]) ||
653 ( ps3_in[1] !== ps3_in[0] ) && ( ps3_in[1] == ps3_in[2]) ||
654 ( ps4_in[1] !== ps4_in[0] ) && ( ps4_in[1] == ps4_in[2]) ||
655 ( ps5_in[1] !== ps5_in[0] ) && ( ps5_in[1] == ps5_in[2]) ||
656 ( ps6_in[1] !== ps6_in[0] ) && ( ps6_in[1] == ps6_in[2]) ||
657 ( ps7_in[1] !== ps7_in[0] ) && ( ps7_in[1] == ps7_in[2]) ||
658 ( ps8_in[1] !== ps8_in[0] ) && ( ps8_in[1] == ps8_in[2]) ||
659 ( ps9_in[1] !== ps9_in[0] ) && ( ps9_in[1] == ps9_in[2]) ||
660 ( ps10_in[1] !== ps10_in[0] ) && ( ps10_in[1] == ps10_in[2]) ||
661 ( ps11_in[1] !== ps11_in[0] ) && ( ps11_in[1] == ps11_in[2])
662 ) // failed lane is 0
663 begin
664 if ( ({ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1]} == 12'h7fe) & !ts1_in_progress ) begin
665 curr_state=`AMB_INIT_POLL;
666 ts1_start_reg[11:0]=12'h0;
667 end
668 end else begin
669 if ( ({ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0]} == 12'h7fe) & !ts1_in_progress ) begin
670 curr_state=`AMB_INIT_POLL;
671 ts1_start_reg[11:0]=12'h0;
672 end
673
674 end
675
676 if ( ps_in == ps_in_bar )
677 curr_state=`AMB_INIT_DISABLE;
678
679
680 end
681
682 `AMB_INIT_POLL : begin
683
684 if ( detected_2of3_enter_ei )
685 curr_state=`AMB_INIT_DISABLE;
686
687 ts2_start_reg=12'hfff; // start testing sequence
688 `ifdef AXIS_FBDIMM_1AMB
689 fsm_added_delay_reg= fbd_poll_add_latency; //8'h4; // add 6.5 dram cycles workth of delay
690 `else
691 `ifdef FBDIMM_FAST_NB
692 fsm_added_delay_reg= fbd_poll_add_latency; // add 6.5 dram cycles workth of delay
693 `else
694 fsm_added_delay_reg=8'h2; // add 6.5 dram cycles workth of delay
695 `endif
696 `endif
697
698
699
700 //if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ) // failed lane is 0
701 if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ||
702 ( ps1_in[1] !== ps1_in[0] ) && ( ps1_in[1] == ps1_in[2]) ||
703 ( ps2_in[1] !== ps2_in[0] ) && ( ps2_in[1] == ps2_in[2]) ||
704 ( ps3_in[1] !== ps3_in[0] ) && ( ps3_in[1] == ps3_in[2]) ||
705 ( ps4_in[1] !== ps4_in[0] ) && ( ps4_in[1] == ps4_in[2]) ||
706 ( ps5_in[1] !== ps5_in[0] ) && ( ps5_in[1] == ps5_in[2]) ||
707 ( ps6_in[1] !== ps6_in[0] ) && ( ps6_in[1] == ps6_in[2]) ||
708 ( ps7_in[1] !== ps7_in[0] ) && ( ps7_in[1] == ps7_in[2]) ||
709 ( ps8_in[1] !== ps8_in[0] ) && ( ps8_in[1] == ps8_in[2]) ||
710 ( ps9_in[1] !== ps9_in[0] ) && ( ps9_in[1] == ps9_in[2]) ||
711 ( ps10_in[1] !== ps10_in[0] ) && ( ps10_in[1] == ps10_in[2]) ||
712 ( ps11_in[1] !== ps11_in[0] ) && ( ps11_in[1] == ps11_in[2])
713 ) // failed lane is 0
714 begin
715 if ( ({ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1]} == 12'h3fe) )
716 curr_state=`AMB_INIT_CONFIG;
717 end else begin
718 if ( ({ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0]} == 12'h3fe) )
719 curr_state=`AMB_INIT_CONFIG;
720 end
721
722
723 end
724 `AMB_INIT_CONFIG : begin
725
726 if ( detected_2of3_enter_ei )
727 curr_state=`AMB_INIT_DISABLE;
728
729 ts3_start_reg=12'hfff; // start testing sequence
730
731 if ( ps0_in | ps1_in | ps2_in | ps3_in | ps4_in | ps5_in | ps6_in | ps7_in | ps8_in | ps9_in | ps10_in | ps11_in )
732 nop_cnt = 0;
733 else
734 nop_cnt=nop_cnt+1;
735
736 if ( nop_cnt > 10 )
737 curr_state=`AMB_INIT_LO;
738
739
740 end
741 `AMB_INIT_LO : begin
742
743 if ( detected_2of3_enter_ei )
744 curr_state=`AMB_INIT_DISABLE;
745
746 if ( enter_recalibrate ) begin
747 curr_state=`AMB_INIT_RECALIB;
748 Recalibrate_Timer = 9'h0;
749 end
750 if ( enter_los ) begin
751 curr_state=`AMB_INIT_LOS;
752 LOs_Timer=9'h0;
753 end
754
755 begin
756 init_reg = 0;
757 fsm_added_delay_reg=8'h0 ;
758 end
759
760 end
761 `AMB_INIT_RECALIB: begin
762
763 if ( detected_2of3_enter_ei )
764 curr_state=`AMB_INIT_DISABLE;
765
766`ifdef AXIS_FBDIMM_HW
767`else
768 `PR_ALWAYS ("amb_init",`DBG_0,"Entering AMB Recalibrate State!");
769`endif
770 init_reg=1;
771 if ( Recalibrate_Timer == (recalibdur_reg[6:1]*12) ) // 32 frames
772 curr_state=`AMB_INIT_LO;
773 else
774 Recalibrate_Timer= Recalibrate_Timer + 9'h1;
775
776 end
777 `AMB_INIT_LOS : begin
778
779 if ( detected_2of3_enter_ei )
780 curr_state=`AMB_INIT_DISABLE;
781
782`ifdef AXIS_FBDIMM_HW
783`else
784 `PR_ALWAYS ("amb_init",`DBG_0,"Entering AMB LOs State!");
785`endif
786
787 if ( LOs_Timer == (l0sdur_reg[6:1]*12) ) // 32 frames
788 curr_state=`AMB_INIT_LO;
789 else
790 LOs_Timer= LOs_Timer + 9'h1;
791
792 end
793 endcase
794
795end
796
797
798
799
800assign pn_sb2nbmap = ( sb2nbmap_reg == 3'h0 ) ? {ps_in[3:0],ps_in[4:0],ps_in[4:0]} :
801 ( sb2nbmap_reg == 3'h1 ) ? {ps_in[8:5],ps_in[9:5],ps_in[9:5]} : ps_in ;
802
803
804
805
806
807`ifdef AXIS_FBDIMM_NO_FSR
808always@(posedge clk_int)
809`else
810// Need to leave this one on so that frm_boundary could be sent to other blocks
811always@(posedge link_clk)
812`endif
813begin
814 if ( fsr_counter == 4'h1 )
815 fsr_counter = 4'h6;
816 else
817 fsr_counter = fsr_counter - 1;
818
819 if ( fsr_counter2 == 4'h1 )
820 fsr_counter2 = 4'hc;
821 else
822 fsr_counter2 = fsr_counter2 - 1;
823
824`ifdef DTM_ENABLED
825
826 if ( fsr_counter_dtm == 4'h1 )
827 fsr_counter_dtm = 4'h6;
828 else
829 fsr_counter_dtm = fsr_counter_dtm - 1;
830
831 if ( fsr_counter2_dtm == 4'h1 )
832 fsr_counter2_dtm = 4'hc;
833 else
834 fsr_counter2_dtm = fsr_counter2_dtm - 1;
835
836`endif
837
838end
839
840assign frm_begin = (dtm_enabled && entered_LO ) ? frm_begin_dtm : ( fsr_counter == lock_counter ) ? 1'b1 : 1'b0 ;
841assign frm_boundary = (bypass_init) ? ((fsr_counter2) == (lock_counter+6)) : (fsr_counter2 == lock_counter2) ;
842
843`ifdef DTM_ENABLED
844assign frm_begin_dtm = (fsr_counter_dtm == lock_counter_dtm ) ? 1'b1: 1'b0;
845assign frm_boundary_dtm = (bypass_init) ? ((fsr_counter2_dtm) == (lock_counter_dtm+6)) : (fsr_counter2_dtm == lock_counter2_dtm) ;
846`endif
847
848`ifdef AXIS_FBDIMM_NO_FSR
849always@(negedge clk_int) if ( ~bypass_init )
850`else
851always@(negedge link_clk_int) if ( ~bypass_init )
852`endif // AXIS_FBDIMM_NO_FSR
853begin
854 if (header_detected )
855 begin
856 lock_counter <= prev_counter;
857 lock_counter2 <= prev_counter2;
858 end
859 else begin
860 prev_counter <= fsr_counter;
861 prev_counter2 <= fsr_counter2;
862 end
863end
864
865`ifdef DTM_ENABLED
866
867always@(negedge dtm_link_clk_int) if ( ~bypass_init )
868begin
869
870 if ( rst || ( dtm_enabled && dtm_rst))
871 lock_counter2_dtm <= 0;
872
873 if (header_detected_dtm )
874 begin
875 lock_counter_dtm <= prev_counter_dtm;
876 lock_counter2_dtm <= prev_counter2_dtm;
877 end
878 else begin
879 prev_counter_dtm <= fsr_counter_dtm;
880 prev_counter2_dtm <= fsr_counter2_dtm;
881 end
882end
883
884`endif
885
886
887`ifdef AXIS_FBDIMM_NO_FSR
888always@(negedge clk_int) if ( ~bypass_init && ( curr_state == `AMB_INIT_TRAIN ))
889`else
890always@(posedge link_clk_int) if ( ~bypass_init && ( curr_state == `AMB_INIT_TRAIN ))
891`endif
892begin
893 if ( ireg_l0[47:36] == 12'hbfe )
894 header_detected<=1;
895 else
896 header_detected<=0;
897end
898else
899 header_detected<=0;
900
901`ifdef DTM_ENABLED
902
903always@(posedge dtm_link_clk_int) if ( ~bypass_init)
904begin
905 if ( ireg_l0[47:36] == 12'hbfe )
906 header_detected_dtm<=1;
907 else
908 header_detected_dtm<=0;
909end
910
911`endif
912
913always@(posedge dram_clk)
914begin
915 if (header_detected )
916 enable_fsm=1;
917end
918
919
920reg [13:0] pn_shift_reg;
921reg overwrite;
922
923
924
925
926initial begin
927 ireg_l0 = 48'h000000000;
928 ireg_l1 = 48'h000000000;
929 ireg_l2 = 48'h00000000;
930 ireg_l3 = 48'h00000000;
931 ireg_l4 = 48'h00000000;
932 ireg_l5 = 48'h00000000;
933 ireg_l6 = 48'h00000000;
934 ireg_l7 = 48'h000000000;
935 ireg_l8 = 48'h000000000;
936 ireg_l9 = 48'h000000000;
937
938end
939
940reg ow;
941reg ts1_ow_en;
942reg [2:0] ts3_pattern_state;
943reg [11:0] ts3_pattern;
944reg [47:0] ts3_ireg;
945reg ts3_ow;
946
947initial ts1_ow_en=0;
948
949always@(negedge frm_boundary_fast )
950begin
951if ( init_seq_started ) begin //init_seq_started ) begin
952
953 if ( ( curr_state == `AMB_INIT_TRAIN ))
954 tsid <= 0;
955
956 if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ||
957 ( ps1_in[1] !== ps1_in[0] ) && ( ps1_in[1] == ps1_in[2]) ||
958 ( ps2_in[1] !== ps2_in[0] ) && ( ps2_in[1] == ps2_in[2]) ||
959 ( ps3_in[1] !== ps3_in[0] ) && ( ps3_in[1] == ps3_in[2]) ||
960 ( ps4_in[1] !== ps4_in[0] ) && ( ps4_in[1] == ps4_in[2]) ||
961 ( ps5_in[1] !== ps5_in[0] ) && ( ps5_in[1] == ps5_in[2]) ||
962 ( ps6_in[1] !== ps6_in[0] ) && ( ps6_in[1] == ps6_in[2]) ||
963 ( ps7_in[1] !== ps7_in[0] ) && ( ps7_in[1] == ps7_in[2]) ||
964 ( ps8_in[1] !== ps8_in[0] ) && ( ps8_in[1] == ps8_in[2]) ||
965 ( ps9_in[1] !== ps9_in[0] ) && ( ps9_in[1] == ps9_in[2]) ||
966 ( ps10_in[1] !== ps10_in[0] ) && ( ps10_in[1] == ps10_in[2]) ||
967 ( ps11_in[1] !== ps11_in[0] ) && ( ps11_in[1] == ps11_in[2])
968 ) // failed lane is 0
969 begin
970 if ( ireg_l1[47:0] == 48'h345678345678 )
971 ts1_ow_en=0;
972 end else begin
973 if ( ireg_l0[47:0] == 48'h345678345678 )
974 ts1_ow_en=0;
975 end
976
977
978if ( ( detect_test_hdr_2of3 ) && ( curr_state == `AMB_INIT_TEST ) && !ts1_ow_en ) begin
979 ow=1;
980 ts1_ow_en=1;
981 //if (( ps0_in[0] !== ps0_in[1] ) && ( ps0_in[1] == ps0_in[2]) ) // failed lane is 0
982 if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ||
983 ( ps1_in[1] !== ps1_in[0] ) && ( ps1_in[1] == ps1_in[2]) ||
984 ( ps2_in[1] !== ps2_in[0] ) && ( ps2_in[1] == ps2_in[2]) ||
985 ( ps3_in[1] !== ps3_in[0] ) && ( ps3_in[1] == ps3_in[2]) ||
986 ( ps4_in[1] !== ps4_in[0] ) && ( ps4_in[1] == ps4_in[2]) ||
987 ( ps5_in[1] !== ps5_in[0] ) && ( ps5_in[1] == ps5_in[2]) ||
988 ( ps6_in[1] !== ps6_in[0] ) && ( ps6_in[1] == ps6_in[2]) ||
989 ( ps7_in[1] !== ps7_in[0] ) && ( ps7_in[1] == ps7_in[2]) ||
990 ( ps8_in[1] !== ps8_in[0] ) && ( ps8_in[1] == ps8_in[2]) ||
991 ( ps9_in[1] !== ps9_in[0] ) && ( ps9_in[1] == ps9_in[2]) ||
992 ( ps10_in[1] !== ps10_in[0] ) && ( ps10_in[1] == ps10_in[2]) ||
993 ( ps11_in[1] !== ps11_in[0] ) && ( ps11_in[1] == ps11_in[2])
994 ) // failed lane is 0
995 sb2nbmap_reg = ireg_l1[31:28];
996 else
997 sb2nbmap_reg = ireg_l0[31:28];
998
999 ireg_l0[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0], ps3_in[0], ps2_in[0], ps1_in[0], ps0_in[0], ireg_l0[47:28],LastAMB_ID,ireg_l0[23:12]};
1000 ireg_l1[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1], ps5_in[1], ps4_in[1], ps3_in[1], ps2_in[1], ps1_in[1], ps0_in[1], ireg_l1[47:28],LastAMB_ID,ireg_l1[23:12]};
1001 ireg_l2[47:0] <= { ps11_in[2], ps10_in[2], ps9_in[2], ps8_in[2], ps7_in[2], ps6_in[2], ps5_in[2], ps4_in[2], ps3_in[2], ps2_in[2], ps1_in[2], ps0_in[2], ireg_l2[47:28],LastAMB_ID,ireg_l2[23:12]};
1002 ireg_l3[47:0] <= { ps11_in[3], ps10_in[3], ps9_in[3], ps8_in[3], ps7_in[3], ps6_in[3], ps5_in[3], ps4_in[3], ps3_in[3], ps2_in[3], ps1_in[3], ps0_in[3], ireg_l3[47:28],LastAMB_ID,ireg_l3[23:12]};
1003 ireg_l4[47:0] <= { ps11_in[4], ps10_in[4], ps9_in[4], ps8_in[4], ps7_in[4], ps6_in[4], ps5_in[4], ps4_in[4], ps3_in[4], ps2_in[4], ps1_in[4], ps0_in[4], ireg_l4[47:28],LastAMB_ID,ireg_l4[23:12]};
1004 ireg_l5[47:0] <= { ps11_in[5], ps10_in[5], ps9_in[5], ps8_in[5], ps7_in[5], ps6_in[5], ps5_in[5], ps4_in[5], ps3_in[5], ps2_in[5], ps1_in[5], ps0_in[5], ireg_l5[47:28],LastAMB_ID,ireg_l5[23:12]};
1005 ireg_l6[47:0] <= { ps11_in[6], ps10_in[6], ps9_in[6], ps8_in[6], ps7_in[6], ps6_in[6], ps5_in[6], ps4_in[6], ps3_in[6], ps2_in[6], ps1_in[6], ps0_in[6], ireg_l6[47:28],LastAMB_ID,ireg_l6[23:12]};
1006 ireg_l7[47:0] <= { ps11_in[7], ps10_in[7], ps9_in[7], ps8_in[7], ps7_in[7], ps6_in[7], ps5_in[7], ps4_in[7], ps3_in[7], ps2_in[7], ps1_in[7], ps0_in[7], ireg_l7[47:28],LastAMB_ID,ireg_l7[23:12]};
1007 ireg_l8[47:0] <= { ps11_in[8], ps10_in[8], ps9_in[8], ps8_in[8], ps7_in[8], ps6_in[8], ps5_in[8], ps4_in[8], ps3_in[8], ps2_in[8], ps1_in[8], ps0_in[8], ireg_l8[47:28],LastAMB_ID,ireg_l8[23:12]};
1008 ireg_l9[47:0] <= { ps11_in[9], ps10_in[9], ps9_in[9], ps8_in[9], ps7_in[9], ps6_in[9], ps5_in[9], ps4_in[9], ps3_in[9], ps2_in[9], ps1_in[9], ps0_in[9], ireg_l9[47:28],LastAMB_ID,ireg_l9[23:12]};
1009
1010 end
1011 else if (( detect_cfg_hdr_2of3 & ~frm_boundary_fast) && ( curr_state == `AMB_INIT_CONFIG ) ) begin
1012 //ow=1;
1013 // if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ) // failed lane is 0
1014 if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ||
1015 ( ps1_in[1] !== ps1_in[0] ) && ( ps1_in[1] == ps1_in[2]) ||
1016 ( ps2_in[1] !== ps2_in[0] ) && ( ps2_in[1] == ps2_in[2]) ||
1017 ( ps3_in[1] !== ps3_in[0] ) && ( ps3_in[1] == ps3_in[2]) ||
1018 ( ps4_in[1] !== ps4_in[0] ) && ( ps4_in[1] == ps4_in[2]) ||
1019 ( ps5_in[1] !== ps5_in[0] ) && ( ps5_in[1] == ps5_in[2]) ||
1020 ( ps6_in[1] !== ps6_in[0] ) && ( ps6_in[1] == ps6_in[2]) ||
1021 ( ps7_in[1] !== ps7_in[0] ) && ( ps7_in[1] == ps7_in[2]) ||
1022 ( ps8_in[1] !== ps8_in[0] ) && ( ps8_in[1] == ps8_in[2]) ||
1023 ( ps9_in[1] !== ps9_in[0] ) && ( ps9_in[1] == ps9_in[2]) ||
1024 ( ps10_in[1] !== ps10_in[0] ) && ( ps10_in[1] == ps10_in[2]) ||
1025 ( ps11_in[1] !== ps11_in[0] ) && ( ps11_in[1] == ps11_in[2])
1026 ) // failed lane is 0
1027 begin
1028 nb_config_reg <= ireg_l1[45:42];
1029 sb_config_reg <= ireg_l1[39:36];
1030
1031 ireg_l0[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1], ps3_in[1], ps2_in[1], ps1_in[1], ps0_in[1], ireg_l0[47:36],8'h0,LastAMB_ID, ireg_l0[23:12]};
1032 ireg_l1[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1], ps3_in[1], ps2_in[1], ps1_in[1], ps0_in[1], ireg_l1[47:36],8'h0,LastAMB_ID, ireg_l1[23:12]};
1033 ireg_l2[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1], ps3_in[1], ps2_in[1], ps1_in[1], ps0_in[1], ireg_l2[47:36],8'h0,LastAMB_ID, ireg_l2[23:12]};
1034 ireg_l3[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1], ps3_in[1], ps2_in[1], ps1_in[1], ps0_in[1], ireg_l3[47:36],8'h0,LastAMB_ID, ireg_l3[23:12]};
1035 ireg_l4[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1], ps3_in[1], ps2_in[1], ps1_in[1], ps0_in[1], ireg_l4[47:36],8'h0,LastAMB_ID, ireg_l4[23:12]};
1036 ireg_l5[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1], ps3_in[1], ps2_in[1], ps1_in[1], ps0_in[1], ireg_l5[47:36],8'h0,LastAMB_ID, ireg_l5[23:12]};
1037 ireg_l6[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1], ps3_in[1], ps2_in[1], ps1_in[1], ps0_in[1], ireg_l6[47:36],8'h0,LastAMB_ID, ireg_l6[23:12]};
1038 ireg_l7[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1], ps3_in[1], ps2_in[1], ps1_in[1], ps0_in[1], ireg_l7[47:36],8'h0,LastAMB_ID, ireg_l7[23:12]};
1039 ireg_l8[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1], ps3_in[1], ps2_in[1], ps1_in[1], ps0_in[1], ireg_l8[47:36],8'h0,LastAMB_ID, ireg_l8[23:12]};
1040 ireg_l9[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1], ps3_in[1], ps2_in[1], ps1_in[1], ps0_in[1], ireg_l9[47:36],8'h0,LastAMB_ID,ireg_l9[23:12]};
1041 end
1042 else
1043 begin
1044 nb_config_reg <= ireg_l0[45:42];
1045 sb_config_reg <= ireg_l0[39:36];
1046
1047 ireg_l0[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0], ps3_in[0], ps2_in[0], ps1_in[0], ps0_in[0], ireg_l0[47:36],8'h0,LastAMB_ID, ireg_l0[23:12]};
1048 ireg_l1[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0], ps3_in[0], ps2_in[0], ps1_in[0], ps0_in[0], ireg_l1[47:36],8'h0,LastAMB_ID, ireg_l1[23:12]};
1049 ireg_l2[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0], ps3_in[0], ps2_in[0], ps1_in[0], ps0_in[0], ireg_l2[47:36],8'h0,LastAMB_ID, ireg_l2[23:12]};
1050 ireg_l3[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0], ps3_in[0], ps2_in[0], ps1_in[0], ps0_in[0], ireg_l3[47:36],8'h0,LastAMB_ID, ireg_l3[23:12]};
1051 ireg_l4[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0], ps3_in[0], ps2_in[0], ps1_in[0], ps0_in[0], ireg_l4[47:36],8'h0,LastAMB_ID, ireg_l4[23:12]};
1052 ireg_l5[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0], ps3_in[0], ps2_in[0], ps1_in[0], ps0_in[0], ireg_l5[47:36],8'h0,LastAMB_ID, ireg_l5[23:12]};
1053 ireg_l6[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0], ps3_in[0], ps2_in[0], ps1_in[0], ps0_in[0], ireg_l6[47:36],8'h0,LastAMB_ID, ireg_l6[23:12]};
1054 ireg_l7[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0], ps3_in[0], ps2_in[0], ps1_in[0], ps0_in[0], ireg_l7[47:36],8'h0,LastAMB_ID, ireg_l7[23:12]};
1055 ireg_l8[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0], ps3_in[0], ps2_in[0], ps1_in[0], ps0_in[0], ireg_l8[47:36],8'h0,LastAMB_ID, ireg_l8[23:12]};
1056 ireg_l9[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0], ps3_in[0], ps2_in[0], ps1_in[0], ps0_in[0], ireg_l9[47:36],8'h0,LastAMB_ID,ireg_l9[23:12]};
1057 end
1058
1059
1060 end
1061 else if ( ( detect_poll_hdr_2of3) && ( curr_state == `AMB_INIT_POLL ) ) begin
1062 ow=1;
1063 tsid <= tsid + 4'h1;
1064
1065 // if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ) // failed lane is 0
1066 if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ||
1067 ( ps1_in[1] !== ps1_in[0] ) && ( ps1_in[1] == ps1_in[2]) ||
1068 ( ps2_in[1] !== ps2_in[0] ) && ( ps2_in[1] == ps2_in[2]) ||
1069 ( ps3_in[1] !== ps3_in[0] ) && ( ps3_in[1] == ps3_in[2]) ||
1070 ( ps4_in[1] !== ps4_in[0] ) && ( ps4_in[1] == ps4_in[2]) ||
1071 ( ps5_in[1] !== ps5_in[0] ) && ( ps5_in[1] == ps5_in[2]) ||
1072 ( ps6_in[1] !== ps6_in[0] ) && ( ps6_in[1] == ps6_in[2]) ||
1073 ( ps7_in[1] !== ps7_in[0] ) && ( ps7_in[1] == ps7_in[2]) ||
1074 ( ps8_in[1] !== ps8_in[0] ) && ( ps8_in[1] == ps8_in[2]) ||
1075 ( ps9_in[1] !== ps9_in[0] ) && ( ps9_in[1] == ps9_in[2]) ||
1076 ( ps10_in[1] !== ps10_in[0] ) && ( ps10_in[1] == ps10_in[2]) ||
1077 ( ps11_in[1] !== ps11_in[0] ) && ( ps11_in[1] == ps11_in[2])
1078 ) // failed lane is 0
1079 begin
1080 ireg_l0[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1], 2'h0, nb_width_capability,1'h0,tsid, ireg_l0[35:12]};
1081 ireg_l1[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1], 2'h0, nb_width_capability,1'h0,tsid ,ireg_l1[35:12]};
1082 ireg_l2[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1], 2'h0, nb_width_capability,1'h0,tsid, ireg_l2[35:12]};
1083 ireg_l3[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1], 2'h0, nb_width_capability,1'h0,tsid, ireg_l3[35:12]};
1084 ireg_l4[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1], 2'h0, nb_width_capability,1'h0,tsid, ireg_l4[35:12]};
1085 ireg_l5[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1], 2'h0, nb_width_capability,1'h0 ,tsid, ireg_l5[35:12]};
1086 ireg_l6[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1], 2'h0, nb_width_capability,1'h0,tsid, ireg_l6[35:12]};
1087 ireg_l7[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1], 2'h0, nb_width_capability,1'h0 ,tsid, ireg_l7[35:12]};
1088 ireg_l8[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1], 2'h0, nb_width_capability,1'h0,tsid, ireg_l8[35:12]};
1089 ireg_l9[47:0] <= { ps11_in[1], ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[9],2'h0, nb_width_capability,1'h0 ,tsid, ireg_l9[35:12]};
1090 end else begin
1091 ireg_l0[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0], 2'h0, nb_width_capability,1'h0,tsid, ireg_l0[35:12]};
1092 ireg_l1[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0], 2'h0, nb_width_capability,1'h0,tsid ,ireg_l1[35:12]};
1093 ireg_l2[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0], 2'h0, nb_width_capability,1'h0,tsid, ireg_l2[35:12]};
1094 ireg_l3[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0], 2'h0, nb_width_capability,1'h0,tsid, ireg_l3[35:12]};
1095 ireg_l4[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0], 2'h0, nb_width_capability,1'h0,tsid, ireg_l4[35:12]};
1096 ireg_l5[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0], 2'h0, nb_width_capability,1'h0 ,tsid, ireg_l5[35:12]};
1097 ireg_l6[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0], 2'h0, nb_width_capability,1'h0,tsid, ireg_l6[35:12]};
1098 ireg_l7[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0], 2'h0, nb_width_capability,1'h0 ,tsid, ireg_l7[35:12]};
1099 ireg_l8[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0], 2'h0, nb_width_capability,1'h0,tsid, ireg_l8[35:12]};
1100 ireg_l9[47:0] <= { ps11_in[0], ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[9],2'h0, nb_width_capability,1'h0 ,tsid, ireg_l9[35:12]};
1101 end
1102
1103 end
1104 else if ( curr_state == `AMB_INIT_CONFIG )
1105 begin
1106 ts3_ow =1;
1107 // if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ) // failed lane is 0
1108 if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ||
1109 ( ps1_in[1] !== ps1_in[0] ) && ( ps1_in[1] == ps1_in[2]) ||
1110 ( ps2_in[1] !== ps2_in[0] ) && ( ps2_in[1] == ps2_in[2]) ||
1111 ( ps3_in[1] !== ps3_in[0] ) && ( ps3_in[1] == ps3_in[2]) ||
1112 ( ps4_in[1] !== ps4_in[0] ) && ( ps4_in[1] == ps4_in[2]) ||
1113 ( ps5_in[1] !== ps5_in[0] ) && ( ps5_in[1] == ps5_in[2]) ||
1114 ( ps6_in[1] !== ps6_in[0] ) && ( ps6_in[1] == ps6_in[2]) ||
1115 ( ps7_in[1] !== ps7_in[0] ) && ( ps7_in[1] == ps7_in[2]) ||
1116 ( ps8_in[1] !== ps8_in[0] ) && ( ps8_in[1] == ps8_in[2]) ||
1117 ( ps9_in[1] !== ps9_in[0] ) && ( ps9_in[1] == ps9_in[2]) ||
1118 ( ps10_in[1] !== ps10_in[0] ) && ( ps10_in[1] == ps10_in[2]) ||
1119 ( ps11_in[1] !== ps11_in[0] ) && ( ps11_in[1] == ps11_in[2])
1120 ) // failed lane is 0
1121 begin
1122 ireg_l0[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l0[47:12]};
1123 ireg_l1[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l1[47:12]};
1124 ireg_l2[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l2[47:12]};
1125 ireg_l3[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l3[47:12]};
1126 ireg_l4[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l4[47:12]};
1127 ireg_l5[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l5[47:12]};
1128 ireg_l6[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l6[47:12]};
1129 ireg_l7[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l7[47:12]};
1130 ireg_l8[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l8[47:12]};
1131 ireg_l9[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l9[47:12]};
1132 end
1133 else
1134 begin
1135
1136 ireg_l0[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l0[47:12]};
1137 ireg_l1[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l1[47:12]};
1138 ireg_l2[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l2[47:12]};
1139 ireg_l3[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l3[47:12]};
1140 ireg_l4[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l4[47:12]};
1141 ireg_l5[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l5[47:12]};
1142 ireg_l6[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l6[47:12]};
1143 ireg_l7[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l7[47:12]};
1144 ireg_l8[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l8[47:12]};
1145 ireg_l9[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l9[47:12]};
1146 end
1147
1148 end
1149 else if ( curr_state == `AMB_INIT_TEST ) begin
1150
1151 ts3_ow=0;
1152 ow=0;
1153 ireg_l0[47:0] <= { ps11_in[0], ps10_in[0], ps9_in[0], ps8_in[0], ps7_in[0], ps6_in[0],ps5_in[0],ps4_in[0], ps3_in[0], ps2_in[0], ps1_in[0], ps0_in[0], ireg_l0[47:12]};
1154 ireg_l1[47:0] <= { ps11_in[1], ps10_in[1], ps9_in[1], ps8_in[1], ps7_in[1], ps6_in[1], ps5_in[1], ps4_in[1], ps3_in[1], ps2_in[1], ps1_in[1], ps0_in[1], ireg_l1[47:12]};
1155 ireg_l2[47:0] <= { ps11_in[2], ps10_in[2], ps9_in[2], ps8_in[2], ps7_in[2], ps6_in[2], ps5_in[2], ps4_in[2], ps3_in[2], ps2_in[2], ps1_in[2], ps0_in[2], ireg_l2[47:12]};
1156 ireg_l3[47:0] <= { ps11_in[3], ps10_in[3], ps9_in[3], ps8_in[3], ps7_in[3], ps6_in[3], ps5_in[3], ps4_in[3], ps3_in[3], ps2_in[3], ps1_in[3], ps0_in[3], ireg_l3[47:12]};
1157 ireg_l4[47:0] <= { ps11_in[4], ps10_in[4], ps9_in[4], ps8_in[4], ps7_in[4], ps6_in[4], ps5_in[4], ps4_in[4], ps3_in[4], ps2_in[4], ps1_in[4], ps0_in[4], ireg_l4[47:12]};
1158 ireg_l5[47:0] <= { ps11_in[5], ps10_in[5], ps9_in[5], ps8_in[5], ps7_in[5], ps6_in[5], ps5_in[5], ps4_in[5], ps3_in[5], ps2_in[5], ps1_in[5], ps0_in[5], ireg_l5[47:12]};
1159 ireg_l6[47:0] <= { ps11_in[6], ps10_in[6], ps9_in[6], ps8_in[6], ps7_in[6], ps6_in[6], ps5_in[6], ps4_in[6], ps3_in[6], ps2_in[6], ps1_in[6], ps0_in[6], ireg_l6[47:12]};
1160 ireg_l7[47:0] <= { ps11_in[7], ps10_in[7], ps9_in[7], ps8_in[7], ps7_in[7], ps6_in[7], ps5_in[7], ps4_in[7], ps3_in[7], ps2_in[7], ps1_in[7], ps0_in[7], ireg_l7[47:12]};
1161 ireg_l8[47:0] <= { ps11_in[8], ps10_in[8], ps9_in[8], ps8_in[8], ps7_in[8], ps6_in[8], ps5_in[8], ps4_in[8], ps3_in[8], ps2_in[8], ps1_in[8], ps0_in[8], ireg_l8[47:12]};
1162 ireg_l9[47:0] <= { ps11_in[9], ps10_in[9], ps9_in[9], ps8_in[9], ps7_in[9], ps6_in[9], ps5_in[9], ps4_in[9], ps3_in[9], ps2_in[9], ps1_in[9], ps0_in[9], ireg_l9[47:12]};
1163
1164 end else begin
1165
1166 ts3_ow=0;
1167 ow=0;
1168
1169 if (( ps0_in[1] !== ps0_in[0] ) && ( ps0_in[1] == ps0_in[2]) ||
1170 ( ps1_in[1] !== ps1_in[0] ) && ( ps1_in[1] == ps1_in[2]) ||
1171 ( ps2_in[1] !== ps2_in[0] ) && ( ps2_in[1] == ps2_in[2]) ||
1172 ( ps3_in[1] !== ps3_in[0] ) && ( ps3_in[1] == ps3_in[2]) ||
1173 ( ps4_in[1] !== ps4_in[0] ) && ( ps4_in[1] == ps4_in[2]) ||
1174 ( ps5_in[1] !== ps5_in[0] ) && ( ps5_in[1] == ps5_in[2]) ||
1175 ( ps6_in[1] !== ps6_in[0] ) && ( ps6_in[1] == ps6_in[2]) ||
1176 ( ps7_in[1] !== ps7_in[0] ) && ( ps7_in[1] == ps7_in[2]) ||
1177 ( ps8_in[1] !== ps8_in[0] ) && ( ps8_in[1] == ps8_in[2]) ||
1178 ( ps9_in[1] !== ps9_in[0] ) && ( ps9_in[1] == ps9_in[2]) ||
1179 ( ps10_in[1] !== ps10_in[0] ) && ( ps10_in[1] == ps10_in[2]) ||
1180 ( ps11_in[1] !== ps11_in[0] ) && ( ps11_in[1] == ps11_in[2])
1181 ) // failed lane is 0
1182 begin
1183 ireg_l0[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l0[47:12]};
1184 ireg_l1[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l1[47:12]};
1185 ireg_l2[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l2[47:12]};
1186 ireg_l3[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l3[47:12]};
1187 ireg_l4[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l4[47:12]};
1188 ireg_l5[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l5[47:12]};
1189 ireg_l6[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l6[47:12]};
1190 ireg_l7[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l7[47:12]};
1191 ireg_l8[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l8[47:12]};
1192 ireg_l9[47:0] <= { ps11_in[1],ps10_in[1],ps9_in[1],ps8_in[1],ps7_in[1],ps6_in[1],ps5_in[1],ps4_in[1],ps3_in[1],ps2_in[1],ps1_in[1],ps0_in[1],ireg_l9[47:12]};
1193 end
1194 else
1195 begin
1196 ireg_l0[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l0[47:12]};
1197 ireg_l1[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l1[47:12]};
1198 ireg_l2[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l2[47:12]};
1199 ireg_l3[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l3[47:12]};
1200 ireg_l4[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l4[47:12]};
1201 ireg_l5[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l5[47:12]};
1202 ireg_l6[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l6[47:12]};
1203 ireg_l7[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l7[47:12]};
1204 ireg_l8[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l8[47:12]};
1205 ireg_l9[47:0] <= { ps11_in[0],ps10_in[0],ps9_in[0],ps8_in[0],ps7_in[0],ps6_in[0],ps5_in[0],ps4_in[0],ps3_in[0],ps2_in[0],ps1_in[0],ps0_in[0],ireg_l9[47:12]};
1206 end
1207
1208 end
1209
1210
1211end
1212
1213end
1214
1215
1216initial begin
1217ts3_ireg = {12'h3fe,36'h0};
1218ts3_pattern_state=0;
1219ts3_pattern = 12'h3fe;
1220end
1221
1222always@(negedge frm_boundary_fast ) if ( curr_state == `AMB_INIT_CONFIG )
1223begin
1224 case ( ts3_pattern_state )
1225 3'h0: begin
1226 ts3_pattern <= {8'h0,LastAMB_ID};
1227 ts3_pattern_state <= 3'h1;
1228 end
1229 3'h1: begin
1230 ts3_pattern_state <= 3'h2;
1231 end
1232 3'h2: begin
1233 ts3_pattern <= {2'b01, ps3_in[1], ps2_in[1],ps1_in[1],ps0_in[1], ps6_in[0],2'b00,ps9_in[1], ps8_in[1],ps7_in[1],ps6_in[1]};
1234 ts3_pattern_state <= 3'h3;
1235 end
1236 3'h3: begin
1237 ts3_pattern <= 12'haaa;
1238 ts3_pattern_state <= 3'h4;
1239 end
1240 3'h4: begin
1241 ts3_pattern <= 12'haaa;
1242 ts3_pattern_state <= 3'h5;
1243 end
1244 3'h5: begin
1245 ts3_pattern <= 12'haaa;
1246 ts3_pattern_state <= 3'h6;
1247 end
1248 3'h6: begin
1249 ts3_pattern <= 12'h3fe;
1250 ts3_pattern_state <= 3'h0;
1251 end
1252 endcase
1253
1254end
1255
1256
1257
1258
1259assign pn0_out_tmp = (enter_calibrate_state ) ? 14'h3fff :
1260 ( sb2nbmap_reg == 3'h0 ) ? {ireg_l3[0],ireg_l2[0],ireg_l1[0],ireg_l0[0],ireg_l4[0],ireg_l3[0],ireg_l2[0],ireg_l1[0], ireg_l0[0], ireg_l4[0],ireg_l3[0],ireg_l2[0],ireg_l1[0],ireg_l0[0]} :
1261 ( sb2nbmap_reg == 3'h1 ) ? {ireg_l8[0],ireg_l7[0],ireg_l6[0],ireg_l5[0],ireg_l9[0],ireg_l8[0],ireg_l7[0],ireg_l6[0], ireg_l5[0], ireg_l9[0],ireg_l8[0],ireg_l7[0],ireg_l6[0],ireg_l5[0]} :
1262 {ireg_l3[0],ireg_l2[0],ireg_l1[0],ireg_l0[0],ireg_l4[0],ireg_l3[0],ireg_l2[0],ireg_l1[0], ireg_l0[0], ireg_l4[0],ireg_l3[0],ireg_l2[0],ireg_l1[0],ireg_l0[0]};
1263
1264assign pn1_out_tmp = (enter_calibrate_state ) ? 14'h3fff :
1265 ( sb2nbmap_reg == 3'h0 ) ? {ireg_l3[1],ireg_l2[1],ireg_l1[1],ireg_l0[1],ireg_l4[1],ireg_l3[1],ireg_l2[1],ireg_l1[1], ireg_l0[1], ireg_l4[1],ireg_l3[1],ireg_l2[1],ireg_l1[1],ireg_l0[1]} :
1266 ( sb2nbmap_reg == 3'h1 ) ? {ireg_l8[1],ireg_l7[1],ireg_l6[1],ireg_l5[1],ireg_l9[1],ireg_l8[1],ireg_l7[1],ireg_l6[1], ireg_l5[1], ireg_l9[1],ireg_l8[1],ireg_l7[1],ireg_l6[1],ireg_l5[1]} :
1267 {ireg_l3[1],ireg_l2[1],ireg_l1[1],ireg_l0[1],ireg_l4[1],ireg_l3[1],ireg_l2[1],ireg_l1[1], ireg_l0[1], ireg_l4[1],ireg_l3[1],ireg_l2[1],ireg_l1[1],ireg_l0[1]};
1268
1269assign pn2_out_tmp = (enter_calibrate_state ) ? 14'h3fff :
1270 ( sb2nbmap_reg == 3'h0 ) ? {ireg_l3[2],ireg_l2[2],ireg_l1[2],ireg_l0[2],ireg_l4[2],ireg_l3[2],ireg_l2[2],ireg_l1[2], ireg_l0[2], ireg_l4[2],ireg_l3[2],ireg_l2[2],ireg_l1[2],ireg_l0[2]} :
1271 ( sb2nbmap_reg == 3'h1 ) ? {ireg_l8[2],ireg_l7[2],ireg_l6[2],ireg_l5[2],ireg_l9[2],ireg_l8[2],ireg_l7[2],ireg_l6[2], ireg_l5[2], ireg_l9[2],ireg_l8[2],ireg_l7[2],ireg_l6[2],ireg_l5[2]} :
1272 {ireg_l3[2],ireg_l2[2],ireg_l1[2],ireg_l0[2],ireg_l4[2],ireg_l3[2],ireg_l2[2],ireg_l1[2], ireg_l0[2], ireg_l4[2],ireg_l3[2],ireg_l2[2],ireg_l1[2],ireg_l0[2]};
1273
1274assign pn3_out_tmp = (enter_calibrate_state ) ? 14'h3fff :
1275 ( sb2nbmap_reg == 3'h0 ) ? {ireg_l3[3],ireg_l2[3],ireg_l1[3],ireg_l0[3],ireg_l4[3],ireg_l3[3],ireg_l2[3],ireg_l1[3], ireg_l0[3], ireg_l4[3],ireg_l3[3],ireg_l2[3],ireg_l1[3],ireg_l0[3]} :
1276 ( sb2nbmap_reg == 3'h1 ) ? {ireg_l8[3],ireg_l7[3],ireg_l6[3],ireg_l5[3],ireg_l9[3],ireg_l8[3],ireg_l7[3],ireg_l6[3], ireg_l5[3], ireg_l9[3],ireg_l8[3],ireg_l7[3],ireg_l6[3],ireg_l5[3]} :
1277 {ireg_l3[3],ireg_l2[3],ireg_l1[3],ireg_l0[3],ireg_l4[3],ireg_l3[3],ireg_l2[3],ireg_l1[3], ireg_l0[3], ireg_l4[3],ireg_l3[3],ireg_l2[3],ireg_l1[3],ireg_l0[3]};
1278
1279assign pn4_out_tmp = (enter_calibrate_state ) ? 14'h3fff :
1280 ( sb2nbmap_reg == 3'h0 ) ? {ireg_l3[4],ireg_l2[4],ireg_l1[4],ireg_l0[4],ireg_l4[4],ireg_l3[4],ireg_l2[4],ireg_l1[4], ireg_l0[4], ireg_l4[4],ireg_l3[4],ireg_l2[4],ireg_l1[4],ireg_l0[4]} :
1281 ( sb2nbmap_reg == 3'h1 ) ? {ireg_l8[4],ireg_l7[4],ireg_l6[4],ireg_l5[4],ireg_l9[4],ireg_l8[4],ireg_l7[4],ireg_l6[4], ireg_l5[4], ireg_l9[4],ireg_l8[4],ireg_l7[4],ireg_l6[4],ireg_l5[4]} :
1282 {ireg_l3[4],ireg_l2[4],ireg_l1[4],ireg_l0[4],ireg_l4[4],ireg_l3[4],ireg_l2[4],ireg_l1[4], ireg_l0[4], ireg_l4[4],ireg_l3[4],ireg_l2[4],ireg_l1[4],ireg_l0[4]};
1283
1284assign pn5_out_tmp = (enter_calibrate_state ) ? 14'h3fff :
1285 ( sb2nbmap_reg == 3'h0 ) ? {ireg_l3[5],ireg_l2[5],ireg_l1[5],ireg_l0[5],ireg_l4[5],ireg_l3[5],ireg_l2[5],ireg_l1[5], ireg_l0[5], ireg_l4[5],ireg_l3[5],ireg_l2[5],ireg_l1[5],ireg_l0[5]} :
1286 ( sb2nbmap_reg == 3'h1 ) ? {ireg_l8[5],ireg_l7[5],ireg_l6[5],ireg_l5[5],ireg_l9[5],ireg_l8[5],ireg_l7[5],ireg_l6[5], ireg_l5[5], ireg_l9[5],ireg_l8[5],ireg_l7[5],ireg_l6[5],ireg_l5[5]} :
1287 {ireg_l3[5],ireg_l2[5],ireg_l1[5],ireg_l0[5],ireg_l4[5],ireg_l3[5],ireg_l2[5],ireg_l1[5], ireg_l0[5], ireg_l4[5],ireg_l3[5],ireg_l2[5],ireg_l1[5],ireg_l0[5]};
1288
1289assign pn6_out_tmp = (enter_calibrate_state ) ? 14'h3fff :
1290 ( sb2nbmap_reg == 3'h0 ) ? {ireg_l3[6],ireg_l2[6],ireg_l1[6],ireg_l0[6],ireg_l4[6],ireg_l3[6],ireg_l2[6],ireg_l1[6], ireg_l0[6], ireg_l4[6],ireg_l3[6],ireg_l2[6],ireg_l1[6],ireg_l0[6]} :
1291 ( sb2nbmap_reg == 3'h1 ) ? {ireg_l8[6],ireg_l7[6],ireg_l6[6],ireg_l5[6],ireg_l9[6],ireg_l8[6],ireg_l7[6],ireg_l6[6], ireg_l5[6], ireg_l9[6],ireg_l8[6],ireg_l7[6],ireg_l6[6],ireg_l5[6]} :
1292 {ireg_l3[6],ireg_l2[6],ireg_l1[6],ireg_l0[6],ireg_l4[6],ireg_l3[6],ireg_l2[6],ireg_l1[6], ireg_l0[6], ireg_l4[6],ireg_l3[6],ireg_l2[6],ireg_l1[6],ireg_l0[6]};
1293
1294assign pn7_out_tmp = (enter_calibrate_state ) ? 14'h3fff :
1295 ( sb2nbmap_reg == 3'h0 ) ? {ireg_l3[7],ireg_l2[7],ireg_l1[7],ireg_l0[7],ireg_l4[7],ireg_l3[7],ireg_l2[7],ireg_l1[7], ireg_l0[7], ireg_l4[7],ireg_l3[7],ireg_l2[7],ireg_l1[7],ireg_l0[7]} :
1296 ( sb2nbmap_reg == 3'h1 ) ? {ireg_l8[7],ireg_l7[7],ireg_l6[7],ireg_l5[7],ireg_l9[7],ireg_l8[7],ireg_l7[7],ireg_l6[7], ireg_l5[7], ireg_l9[7],ireg_l8[7],ireg_l7[7],ireg_l6[7],ireg_l5[7]} :
1297 {ireg_l3[7],ireg_l2[7],ireg_l1[7],ireg_l0[7],ireg_l4[7],ireg_l3[7],ireg_l2[7],ireg_l1[7], ireg_l0[7], ireg_l4[7],ireg_l3[7],ireg_l2[7],ireg_l1[7],ireg_l0[7]};
1298
1299assign pn8_out_tmp = (enter_calibrate_state ) ? 14'h3fff :
1300 ( sb2nbmap_reg == 3'h0 ) ? {ireg_l3[8],ireg_l2[8],ireg_l1[8],ireg_l0[8],ireg_l4[8],ireg_l3[8],ireg_l2[8],ireg_l1[8], ireg_l0[8], ireg_l4[8],ireg_l3[8],ireg_l2[8],ireg_l1[8],ireg_l0[8]} :
1301 ( sb2nbmap_reg == 3'h1 ) ? {ireg_l8[8],ireg_l7[8],ireg_l6[8],ireg_l5[8],ireg_l9[8],ireg_l8[8],ireg_l7[8],ireg_l6[8], ireg_l5[8], ireg_l9[8],ireg_l8[8],ireg_l7[8],ireg_l6[8],ireg_l5[8]} :
1302 {ireg_l3[8],ireg_l2[8],ireg_l1[8],ireg_l0[8],ireg_l4[8],ireg_l3[8],ireg_l2[8],ireg_l1[8], ireg_l0[8], ireg_l4[8],ireg_l3[8],ireg_l2[8],ireg_l1[8],ireg_l0[8]};
1303
1304assign pn9_out_tmp = (enter_calibrate_state ) ? 14'h3fff :
1305 ( sb2nbmap_reg == 3'h0 ) ? {ireg_l3[9],ireg_l2[9],ireg_l1[9],ireg_l0[9],ireg_l4[9],ireg_l3[9],ireg_l2[9],ireg_l1[9], ireg_l0[9], ireg_l4[9],ireg_l3[9],ireg_l2[9],ireg_l1[9],ireg_l0[9]} :
1306 ( sb2nbmap_reg == 3'h1 ) ? {ireg_l8[9],ireg_l7[9],ireg_l6[9],ireg_l5[9],ireg_l9[9],ireg_l8[9],ireg_l7[9],ireg_l6[9], ireg_l5[9], ireg_l9[9],ireg_l8[9],ireg_l7[9],ireg_l6[9],ireg_l5[9]} :
1307 {ireg_l3[9],ireg_l2[9],ireg_l1[9],ireg_l0[9],ireg_l4[9],ireg_l3[9],ireg_l2[9],ireg_l1[9], ireg_l0[9], ireg_l4[9],ireg_l3[9],ireg_l2[9],ireg_l1[9],ireg_l0[9]};
1308
1309assign pn10_out_tmp = (enter_calibrate_state ) ? 14'h3fff :
1310 ( sb2nbmap_reg == 3'h0 ) ? {ireg_l3[10],ireg_l2[10],ireg_l1[10],ireg_l0[10],ireg_l4[10],ireg_l3[10],ireg_l2[10],ireg_l1[10], ireg_l0[10], ireg_l4[10],ireg_l3[10],ireg_l2[10],ireg_l1[10],ireg_l0[10]} :
1311 ( sb2nbmap_reg == 3'h1 ) ? {ireg_l8[10],ireg_l7[10],ireg_l6[10],ireg_l5[10],ireg_l9[10],ireg_l8[10],ireg_l7[10],ireg_l6[10], ireg_l5[10], ireg_l9[10],ireg_l8[10],ireg_l7[10],ireg_l6[10],ireg_l5[10]} :
1312 {ireg_l3[10],ireg_l2[10],ireg_l1[10],ireg_l0[10],ireg_l4[10],ireg_l3[10],ireg_l2[10],ireg_l1[10], ireg_l0[10], ireg_l4[10],ireg_l3[10],ireg_l2[10],ireg_l1[10],ireg_l0[10]};
1313
1314assign pn11_out_tmp = (enter_calibrate_state ) ? 14'h3fff :
1315 ( sb2nbmap_reg == 3'h0 ) ? {ireg_l3[11],ireg_l2[11],ireg_l1[11],ireg_l0[11],ireg_l4[11],ireg_l3[11],ireg_l2[11],ireg_l1[11], ireg_l0[11], ireg_l4[11],ireg_l3[11],ireg_l2[11],ireg_l1[11],ireg_l0[11]} :
1316 ( sb2nbmap_reg == 3'h1 ) ? {ireg_l8[11],ireg_l7[11],ireg_l6[11],ireg_l5[11],ireg_l9[11],ireg_l8[11],ireg_l7[11],ireg_l6[11], ireg_l5[11], ireg_l9[11],ireg_l8[11],ireg_l7[11],ireg_l6[11],ireg_l5[11]} :
1317 {ireg_l3[11],ireg_l2[11],ireg_l1[11],ireg_l0[11],ireg_l4[11],ireg_l3[11],ireg_l2[11],ireg_l1[11], ireg_l0[11], ireg_l4[11],ireg_l3[11],ireg_l2[11],ireg_l1[11],ireg_l0[11]};
1318
1319
1320
1321shifter_p #(NB_LINK) shft0 (.signal_in ( pn0_out_tmp),
1322 .signal_out (pn0_out),
1323 .delay_cycles (delay_reg),
1324 .clk ( frm_boundary_fast));
1325shifter_p #(NB_LINK) shft1 (.signal_in ( pn1_out_tmp),
1326 .signal_out (pn1_out),
1327 .delay_cycles (delay_reg),
1328 .clk ( frm_boundary_fast));
1329shifter_p #(NB_LINK) shft2 (.signal_in ( pn2_out_tmp),
1330 .signal_out (pn2_out),
1331 .delay_cycles (delay_reg),
1332 .clk (frm_boundary_fast));
1333shifter_p #(NB_LINK) shft3 (.signal_in ( pn3_out_tmp),
1334 .signal_out (pn3_out),
1335 .delay_cycles (delay_reg),
1336 .clk (frm_boundary_fast));
1337shifter_p #(NB_LINK) shft4 (.signal_in ( pn4_out_tmp),
1338 .signal_out (pn4_out),
1339 .delay_cycles (delay_reg),
1340 .clk ( frm_boundary_fast));
1341shifter_p #(NB_LINK) shft5 (.signal_in ( pn5_out_tmp),
1342 .signal_out (pn5_out),
1343 .delay_cycles (delay_reg),
1344 .clk ( frm_boundary_fast));
1345shifter_p #(NB_LINK) shft6 (.signal_in ( pn6_out_tmp),
1346 .signal_out (pn6_out),
1347 .delay_cycles (delay_reg),
1348 .clk ( frm_boundary_fast));
1349shifter_p #(NB_LINK) shft7 (.signal_in ( pn7_out_tmp),
1350 .signal_out (pn7_out),
1351 .delay_cycles (delay_reg),
1352 .clk ( frm_boundary_fast));
1353shifter_p #(NB_LINK) shft8 (.signal_in ( pn8_out_tmp),
1354 .signal_out (pn8_out),
1355 .delay_cycles (delay_reg),
1356 .clk ( frm_boundary_fast));
1357shifter_p #(NB_LINK) shft9 (.signal_in ( pn9_out_tmp),
1358 .signal_out (pn9_out),
1359 .delay_cycles (delay_reg),
1360 .clk ( frm_boundary_fast));
1361shifter_p #(NB_LINK) shft10 (.signal_in ( pn10_out_tmp),
1362 .signal_out (pn10_out),
1363 .delay_cycles (delay_reg),
1364 .clk ( frm_boundary_fast));
1365shifter_p #(NB_LINK) shft11 (.signal_in ( pn11_out_tmp),
1366 .signal_out (pn11_out),
1367 .delay_cycles (delay_reg),
1368 .clk ( frm_boundary_fast));
1369
1370
1371
1372
1373
1374initial begin
1375enter_calibrate_state = 0;
1376end
1377
1378assign pn = ( enter_calibrate_state ) ? 14'h3fff : pn_init ;
1379assign pn_bar = ( curr_state == `AMB_INIT_DISABLE ) ? pn : ~pn;
1380
1381
1382assign frm_start= frm_boundary; //|frm_align[13:0];
1383
1384assign ps_in = ps;
1385assign ps_in_bar = ps_bar;
1386
1387
1388
1389voting_logic mod_detect_test_hdr_2of3(.a ( (ireg_l0[23:12] == 12'hffe ) ),
1390 .b ( (ireg_l1[23:12] == 12'hffe ) ),
1391 .c ( (ireg_l2[23:12] == 12'hffe ) ),
1392 .out ( detect_test_hdr_2of3 ));
1393
1394voting_logic mod_detect_cfg_hdr_2of3(.a ( (ireg_l0[23:12] == 12'h3fe ) ),
1395 .b ( (ireg_l1[23:12] == 12'h3fe ) ),
1396 .c ( (ireg_l2[23:12] == 12'h3fe ) ),
1397 .out ( detect_cfg_hdr_2of3 ));
1398
1399voting_logic mod_detect_poll_hdr_2of3(.a ( (ireg_l0[23:12] == 12'h7fe ) ),
1400 .b ( (ireg_l1[23:12] == 12'h7fe ) ),
1401 .c ( (ireg_l2[23:12] == 12'h7fe ) ),
1402 .out ( detect_poll_hdr_2of3 ));
1403
1404
1405endmodule
Full OpenSPARC design & verification tarball including full HDL.