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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: channel_mon.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `ifdef AXIS_FBDIMM_HW | |
36 | `else | |
37 | module channel_mon ( ps , pn , ps_bar, | |
38 | sb_cmd_rdy,sb_cmd_type,sb_cmd_encoding, | |
39 | sb_frm_rdy, ps0,ps1,ps2,ps3,ps4,ps5,ps6,ps7,ps8,ps9,ps10,ps11,ps12, | |
40 | nb_frm_rdy, pn0,pn1,pn2,pn3,pn4,pn5,pn6,pn7,pn8,pn9,pn10,pn11,pn12, | |
41 | nb_frm_type, | |
42 | write_fifo_empty, | |
43 | init_out, rst , sclk,dram_clk); | |
44 | ||
45 | // Parameters | |
46 | parameter SB_LINK = 10; | |
47 | parameter NB_LINK = 14; | |
48 | ||
49 | // Inputs/Outputs | |
50 | input [SB_LINK-1:0] ps,ps_bar; // primary southbound | |
51 | input [NB_LINK-1:0] pn; // primary northbound | |
52 | output [SB_LINK-1:0] ps0,ps1,ps2,ps3,ps4,ps5,ps6,ps7,ps8,ps9,ps10,ps11,ps12; | |
53 | output [NB_LINK-1:0] pn0,pn1,pn2,pn3,pn4,pn5,pn6,pn7,pn8,pn9,pn10,pn11,pn12; | |
54 | input sclk,dram_clk; | |
55 | output init_out; | |
56 | input rst; | |
57 | input write_fifo_empty; | |
58 | output [2:0] sb_cmd_rdy; | |
59 | output [14:0] sb_cmd_type; | |
60 | output [71:0] sb_cmd_encoding; | |
61 | output nb_frm_rdy; | |
62 | output [1:0] nb_frm_type; | |
63 | output sb_frm_rdy; | |
64 | ||
65 | //internal registers | |
66 | reg [SB_LINK-1:0] trans_3,trans_2,trans_1,trans_0; | |
67 | reg [SB_LINK-1:0] sb_frame[11:0]; | |
68 | reg [23:0] aC,bC,cC; | |
69 | reg [3:0] sb_config; | |
70 | reg [3:0] nb_config; | |
71 | reg [2:0] cmd_B[3:0]; | |
72 | reg [2:0] cmd_C[3:0]; | |
73 | reg [71:0] aData; | |
74 | reg [21:0] FE; | |
75 | reg [31:0] D; | |
76 | reg [71:0] WDATA; | |
77 | reg [4:0] curr_state,next_state; | |
78 | reg [2:0] WS; | |
79 | reg [3:0] WS_tmp,BE; | |
80 | reg [13:0] FE_latch,aE; | |
81 | reg [1:0] Write_Frame_Count,F; | |
82 | reg [12:0] sync_counter_reg; | |
83 | reg [13:0] Test_aE,Test_FE,calc_aE_reg,Test1_FE,calc_aE; | |
84 | reg [21:0] calc_FE_latch_reg,calc_FE_reg; | |
85 | reg [71:0] Data_72; | |
86 | reg [25:0] Command_26; | |
87 | reg [31:0] cfg_data; | |
88 | reg [11:0] frmdata_0,frmdata_1,frmdata_2,frmdata_3,frmdata_4,frmdata_5; | |
89 | reg [11:0] frmdata_6,frmdata_7,frmdata_8,frmdata_9,frmdata_10; | |
90 | reg [5:0] nosync_framecount; | |
91 | reg [8:0] LOs_Timer,Recalibrate_Timer; | |
92 | reg [3:0] fsr_counter,lock_counter,lock_counter2,prev_counter; | |
93 | reg [3:0] fsr_counter2,prev_counter2; | |
94 | reg [2:0] sb_cmd_rdy_reg; | |
95 | reg [14:0] sb_cmd_type_reg; | |
96 | reg [71:0] sb_cmd_encoding_reg; | |
97 | reg [8:0] sb_cmd_ds_reg; | |
98 | reg [15:0] ts0_pattern; | |
99 | reg [10:0] calibrate_state_counter; | |
100 | reg [NB_LINK-1:0] nb_frame[11:0]; | |
101 | reg [1:0] inbank_debug_count; | |
102 | reg [23:0] Command; | |
103 | reg [SB_LINK-1:0] C1,C2,C3,C4; | |
104 | reg [6:0] config_reg_cmd_latency_count; | |
105 | reg [4:0] frame_cnt; | |
106 | reg [7:0] sync_interval_frm_count; | |
107 | reg [7:0] self_refresh_exit_counter; | |
108 | reg [31:0] register_memory[0:2048]; // register memory image same should be same as fbdimm model | |
109 | reg [3:0] init_curr_state; | |
110 | reg [63:0] link_clk_count; | |
111 | reg [143:0] ts0_reg0,ts0_reg1,ts0_reg2,ts0_reg3,ts0_reg4,ts0_reg5,ts0_reg6; | |
112 | reg [143:0] ts0_reg7,ts0_reg8,ts0_reg9; | |
113 | reg [11:0] SB_transfer_reg,NB_transfer_reg; | |
114 | reg [10:0] polling_counter; | |
115 | reg [10:0] channel_latency; | |
116 | reg [47:0] initialization_register_link0; | |
117 | reg frame_complete; | |
118 | reg pending_config_reg_cmd; | |
119 | reg F0,F1; | |
120 | reg frm_boundary_d1; | |
121 | reg event_self_refresh_exit,event_dram_write_cmd,event_dram_nonread_cmd; | |
122 | reg latency_calculated; | |
123 | reg training_sequence_start_reg; | |
124 | reg header_detected,enable_fsm; | |
125 | reg Curr_Command_A_is_Sync,Prev_Command_A_is_Sync; | |
126 | reg command_A_rdy,command_B_rdy,command_C_rdy; | |
127 | reg tmpWS,Write_Frame_Reg,invalidate_Write_FIFO_reg,sb_crc_error_reg,init_reg,init_reg_d1; | |
128 | reg cfg_rd,reset_sync,sync_cmd_data,sync_detected_reg,first_sync_detected_reg; | |
129 | reg autoref_write_reg,detected_autorefresh_cmd,sync_cmd_rdy,Last_TID,failover_sb,enter_recalibrate,enter_los; | |
130 | reg nb_12,bypass_init,failover_nb_13,failover_nb_14,enter_calibrate_state; | |
131 | reg nb_header_detected, sb_header_detected; | |
132 | reg [3:0] nb_frm_counter; | |
133 | reg [3:0] nb_lock_counter; | |
134 | reg nb_frm_boundary_d1; | |
135 | wire ts0_ready_2of3; | |
136 | wire sb_crc_error_reg_d; | |
137 | wire link_clk = sclk; | |
138 | wire link_clk_en; | |
139 | wire link_clk_int; | |
140 | wire [13:0] CRC14; | |
141 | wire [21:0] CRC22; | |
142 | wire enter_disable_state; | |
143 | wire first_sync_detected_reg_d1; | |
144 | wire [9:0] CRC10_cmd_failover,CRC10_data_failover; | |
145 | wire [SB_LINK-1:0] ps_map,ps_map_bar; | |
146 | wire [SB_LINK-1:0] sb0 = sb_frame[0]; | |
147 | wire [SB_LINK-1:0] sb1 = sb_frame[1]; | |
148 | wire [SB_LINK-1:0] sb2 = sb_frame[2]; | |
149 | wire [SB_LINK-1:0] sb3 = sb_frame[3]; | |
150 | wire [SB_LINK-1:0] sb4 = sb_frame[4]; | |
151 | wire [SB_LINK-1:0] sb5 = sb_frame[5]; | |
152 | wire [SB_LINK-1:0] sb6 = sb_frame[6]; | |
153 | wire frm_begin,frm_boundary,nb_frm_boundary; | |
154 | wire pn_data,pn_data_d1; | |
155 | wire pn_status, pn_status_d1; | |
156 | wire pn_alert, pn_alert_d1; | |
157 | wire [2:0] sb2nbmap; | |
158 | wire soft_channel_reset = invalidate_Write_FIFO_reg; | |
159 | ||
160 | assign init_out = init_reg; | |
161 | assign sb_cmd_rdy = sb_cmd_rdy_reg; | |
162 | assign sb_cmd_type=sb_cmd_type_reg; | |
163 | assign sb_cmd_encoding=sb_cmd_encoding_reg; | |
164 | wire [NB_LINK-1:0] pn_reg; | |
165 | wire alert_frame; | |
166 | wire training_sequence_start=training_sequence_start_reg; | |
167 | ||
168 | assign sb_frm_rdy = frm_boundary_d1 | header_detected ; | |
169 | ||
170 | assign link_clk_en = (ps === ps_bar ) ? 1'b1 : | |
171 | ( ~init_reg ) ? 1'b0 : | |
172 | 1'b1; | |
173 | assign link_clk_int = link_clk & link_clk_en; | |
174 | ||
175 | ||
176 | ||
177 | assign nb_frm_rdy = (nb_frm_boundary | nb_header_detected ) ? 1'b1 : 1'b0; | |
178 | assign nb_frm_type = ( pn_data ) ? 2'h1: | |
179 | ( pn_status ) ? 2'h2: | |
180 | ( alert_frame ) ? 2'h3: | |
181 | 2'h0; | |
182 | ||
183 | ||
184 | assign ps_map = ( sb_config == 4'b1111 ) ? ps : // all lanes are good | |
185 | ( sb_config == 4'b1001 ) ? {1'b0,ps[8:0]} : // map out lane 9 | |
186 | ( sb_config == 4'b1000 ) ? {ps[8] ,1'b0,ps[7:0]} : // map out lane 8 | |
187 | ( sb_config == 4'b0111 ) ? {ps[8:7],1'b0,ps[6:0]} : // map out lane 7 | |
188 | ( sb_config == 4'b0110 ) ? {ps[8:6],1'b0,ps[5:0]} : // map out lane 6 | |
189 | ( sb_config == 4'b0101 ) ? {ps[8:5],1'b0,ps[4:0]} : // map out lane 5 | |
190 | ( sb_config == 4'b0100 ) ? {ps[8:4],1'b0,ps[3:0]} : // map out lane 4 | |
191 | ( sb_config == 4'b0011 ) ? {ps[8:3],1'b0,ps[2:0]} : // map out lane 3 | |
192 | ( sb_config == 4'b0010 ) ? {ps[8:2],1'b0,ps[1:0]} : // map out lane 2 | |
193 | ( sb_config == 4'b0001 ) ? {ps[8:1],1'b0,ps[0]} : // map out lane 1 | |
194 | ( sb_config == 4'b0000 ) ? {ps[9:1]} : ps ; // map out lane 0 | |
195 | ||
196 | assign ps_map_bar = ( sb_config == 4'b1111 ) ? ps_bar : // all lanes are good | |
197 | ( sb_config == 4'b1001 ) ? {1'b0,ps_bar[8:0]} : // map out lane 9 | |
198 | ( sb_config == 4'b1000 ) ? {ps_bar[8] ,1'b0,ps_bar[7:0]} : // map out lane 8 | |
199 | ( sb_config == 4'b0111 ) ? {ps_bar[8:7],1'b0,ps_bar[6:0]} : // map out lane 7 | |
200 | ( sb_config == 4'b0110 ) ? {ps_bar[8:6],1'b0,ps_bar[5:0]} : // map out lane 6 | |
201 | ( sb_config == 4'b0101 ) ? {ps_bar[8:5],1'b0,ps_bar[4:0]} : // map out lane 5 | |
202 | ( sb_config == 4'b0100 ) ? {ps_bar[8:4],1'b0,ps_bar[3:0]} : // map out lane 4 | |
203 | ( sb_config == 4'b0011 ) ? {ps_bar[8:3],1'b0,ps_bar[2:0]} : // map out lane 3 | |
204 | ( sb_config == 4'b0010 ) ? {ps_bar[8:2],1'b0,ps_bar[1:0]} : // map out lane 2 | |
205 | ( sb_config == 4'b0001 ) ? {ps_bar[8:1],1'b0,ps_bar[0]} : // map out lane 1 | |
206 | ( sb_config == 4'b0000 ) ? {ps_bar[9:1]} : ps_bar ; // map out lane 0 | |
207 | ||
208 | ||
209 | ||
210 | // AMB registers | |
211 | wire [31:0] sync_train_interval_reg = register_memory[{3'h1,8'h78}]; | |
212 | wire [31:0] fbdreg_dsreftc = register_memory[{3'h3,8'h74}]; // dram self refresh and timing control | |
213 | ||
214 | ||
215 | wire [12:0] Write_Frame_Wire_d; | |
216 | wire [23:0] command_select = (command_A_rdy) ? aC[23:0] : | |
217 | (command_B_rdy) ? bC[23:0] : | |
218 | (command_C_rdy) ? cC[23:0] : 24'h0; | |
219 | ||
220 | ||
221 | reg [13:0] pn0_reg,pn1_reg,pn2_reg,pn3_reg; | |
222 | reg [13:0] pn4_reg,pn5_reg,pn6_reg,pn7_reg; | |
223 | reg [13:0] pn8_reg,pn9_reg,pn10_reg,pn11_reg; | |
224 | ||
225 | assign pn0 = pn0_reg; | |
226 | assign pn1 = pn1_reg; | |
227 | assign pn2 = pn2_reg; | |
228 | assign pn3 = pn3_reg; | |
229 | assign pn4 = pn4_reg; | |
230 | assign pn5 = pn5_reg; | |
231 | assign pn6 = pn6_reg; | |
232 | assign pn7 = pn7_reg; | |
233 | assign pn8 = pn8_reg; | |
234 | assign pn9 = pn9_reg; | |
235 | assign pn10 = pn10_reg; | |
236 | assign pn11 = pn11_reg; | |
237 | ||
238 | ||
239 | ||
240 | always@(posedge link_clk) | |
241 | nb_frm_boundary_d1 <= nb_frm_boundary; | |
242 | ||
243 | ||
244 | always@(negedge link_clk) | |
245 | begin | |
246 | frm_boundary_d1 <= frm_boundary; | |
247 | end | |
248 | ||
249 | ||
250 | dff_p #(1) pn_data_delay1 (.signal_in ( pn_data ), | |
251 | .signal_out (pn_data_d1), | |
252 | .clk (link_clk)); | |
253 | ||
254 | dff_p #(1) pn_status_delay1(.signal_in ( pn_status ), | |
255 | .signal_out (pn_status_d1), | |
256 | .clk (link_clk)); | |
257 | ||
258 | dff_p #(1) pn_alert_delay1(.signal_in ( pn_alert ), | |
259 | .signal_out (pn_alert_d1), | |
260 | .clk (link_clk)); | |
261 | ||
262 | always@(negedge link_clk) | |
263 | begin | |
264 | pn0_reg <= pn1_reg; | |
265 | pn1_reg <= pn2_reg; | |
266 | pn2_reg <= pn3_reg; | |
267 | pn3_reg <= pn4_reg; | |
268 | pn4_reg <= pn5_reg; | |
269 | pn5_reg <= pn6_reg; | |
270 | pn6_reg <= pn7_reg; | |
271 | pn7_reg <= pn8_reg; | |
272 | pn8_reg <= pn9_reg; | |
273 | pn9_reg <= pn10_reg; | |
274 | pn10_reg <= pn11_reg; | |
275 | pn11_reg <= pn; | |
276 | ||
277 | end | |
278 | ||
279 | ||
280 | always@(posedge link_clk) | |
281 | init_reg_d1 <= init_reg; | |
282 | ||
283 | always@(posedge link_clk) | |
284 | begin | |
285 | ||
286 | // checks | |
287 | ||
288 | if ( event_dram_write_cmd || | |
289 | event_dram_nonread_cmd ) | |
290 | begin | |
291 | if ( self_refresh_exit_counter >= fbdreg_dsreftc[15:8] ) | |
292 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: DRAM self-refresh exit to non-read comman timing violation!"); | |
293 | self_refresh_exit_counter = 0; | |
294 | end | |
295 | ||
296 | // counter unpdates | |
297 | ||
298 | if ( event_self_refresh_exit ) | |
299 | self_refresh_exit_counter = self_refresh_exit_counter + 1; | |
300 | else | |
301 | self_refresh_exit_counter = 0; | |
302 | ||
303 | end | |
304 | ||
305 | ||
306 | wire read_cmd_rdy = ( command_A_rdy | command_B_rdy | command_C_rdy ) && (command_select[20:18] == 3'b010 ); | |
307 | wire [38:0] read_cmd_rdy_d,sync_cmd_rdy_d; | |
308 | wire sync_cmd_rdy_d1; | |
309 | ||
310 | assign pn_data = (read_cmd_rdy_d[1]) | (read_cmd_rdy_d[2]); | |
311 | assign pn_status = sync_cmd_rdy_d1; | |
312 | assign pn_alert = sb_crc_error_reg_d; | |
313 | ||
314 | ||
315 | initial begin | |
316 | channel_latency=0; | |
317 | init_reg = 1; | |
318 | end | |
319 | ||
320 | shifter_p #(1) alert_frm_dly ( .signal_in (sb_crc_error_reg), | |
321 | .signal_out ( sb_crc_error_reg_d), | |
322 | .delay_cycles ( 10'd24), | |
323 | .clk (link_clk)); | |
324 | ||
325 | shifter_p #(1) read_cmd_delay_d1 ( .signal_in (read_cmd_rdy), | |
326 | .signal_out (read_cmd_rdy_d[1]), | |
327 | .delay_cycles ( channel_latency - 4 + 12 ), | |
328 | .clk (link_clk)); | |
329 | ||
330 | shifter_p #(1) read_cmd_delay_d2 ( .signal_in (read_cmd_rdy_d[1]), | |
331 | .signal_out (read_cmd_rdy_d[2]), | |
332 | .delay_cycles (10'hc), | |
333 | .clk (link_clk)); | |
334 | ||
335 | shifter_p #(1) read_cmd_delay_d3 ( .signal_in (read_cmd_rdy_d[2]), | |
336 | .signal_out (read_cmd_rdy_d[3]), | |
337 | .delay_cycles (10'h1), | |
338 | .clk (link_clk)); | |
339 | ||
340 | // sync command ready | |
341 | ||
342 | shifter_p #(1) sync_cmd_delay_d1 ( .signal_in (sync_cmd_rdy && ( aC[20:18] == 3'b000 ) && ( aC[17:14] == 4'b0001)), | |
343 | .signal_out (sync_cmd_rdy_d1), | |
344 | .delay_cycles ( channel_latency - 4 + 12 ), | |
345 | .clk (link_clk)); | |
346 | ||
347 | shifter_p #(1) sync_cmd_delay_d2 ( .signal_in (sync_cmd_rdy_d[1]), | |
348 | .signal_out (sync_cmd_rdy_d[2]), | |
349 | .delay_cycles (10'h1), | |
350 | .clk (link_clk)); | |
351 | ||
352 | ||
353 | reg autoref = 1'b0; | |
354 | ||
355 | always@(posedge link_clk) if ( ~init_reg & ( command_A_rdy | command_B_rdy | command_C_rdy ) ) | |
356 | begin | |
357 | ||
358 | event_dram_write_cmd = 1'b0; | |
359 | event_dram_nonread_cmd = 1'b0; | |
360 | ||
361 | ||
362 | if ( command_select[20] && ( ( !F0 && !F1) || F1 ) ) | |
363 | `PR_ALWAYS ("ch_mon",`DBG_0,"FBDIMM: Command A: ACTIVATE"); | |
364 | else | |
365 | case (command_select[20:18]) | |
366 | 3'b000: begin | |
367 | if ( command_select[17:14] == 4'h0 ) begin | |
368 | // case ( {command_A_rdy,command_B_rdy,command_C_rdy} ) | |
369 | // 3'b100: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command A: NOP"); end | |
370 | // 3'b010: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command B: NOP"); end | |
371 | // 3'b001: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command C: NOP"); end | |
372 | // endcase | |
373 | end | |
374 | else if ( command_select[17:14] == 4'h1 ) begin | |
375 | case ( {command_A_rdy,command_B_rdy,command_C_rdy} ) | |
376 | 3'b100: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command A: SYNC"); end | |
377 | 3'b010: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command B: SYNC"); end | |
378 | 3'b001: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command C: SYNC"); end | |
379 | endcase | |
380 | end | |
381 | else if ( command_select[17:14] == 4'h2 ) begin | |
382 | case ( {command_A_rdy,command_B_rdy,command_C_rdy} ) | |
383 | 3'b100: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command A: Soft channel Reset"); end | |
384 | 3'b010: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command B: Soft channel Reset"); end | |
385 | 3'b001: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command C: Soft channel Reset"); end | |
386 | endcase | |
387 | end | |
388 | else if ( command_select[17:14] == 4'h4 ) begin | |
389 | case ( {command_A_rdy,command_B_rdy,command_C_rdy} ) | |
390 | 3'b100: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command A: Read Config"); end | |
391 | 3'b010: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command B: Read Config"); end | |
392 | 3'b001: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command C: Read Config"); end | |
393 | endcase | |
394 | end | |
395 | else if ( command_select[17:14] == 4'h5 ) begin | |
396 | case ( {command_A_rdy,command_B_rdy,command_C_rdy} ) | |
397 | 3'b100: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command A: Write Config"); autoref_write_reg = 1; end | |
398 | 3'b010: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command B: Write Config"); autoref_write_reg = 1; end | |
399 | 3'b001: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command C: Write Config"); autoref_write_reg = 1; end | |
400 | endcase | |
401 | end | |
402 | else if ( command_select[17:14] == 4'h6 ) begin | |
403 | case ( {command_A_rdy,command_B_rdy,command_C_rdy} ) | |
404 | 3'b100: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command A: Dram cke rank"); end | |
405 | 3'b010: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command B: Dram cke rank"); end | |
406 | 3'b001: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command C: Dram cke rank"); end | |
407 | endcase | |
408 | end | |
409 | else if ( command_select[17:14] == 4'h7 ) begin | |
410 | case ( {command_A_rdy,command_B_rdy,command_C_rdy} ) | |
411 | 3'b100: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command A: Dram cke dimm"); end | |
412 | 3'b010: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command B: Dram cke dimm"); end | |
413 | 3'b001: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command C: Dram cke dimm"); end | |
414 | endcase | |
415 | end | |
416 | else begin | |
417 | case ( {command_A_rdy,command_B_rdy,command_C_rdy} ) | |
418 | 3'b100: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: ERROR: Command A: undefined"); end | |
419 | 3'b010: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: ERROR: Command B: undefined"); end | |
420 | 3'b001: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: ERROR: Command C: undefined"); end | |
421 | endcase | |
422 | end | |
423 | end | |
424 | 3'b011: begin | |
425 | event_dram_write_cmd = 1; | |
426 | case ( {command_A_rdy,command_B_rdy,command_C_rdy} ) | |
427 | 3'b100: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command A: Write"); end | |
428 | 3'b010: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command B: Write"); end | |
429 | 3'b001: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command C: Write"); end | |
430 | endcase | |
431 | end | |
432 | 3'b010: begin | |
433 | case ( {command_A_rdy,command_B_rdy,command_C_rdy} ) | |
434 | 3'b100: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command A: Read"); end | |
435 | 3'b010: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command B: Read"); end | |
436 | 3'b001: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command C: Read"); end | |
437 | endcase | |
438 | end | |
439 | 3'b001: begin | |
440 | event_dram_nonread_cmd = 1; | |
441 | case (command_select[12:10]) | |
442 | 3'b111: begin | |
443 | case ( {command_A_rdy,command_B_rdy,command_C_rdy} ) | |
444 | 3'b100: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command A: Precharge All"); end | |
445 | 3'b010: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command B: Precharge All"); end | |
446 | 3'b001: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command C: Precharge All"); end | |
447 | endcase | |
448 | end | |
449 | 3'b110: begin | |
450 | case ( {command_A_rdy,command_B_rdy,command_C_rdy} ) | |
451 | 3'b100: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command A: Precharge Single"); end | |
452 | 3'b010: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command B: Precharge Single"); end | |
453 | 3'b001: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command C: Precharge Single"); end | |
454 | endcase | |
455 | end | |
456 | 3'b101: begin | |
457 | case ( {command_A_rdy,command_B_rdy,command_C_rdy} ) | |
458 | 3'b100: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command A: Auto Refresh"); detected_autorefresh_cmd = 1; end | |
459 | 3'b010: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command B: Auto Refresh"); detected_autorefresh_cmd = 1; end | |
460 | 3'b001: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command C: Auto Refresh"); detected_autorefresh_cmd = 1; end | |
461 | endcase | |
462 | end | |
463 | 3'b100: begin | |
464 | case ( {command_A_rdy,command_B_rdy,command_C_rdy} ) | |
465 | 3'b100: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command A: Enter Self Refresh"); end | |
466 | 3'b010: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command B: Enter Self Refresh"); end | |
467 | 3'b001: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command C: Enter Self Refresh"); end | |
468 | endcase | |
469 | end | |
470 | 3'b011: begin | |
471 | case ( {command_A_rdy,command_B_rdy,command_C_rdy} ) | |
472 | 3'b100: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command A: Exit Self Refresh/Exit Power Down"); end | |
473 | 3'b010: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command B: Exit Self Refresh/Exit Power Down"); end | |
474 | 3'b001: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command C: Exit Self Refresh/Exit Power Down"); end | |
475 | endcase | |
476 | event_self_refresh_exit = 1; | |
477 | end | |
478 | 3'b010: begin | |
479 | case ( {command_A_rdy,command_B_rdy,command_C_rdy} ) | |
480 | 3'b100: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command A: Enter Power Down"); end | |
481 | 3'b010: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command B: Enter Power Down"); end | |
482 | 3'b001: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command C: Enter Power Down"); end | |
483 | endcase | |
484 | end | |
485 | endcase | |
486 | end | |
487 | default: begin | |
488 | case ( {command_A_rdy,command_B_rdy,command_C_rdy} ) | |
489 | 3'b100: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command A: Undefined"); end | |
490 | 3'b010: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command B: Undefined"); end | |
491 | 3'b001: begin `PR_ALWAYS ("ch_mon",`DBG_4,"FBDIMM: Command C: Undefined"); end | |
492 | endcase | |
493 | end | |
494 | ||
495 | endcase | |
496 | ||
497 | ||
498 | end | |
499 | ||
500 | /************************* SB DECODER LOGIC *******************/ | |
501 | ||
502 | always@(posedge link_clk) if ( ~init_reg_d1) | |
503 | curr_state <= next_state; | |
504 | ||
505 | always@(negedge link_clk) if ( ~init_reg_d1) | |
506 | begin | |
507 | reset_sync=0; | |
508 | //curr_state = next_state; | |
509 | case(curr_state) | |
510 | `TRANSFER_0: begin | |
511 | calc_FE_latch_reg= FE; | |
512 | Prev_Command_A_is_Sync = Curr_Command_A_is_Sync; | |
513 | ||
514 | if ( ps_map[6] == 0 ) begin // if f0=0 | |
515 | next_state = `TRANSFER_1; | |
516 | end | |
517 | if ( Write_Frame_Count[1:0] != 2'b0 ) // Means in the middle of 4 consecutive wr fr | |
518 | next_state = `TRANSFER_1; | |
519 | ||
520 | if ( ps_map[6] == 1 ) | |
521 | next_state = `TRANSFER_1; | |
522 | ||
523 | {aE[0],aE[7],aE[8],F[0],aC[20],aC[16],aC[12],aC[8],aC[4],aC[0]} = ps_map[9:0]; | |
524 | tmpWS=ps_map[6]; // get F0 | |
525 | command_C_rdy = 0; | |
526 | {Command_26[24],Command_26[23],Command_26[16],Command_26[15],Command_26[8],Command_26[7],Command_26[0]}=ps_map[6:0]; | |
527 | ||
528 | if ( failover_sb ) | |
529 | {FE[3],FE[4]}={ps_map[8],ps_map[7]}; | |
530 | else | |
531 | {FE[0],FE[7],FE[8]}={ps_map[9],ps_map[8],ps_map[7]}; | |
532 | ||
533 | { frmdata_4[11], frmdata_3[11], frmdata_2[11], frmdata_1[11], frmdata_0[11]} = ps_map[4:0]; | |
534 | { frmdata_9[11], frmdata_8[11], frmdata_7[11], frmdata_6[11], frmdata_5[11]} = ps_map[9:5]; | |
535 | ||
536 | end | |
537 | `TRANSFER_1: begin | |
538 | next_state = `TRANSFER_2; | |
539 | {aE[1],aE[6],aE[9],F[1],aC[21],aC[17],aC[13],aC[9],aC[5],aC[1]} = ps_map[9:0]; | |
540 | ||
541 | if ( failover_sb ) | |
542 | {FE[2],FE[5]}={ps_map[8],ps_map[7]}; | |
543 | else | |
544 | {FE[1],FE[6],FE[9]}={ps_map[9],ps_map[8],ps_map[7]}; | |
545 | ||
546 | {Command_26[25],Command_26[22],Command_26[17],Command_26[14],Command_26[9],Command_26[6],Command_26[1]}=ps_map[6:0]; | |
547 | ||
548 | if ( ps_map[6] == 0 ) begin // if f1=0 , then command frame | |
549 | end | |
550 | if ( ps_map[6] == 1 ) begin // if f1=1 | |
551 | WS_tmp[3:0] = {tmpWS,WS_tmp[3:1]}; | |
552 | Write_Frame_Reg = 1; | |
553 | end | |
554 | ||
555 | ||
556 | { frmdata_4[10], frmdata_3[10], frmdata_2[10], frmdata_1[10], frmdata_0[10]} = ps_map[4:0]; | |
557 | { frmdata_9[10], frmdata_8[10], frmdata_7[10], frmdata_6[10], frmdata_5[10]} = ps_map[9:5]; | |
558 | ||
559 | end | |
560 | `TRANSFER_2: begin | |
561 | Write_Frame_Reg = 0; | |
562 | next_state = `TRANSFER_3; | |
563 | {Command_26[21],Command_26[18],Command_26[13],Command_26[10],Command_26[5],Command_26[2]}=ps_map[5:0]; | |
564 | ||
565 | {aE[2],aE[5],aE[10],aE[13],aC[22],aC[18],aC[14],aC[10],aC[6],aC[2]} = ps_map[9:0]; | |
566 | ||
567 | if ( failover_sb ) | |
568 | {FE[1],FE[6],FE[9]}={ps_map[8],ps_map[7],ps_map[6]}; | |
569 | else | |
570 | {FE[2],FE[5],FE[10],FE[13]}={ps_map[9],ps_map[8],ps_map[7],ps_map[6]}; | |
571 | ||
572 | { frmdata_4[9], frmdata_3[9], frmdata_2[9], frmdata_1[9], frmdata_0[9]} = ps_map[4:0]; | |
573 | { frmdata_9[9], frmdata_8[9], frmdata_7[9], frmdata_6[9], frmdata_5[9]} = ps_map[9:5]; | |
574 | ||
575 | end | |
576 | `TRANSFER_3: begin | |
577 | next_state = `TRANSFER_4; | |
578 | {aE[3],aE[4],aE[11],aE[12],aC[23],aC[19],aC[15],aC[11],aC[7],aC[3]} = ps_map[9:0]; | |
579 | {Command_26[20],Command_26[19],Command_26[12],Command_26[11],Command_26[4],Command_26[3]}=ps_map[5:0]; | |
580 | ||
581 | if ( failover_sb ) | |
582 | {FE[0],FE[7],FE[8]}={ps_map[8],ps_map[7],ps_map[6]}; | |
583 | else | |
584 | {FE[3],FE[4],FE[11],FE[12]}={ps_map[9],ps_map[8],ps_map[7],ps_map[6]}; | |
585 | command_A_rdy = 1; | |
586 | if ( aC[20:14] == 6'h1) | |
587 | Curr_Command_A_is_Sync=1; | |
588 | else | |
589 | Curr_Command_A_is_Sync=0; | |
590 | ||
591 | ||
592 | sync_cmd_rdy=1; | |
593 | { frmdata_4[8], frmdata_3[8], frmdata_2[8], frmdata_1[8], frmdata_0[8]} = ps_map[4:0]; | |
594 | { frmdata_9[8], frmdata_8[8], frmdata_7[8], frmdata_6[8], frmdata_5[8]} = ps_map[9:5]; | |
595 | ||
596 | end | |
597 | `TRANSFER_4: begin | |
598 | next_state = `TRANSFER_5; | |
599 | FE[21]=ps_map[9]; | |
600 | {bC[20],bC[16],bC[12],bC[8],bC[4],bC[0]}=ps_map[5:0]; | |
601 | WDATA[8:0]=ps_map[8:0]; | |
602 | cmd_B[0] = ps_map[8:6]; | |
603 | command_A_rdy = 0; | |
604 | sync_cmd_rdy=0; | |
605 | Data_72[8:0]=ps_map[8:0]; | |
606 | calc_aE_reg=calc_aE; | |
607 | { frmdata_4[3], frmdata_3[3], frmdata_2[3], frmdata_1[3], frmdata_0[3]} = ps_map[4:0]; | |
608 | { frmdata_9[3], frmdata_8[3], frmdata_7[3], frmdata_6[3], frmdata_5[3]} = ps_map[9:5]; | |
609 | ||
610 | end | |
611 | `TRANSFER_5: begin | |
612 | next_state = `TRANSFER_6; | |
613 | FE[20]=ps_map[9]; | |
614 | {bC[21],bC[17],bC[13],bC[9],bC[5],bC[1]}=ps_map[5:0]; | |
615 | cmd_B[1] = ps_map[8:6]; | |
616 | WDATA[17:9]=ps_map[8:0]; | |
617 | Data_72[17:9]={ps_map[0],ps_map[1],ps_map[2],ps_map[3],ps_map[4],ps_map[5],ps_map[6],ps_map[7],ps_map[8]}; | |
618 | { frmdata_4[2], frmdata_3[2], frmdata_2[2], frmdata_1[2], frmdata_0[2]} = ps_map[4:0]; | |
619 | { frmdata_9[2], frmdata_8[2], frmdata_7[2], frmdata_6[2], frmdata_5[2]} = ps_map[9:5]; | |
620 | end | |
621 | `TRANSFER_6: begin | |
622 | next_state = `TRANSFER_7; | |
623 | FE[19]=ps_map[9]; | |
624 | {bC[22],bC[18],bC[14],bC[10],bC[6],bC[2]}=ps_map[5:0]; | |
625 | WDATA[26:18]=ps_map[8:0]; | |
626 | cmd_B[2] = ps_map[8:6]; | |
627 | Data_72[26:18]=ps_map[8:0]; | |
628 | { frmdata_4[1], frmdata_3[1], frmdata_2[1], frmdata_1[1], frmdata_0[1]} = ps_map[4:0]; | |
629 | { frmdata_9[1], frmdata_8[1], frmdata_7[1], frmdata_6[1], frmdata_5[1]} = ps_map[9:5]; | |
630 | ||
631 | end | |
632 | `TRANSFER_7: begin | |
633 | next_state = `TRANSFER_8; | |
634 | FE[18]=ps_map[9]; | |
635 | {bC[23],bC[19],bC[15],bC[11],bC[7],bC[3]}=ps_map[5:0]; | |
636 | if ( (cmd_B[0] == 3'h0 ) && | |
637 | (cmd_B[1] == 3'h0 ) && | |
638 | (cmd_B[2] == 3'h0 ) && | |
639 | (ps_map[8:6] == 3'h0 ) && (F[1:0] == 2'h0 )) begin | |
640 | command_B_rdy = 1; | |
641 | end | |
642 | ||
643 | Data_72[35:27]={ps_map[0],ps_map[1],ps_map[2],ps_map[3],ps_map[4],ps_map[5],ps_map[6],ps_map[7],ps_map[8]}; | |
644 | WDATA[35:27]=ps_map[8:0]; | |
645 | { frmdata_4[0], frmdata_3[0], frmdata_2[0], frmdata_1[0], frmdata_0[0]} = ps_map[4:0]; | |
646 | { frmdata_9[0], frmdata_8[0], frmdata_7[0], frmdata_6[0], frmdata_5[0]} = ps_map[9:5]; | |
647 | ||
648 | end | |
649 | `TRANSFER_8: begin | |
650 | next_state = `TRANSFER_9; | |
651 | FE[17]=ps_map[9]; | |
652 | command_B_rdy = 0; | |
653 | {cC[20],cC[16],cC[12],cC[8],cC[4],cC[0]}=ps_map[5:0]; | |
654 | {BE[0],D[28],D[24],D[20],D[16],D[12],D[8],D[4],D[0]}=ps_map[8:0]; | |
655 | cmd_C[0]=ps_map[8:6]; | |
656 | WDATA[44:36]=ps_map[8:0]; | |
657 | Data_72[44:36]=ps_map[8:0]; | |
658 | { frmdata_4[7], frmdata_3[7], frmdata_2[7], frmdata_1[7], frmdata_0[7]} = ps_map[4:0]; | |
659 | { frmdata_9[7], frmdata_8[7], frmdata_7[7], frmdata_6[7], frmdata_5[7]} = ps_map[9:5]; | |
660 | ||
661 | end | |
662 | `TRANSFER_9: begin | |
663 | next_state = `TRANSFER_10; | |
664 | FE[16]=ps_map[9]; | |
665 | {cC[21],cC[17],cC[13],cC[9],cC[5],cC[1]}=ps_map[5:0]; | |
666 | {BE[1],D[29],D[25],D[21],D[17],D[13],D[9],D[5],D[1]}=ps_map[8:0]; | |
667 | WDATA[53:45]=ps_map[8:0]; | |
668 | cmd_C[1]=ps_map[8:6]; | |
669 | Data_72[53:45]={ps_map[0],ps_map[1],ps_map[2],ps_map[3],ps_map[4],ps_map[5],ps_map[6],ps_map[7],ps_map[8]}; | |
670 | { frmdata_4[6], frmdata_3[6], frmdata_2[6], frmdata_1[6], frmdata_0[6]} = ps_map[4:0]; | |
671 | { frmdata_9[6], frmdata_8[6], frmdata_7[6], frmdata_6[6], frmdata_5[6]} = ps_map[9:5]; | |
672 | ||
673 | end | |
674 | `TRANSFER_10: begin | |
675 | next_state = `TRANSFER_11; | |
676 | FE[15]=ps_map[9]; | |
677 | {cC[22],cC[18],cC[14],cC[10],cC[6],cC[2]}=ps_map[5:0]; | |
678 | {BE[2],D[30],D[26],D[22],D[18],D[14],D[10],D[6],D[2]}=ps_map[8:0]; | |
679 | WDATA[62:54]=ps_map[8:0]; | |
680 | cmd_C[2]=ps_map[8:6]; | |
681 | Data_72[62:54]=ps_map[8:0]; | |
682 | ||
683 | { frmdata_4[5], frmdata_3[5], frmdata_2[5], frmdata_1[5], frmdata_0[5]} = ps_map[4:0]; | |
684 | { frmdata_9[5], frmdata_8[5], frmdata_7[5], frmdata_6[5], frmdata_5[5]} = ps_map[9:5]; | |
685 | ||
686 | end | |
687 | `TRANSFER_11: begin | |
688 | next_state = `TRANSFER_0; | |
689 | FE[14]=ps_map[9]; | |
690 | {cC[23],cC[19],cC[15],cC[11],cC[7],cC[3]}=ps_map[5:0]; | |
691 | {BE[3],D[31],D[27],D[23],D[19],D[15],D[11],D[7],D[3]}=ps_map[8:0]; | |
692 | WDATA[71:63]=ps_map[8:0]; | |
693 | Write_Frame_Reg = 0; | |
694 | if ( (cmd_C[0] == 3'h0 ) && | |
695 | (cmd_C[1] == 3'h0 ) && | |
696 | (cmd_C[2] == 3'h0 ) && | |
697 | (ps_map[8:6] == 3'h0 ) && (F[1:0] == 2'h0) ) begin | |
698 | command_C_rdy = 1; | |
699 | end | |
700 | WS=WS_tmp[2:0]; | |
701 | ||
702 | Write_Frame_Count[1:0] = Write_Frame_Count[1:0] + 2'b1; | |
703 | Data_72[71:63]={ps_map[0],ps_map[1],ps_map[2],ps_map[3],ps_map[4],ps_map[5],ps_map[6],ps_map[7],ps_map[8]}; | |
704 | ||
705 | { frmdata_4[4], frmdata_3[4], frmdata_2[4], frmdata_1[4], frmdata_0[4]} = ps_map[4:0]; | |
706 | { frmdata_9[4], frmdata_8[4], frmdata_7[4], frmdata_6[4], frmdata_5[4]} = ps_map[9:5]; | |
707 | ||
708 | `ifdef AXIS_FBDIMM_HW | |
709 | `else | |
710 | /* if ( !sb_crc_error ) begin | |
711 | register_memory[{3'b001,8'hae}]=frmdata_0; | |
712 | register_memory[{3'b001,8'hac}]=frmdata_1; | |
713 | register_memory[{3'b001,8'haa}]=frmdata_2; | |
714 | register_memory[{3'b001,8'ha8}]=frmdata_3; | |
715 | register_memory[{3'b001,8'ha6}]=frmdata_4; | |
716 | register_memory[{3'b001,8'ha4}]=frmdata_5; | |
717 | register_memory[{3'b001,8'ha2}]=frmdata_6; | |
718 | register_memory[{3'b001,8'ha0}]=frmdata_7; | |
719 | register_memory[{3'b001,8'h9e}]=frmdata_8; | |
720 | register_memory[{3'b001,8'h9c}]=frmdata_9; | |
721 | register_memory[{3'b001,8'hae}]=frmdata_10; | |
722 | end | |
723 | */ | |
724 | `endif | |
725 | ||
726 | ||
727 | ||
728 | end | |
729 | default: $display("unknown state"); | |
730 | endcase | |
731 | ||
732 | ||
733 | end else begin | |
734 | command_A_rdy = 1'b0; | |
735 | command_B_rdy = 1'b0; | |
736 | command_C_rdy = 1'b0; | |
737 | curr_state = `TRANSFER_0; | |
738 | next_state = `TRANSFER_0; | |
739 | end | |
740 | ||
741 | ||
742 | always@(posedge link_clk) if (( curr_state == `TRANSFER_11 ) && ~init_reg_d1 ) | |
743 | begin | |
744 | ||
745 | // CRC checks | |
746 | // if TestaE[n] !== aE[n] | |
747 | ||
748 | Test_aE[13:0] = {FE_latch[13] ^ aE[13], | |
749 | FE_latch[12] ^ aE[12], | |
750 | FE_latch[11] ^ aE[11], | |
751 | FE_latch[10] ^ aE[10], | |
752 | FE_latch[09] ^ aE[09], | |
753 | FE_latch[08] ^ aE[08], | |
754 | FE_latch[07] ^ aE[07], | |
755 | FE_latch[06] ^ aE[06], | |
756 | FE_latch[05] ^ aE[05], | |
757 | FE_latch[04] ^ aE[04], | |
758 | FE_latch[03] ^ aE[03], | |
759 | FE_latch[02] ^ aE[02], | |
760 | FE_latch[01] ^ aE[01], | |
761 | FE_latch[00] ^ aE[00]}; | |
762 | ||
763 | if (!failover_sb) | |
764 | if ( !Prev_Command_A_is_Sync ) | |
765 | if ( ((FE_latch[13] ^ aE[13]) !== CRC14[13] ) || | |
766 | ((FE_latch[12] ^ aE[12]) !== CRC14[12] ) || | |
767 | ((FE_latch[11] ^ aE[11]) !== CRC14[11] ) || | |
768 | ((FE_latch[10] ^ aE[10]) !== CRC14[10] ) || | |
769 | ((FE_latch[09] ^ aE[09]) !== CRC14[09] ) || | |
770 | ((FE_latch[08] ^ aE[08]) !== CRC14[08] ) || | |
771 | ((FE_latch[07] ^ aE[07]) !== CRC14[07] ) || | |
772 | ((FE_latch[06] ^ aE[06]) !== CRC14[06] ) || | |
773 | ((FE_latch[05] ^ aE[05]) !== CRC14[05] ) || | |
774 | ((FE_latch[04] ^ aE[04]) !== CRC14[04] ) || | |
775 | ((FE_latch[03] ^ aE[03]) !== CRC14[03] ) || | |
776 | ((FE_latch[02] ^ aE[02]) !== CRC14[02] ) || | |
777 | ((FE_latch[01] ^ aE[01]) !== CRC14[01] ) || | |
778 | ((FE_latch[00] ^ aE[00]) !== CRC14[00] ) | |
779 | ) | |
780 | begin | |
781 | `ifdef AXIS_FBDIMM_HW | |
782 | `else | |
783 | `PR_ALWAYS ("ch_mon",`DBG_1,"ERROR: Command has CRC mismatch => Test_aE %h != aE %h \n",Test_aE,CRC14); | |
784 | `endif | |
785 | sb_crc_error_reg=1; | |
786 | end | |
787 | else if ( sync_detected_reg || soft_channel_reset ) | |
788 | sb_crc_error_reg=0; | |
789 | ||
790 | ||
791 | if (failover_sb) | |
792 | if ( !Prev_Command_A_is_Sync ) | |
793 | if ( ((FE_latch[13] ^ aE[13]) !== CRC10_cmd_failover[09] ) || | |
794 | ((FE_latch[12] ^ aE[12]) !== CRC10_cmd_failover[08] ) || | |
795 | ((FE_latch[11] ^ aE[11]) !== CRC10_cmd_failover[07] ) || | |
796 | ((FE_latch[10] ^ aE[10]) !== CRC10_cmd_failover[06] ) || | |
797 | ((FE_latch[09] ^ aE[09]) !== CRC10_cmd_failover[05] ) || | |
798 | ((FE_latch[08] ^ aE[08]) !== CRC10_cmd_failover[04] ) || | |
799 | ((FE_latch[07] ^ aE[07]) !== CRC10_cmd_failover[03] ) || | |
800 | ((FE_latch[06] ^ aE[06]) !== CRC10_cmd_failover[02] ) || | |
801 | ((FE_latch[05] ^ aE[05]) !== CRC10_cmd_failover[01] ) || | |
802 | ((FE_latch[04] ^ aE[04]) !== CRC10_cmd_failover[00] ) | |
803 | ) | |
804 | begin | |
805 | `ifdef AXIS_FBDIMM_HW | |
806 | `else | |
807 | `PR_ALWAYS ("ch_mon",`DBG_1,"ERROR: Failover mode: Command has CRC mismatch => FE_Latch %h ^ aE %h != CRC10_cmd_failover = %h \n",FE_latch[13:4],aE[13:4],CRC10_cmd_failover); | |
808 | `endif | |
809 | sb_crc_error_reg=1; | |
810 | end | |
811 | else if ( sync_detected_reg || soft_channel_reset ) | |
812 | sb_crc_error_reg=0; | |
813 | ||
814 | if ( failover_sb ) | |
815 | Test1_FE[13:0] = {CRC10_cmd_failover[09] ^ aE[13], | |
816 | CRC10_cmd_failover[08] ^ aE[12], | |
817 | CRC10_cmd_failover[07] ^ aE[11], | |
818 | CRC10_cmd_failover[06] ^ aE[10], | |
819 | CRC10_cmd_failover[05] ^ aE[09], | |
820 | CRC10_cmd_failover[04] ^ aE[08], | |
821 | CRC10_cmd_failover[03] ^ aE[07], | |
822 | CRC10_cmd_failover[02] ^ aE[06], | |
823 | CRC10_cmd_failover[01] ^ aE[05], | |
824 | CRC10_cmd_failover[00] ^ aE[04], | |
825 | 1'b0, | |
826 | 1'b0, | |
827 | 1'b0, | |
828 | 1'b0}; | |
829 | else | |
830 | Test1_FE[13:0] = {CRC14[13] ^ aE[13], | |
831 | CRC14[12] ^ aE[12], | |
832 | CRC14[11] ^ aE[11], | |
833 | CRC14[10] ^ aE[10], | |
834 | CRC14[09] ^ aE[09], | |
835 | CRC14[08] ^ aE[08], | |
836 | CRC14[07] ^ aE[07], | |
837 | CRC14[06] ^ aE[06], | |
838 | CRC14[05] ^ aE[05], | |
839 | CRC14[04] ^ aE[04], | |
840 | CRC14[03] ^ aE[03], | |
841 | CRC14[02] ^ aE[02], | |
842 | CRC14[01] ^ aE[01], | |
843 | CRC14[00] ^ aE[00]}; | |
844 | ||
845 | ||
846 | if ( !failover_sb ) | |
847 | if ( !Prev_Command_A_is_Sync ) | |
848 | if ( ((CRC14[13] ^ aE[13]) !== FE_latch[13] ) || | |
849 | ((CRC14[12] ^ aE[12]) !== FE_latch[12] ) || | |
850 | ((CRC14[11] ^ aE[11]) !== FE_latch[11] ) || | |
851 | ((CRC14[10] ^ aE[10]) !== FE_latch[10] ) || | |
852 | ((CRC14[09] ^ aE[09]) !== FE_latch[09] ) || | |
853 | ((CRC14[08] ^ aE[08]) !== FE_latch[08] ) || | |
854 | ((CRC14[07] ^ aE[07]) !== FE_latch[07] ) || | |
855 | ((CRC14[06] ^ aE[06]) !== FE_latch[06] ) || | |
856 | ((CRC14[05] ^ aE[05]) !== FE_latch[05] ) || | |
857 | ((CRC14[04] ^ aE[04]) !== FE_latch[04] ) || | |
858 | ((CRC14[03] ^ aE[03]) !== FE_latch[03] ) || | |
859 | ((CRC14[02] ^ aE[02]) !== FE_latch[02] ) || | |
860 | ((CRC14[01] ^ aE[01]) !== FE_latch[01] ) || | |
861 | ((CRC14[00] ^ aE[00]) !== FE_latch[00] ) ) | |
862 | begin | |
863 | `PR_ALWAYS ("ch_mon",`DBG_1,"ERROR: Data has CRC mismatch Test1_FE = %h != FE = %h\n",Test1_FE,FE_latch); | |
864 | sb_crc_error_reg=1; | |
865 | end | |
866 | else if ( sync_detected_reg || soft_channel_reset ) | |
867 | sb_crc_error_reg=0; | |
868 | ||
869 | ||
870 | if ( failover_sb ) | |
871 | if ( !Prev_Command_A_is_Sync ) | |
872 | if ( ((CRC10_cmd_failover[09] ^ aE[13]) !== FE_latch[13] ) || | |
873 | ((CRC10_cmd_failover[08] ^ aE[12]) !== FE_latch[12] ) || | |
874 | ((CRC10_cmd_failover[07] ^ aE[11]) !== FE_latch[11] ) || | |
875 | ((CRC10_cmd_failover[06] ^ aE[10]) !== FE_latch[10] ) || | |
876 | ((CRC10_cmd_failover[05] ^ aE[09]) !== FE_latch[09] ) || | |
877 | ((CRC10_cmd_failover[04] ^ aE[08]) !== FE_latch[08] ) || | |
878 | ((CRC10_cmd_failover[03] ^ aE[07]) !== FE_latch[07] ) || | |
879 | ((CRC10_cmd_failover[02] ^ aE[06]) !== FE_latch[06] ) || | |
880 | ((CRC10_cmd_failover[01] ^ aE[05]) !== FE_latch[05] ) || | |
881 | ((CRC10_cmd_failover[00] ^ aE[04]) !== FE_latch[04] ) ) | |
882 | begin | |
883 | `PR_ALWAYS ("ch_mon",`DBG_1,"ERROR: Failover mode: Data has CRC mismatch Test1_FE = %h != FE = %h\n",Test1_FE,FE_latch); | |
884 | sb_crc_error_reg=1; | |
885 | end | |
886 | else if ( sync_detected_reg || soft_channel_reset ) | |
887 | sb_crc_error_reg=0; | |
888 | ||
889 | // 10th bit lane carries pattern info for sync frames so we will not do this check for sycn frames | |
890 | ||
891 | if ( !failover_sb ) | |
892 | if ( !Curr_Command_A_is_Sync ) | |
893 | if ( FE[21:14] !== CRC22[21:14] ) begin | |
894 | `PR_ALWAYS ("ch_mon",`DBG_1,"ERROR: Data has CRC mismatch Test2_FE[21:14] = %h != CRC[21:14] = %h\n",FE[21:14], CRC22[21:14]); | |
895 | sb_crc_error_reg=1; | |
896 | end | |
897 | else if ( sync_detected_reg || soft_channel_reset ) | |
898 | sb_crc_error_reg=0; | |
899 | @(negedge link_clk); | |
900 | if ( failover_sb ) | |
901 | FE_latch = {CRC10_data_failover[9:0],4'h0}; | |
902 | else | |
903 | FE_latch = CRC22[13:0]; | |
904 | ||
905 | end | |
906 | else | |
907 | sb_crc_error_reg=0; | |
908 | ||
909 | ||
910 | // Channel Commands | |
911 | ||
912 | reg Write_Config_reg; | |
913 | wire Write_Config_reg_d1,Write_Config_reg_d2,Write_Config_reg_d3,Write_Config_reg_d4; | |
914 | reg [10:0] Write_Config_addr_reg; | |
915 | ||
916 | always@(posedge link_clk) | |
917 | begin | |
918 | ||
919 | // channel reset command | |
920 | if ( command_A_rdy && ( aC[20:18] == 3'b000 ) && ( aC[17:14] == 4'b0010) ) | |
921 | begin | |
922 | `ifdef AXIS_FBDIMM_HW | |
923 | `else | |
924 | `PR_ALWAYS ("ch_mon",`DBG_0,"Soft Channel Reset detected. Invalidating all write FIFOs"); | |
925 | `endif | |
926 | invalidate_Write_FIFO_reg=1; | |
927 | end | |
928 | else | |
929 | invalidate_Write_FIFO_reg=0; | |
930 | ||
931 | // write config command | |
932 | if ( command_B_rdy && ( bC[20:14] == 7'b0000101 ) && ( bC[12] == ~Last_TID ) ) | |
933 | begin | |
934 | `ifdef AXIS_FBDIMM_HW | |
935 | `else | |
936 | `PR_ALWAYS ("ch_mon",`DBG_0,"Write config register received : Function number %h Register Address %h",bC[10:8],bC[10:0]); | |
937 | `endif | |
938 | ||
939 | Last_TID=bC[12]; // update last tid | |
940 | Write_Config_reg=1; | |
941 | Write_Config_addr_reg=bC[10:0]; | |
942 | end | |
943 | else | |
944 | Write_Config_reg=0; | |
945 | ||
946 | ||
947 | // read config command | |
948 | if ( (command_A_rdy || command_B_rdy || command_C_rdy) && ( command_select[20:14] == 7'b0000100 ) ) | |
949 | begin | |
950 | `ifdef AXIS_FBDIMM_HW | |
951 | `else | |
952 | `PR_ALWAYS ("ch_mon",`DBG_0,"Read config register received : Function number %h Register Address %h Register data %h",command_select[10:8],command_select[7:2],register_memory[command_select[10:0]]); | |
953 | cfg_data=register_memory[command_select[10:0]]; | |
954 | `endif | |
955 | cfg_rd=1; | |
956 | end | |
957 | else | |
958 | cfg_rd=0; | |
959 | ||
960 | // sync command | |
961 | if ( sync_cmd_rdy && ( aC[20:18] == 3'b000 ) && ( aC[17:14] == 4'b0001) ) | |
962 | begin | |
963 | `ifdef AXIS_FBDIMM_HW | |
964 | `else | |
965 | `PR_ALWAYS ("ch_mon",`DBG_0,"Sync detected. sd=%h ier=%b erc=%b el0s=%b r1,r0=%h",aC[12:11],aC[6],aC[5],aC[4],aC[1:0]); | |
966 | `endif | |
967 | sync_detected_reg=1; | |
968 | first_sync_detected_reg <= 1; | |
969 | sync_cmd_data=aC; | |
970 | sync_counter_reg = 0; | |
971 | ||
972 | ||
973 | end | |
974 | else begin | |
975 | sync_detected_reg=0; | |
976 | sync_counter_reg = sync_counter_reg + 1; | |
977 | end | |
978 | ||
979 | end | |
980 | ||
981 | dff_p #(1) sync_delay1 (.signal_in ( first_sync_detected_reg ), | |
982 | .signal_out ( first_sync_detected_reg_d1), | |
983 | .clk (link_clk)); | |
984 | ||
985 | always@(negedge link_clk) | |
986 | begin | |
987 | if ( sync_detected_reg && first_sync_detected_reg_d1 /* && ( sync_interval_frm_count !== 0 ) */ ) begin | |
988 | if ( sync_interval_frm_count < (sync_train_interval_reg * 12 ) ) begin | |
989 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: Sync Train interval reg %d > sync_interval_frm_count %d \n",sync_train_interval_reg,sync_interval_frm_count); | |
990 | end | |
991 | sync_interval_frm_count = 0; | |
992 | end | |
993 | else if ( first_sync_detected_reg ) | |
994 | sync_interval_frm_count = sync_interval_frm_count + 1; | |
995 | ||
996 | end | |
997 | ||
998 | wire [31:0] wcfg_data ={WDATA[70],WDATA[61],WDATA[52],WDATA[43],WDATA[69],WDATA[60],WDATA[51],WDATA[42],WDATA[68],WDATA[59],WDATA[50],WDATA[41],WDATA[67],WDATA[58],WDATA[49],WDATA[40],WDATA[66],WDATA[57],WDATA[48],WDATA[39],WDATA[65],WDATA[56],WDATA[47],WDATA[38],WDATA[64],WDATA[55],WDATA[46],WDATA[37],WDATA[63],WDATA[54],WDATA[45],WDATA[36]}; | |
999 | // wire [31:0] wcfg_data; | |
1000 | ||
1001 | always@(posedge link_clk) | |
1002 | begin | |
1003 | if ( Write_Config_reg_d4 ) | |
1004 | begin | |
1005 | `ifdef AXIS_FBDIMM_HW | |
1006 | `else | |
1007 | register_memory[Write_Config_addr_reg]={WDATA[71:63],WDATA[62:54],WDATA[53:45],WDATA[44:36]}; | |
1008 | ||
1009 | register_memory[Write_Config_addr_reg]= wcfg_data; | |
1010 | `PR_ALWAYS ("ch_mon",`DBG_0,"Write config data: %h", wcfg_data); | |
1011 | ||
1012 | `endif | |
1013 | end | |
1014 | ||
1015 | end | |
1016 | ||
1017 | ||
1018 | /**************************************************************/ | |
1019 | ||
1020 | ||
1021 | ||
1022 | ||
1023 | always@(negedge link_clk) if ( ~init_reg_d1) | |
1024 | begin | |
1025 | sb_frame[0] = /*frame_complete ? {SB_LINK { 1'bz}} :*/ sb_frame[1]; | |
1026 | sb_frame[1] = sb_frame[2]; | |
1027 | sb_frame[2] = sb_frame[3]; | |
1028 | sb_frame[3] = sb_frame[4]; | |
1029 | sb_frame[4] = sb_frame[5]; | |
1030 | sb_frame[5] = sb_frame[6]; | |
1031 | sb_frame[6] = sb_frame[7]; | |
1032 | sb_frame[7] = sb_frame[8]; | |
1033 | sb_frame[8] = sb_frame[9]; | |
1034 | sb_frame[9] = sb_frame[10]; | |
1035 | sb_frame[10] = sb_frame[11]; | |
1036 | sb_frame[11] = ps_map; | |
1037 | ||
1038 | ||
1039 | end | |
1040 | ||
1041 | reg [9:0] ps0_reg,ps1_reg,ps2_reg,ps3_reg,ps4_reg,ps5_reg,ps6_reg,ps7_reg,ps8_reg,ps9_reg,ps10_reg,ps11_reg; | |
1042 | ||
1043 | assign ps0 = ps0_reg; | |
1044 | assign ps1 = ps1_reg; | |
1045 | assign ps2 = ps2_reg; | |
1046 | assign ps3 = ps3_reg; | |
1047 | assign ps4 = ps4_reg; | |
1048 | assign ps5 = ps5_reg; | |
1049 | assign ps6 = ps6_reg; | |
1050 | assign ps7 = ps7_reg; | |
1051 | assign ps8 = ps8_reg; | |
1052 | assign ps9 = ps9_reg; | |
1053 | assign ps10 = ps10_reg; | |
1054 | assign ps11 = ps11_reg; | |
1055 | ||
1056 | always@(negedge link_clk) | |
1057 | begin | |
1058 | ps0_reg <= ps1_reg; | |
1059 | ps1_reg <= ps2_reg; | |
1060 | ps2_reg <= ps3_reg; | |
1061 | ps3_reg <= ps4_reg; | |
1062 | ps4_reg <= ps5_reg; | |
1063 | ps5_reg <= ps6_reg; | |
1064 | ps6_reg <= ps7_reg; | |
1065 | ps7_reg <= ps8_reg; | |
1066 | ps8_reg <= ps9_reg; | |
1067 | ps9_reg <= ps10_reg; | |
1068 | ps10_reg <= ps11_reg; | |
1069 | ps11_reg <= ps_map; | |
1070 | ||
1071 | end | |
1072 | ||
1073 | initial begin | |
1074 | Last_TID=0; | |
1075 | sb_config = 4'hf; | |
1076 | nb_config = 4'hf; | |
1077 | first_sync_detected_reg = 0; | |
1078 | sync_cmd_rdy = 0; | |
1079 | sb_crc_error_reg=0; | |
1080 | ||
1081 | `ifdef STINGRAY | |
1082 | frame_cnt=5'hb; | |
1083 | `else | |
1084 | frame_cnt=0; | |
1085 | `endif | |
1086 | ||
1087 | nosync_framecount=0; | |
1088 | curr_state = `TRANSFER_0; | |
1089 | next_state = `TRANSFER_0; | |
1090 | ||
1091 | `ifdef STINGRAY | |
1092 | `else | |
1093 | $readmemh("fbdimm_register.data",register_memory); | |
1094 | `endif | |
1095 | if ( $test$plusargs("mapout_sb9") || | |
1096 | $test$plusargs("mapout_sb8") || | |
1097 | $test$plusargs("mapout_sb7") || | |
1098 | $test$plusargs("mapout_sb6") || | |
1099 | $test$plusargs("mapout_sb5") || | |
1100 | $test$plusargs("mapout_sb4") || | |
1101 | $test$plusargs("mapout_sb3") || | |
1102 | $test$plusargs("mapout_sb2") || | |
1103 | $test$plusargs("mapout_sb1") || | |
1104 | $test$plusargs("mapout_sb0") | |
1105 | ) | |
1106 | failover_sb = 1; | |
1107 | else | |
1108 | failover_sb = 0; | |
1109 | ||
1110 | if ( $test$plusargs("bypass_init")) | |
1111 | lock_counter = 4'h1; | |
1112 | else | |
1113 | lock_counter= 4'h2; | |
1114 | ||
1115 | lock_counter2=4'h1; | |
1116 | nb_lock_counter = 4'h1; | |
1117 | ||
1118 | if ( $test$plusargs("mapout_sb9")) | |
1119 | sb_config = 4'b1001; | |
1120 | if ( $test$plusargs("mapout_sb8")) | |
1121 | sb_config = 4'b1000; | |
1122 | if ( $test$plusargs("mapout_sb7")) | |
1123 | sb_config = 4'b0111; | |
1124 | if ( $test$plusargs("mapout_sb6")) | |
1125 | sb_config = 4'b0110; | |
1126 | if ( $test$plusargs("mapout_sb5")) | |
1127 | sb_config = 4'b0101; | |
1128 | if ( $test$plusargs("mapout_sb4")) | |
1129 | sb_config = 4'b0100; | |
1130 | if ( $test$plusargs("mapout_sb3")) | |
1131 | sb_config = 4'b0011; | |
1132 | if ( $test$plusargs("mapout_sb2")) | |
1133 | sb_config = 4'b0010; | |
1134 | if ( $test$plusargs("mapout_sb1")) | |
1135 | sb_config = 4'b0001; | |
1136 | if ( $test$plusargs("mapout_sb0")) | |
1137 | sb_config = 4'b0000; | |
1138 | ||
1139 | if ( $test$plusargs("fbdimm_dbg_0")) // || $test$plusargs("fbdimm_dbg") ) | |
1140 | $ch_dispmon("ch_mon",`DBG_0,1); | |
1141 | ||
1142 | if ( $test$plusargs("fbdimm_dbg_1")) | |
1143 | $ch_dispmon("ch_mon",`DBG_1,1); | |
1144 | ||
1145 | if ( $test$plusargs("fbdimm_dbg_2")) | |
1146 | $ch_dispmon("ch_mon",`DBG_2,1); | |
1147 | ||
1148 | if ( $test$plusargs("fbdimm_dbg_3")) | |
1149 | $ch_dispmon("ch_mon",`DBG_3,1); | |
1150 | ||
1151 | if ( $test$plusargs("fbdimm_dbg_4")) | |
1152 | $ch_dispmon("ch_mon",`DBG_4,1); | |
1153 | ||
1154 | ||
1155 | ||
1156 | if($test$plusargs("fbdimm_nb_failover_14bit")) | |
1157 | failover_nb_14=1; | |
1158 | else | |
1159 | failover_nb_14=0; | |
1160 | ||
1161 | if($test$plusargs("fbdimm_nb_failover_13bit")) | |
1162 | failover_nb_13=1; | |
1163 | else | |
1164 | failover_nb_13=0; | |
1165 | ||
1166 | ||
1167 | if($test$plusargs("fbdimm_nb_12bit")) | |
1168 | nb_12=1; | |
1169 | else | |
1170 | nb_12=0; | |
1171 | ||
1172 | if ( $test$plusargs("bypass_init") ) begin | |
1173 | init_reg = 0; | |
1174 | bypass_init=1; | |
1175 | end | |
1176 | else | |
1177 | bypass_init=0; | |
1178 | ||
1179 | end | |
1180 | ||
1181 | always@(posedge link_clk) if ( ~init_reg_d1) | |
1182 | begin | |
1183 | if ( (ps_map == { SB_LINK { 1'bx} } ) || | |
1184 | ( ps_map == { SB_LINK { 1'bz} } ) ) | |
1185 | begin | |
1186 | frame_cnt=0; | |
1187 | end | |
1188 | else if ( frame_cnt == 5'hb ) begin | |
1189 | frame_cnt=0; | |
1190 | frame_complete=1; end | |
1191 | else begin | |
1192 | frame_cnt=frame_cnt+1; | |
1193 | frame_complete=0; end | |
1194 | ||
1195 | end | |
1196 | ||
1197 | ||
1198 | always@(posedge link_clk) if ( ~init_reg_d1) begin | |
1199 | ||
1200 | ||
1201 | if ( (sb_cmd_rdy_reg[2] && (sb_cmd_type_reg[14:10] == `CMD_RCFG )) || | |
1202 | (sb_cmd_rdy_reg[2] && (sb_cmd_type_reg[14:10] == `CMD_WCFG )) ) | |
1203 | begin | |
1204 | if ( config_reg_cmd_latency_count <= 24 ) // 2 frames | |
1205 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: Multiple rd=wr config commands present!"); | |
1206 | pending_config_reg_cmd=1; | |
1207 | config_reg_cmd_latency_count = 0 ; | |
1208 | end | |
1209 | else if ( (sb_cmd_rdy_reg[1] && (sb_cmd_type_reg[9:5] == `CMD_RCFG )) || | |
1210 | (sb_cmd_rdy_reg[1] && (sb_cmd_type_reg[9:5] == `CMD_WCFG )) ) | |
1211 | begin | |
1212 | if ( config_reg_cmd_latency_count <= 24 ) // 2 frames | |
1213 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: Multiple rd=wr config commands present!"); | |
1214 | pending_config_reg_cmd=1; | |
1215 | config_reg_cmd_latency_count = 0 ; | |
1216 | end | |
1217 | else if ( (sb_cmd_rdy_reg[0] && (sb_cmd_type_reg[4:0] == `CMD_RCFG )) || | |
1218 | (sb_cmd_rdy_reg[0] && (sb_cmd_type_reg[4:0] == `CMD_WCFG )) ) | |
1219 | begin | |
1220 | if ( config_reg_cmd_latency_count <= 24 ) // 2 frames | |
1221 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: Multiple rd=wr config commands present!"); | |
1222 | pending_config_reg_cmd=1; | |
1223 | config_reg_cmd_latency_count = 0 ; | |
1224 | end | |
1225 | else | |
1226 | config_reg_cmd_latency_count = config_reg_cmd_latency_count + 1; | |
1227 | ||
1228 | end | |
1229 | ||
1230 | // AMB registers | |
1231 | ||
1232 | //----ADDED BY SWATI--- | |
1233 | // Auto-refresh assertion. | |
1234 | reg detected_sync_cmd=0; | |
1235 | reg auto_refresh_bit_in_fsm=0; | |
1236 | reg [15:0] dram_autorefresh_count=0; | |
1237 | wire [31:0] fbdreg_dareftc = register_memory[{3'b011,8'h70}]; // function 3, offset 70h pg 119 | |
1238 | wire [31:0] fbdreg_synctrainint = register_memory[{3'b001,8'h78}]; // function 1, offset 78h pg 103 | |
1239 | wire [7:0] autorefresh_period =fbdreg_dareftc[23:16]; | |
1240 | wire [14:0] autorefresh_interval =fbdreg_dareftc[14:0]; | |
1241 | reg [8:0] autoref_reg_write = 0; | |
1242 | // The moment the autorefresh reg is written the autorefresh_count should be set to 0 | |
1243 | //reg [14:0] autorefresh_interval =3120; | |
1244 | //reg [7:0] autorefresh_period =78; | |
1245 | ||
1246 | always@(posedge dram_clk) | |
1247 | begin | |
1248 | dram_autorefresh_count=dram_autorefresh_count+1; | |
1249 | //$display("\ndram_autorefresh_count = %d\n",dram_autorefresh_count); | |
1250 | //$display("\nautorefresh_interval = %d\n",autorefresh_interval); | |
1251 | if ( detected_autorefresh_cmd == 1 || autoref_write_reg == 1) | |
1252 | begin | |
1253 | dram_autorefresh_count=0; | |
1254 | autoref_write_reg = 0; | |
1255 | detected_autorefresh_cmd = 0; | |
1256 | end | |
1257 | else if( (dram_autorefresh_count == autorefresh_period) ) | |
1258 | begin | |
1259 | `PR_ALWAYS ("ch_mon",`DBG_0,"WARNING: Auto Refresh Cmd has not been sent for auto-refresh period\n"); | |
1260 | end | |
1261 | else if( (dram_autorefresh_count > autorefresh_interval ) ) // The plus 1 is because | |
1262 | // The commands are known only in the next dram clock cycle | |
1263 | begin | |
1264 | if(!auto_refresh_bit_in_fsm) | |
1265 | begin | |
1266 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: Auto Refresh Cmd has not been sent for auto-refresh interval.\n"); | |
1267 | dram_autorefresh_count=0; | |
1268 | end | |
1269 | end | |
1270 | end | |
1271 | //----ADDED BY SWATI--- | |
1272 | ||
1273 | ||
1274 | ||
1275 | always@(posedge frame_complete) if ( ~init_reg_d1) | |
1276 | begin | |
1277 | ||
1278 | if ( ( sb_frame[0] !== { SB_LINK { 1'bz} } ) ) | |
1279 | if ( ( sb_frame[0] | sb_frame[1] | sb_frame[2] | sb_frame[3] | | |
1280 | sb_frame[4] | sb_frame[5] | sb_frame[6] | sb_frame[7] | | |
1281 | sb_frame[8] | sb_frame[9] | sb_frame[10] | sb_frame[11] )) | |
1282 | begin | |
1283 | ||
1284 | ||
1285 | `PR_ALWAYS ("ch_mon",`DBG_4,"----------SB PACKET----------"); | |
1286 | inbank_debug_count=0; | |
1287 | C1 = sb_frame[0]; | |
1288 | C2 = sb_frame[1]; | |
1289 | C3 = sb_frame[2]; | |
1290 | C4 = sb_frame[3]; | |
1291 | F0 = C1[6]; | |
1292 | F1 = C2[6]; | |
1293 | Command[23:0] = { C4[5],C3[5],C2[5],C1[5], | |
1294 | C4[4],C3[4],C2[4],C1[4], | |
1295 | C4[3],C3[3],C2[3],C1[3], | |
1296 | C4[2],C3[2],C2[2],C1[2], | |
1297 | C4[1],C3[1],C2[1],C1[1], | |
1298 | C4[0],C3[0],C2[0],C1[0]}; | |
1299 | sb_cmd_rdy_reg[2] = 1; | |
1300 | sb_cmd_encoding_reg[71:48]=Command[23:0]; | |
1301 | sb_cmd_ds_reg[8:6]= Command[23:21]; | |
1302 | ||
1303 | if (( Command[17:13] == 5'h1f ) && !F1 )begin | |
1304 | inbank_debug_count=inbank_debug_count+1; | |
1305 | end | |
1306 | ||
1307 | if ( Command[20] && ( ( !F0 && !F1) || F1 ) ) begin | |
1308 | `PR_ALWAYS ("ch_mon",`DBG_0,"Command A: ACTIVATE"); | |
1309 | sb_cmd_type_reg[14:10] = `CMD_ACT; | |
1310 | end | |
1311 | else begin | |
1312 | `PR_ALWAYS ("ch_mon",`DBG_4,"Transfer[0] = %h\n",sb_frame[0]); | |
1313 | `PR_ALWAYS ("ch_mon",`DBG_4,"Transfer[1] = %h\n",sb_frame[1]); | |
1314 | `PR_ALWAYS ("ch_mon",`DBG_4,"Transfer[2] = %h\n",sb_frame[2]); | |
1315 | `PR_ALWAYS ("ch_mon",`DBG_4,"Transfer[3] = %h\n",sb_frame[3]); | |
1316 | end | |
1317 | ||
1318 | sb_cmd_rdy_reg[1] = 1; | |
1319 | sb_cmd_encoding_reg[47:24]=Command[23:0]; | |
1320 | sb_cmd_ds_reg[5:3]= Command[23:21]; | |
1321 | if ( F1 & !F0) begin | |
1322 | `PR_ALWAYS ("ch_mon",`DBG_0,"Command B: DATA"); | |
1323 | `PR_ALWAYS ("ch_mon",`DBG_0,"Command C: DATA"); | |
1324 | end | |
1325 | else begin | |
1326 | C1 = sb_frame[4]; | |
1327 | C2 = sb_frame[5]; | |
1328 | C3 = sb_frame[6]; | |
1329 | C4 = sb_frame[7]; | |
1330 | Command[23:0] = { C4[5],C3[5],C2[5],C1[5], | |
1331 | C4[4],C3[4],C2[4],C1[4], | |
1332 | C4[3],C3[3],C2[3],C1[3], | |
1333 | C4[2],C3[2],C2[2],C1[2], | |
1334 | C4[1],C3[1],C2[1],C1[1], | |
1335 | C4[0],C3[0],C2[0],C1[0]}; | |
1336 | if (( Command[17:13] == 5'h1f ) && !F1) begin | |
1337 | if ( inbank_debug_count !== 0 ) | |
1338 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: Only one in-bank debug command allowed per dram clk"); | |
1339 | inbank_debug_count=inbank_debug_count+1; | |
1340 | end | |
1341 | ||
1342 | if ( Command[20] && ( !F0 && !F1) ) begin | |
1343 | `PR_ALWAYS ("ch_mon",`DBG_0,"Command B: ACTIVATE"); | |
1344 | sb_cmd_type_reg[9:5] = `CMD_ACT; | |
1345 | end | |
1346 | else begin | |
1347 | `PR_ALWAYS ("ch_mon",`DBG_4,"Transfer[4] = %h\n",sb_frame[4]); | |
1348 | `PR_ALWAYS ("ch_mon",`DBG_4,"Transfer[5] = %h\n",sb_frame[5]); | |
1349 | `PR_ALWAYS ("ch_mon",`DBG_4,"Transfer[6] = %h\n",sb_frame[6]); | |
1350 | `PR_ALWAYS ("ch_mon",`DBG_4,"Transfer[7] = %h\n",sb_frame[7]); | |
1351 | end | |
1352 | ||
1353 | C1 = sb_frame[8]; | |
1354 | C2 = sb_frame[9]; | |
1355 | C3 = sb_frame[10]; | |
1356 | C4 = sb_frame[11]; | |
1357 | Command[23:0] = { C4[5],C3[5],C2[5],C1[5], | |
1358 | C4[4],C3[4],C2[4],C1[4], | |
1359 | C4[3],C3[3],C2[3],C1[3], | |
1360 | C4[2],C3[2],C2[2],C1[2], | |
1361 | C4[1],C3[1],C2[1],C1[1], | |
1362 | C4[0],C3[0],C2[0],C1[0]}; | |
1363 | sb_cmd_rdy_reg[0] = 1; | |
1364 | sb_cmd_encoding_reg[24:0]=Command[23:0]; | |
1365 | sb_cmd_ds_reg[2:0]= Command[23:21]; | |
1366 | if (( Command[17:13] == 5'h1f ) && !F1 ) begin | |
1367 | if ( inbank_debug_count !== 0 ) | |
1368 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: Only one in-bank debug command allowed per dram clk"); | |
1369 | inbank_debug_count=inbank_debug_count+1; | |
1370 | end | |
1371 | ||
1372 | if ( Command[20] && ( !F0 && !F1) ) begin | |
1373 | `PR_ALWAYS ("ch_mon",`DBG_0,"Command C: ACTIVATE"); | |
1374 | sb_cmd_type_reg[4:0] = `CMD_ACT; | |
1375 | end | |
1376 | else begin | |
1377 | `PR_ALWAYS ("ch_mon",`DBG_4,"Transfer[8] = %h\n",sb_frame[8]); | |
1378 | `PR_ALWAYS ("ch_mon",`DBG_4,"Transfer[9] = %h\n",sb_frame[9]); | |
1379 | `PR_ALWAYS ("ch_mon",`DBG_4,"Transfer[10] = %h\n",sb_frame[10]); | |
1380 | `PR_ALWAYS ("ch_mon",`DBG_4,"Transfer[11] = %h\n",sb_frame[11]); | |
1381 | end | |
1382 | ||
1383 | ||
1384 | // DRAM addr/data Collision checks | |
1385 | ||
1386 | // if cmdA and cmdB are to the same DIMM | |
1387 | if ( sb_cmd_ds_reg[8:6] == sb_cmd_ds_reg[5:3] ) | |
1388 | begin | |
1389 | if ( ( ( sb_cmd_type_reg[14:10] == `CMD_ACT ) || | |
1390 | ( sb_cmd_type_reg[14:10] == `CMD_RD) || | |
1391 | ( sb_cmd_type_reg[14:10] == `CMD_WR) || | |
1392 | ( sb_cmd_type_reg[14:10] == `CMD_PSNG) || | |
1393 | ( sb_cmd_type_reg[14:10] == `CMD_PALL) || | |
1394 | ( sb_cmd_type_reg[14:10] == `CMD_WR) || | |
1395 | ( sb_cmd_type_reg[14:10] == `CMD_WR) || | |
1396 | ( sb_cmd_type_reg[14:10] == `CMD_EnSR) || | |
1397 | ( sb_cmd_type_reg[14:10] == `CMD_ARF) | |
1398 | ||
1399 | ) && ( | |
1400 | ( sb_cmd_type_reg[9:5] == `CMD_ACT) || | |
1401 | ( sb_cmd_type_reg[9:5] == `CMD_RD) || | |
1402 | ( sb_cmd_type_reg[9:5] == `CMD_WR) || | |
1403 | ( sb_cmd_type_reg[9:5] == `CMD_PSNG) || | |
1404 | ( sb_cmd_type_reg[9:5] == `CMD_PALL) || | |
1405 | ( sb_cmd_type_reg[9:5] == `CMD_WR) || | |
1406 | ( sb_cmd_type_reg[9:5] == `CMD_WR) || | |
1407 | ( sb_cmd_type_reg[9:5] == `CMD_EnSR) || | |
1408 | ( sb_cmd_type_reg[9:5] == `CMD_ARF) ) | |
1409 | ) // if | |
1410 | begin | |
1411 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: DRAM cmd/addr pin collision between CMDA and CMDB\n"); | |
1412 | end | |
1413 | ||
1414 | ||
1415 | end | |
1416 | ||
1417 | ||
1418 | if ( sb_cmd_ds_reg[8:6] == sb_cmd_ds_reg[2:0] ) | |
1419 | begin | |
1420 | if ( ( ( sb_cmd_type_reg[14:10] == `CMD_ACT ) || | |
1421 | ( sb_cmd_type_reg[14:10] == `CMD_RD) || | |
1422 | ( sb_cmd_type_reg[14:10] == `CMD_WR) || | |
1423 | ( sb_cmd_type_reg[14:10] == `CMD_PSNG) || | |
1424 | ( sb_cmd_type_reg[14:10] == `CMD_PALL) || | |
1425 | ( sb_cmd_type_reg[14:10] == `CMD_WR) || | |
1426 | ( sb_cmd_type_reg[14:10] == `CMD_WR) || | |
1427 | ( sb_cmd_type_reg[14:10] == `CMD_EnSR) || | |
1428 | ( sb_cmd_type_reg[14:10] == `CMD_ARF) | |
1429 | ||
1430 | ) && ( | |
1431 | ( sb_cmd_type_reg[4:0] == `CMD_ACT) || | |
1432 | ( sb_cmd_type_reg[4:0] == `CMD_RD) || | |
1433 | ( sb_cmd_type_reg[4:0] == `CMD_WR) || | |
1434 | ( sb_cmd_type_reg[4:0] == `CMD_PSNG) || | |
1435 | ( sb_cmd_type_reg[4:0] == `CMD_PALL) || | |
1436 | ( sb_cmd_type_reg[4:0] == `CMD_WR) || | |
1437 | ( sb_cmd_type_reg[4:0] == `CMD_WR) || | |
1438 | ( sb_cmd_type_reg[4:0] == `CMD_EnSR) || | |
1439 | ( sb_cmd_type_reg[4:0] == `CMD_ARF) ) | |
1440 | ) // if | |
1441 | begin | |
1442 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: DRAM cmd/addr pin collision between CMDA and CMDC\n"); | |
1443 | end | |
1444 | end // if | |
1445 | ||
1446 | if ( sb_cmd_ds_reg[2:0] == sb_cmd_ds_reg[5:3] ) | |
1447 | begin | |
1448 | if ( ( ( sb_cmd_type_reg[4:0] == `CMD_ACT ) || | |
1449 | ( sb_cmd_type_reg[4:0] == `CMD_RD) || | |
1450 | ( sb_cmd_type_reg[4:0] == `CMD_WR) || | |
1451 | ( sb_cmd_type_reg[4:0] == `CMD_PSNG) || | |
1452 | ( sb_cmd_type_reg[4:0] == `CMD_PALL) || | |
1453 | ( sb_cmd_type_reg[4:0] == `CMD_WR) || | |
1454 | ( sb_cmd_type_reg[4:0] == `CMD_WR) || | |
1455 | ( sb_cmd_type_reg[4:0] == `CMD_EnSR) || | |
1456 | ( sb_cmd_type_reg[4:0] == `CMD_ARF) | |
1457 | ||
1458 | ) && ( | |
1459 | ( sb_cmd_type_reg[9:5] == `CMD_ACT) || | |
1460 | ( sb_cmd_type_reg[9:5] == `CMD_RD) || | |
1461 | ( sb_cmd_type_reg[9:5] == `CMD_WR) || | |
1462 | ( sb_cmd_type_reg[9:5] == `CMD_PSNG) || | |
1463 | ( sb_cmd_type_reg[9:5] == `CMD_PALL) || | |
1464 | ( sb_cmd_type_reg[9:5] == `CMD_WR) || | |
1465 | ( sb_cmd_type_reg[9:5] == `CMD_WR) || | |
1466 | ( sb_cmd_type_reg[9:5] == `CMD_EnSR) || | |
1467 | ( sb_cmd_type_reg[9:5] == `CMD_ARF) ) | |
1468 | ) // if | |
1469 | begin | |
1470 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: DRAM cmd/addr pin collision between CMDB and CMDC\n"); | |
1471 | end | |
1472 | end // if | |
1473 | ||
1474 | // dram CKE pin collision | |
1475 | ||
1476 | if ( sb_cmd_ds_reg[8:6] == sb_cmd_ds_reg[5:3] ) | |
1477 | begin | |
1478 | if ( ( ( sb_cmd_type_reg[14:10] == `CMD_EnSR ) || | |
1479 | ( sb_cmd_type_reg[14:10] == `CMD_ExSR) || | |
1480 | ( sb_cmd_type_reg[14:10] == `CMD_EnPD) || | |
1481 | ( sb_cmd_type_reg[14:10] == `CMD_DRAM_CKE_DIMM) || | |
1482 | ( sb_cmd_type_reg[14:10] == `CMD_DRAM_CKE_RANK) | |
1483 | ||
1484 | ) && ( | |
1485 | ( sb_cmd_type_reg[9:5] == `CMD_EnSR) || | |
1486 | ( sb_cmd_type_reg[9:5] == `CMD_ExSR) || | |
1487 | ( sb_cmd_type_reg[9:5] == `CMD_EnPD) || | |
1488 | ( sb_cmd_type_reg[9:5] == `CMD_DRAM_CKE_DIMM) || | |
1489 | ( sb_cmd_type_reg[9:5] == `CMD_DRAM_CKE_RANK) ) | |
1490 | ) // if | |
1491 | begin | |
1492 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: DRAM CKE pin collision between CMDA and CMDB\n"); | |
1493 | end | |
1494 | end | |
1495 | ||
1496 | if ( sb_cmd_ds_reg[8:6] == sb_cmd_ds_reg[2:0] ) | |
1497 | begin | |
1498 | if ( ( ( sb_cmd_type_reg[14:10] == `CMD_EnSR ) || | |
1499 | ( sb_cmd_type_reg[14:10] == `CMD_ExSR) || | |
1500 | ( sb_cmd_type_reg[14:10] == `CMD_EnPD) || | |
1501 | ( sb_cmd_type_reg[14:10] == `CMD_DRAM_CKE_DIMM) || | |
1502 | ( sb_cmd_type_reg[14:10] == `CMD_DRAM_CKE_RANK) | |
1503 | ||
1504 | ) && ( | |
1505 | ( sb_cmd_type_reg[4:0] == `CMD_EnSR) || | |
1506 | ( sb_cmd_type_reg[4:0] == `CMD_ExSR) || | |
1507 | ( sb_cmd_type_reg[4:0] == `CMD_EnPD) || | |
1508 | ( sb_cmd_type_reg[4:0] == `CMD_DRAM_CKE_DIMM) || | |
1509 | ( sb_cmd_type_reg[4:0] == `CMD_DRAM_CKE_RANK) ) | |
1510 | ) // if | |
1511 | begin | |
1512 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: DRAM CKE pin collision between CMDA and CMDC\n"); | |
1513 | end | |
1514 | end | |
1515 | ||
1516 | ||
1517 | if ( sb_cmd_ds_reg[2:0] == sb_cmd_ds_reg[5:3] ) | |
1518 | begin | |
1519 | if ( ( ( sb_cmd_type_reg[4:0] == `CMD_EnSR ) || | |
1520 | ( sb_cmd_type_reg[4:0] == `CMD_ExSR) || | |
1521 | ( sb_cmd_type_reg[4:0] == `CMD_EnPD) || | |
1522 | ( sb_cmd_type_reg[4:0] == `CMD_DRAM_CKE_DIMM) || | |
1523 | ( sb_cmd_type_reg[4:0] == `CMD_DRAM_CKE_RANK) | |
1524 | ||
1525 | ) && ( | |
1526 | ( sb_cmd_type_reg[9:5] == `CMD_EnSR) || | |
1527 | ( sb_cmd_type_reg[9:5] == `CMD_ExSR) || | |
1528 | ( sb_cmd_type_reg[9:5] == `CMD_EnPD) || | |
1529 | ( sb_cmd_type_reg[9:5] == `CMD_DRAM_CKE_DIMM) || | |
1530 | ( sb_cmd_type_reg[9:5] == `CMD_DRAM_CKE_RANK) ) | |
1531 | ) // if | |
1532 | begin | |
1533 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: DRAM CKE pin collision between CMDA and CMDB\n"); | |
1534 | end | |
1535 | end | |
1536 | ||
1537 | end // f1 & !f0 | |
1538 | ||
1539 | end | |
1540 | else begin | |
1541 | sb_cmd_rdy_reg[2:0] = 3'b0; | |
1542 | sb_cmd_encoding_reg[71:0] = 72'h0; | |
1543 | sb_cmd_type_reg[14:0]= 15'h0; | |
1544 | end | |
1545 | ||
1546 | //------- ADDED BY SWATI | |
1547 | `ifdef SYNC_PKT_RTL_PRESENT | |
1548 | ||
1549 | if(nosync_framecount[5:0] == 6'd42) | |
1550 | begin | |
1551 | nosync_framecount[5:0] = 0; | |
1552 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: Sync Frame was not sent since last 42 Frames\n"); | |
1553 | end | |
1554 | else if( (nosync_framecount[5:0] <= 6'd42) && (nosync_framecount[5:0] >= fbdreg_synctrainint) ) | |
1555 | begin | |
1556 | if(detected_sync_cmd) | |
1557 | begin | |
1558 | nosync_framecount[5:0] = 0; | |
1559 | end | |
1560 | else if(!detected_sync_cmd) | |
1561 | begin | |
1562 | nosync_framecount[5:0] = nosync_framecount[5:0] + 1; | |
1563 | end | |
1564 | end | |
1565 | else if(nosync_framecount[5:0] <= fbdreg_synctrainint) | |
1566 | begin | |
1567 | if(detected_sync_cmd) | |
1568 | begin | |
1569 | nosync_framecount[5:0] = 0; | |
1570 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: Sync Frame was not sent before the programmed no of Frames\n"); | |
1571 | end | |
1572 | else if(!detected_sync_cmd) | |
1573 | begin | |
1574 | nosync_framecount[5:0] = nosync_framecount[5:0] + 1; | |
1575 | end | |
1576 | end | |
1577 | ||
1578 | `endif | |
1579 | //------- ADDED BY SWATI | |
1580 | ||
1581 | end | |
1582 | ||
1583 | integer round_trip_delay; | |
1584 | reg stop_count; | |
1585 | reg count_enable; | |
1586 | reg [47:0] initialization_register_link1; | |
1587 | ||
1588 | assign nb_frm_boundary = (nb_frm_counter == nb_lock_counter ); | |
1589 | ||
1590 | always @(posedge link_clk_int) | |
1591 | begin | |
1592 | if (~rst) | |
1593 | begin | |
1594 | round_trip_delay <= 0; | |
1595 | count_enable <= 1'b0; | |
1596 | stop_count <= 1'b0; | |
1597 | end | |
1598 | else if(init_curr_state == `AMB_INIT_POLL) | |
1599 | begin | |
1600 | if (nb_header_detected) | |
1601 | begin | |
1602 | count_enable <= 1'b0; | |
1603 | stop_count <= 1'b1; | |
1604 | end | |
1605 | else if (((sb_header_detected) || count_enable) & (!stop_count)) | |
1606 | begin | |
1607 | count_enable <= 1'b1; | |
1608 | round_trip_delay <= round_trip_delay + 1; | |
1609 | end | |
1610 | end | |
1611 | end | |
1612 | ||
1613 | always @(posedge link_clk) | |
1614 | begin | |
1615 | if (~rst) | |
1616 | nb_frm_counter <= 4'h0; | |
1617 | else | |
1618 | begin | |
1619 | if (nb_frm_counter[3:0] == 4'hb) | |
1620 | nb_frm_counter <= 4'h0; | |
1621 | else | |
1622 | nb_frm_counter <= nb_frm_counter + 4'h1; | |
1623 | ||
1624 | if (nb_header_detected) | |
1625 | nb_lock_counter <= nb_frm_counter; | |
1626 | ||
1627 | end | |
1628 | end | |
1629 | ||
1630 | always @(link_clk_int) | |
1631 | begin | |
1632 | if ( ~link_clk_int ) | |
1633 | initialization_register_link1[47:0] <= { pn[0], initialization_register_link1[47:1]}; | |
1634 | end | |
1635 | ||
1636 | always@(posedge link_clk_int) if ( ~bypass_init ) | |
1637 | begin | |
1638 | if ( initialization_register_link1[47:36] == 12'h7fc ) | |
1639 | nb_header_detected<=1; | |
1640 | else | |
1641 | nb_header_detected<=0; | |
1642 | ||
1643 | end | |
1644 | ||
1645 | always@(posedge link_clk_int) if ( ~bypass_init ) | |
1646 | begin | |
1647 | if ( initialization_register_link0[47:36] == 12'h7fe ) | |
1648 | sb_header_detected<=1; | |
1649 | else | |
1650 | sb_header_detected<=0; | |
1651 | end | |
1652 | ||
1653 | ||
1654 | // initialization checks | |
1655 | ||
1656 | reg [15:0] amb_init_disable_count; | |
1657 | reg [15:0] amb_init_train_count; | |
1658 | reg [15:0] amb_init_test_count; | |
1659 | reg [15:0] amb_init_poll_count; | |
1660 | reg [15:0] amb_init_config_count; | |
1661 | reg [15:0] amb_init_lo_count; | |
1662 | reg [15:0] amb_init_recalib_count; | |
1663 | reg [15:0] amb_init_los_count; | |
1664 | reg fast_reset_enabled; | |
1665 | ||
1666 | wire [3:0] amb_id0,amb_id1,amb_id2,amb_id3; | |
1667 | wire [3:0] amb_id4,amb_id5,amb_id6,amb_id7; | |
1668 | wire [3:0] amb_id8,amb_id9,amb_id10,amb_id11; | |
1669 | wire [3:0] amb_id12,amb_id13; | |
1670 | ||
1671 | wire [13:0] ts0_ready; | |
1672 | reg [13:0] ts1_start_reg,ts1_end_reg; | |
1673 | wire [13:0] tr_amb_id_ok,ts_amb_id_ok,cf_amb_id_ok,po_amb_id_ok; | |
1674 | wire [13:0] frm_align; | |
1675 | wire [13:0] ts1_start=ts1_start_reg[11:0]; | |
1676 | wire [13:0] ts1_end; //=ts1_end_reg[11:0]; | |
1677 | reg [7:0] fsm_added_delay_reg; | |
1678 | ||
1679 | reg [13:0] ts2_start_reg,ts2_end_reg; | |
1680 | wire [13:0] ts2_start=ts2_start_reg; | |
1681 | wire [13:0] ts2_end; //=ts2_end_reg; | |
1682 | wire enter_config_state; | |
1683 | wire enter_polling_state; | |
1684 | ||
1685 | reg [13:0] ts3_start_reg,ts3_end_reg; | |
1686 | wire [13:0] ts3_start=ts3_start_reg; | |
1687 | wire [13:0] ts3_end; | |
1688 | reg do_init_check; | |
1689 | ||
1690 | reg [6:0] nop_cnt; | |
1691 | reg [20:0] calibration_count; | |
1692 | reg [9:0] clocktrain_count; | |
1693 | reg [9:0] disable_count; | |
1694 | reg [9:0] enddisable_count; | |
1695 | ||
1696 | ||
1697 | ||
1698 | ||
1699 | initial begin | |
1700 | sync_interval_frm_count = 0; | |
1701 | fsr_counter=4'h7; | |
1702 | fsr_counter2=4'hd; | |
1703 | end | |
1704 | ||
1705 | always@(link_clk_int) | |
1706 | begin | |
1707 | if ( ~link_clk_int ) begin | |
1708 | initialization_register_link0[47:0] <= { ps[0], initialization_register_link0[47:1]}; | |
1709 | end | |
1710 | end | |
1711 | ||
1712 | ||
1713 | always@(posedge link_clk) | |
1714 | begin | |
1715 | if ( fsr_counter == 4'h1 ) | |
1716 | fsr_counter = 4'h6; | |
1717 | else | |
1718 | fsr_counter = fsr_counter - 1; | |
1719 | ||
1720 | if ( fsr_counter2 == 4'h1 ) | |
1721 | fsr_counter2 = 4'hc; | |
1722 | else | |
1723 | fsr_counter2 = fsr_counter2 - 1; | |
1724 | ||
1725 | end | |
1726 | ||
1727 | assign frm_begin = ( fsr_counter == lock_counter ); | |
1728 | assign frm_boundary = (fsr_counter2 == lock_counter2); | |
1729 | ||
1730 | always@(negedge link_clk_int) if ( ~bypass_init ) | |
1731 | begin | |
1732 | if(header_detected) | |
1733 | begin | |
1734 | lock_counter <= prev_counter; | |
1735 | lock_counter2 <= prev_counter2; | |
1736 | end | |
1737 | else begin | |
1738 | prev_counter <= fsr_counter; | |
1739 | prev_counter2 <= fsr_counter2; | |
1740 | end | |
1741 | ||
1742 | end | |
1743 | ||
1744 | ||
1745 | always@(posedge link_clk_int) if ( ~bypass_init ) | |
1746 | begin | |
1747 | if (( initialization_register_link0[47:36] == 12'hbfe) && ( init_curr_state == `AMB_INIT_TRAIN ) ) | |
1748 | header_detected<=1; | |
1749 | else | |
1750 | header_detected<=0; | |
1751 | ||
1752 | end | |
1753 | ||
1754 | always@(posedge dram_clk) | |
1755 | begin | |
1756 | if (header_detected ) | |
1757 | enable_fsm=1; | |
1758 | end | |
1759 | ||
1760 | ||
1761 | ||
1762 | initial calibrate_state_counter=0; | |
1763 | ||
1764 | always@(negedge link_clk_int) | |
1765 | begin | |
1766 | if ( !enter_calibrate_state ) | |
1767 | begin | |
1768 | if ( ps[0] ) | |
1769 | calibrate_state_counter <= calibrate_state_counter +1 ; | |
1770 | else | |
1771 | calibrate_state_counter <= 0; | |
1772 | end | |
1773 | else | |
1774 | calibrate_state_counter <= calibrate_state_counter +1 ; | |
1775 | ||
1776 | if ( ps !== ps_bar ) | |
1777 | begin | |
1778 | if ( calibrate_state_counter > (`tClkTrain * 2 * 12 ) ) | |
1779 | enter_calibrate_state <= 1; | |
1780 | else | |
1781 | enter_calibrate_state <= 0; | |
1782 | end | |
1783 | else | |
1784 | enter_calibrate_state <= 0; | |
1785 | ||
1786 | ||
1787 | end | |
1788 | ||
1789 | reg link_clk_int_shft; | |
1790 | ||
1791 | always@(link_clk_int) begin | |
1792 | if ( link_clk_int ) | |
1793 | link_clk_int_shft <= #1 1'b1 ; | |
1794 | else | |
1795 | link_clk_int_shft <= #1 1'b0 ; | |
1796 | end | |
1797 | ||
1798 | wire exit_disable_state; | |
1799 | ||
1800 | voting_logic chk_dis_ready ( .a ( ps_map[0] !== ps_map_bar[0]), | |
1801 | .b ( ps_map[1] !== ps_map_bar[1]), | |
1802 | .c ( ps_map[2] !== ps_map_bar[2]), | |
1803 | .out ( exit_disable_state)); | |
1804 | ||
1805 | ||
1806 | always@(posedge link_clk_int_shft) | |
1807 | begin | |
1808 | if ( ~rst ) begin | |
1809 | init_curr_state = `AMB_INIT_DISABLE; | |
1810 | init_reg=1; | |
1811 | calibration_count=0; | |
1812 | clocktrain_count=0; | |
1813 | disable_count=0; | |
1814 | do_init_check=1; | |
1815 | enddisable_count=0; | |
1816 | amb_init_disable_count=0; | |
1817 | amb_init_train_count=0; | |
1818 | amb_init_test_count=0; | |
1819 | amb_init_poll_count=0; | |
1820 | amb_init_config_count=0; | |
1821 | amb_init_lo_count=0; | |
1822 | amb_init_recalib_count=0; | |
1823 | amb_init_los_count=0; | |
1824 | end | |
1825 | else begin | |
1826 | if ( init_curr_state !== `AMB_INIT_DISABLE ) | |
1827 | calibration_count=calibration_count+1; | |
1828 | ||
1829 | case(init_curr_state) | |
1830 | `AMB_INIT_DISABLE: begin | |
1831 | ||
1832 | ||
1833 | disable_count = disable_count + 1; | |
1834 | enddisable_count = enddisable_count+1; | |
1835 | amb_init_disable_count = amb_init_disable_count + 1; | |
1836 | init_reg=1; | |
1837 | if ( exit_disable_state ) | |
1838 | begin | |
1839 | if ( enddisable_count < `tEDisable ) | |
1840 | `PR_ALWAYS ("ch_mon",`DBG_4,"ERROR: enddisable_count(%h) < `tEDisable(%h)",enddisable_count, `tEDisable); | |
1841 | else | |
1842 | `PR_ALWAYS ("ch_mon",`DBG_4,"tEDisable timing=%d met!",`tEDisable); | |
1843 | init_curr_state=`AMB_INIT_TRAIN; | |
1844 | training_sequence_start_reg=1; | |
1845 | ts0_pattern=0; | |
1846 | amb_init_disable_count=0; | |
1847 | amb_init_train_count=0; | |
1848 | amb_init_test_count=0; | |
1849 | amb_init_poll_count=0; | |
1850 | amb_init_config_count=0; | |
1851 | amb_init_lo_count=0; | |
1852 | amb_init_recalib_count=0; | |
1853 | amb_init_los_count=0; | |
1854 | `PR_ALWAYS ("ch_mon",`DBG_0,"AMB exiting DISABLE state"); | |
1855 | end | |
1856 | else | |
1857 | training_sequence_start_reg=0; | |
1858 | ||
1859 | end | |
1860 | `AMB_INIT_TRAIN : begin | |
1861 | ||
1862 | ||
1863 | if ( enter_calibrate_state ) begin | |
1864 | training_sequence_start_reg=0; | |
1865 | init_curr_state=`AMB_INIT_CALIB; | |
1866 | end | |
1867 | ||
1868 | if ( enter_disable_state ) begin | |
1869 | training_sequence_start_reg=0; | |
1870 | init_curr_state = `AMB_INIT_DISABLE; | |
1871 | disable_count=0; | |
1872 | enddisable_count=0; | |
1873 | end | |
1874 | ||
1875 | clocktrain_count = clocktrain_count+1; | |
1876 | amb_init_train_count = amb_init_train_count + 1; | |
1877 | ||
1878 | if ( ts0_ready_2of3 ) | |
1879 | begin | |
1880 | `PR_ALWAYS ("ch_mon",`DBG_0,"AMB Training Sequence 0 complete!"); | |
1881 | init_curr_state=`AMB_INIT_TEST; | |
1882 | training_sequence_start_reg=0; | |
1883 | ||
1884 | end | |
1885 | else begin | |
1886 | ts0_pattern = ts0_pattern + 1; | |
1887 | ts0_reg0[143:0] = {ts0_reg0[142:0],ps_map[0]}; | |
1888 | ts0_reg1[143:0] = {ts0_reg1[142:0],ps_map[1]}; | |
1889 | ts0_reg2[143:0] = {ts0_reg2[142:0],ps_map[2]}; | |
1890 | ts0_reg3[143:0] = {ts0_reg3[142:0],ps_map[3]}; | |
1891 | ts0_reg4[143:0] = {ts0_reg4[142:0],ps_map[4]}; | |
1892 | ts0_reg5[143:0] = {ts0_reg5[142:0],ps_map[5]}; | |
1893 | ts0_reg6[143:0] = {ts0_reg6[142:0],ps_map[6]}; | |
1894 | ts0_reg7[143:0] = {ts0_reg7[142:0],ps_map[7]}; | |
1895 | ts0_reg8[143:0] = {ts0_reg8[142:0],ps_map[8]}; | |
1896 | ts0_reg9[143:0] = {ts0_reg9[142:0],ps_map[9]}; | |
1897 | ||
1898 | end | |
1899 | end | |
1900 | ||
1901 | `AMB_INIT_CALIB : begin | |
1902 | if ( enter_disable_state ) | |
1903 | init_curr_state=`AMB_INIT_DISABLE; | |
1904 | end | |
1905 | `AMB_INIT_TEST : begin | |
1906 | if ( enter_disable_state ) begin | |
1907 | init_curr_state = `AMB_INIT_DISABLE; | |
1908 | disable_count=0; | |
1909 | enddisable_count=0; | |
1910 | end | |
1911 | ||
1912 | ts1_start_reg[11:0]=12'hfff; // start testing sequence | |
1913 | amb_init_test_count = amb_init_test_count + 1; | |
1914 | ||
1915 | ||
1916 | if ( enter_polling_state ) begin | |
1917 | init_curr_state=`AMB_INIT_POLL; | |
1918 | ts1_start_reg[11:0]=12'h0; | |
1919 | `PR_ALWAYS ("ch_mon",`DBG_0,"AMB Testing sequence complete!"); | |
1920 | end | |
1921 | ||
1922 | ||
1923 | end | |
1924 | `AMB_INIT_POLL : begin | |
1925 | if ( enter_disable_state ) begin | |
1926 | init_curr_state = `AMB_INIT_DISABLE; | |
1927 | disable_count=0; | |
1928 | enddisable_count=0; | |
1929 | end | |
1930 | ||
1931 | amb_init_poll_count = amb_init_poll_count + 1; | |
1932 | ts2_start_reg=12'hfff; // start testing sequence | |
1933 | fsm_added_delay_reg=8'h48; // add 6 dram cycles worth of delay | |
1934 | if ( enter_config_state ) begin | |
1935 | init_curr_state=`AMB_INIT_CONFIG; | |
1936 | `PR_ALWAYS ("ch_mon",`DBG_0,"AMB Polling sequence complete!"); | |
1937 | end | |
1938 | ||
1939 | ||
1940 | end | |
1941 | `AMB_INIT_CONFIG : begin | |
1942 | if ( enter_disable_state ) begin | |
1943 | init_curr_state = `AMB_INIT_DISABLE; | |
1944 | disable_count=0; | |
1945 | enddisable_count=0; | |
1946 | end | |
1947 | ||
1948 | ts3_start_reg=12'hfff; // start testing sequence | |
1949 | amb_init_config_count = amb_init_config_count + 1; | |
1950 | ||
1951 | if ( (ps_map == 0 ) ) | |
1952 | nop_cnt=nop_cnt+1; | |
1953 | else | |
1954 | nop_cnt = 0; | |
1955 | ||
1956 | if ( nop_cnt > 46 ) | |
1957 | init_curr_state=`AMB_INIT_LO; | |
1958 | ||
1959 | ||
1960 | if ( (ts3_end[0] ) && ( nop_cnt !== 0 )) begin | |
1961 | `PR_ALWAYS ("ch_mon",`DBG_0,"AMB Config sequence complete!"); | |
1962 | ||
1963 | // Host sent a command which was not a NOP before 4 NOP frames are complete | |
1964 | if ( (nop_cnt < 46 ) && ( ps_map != 0 ) ) | |
1965 | `PR_ALWAYS ("ch_mon",`DBG_4,"ERROR: Host needs to send at least 4 NOP frames before entering LOs"); | |
1966 | end | |
1967 | ||
1968 | end | |
1969 | `AMB_INIT_LO : begin | |
1970 | if ( enter_disable_state ) begin | |
1971 | init_curr_state = `AMB_INIT_DISABLE; | |
1972 | disable_count=0; | |
1973 | enddisable_count=0; | |
1974 | end | |
1975 | ||
1976 | fsm_added_delay_reg=8'h00; // add 0 dram cycles workth of delay | |
1977 | amb_init_lo_count = amb_init_lo_count + 1; | |
1978 | ||
1979 | if ( do_init_check ) begin | |
1980 | init_reg=0; | |
1981 | `PR_ALWAYS ("ch_mon",`DBG_0,"AMB LO state entered"); | |
1982 | ||
1983 | if ( calibration_count < `tCalibrate ) | |
1984 | `PR_ALWAYS ("ch_mon",`DBG_4,"ERROR: calibration_count(%h) > `tCalibrate(%h)" , calibration_count,`tCalibrate); | |
1985 | else | |
1986 | `PR_ALWAYS ("ch_mon",`DBG_4,"tCalibrate timing %d met!",`tCalibrate); | |
1987 | ||
1988 | ||
1989 | if ( clocktrain_count < `tClkTrain ) | |
1990 | `PR_ALWAYS ("ch_mon",`DBG_4,"ERROR: clocktrain_count(%h) > `tClktrain(%h)",clocktrain_count,`tClkTrain); | |
1991 | else | |
1992 | `PR_ALWAYS ("ch_mon",`DBG_4,"tClktrain %d timing met!",`tCalibrate); | |
1993 | ||
1994 | ||
1995 | if ( disable_count < `tDisable ) | |
1996 | `PR_ALWAYS ("ch_mon",`DBG_4,"ERROR: disable_count(%h) < `tDisable(%h)",disable_count, `tDisable); | |
1997 | else | |
1998 | `PR_ALWAYS ("ch_mon",`DBG_4,"tDisable timing %d met!",`tDisable); | |
1999 | ||
2000 | if ( ts0_pattern < (`TS0_FRAMES * 12 ) ) | |
2001 | `PR_ALWAYS ("ch_mon",`DBG_4,"ERROR: ts0 patterns received (%h) < ts0 patterns expected (%h) (divide by 12 to get actual # of frames)\n",ts0_pattern,`TS0_FRAMES); | |
2002 | ||
2003 | do_init_check=0; | |
2004 | end | |
2005 | /* | |
2006 | if ( fast_reset_enabled ) | |
2007 | begin | |
2008 | if ( (amb_init_disable_count < 1572 ) || // 131 frm * 12 | |
2009 | (amb_init_train_count < 39600) || // 3300 frm * 12 | |
2010 | (amb_init_test_count < 756 ) || // 63 frm *12 | |
2011 | (amb_init_poll_count < 468 ) || // 39 frm *12 | |
2012 | (amb_init_config_count < 468 ) || // 39 frm *12 | |
2013 | (amb_init_lo_count < 276 )) // 23 frm *12 | |
2014 | begin | |
2015 | `PR_ALWAYS ("ch_mon",`DBG_4,"ERROR: Fast reset duration timing violated!\n"); | |
2016 | end | |
2017 | ||
2018 | end | |
2019 | */ | |
2020 | ||
2021 | if ( enter_disable_state ) | |
2022 | begin | |
2023 | if ( write_fifo_empty /* amb.ch_monr.write_fifo.rempty */ == 0 ) | |
2024 | `PR_ALWAYS ("ch_mon",`DBG_4,"ERROR: Host has sent electrical idle before writes are done!"); | |
2025 | init_curr_state = `AMB_INIT_DISABLE; | |
2026 | disable_count=0; | |
2027 | enddisable_count=0; | |
2028 | fast_reset_enabled =1; | |
2029 | end | |
2030 | ||
2031 | if ( enter_recalibrate ) begin | |
2032 | init_curr_state=`AMB_INIT_RECALIB; | |
2033 | Recalibrate_Timer = 9'h0; | |
2034 | end | |
2035 | if ( enter_los ) begin | |
2036 | init_curr_state=`AMB_INIT_LOS; | |
2037 | LOs_Timer=9'h0; | |
2038 | end | |
2039 | ||
2040 | ||
2041 | init_reg=0; | |
2042 | ||
2043 | end | |
2044 | `AMB_INIT_RECALIB: begin | |
2045 | if ( enter_disable_state ) begin | |
2046 | init_curr_state = `AMB_INIT_DISABLE; | |
2047 | disable_count=0; | |
2048 | enddisable_count=0; | |
2049 | end | |
2050 | ||
2051 | `PR_ALWAYS ("amb_init",`DBG_0,"Entering AMB Recalibrate State!"); | |
2052 | amb_init_recalib_count = amb_init_recalib_count + 1; | |
2053 | ||
2054 | init_reg=1; | |
2055 | if ( LOs_Timer == 9'h180 ) // 32 frames | |
2056 | init_curr_state=`AMB_INIT_LO; | |
2057 | else | |
2058 | LOs_Timer= LOs_Timer + 9'h1; | |
2059 | ||
2060 | end | |
2061 | `AMB_INIT_LOS : begin | |
2062 | if ( enter_disable_state ) begin | |
2063 | init_curr_state = `AMB_INIT_DISABLE; | |
2064 | disable_count=0; | |
2065 | enddisable_count=0; | |
2066 | end | |
2067 | ||
2068 | `PR_ALWAYS ("amb_init",`DBG_0,"Entering AMB LOs State!"); | |
2069 | amb_init_los_count = amb_init_los_count + 1; | |
2070 | init_reg=1; | |
2071 | if ( Recalibrate_Timer == 9'h180 ) // 32 frames | |
2072 | init_curr_state=`AMB_INIT_LO; | |
2073 | else | |
2074 | Recalibrate_Timer= Recalibrate_Timer + 9'h1; | |
2075 | ||
2076 | end | |
2077 | endcase | |
2078 | end | |
2079 | ||
2080 | end | |
2081 | ||
2082 | ||
2083 | training_sequence_fsm #(0) tr_ps0 (.ps_bit (ps_map[0]), | |
2084 | .ps_bit_bar ( ps_map_bar[0] ), | |
2085 | .link_clk (link_clk_int), | |
2086 | .amb_id (amb_id0), | |
2087 | .frm_align (frm_align[0]), | |
2088 | .training_sequence_start ( training_sequence_start), | |
2089 | .training_sequence_end (ts0_ready[0]), | |
2090 | .amb_id_ok (tr_amb_id_ok[0])); | |
2091 | ||
2092 | training_sequence_fsm #(0) tr_ps1 (.ps_bit (ps_map[1]), | |
2093 | .ps_bit_bar ( ps_map_bar[1] ), | |
2094 | .link_clk (link_clk_int), | |
2095 | .amb_id (amb_id0), | |
2096 | .frm_align (frm_align[1]), | |
2097 | .training_sequence_start ( training_sequence_start), | |
2098 | .training_sequence_end (ts0_ready[1]), | |
2099 | .amb_id_ok (tr_amb_id_ok[1])); | |
2100 | ||
2101 | training_sequence_fsm #(0) tr_ps2 (.ps_bit (ps_map[2]), | |
2102 | .ps_bit_bar ( ps_map_bar[2] ), | |
2103 | .link_clk (link_clk_int), | |
2104 | .amb_id (amb_id0), | |
2105 | .frm_align (frm_align[2]), | |
2106 | .training_sequence_start ( training_sequence_start), | |
2107 | .training_sequence_end (ts0_ready[2]), | |
2108 | .amb_id_ok (tr_amb_id_ok[2])); | |
2109 | ||
2110 | voting_logic chk_ts0_ready ( .a ( ts0_ready[0]), | |
2111 | .b ( ts0_ready[1]), | |
2112 | .c ( ts0_ready[2]), | |
2113 | .out ( ts0_ready_2of3)); | |
2114 | ||
2115 | voting_logic chk_enter_disable ( .a ( ps_map[0] == ps_map_bar[0] ), | |
2116 | .b ( ps_map[1] == ps_map_bar[1] ), | |
2117 | .c ( ps_map[2] == ps_map_bar[2] ), | |
2118 | .out ( enter_disable_state)); | |
2119 | ||
2120 | training_sequence_fsm_chk #(0) tr_ps0_chk (.ps_bit (ps_map[0]), | |
2121 | .ps_bit_bar ( ps_map_bar[0]), | |
2122 | .link_clk (link_clk_int), | |
2123 | .training_sequence_start ( training_sequence_start)); | |
2124 | ||
2125 | ||
2126 | /****************/ | |
2127 | ||
2128 | testing_state_fsm #(0) ts_ps0 (.ps_bit (ps_map[0]), | |
2129 | .link_clk (link_clk_int), | |
2130 | .amb_id (amb_id0), | |
2131 | .testing_state_start (ts1_start[0]), | |
2132 | .testing_state_end (ts1_end[0]), | |
2133 | .amb_id_ok (ts_amb_id_ok[0]), | |
2134 | .sb2nbmap (sb2nbmap) | |
2135 | ); | |
2136 | ||
2137 | testing_state_fsm #(0) ts_ps1 (.ps_bit (ps_map[1]), | |
2138 | .link_clk (link_clk_int), | |
2139 | .amb_id (amb_id0), | |
2140 | .testing_state_start (ts1_start[1]), | |
2141 | .testing_state_end (ts1_end[1]), | |
2142 | .amb_id_ok (ts_amb_id_ok[1]), | |
2143 | .sb2nbmap (sb2nbmap) | |
2144 | ); | |
2145 | ||
2146 | testing_state_fsm #(0) ts_ps2 (.ps_bit (ps_map[2]), | |
2147 | .link_clk (link_clk_int), | |
2148 | .amb_id (amb_id0), | |
2149 | .testing_state_start (ts1_start[2]), | |
2150 | .testing_state_end (ts1_end[2]), | |
2151 | .amb_id_ok (ts_amb_id_ok[2]), | |
2152 | .sb2nbmap (sb2nbmap) | |
2153 | ); | |
2154 | ||
2155 | voting_logic chk_enter_polling_state (.a ( ts1_end[0]), | |
2156 | .b ( ts1_end[1]), | |
2157 | .c ( ts1_end[2]), | |
2158 | .out ( enter_polling_state)); | |
2159 | ||
2160 | ||
2161 | testing_state_fsm_chk #(0) ts_ps0_chk (.ps_bit (ps_map[0]), | |
2162 | .link_clk (link_clk_int), | |
2163 | .testing_state_start (ts1_start[0]) | |
2164 | ); | |
2165 | ||
2166 | /****************/ | |
2167 | ||
2168 | polling_state_fsm #(0) po_ps0 (.ps_bit (ps_map[0]), | |
2169 | .link_clk (link_clk_int), | |
2170 | .amb_id (amb_id0), | |
2171 | .polling_state_start (ts2_start[0]), | |
2172 | .amb_id_ok (po_amb_id_ok[0]), | |
2173 | .polling_state_end (ts2_end[0]) | |
2174 | ); | |
2175 | polling_state_fsm #(0) po_ps1 (.ps_bit (ps_map[1]), | |
2176 | .link_clk (link_clk_int), | |
2177 | .amb_id (amb_id0), | |
2178 | .polling_state_start (ts2_start[1]), | |
2179 | .amb_id_ok (po_amb_id_ok[1]), | |
2180 | .polling_state_end (ts2_end[1]) | |
2181 | ); | |
2182 | polling_state_fsm #(0) po_ps2 (.ps_bit (ps_map[2]), | |
2183 | .link_clk (link_clk_int), | |
2184 | .amb_id (amb_id0), | |
2185 | .polling_state_start (ts2_start[2]), | |
2186 | .amb_id_ok (po_amb_id_ok[2]), | |
2187 | .polling_state_end (ts2_end[2]) | |
2188 | ); | |
2189 | ||
2190 | polling_state_fsm_chk #(0) po_ps0_chk (.ps_bit (ps_map[0]), | |
2191 | .link_clk (link_clk_int), | |
2192 | .polling_state_start (ts2_start[0]) | |
2193 | ); | |
2194 | ||
2195 | voting_logic chk_enter_config_state (.a ( ts2_end[0]), | |
2196 | .b ( ts2_end[1]), | |
2197 | .c ( ts2_end[2]), | |
2198 | .out ( enter_config_state)); | |
2199 | ||
2200 | /****************/ | |
2201 | ||
2202 | config_state_fsm #(0) cfg_ps0 (.ps_bit (ps_map[0]), | |
2203 | .link_clk (link_clk_int), | |
2204 | .amb_id (amb_id0), | |
2205 | .config_state_start (ts3_start[0]), | |
2206 | .config_state_end (ts3_end[0]), | |
2207 | .amb_id_ok (cf_amb_id_ok[0]) | |
2208 | ); | |
2209 | config_state_fsm #(0) cfg_ps1 (.ps_bit (ps_map[1]), | |
2210 | .link_clk (link_clk_int), | |
2211 | .amb_id (amb_id0), | |
2212 | .config_state_start (ts3_start[1]), | |
2213 | .config_state_end (ts3_end[1]), | |
2214 | .amb_id_ok (cf_amb_id_ok[1]) | |
2215 | ); | |
2216 | config_state_fsm #(0) cfg_ps2 (.ps_bit (ps_map[2]), | |
2217 | .link_clk (link_clk_int), | |
2218 | .amb_id (amb_id0), | |
2219 | .config_state_start (ts3_start[2]), | |
2220 | .config_state_end (ts3_end[2]), | |
2221 | .amb_id_ok (cf_amb_id_ok[2]) | |
2222 | ); | |
2223 | ||
2224 | config_state_fsm_chk #(0) cfg_ps0_chk (.ps_bit (ps_map[0]), | |
2225 | .link_clk (link_clk_int), | |
2226 | .config_state_start (ts3_start[0]) | |
2227 | ); | |
2228 | ||
2229 | ||
2230 | reg [SB_LINK-1:0] frm_mem[0:11]; | |
2231 | ||
2232 | /* Calculate Channel latency */ | |
2233 | ||
2234 | ||
2235 | initial begin | |
2236 | latency_calculated = 1'b0; | |
2237 | polling_counter = 11'h0; | |
2238 | end | |
2239 | ||
2240 | always@(negedge link_clk ) | |
2241 | begin | |
2242 | SB_transfer_reg[11:0] = { ps[0], SB_transfer_reg[11:1]}; | |
2243 | // NB_transfer_reg[11:0] = { pn[0], NB_transfer_reg[11:1]}; | |
2244 | end | |
2245 | ||
2246 | always@(negedge nb_frm_rdy) | |
2247 | begin | |
2248 | NB_transfer_reg[11:0] = {pn11[0],pn10[0],pn9[0],pn8[0],pn7[0],pn6[0],pn5[0],pn4[0],pn3[0],pn2[0],pn1[0],pn0[0]}; | |
2249 | end | |
2250 | ||
2251 | reg start_counter; | |
2252 | initial start_counter = 0; | |
2253 | ||
2254 | always@(posedge link_clk ) | |
2255 | begin | |
2256 | if (( SB_transfer_reg == 12'h7fe ) & !latency_calculated & (init_curr_state == `AMB_INIT_POLL) & !start_counter) | |
2257 | begin | |
2258 | start_counter = 1; | |
2259 | polling_counter=0; | |
2260 | end | |
2261 | if (( NB_transfer_reg == 12'h7fe ) & !latency_calculated & (init_curr_state == `AMB_INIT_POLL)) | |
2262 | begin | |
2263 | latency_calculated = 1'b1; | |
2264 | channel_latency = polling_counter; | |
2265 | start_counter = 0; | |
2266 | end | |
2267 | if ( start_counter ) | |
2268 | polling_counter = polling_counter + 12'h1; | |
2269 | ||
2270 | end | |
2271 | ||
2272 | ||
2273 | /****** DELAY LOGIC ******/ | |
2274 | dff_fbd #(1) WCR1( .signal_in (Write_Config_reg), | |
2275 | .signal_out (Write_Config_reg_d1), | |
2276 | .clk (link_clk)); | |
2277 | ||
2278 | dff_fbd #(1) WCR2( .signal_in (Write_Config_reg_d1), | |
2279 | .signal_out (Write_Config_reg_d2), | |
2280 | .clk (link_clk)); | |
2281 | ||
2282 | dff_fbd #(1) WCR3( .signal_in (Write_Config_reg_d2), | |
2283 | .signal_out (Write_Config_reg_d3), | |
2284 | .clk (link_clk)); | |
2285 | ||
2286 | dff_fbd #(1) WCR4( .signal_in (Write_Config_reg_d3), | |
2287 | .signal_out (Write_Config_reg_d4), | |
2288 | .clk (link_clk)); | |
2289 | ||
2290 | crc_FE data_crc(.B(Data_72) , | |
2291 | .E (CRC22)); | |
2292 | ||
2293 | crc_FE_failover data_crc_failover (.B(Data_72) , | |
2294 | .E (CRC10_data_failover)); | |
2295 | ||
2296 | ||
2297 | crc_aE cmd_crc ( .B(Command_26), | |
2298 | .E (CRC14)); | |
2299 | ||
2300 | crc_aE_failover cmd_crc_failover ( .B(Command_26), | |
2301 | .E (CRC10_cmd_failover)); | |
2302 | ||
2303 | ||
2304 | reg [13:0] pn_prev1,pn_prev2; | |
2305 | ||
2306 | ||
2307 | wire is_idle = ( pn0 == pn1 ) & (pn0 == pn2) & (pn0 == pn3) & (pn0 == pn4 ) & (pn0 == pn5 ) & | |
2308 | ( pn6 == pn7 ) & (pn6 == pn8) & (pn6 == pn9) & (pn6 == pn10) & (pn6 == pn11 ) & | |
2309 | ( pn0 !== 14'h0 ) & | |
2310 | ( pn1 !== 14'h0 ) & | |
2311 | ( pn2 !== 14'h0 ) & | |
2312 | ( pn3 !== 14'h0 ) & | |
2313 | ( pn4 !== 14'h0 ) & | |
2314 | ( pn5 !== 14'h0 ) & | |
2315 | ( pn6 !== 14'h0 ) & | |
2316 | ( pn7 !== 14'h0 ) & | |
2317 | ( pn8 !== 14'h0 ) & | |
2318 | ( pn9 !== 14'h0 ) & | |
2319 | ( pn10 !== 14'h0 ) & | |
2320 | ( pn11 !== 14'h0 ) ; | |
2321 | ||
2322 | ||
2323 | always@(negedge nb_frm_rdy) if ( is_idle ) | |
2324 | begin | |
2325 | pn_prev1 <= pn0; | |
2326 | pn_prev2 <= pn_prev1; | |
2327 | end | |
2328 | else begin | |
2329 | pn_prev1 <= 0; | |
2330 | pn_prev2 <= 0; | |
2331 | end | |
2332 | ||
2333 | reg [13:0] pn_prev1_d; | |
2334 | ||
2335 | always@(posedge link_clk) | |
2336 | pn_prev1_d <= pn_prev1; | |
2337 | ||
2338 | reg [47:0] ireg_l0; | |
2339 | reg [47:0] ireg_l1; | |
2340 | reg [47:0] ireg_l2; | |
2341 | ||
2342 | ||
2343 | wire detect_2of3_cfg_hdr; | |
2344 | ||
2345 | voting_logic dtct_cfg_hdr (.a ( ireg_l0[23:12] == 12'h3fe), | |
2346 | .b ( ireg_l1[23:12] == 12'h3fe), | |
2347 | .c ( ireg_l2[23:12] == 12'h3fe), | |
2348 | .out ( detect_2of3_cfg_hdr )); | |
2349 | ||
2350 | always@(negedge frm_boundary ) | |
2351 | begin | |
2352 | if ( detect_2of3_cfg_hdr ) begin | |
2353 | if (( ps0[1] !== ps0[0] ) && ( ps0[1] == ps0[2]) ) // failed lane is 0 | |
2354 | begin | |
2355 | nb_config <= ireg_l1[45:42]; | |
2356 | sb_config <= ireg_l1[39:36]; | |
2357 | end | |
2358 | else | |
2359 | begin | |
2360 | nb_config <= ireg_l0[45:42]; | |
2361 | sb_config <= ireg_l0[39:36]; | |
2362 | end | |
2363 | end // if ( detect_2of3_cfg_hdr | |
2364 | ||
2365 | ireg_l0[47:0] <= { ps11[0], ps10[0], ps9[0],ps8[0],ps7[0],ps6[0],ps5[0],ps4[0],ps3[0],ps2[0],ps1[0],ps0[0],ireg_l0[47:12]}; | |
2366 | ireg_l1[47:0] <= { ps11[1], ps10[1], ps9[1],ps8[1],ps7[1],ps6[1],ps5[1],ps4[1],ps3[1],ps2[1],ps1[1],ps0[1],ireg_l1[47:12]}; | |
2367 | ireg_l2[47:0] <= { ps11[2], ps10[2], ps9[2],ps8[2],ps7[2],ps6[2],ps5[2],ps4[2],ps3[2],ps2[2],ps1[2],ps0[2],ireg_l2[47:12]}; | |
2368 | ||
2369 | ||
2370 | end | |
2371 | ||
2372 | `ifdef STINGRAY | |
2373 | chmon_idle_lfsr idle_frame_generator( .reset (init_reg ), //sync_cmd_rdy_d1 ), | |
2374 | .pn_prev_in ( pn_prev1_d ), | |
2375 | .pn_curr_in ( pn0 ), | |
2376 | .is_idle ( is_idle ), | |
2377 | .alert_frame ( alert_frame), | |
2378 | .frm_begin ( frm_begin), | |
2379 | .frm_boundary ( nb_frm_rdy), | |
2380 | .nb_config ( nb_config), | |
2381 | .clk (link_clk)); | |
2382 | ||
2383 | `endif // STINGRAY | |
2384 | ||
2385 | endmodule | |
2386 | ||
2387 | `endif |