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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: config_state_fsm.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `ifdef AXIS_FBDIMM_NO_FSR | |
36 | `else | |
37 | module config_state_fsm(ps_bit,link_clk,amb_id,config_state_start,config_state_end,amb_id_ok); | |
38 | ||
39 | parameter DS=0; | |
40 | ||
41 | input ps_bit; | |
42 | input link_clk; | |
43 | output [3:0] amb_id; | |
44 | input config_state_start; | |
45 | output config_state_end; | |
46 | output amb_id_ok; | |
47 | ||
48 | reg [2:0] SB2NB_Map; | |
49 | reg [11:0] tr_reg; | |
50 | reg [4:0] tr_state; | |
51 | reg [4:0] tr_count; | |
52 | reg [11:0] clk_trn_ptrn; | |
53 | reg [3:0] clk_grp; | |
54 | reg ts1_ready_reg; | |
55 | reg [3:0] amb_id_reg; | |
56 | reg [23:0] test_param_reg; | |
57 | reg [7:8] test_param_count; | |
58 | reg [35:0] end_del_reg; | |
59 | reg config_state_start_reg,config_state_end_reg; | |
60 | ||
61 | assign amb_id=amb_id_reg; | |
62 | assign amb_id_ok = ( amb_id_reg == DS) ? 1'b1: 1'b0; | |
63 | ||
64 | initial begin | |
65 | tr_state=0; | |
66 | tr_count=0; | |
67 | amb_id_reg=0; | |
68 | ||
69 | test_param_count=0; | |
70 | end | |
71 | ||
72 | assign config_state_end=config_state_end_reg; | |
73 | ||
74 | always@(posedge link_clk) if ( config_state_start ) | |
75 | begin | |
76 | case(tr_state) | |
77 | `IDLE: begin | |
78 | tr_reg[11:0] <= {ps_bit, tr_reg[11:1] }; | |
79 | ||
80 | if ( {ps_bit, tr_reg[11:1] } == 12'b001111111110 ) begin | |
81 | tr_state<=`TS_TEST_1; | |
82 | `ifdef FBD_DBG | |
83 | `PR_ALWAYS("amb_init",`DBG_0,"%d: AMB Detected CONFIG",$time); | |
84 | `endif | |
85 | end | |
86 | ||
87 | end | |
88 | `TS_TEST_1: begin | |
89 | case(tr_count) | |
90 | 4'b0000: begin tr_reg[0] <= ps_bit; tr_count=tr_count+1; end | |
91 | 4'b0001: begin tr_reg[1] <= ps_bit; tr_count=tr_count+1; end | |
92 | 4'b0010: begin tr_reg[2] <= ps_bit; tr_count=tr_count+1;end | |
93 | 4'b0011: begin tr_reg[3] <= ps_bit; tr_count=tr_count+1; end | |
94 | 4'b0100: begin tr_reg[4] <= ps_bit; tr_count=tr_count+1; end | |
95 | 4'b0101: begin tr_reg[5] <= ps_bit; tr_count=tr_count+1; end | |
96 | 4'b0110: begin tr_reg[6] <= ps_bit; tr_count=tr_count+1; end | |
97 | 4'b0111: begin tr_reg[7] <= ps_bit; tr_count=tr_count+1; end | |
98 | 4'b1000: begin tr_reg[8] <= ps_bit; tr_count=tr_count+1; end | |
99 | 4'b1001: begin tr_reg[9] <= ps_bit; tr_count=tr_count+1; end | |
100 | 4'b1010: begin tr_reg[10] <= ps_bit; tr_count=tr_count+1; end | |
101 | 4'b1011: begin tr_reg[11] <= ps_bit; tr_state <=`TS_TEST_2; | |
102 | tr_count=1;clk_grp=0; amb_id_reg[3:0]=tr_reg[3:0];SB2NB_Map=tr_reg[6:4]; | |
103 | `ifdef FBD_DBG | |
104 | `PR_ALWAYS("amb_init",`DBG_4,"TS_TEST Control values: ambid=%h sb2nbmap %h",tr_reg[3:0],tr_reg[6:4]); | |
105 | `endif | |
106 | end | |
107 | endcase | |
108 | end | |
109 | ||
110 | `TS_TEST_2: begin | |
111 | end_del_reg[35:0] <= { end_del_reg[34:0],ps_bit}; | |
112 | ||
113 | if ( { end_del_reg[34:0],ps_bit} == {12'b101010101010,12'b101010101010,12'b101010101010} ) | |
114 | begin | |
115 | `ifdef FBD_DBG | |
116 | `PR_ALWAYS("amb_init",`DBG_0,"AMB_INIT config end detected"); | |
117 | `endif | |
118 | config_state_end_reg<=1; | |
119 | tr_state<=`IDLE; | |
120 | ||
121 | end | |
122 | else | |
123 | config_state_end_reg<=0; | |
124 | ||
125 | end | |
126 | ||
127 | endcase | |
128 | ||
129 | ||
130 | end | |
131 | ||
132 | ||
133 | endmodule | |
134 | ||
135 | ||
136 | module config_state_fsm_chk(ps_bit,link_clk,config_state_start); | |
137 | ||
138 | parameter DS=0; | |
139 | ||
140 | input ps_bit; | |
141 | input link_clk; | |
142 | input config_state_start; | |
143 | ||
144 | reg [2:0] SB2NB_Map; | |
145 | reg [71:0] tr_reg; | |
146 | reg [4:0] tr_state; | |
147 | reg [9:0] tr_count; | |
148 | reg [11:0] clk_trn_ptrn; | |
149 | reg [3:0] clk_grp; | |
150 | reg ts1_ready_reg; | |
151 | reg [3:0] amb_id_reg; | |
152 | reg [23:0] test_param_reg; | |
153 | reg [7:8] test_param_count; | |
154 | reg [35:0] end_del_reg; | |
155 | reg config_state_start_reg,config_state_end_reg; | |
156 | ||
157 | initial begin | |
158 | tr_state=0; | |
159 | tr_count=0; | |
160 | amb_id_reg=0; | |
161 | ||
162 | test_param_count=0; | |
163 | end | |
164 | ||
165 | ||
166 | always@(posedge link_clk) if ( config_state_start ) | |
167 | begin | |
168 | ||
169 | case(tr_state) | |
170 | `IDLE: begin | |
171 | // ts1_ready_reg=0; | |
172 | tr_reg[71:0] = { ps_bit,tr_reg[71:1]}; | |
173 | ||
174 | if (tr_reg[71:60] == 12'b001111111110 ) begin | |
175 | tr_state<=`TS_TEST_1; | |
176 | end | |
177 | ||
178 | end | |
179 | `TS_TEST_1: begin | |
180 | tr_reg[71:0] = {ps_bit,tr_reg[71:1]}; | |
181 | tr_count=tr_count+1; | |
182 | ||
183 | if ( (tr_count == 8'h3c) && (tr_reg[71:0] != 0 ) ) begin | |
184 | `ifdef AXIS_FBDIMM_HW | |
185 | `else | |
186 | `PR_ALWAYS("ch_mon",`DBG_0,"cfg_reg: %h ",tr_reg); | |
187 | ||
188 | if ( tr_reg[11:0] != 12'h3fe ) | |
189 | `PR_ALWAYS("ch_mon",`DBG_0,"ERROR: 3fe pattern not found for config state "); | |
190 | ||
191 | if ( {tr_reg[23:21]} != {2'b00} ) | |
192 | `PR_ALWAYS("ch_mon",`DBG_0,"ERROR: grp1 pattern in testing is wrong! "); | |
193 | ||
194 | if ( (tr_reg[20:17] == 4'b0010 ) || | |
195 | (tr_reg[20:17] == 4'b0110 ) || | |
196 | (tr_reg[20] )) | |
197 | `PR_ALWAYS("ch_mon",`DBG_0,"ERROR: Protocol selection field value(%b) in testing is reserved! ",tr_reg[20:17]); | |
198 | ||
199 | if ( (tr_reg[27:24] == 4'b1110 ) || | |
200 | (tr_reg[27:24] == 4'b1101 ) || | |
201 | (tr_reg[27:24] == 4'b1100 ) || | |
202 | (tr_reg[27:24] == 4'b1010 ) ) | |
203 | `PR_ALWAYS("ch_mon",`DBG_0,"ERROR: SB_Config field has a reserved value of %h in it!",tr_reg[27:24]); | |
204 | ||
205 | `endif | |
206 | tr_count=0; | |
207 | tr_state<=`IDLE; | |
208 | end | |
209 | end | |
210 | ||
211 | endcase | |
212 | ||
213 | end | |
214 | endmodule | |
215 | ||
216 | `endif // AXIS_FBDIMM_HW |