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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dtm_training.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dtm_training(link_clk,dtm_ps,dtm_ps_bar,ps,ps_bar,rst,dtm_enabled,tr_complete,dtm_sb_dummy); | |
36 | ||
37 | input link_clk; | |
38 | input [9:0] ps; | |
39 | input [9:0] ps_bar; | |
40 | input dtm_enabled; | |
41 | output [9:0] dtm_ps; | |
42 | output [9:0] dtm_ps_bar; | |
43 | output tr_complete; | |
44 | output [9:0] dtm_sb_dummy; | |
45 | output rst; | |
46 | reg [9:0] dtm_ps_reg; | |
47 | reg [9:0] dtm_ps_bar_reg; | |
48 | reg [11:0] ts0_header; | |
49 | reg [11:0] ts0_grp1,dtm_ts0_pattern_num; | |
50 | reg [11:0] ts0_grp2_11; | |
51 | reg [7:0] pattern_counter; | |
52 | reg [143:0] dtm_ts0_pattern; | |
53 | reg [9:0] required_delay; | |
54 | reg [11:0] num_ts0; | |
55 | reg init_reg; | |
56 | reg dtm_en; | |
57 | wire init; | |
58 | reg [3:0] num_nop; | |
59 | reg dummy; | |
60 | reg [3:0] reinit_count; | |
61 | reg tr_complete_reg; | |
62 | wire tr_complete_reg_d1,tr_complete_reg_d2; | |
63 | reg rst_reg; | |
64 | reg rst_reg_cnt; | |
65 | reg dtm_tr_complete_reg; | |
66 | reg [9:0] dtm_sb_dummy_reg; // Prepare headers according to the MCU SB data | |
67 | wire link_clk_en = (ps === ps_bar)? 1'b1 : ~(init_reg)? 1'b0 : 1'b1; | |
68 | wire link_clk_int = link_clk & link_clk_en; | |
69 | assign dtm_ps = dtm_ps_reg; | |
70 | assign dtm_ps_bar = dtm_ps_bar_reg; | |
71 | assign tr_complete = tr_complete_reg_d1; | |
72 | assign dtm_sb_dummy = dtm_sb_dummy_reg; | |
73 | assign init = (link_clk_en)? 1'b1 : init_reg; | |
74 | assign rst = rst_reg; | |
75 | ||
76 | initial begin | |
77 | ts0_header = 12'hbfe; | |
78 | ts0_grp1 = 12'h00a; | |
79 | ts0_grp2_11 = 12'haaa; | |
80 | dtm_ts0_pattern = {{10{ts0_grp2_11}},ts0_grp1,ts0_header}; | |
81 | pattern_counter = 8'h00; | |
82 | rst_reg_cnt = 1; | |
83 | rst_reg = 0; | |
84 | reinit_count = 0; | |
85 | required_delay = 0; | |
86 | dtm_ps_reg = 10'hxxx; | |
87 | dtm_ps_bar_reg = 10'hxxx; | |
88 | ||
89 | `ifdef PALLADIUM | |
90 | dtm_en = dtm_enabled; | |
91 | `else | |
92 | #10 dtm_en = dtm_enabled; | |
93 | `endif | |
94 | ||
95 | num_nop = 10; | |
96 | num_ts0 = 0; | |
97 | dtm_ts0_pattern_num=25; | |
98 | dummy=$value$plusargs("dtm_ts0_pattern=%h",dtm_ts0_pattern_num); | |
99 | init_reg = 1; | |
100 | tr_complete_reg = 0; | |
101 | end | |
102 | ||
103 | `ifdef FBDIMM_BUG_107438 | |
104 | always@(dtm_enabled) | |
105 | dtm_en <= dtm_enabled; | |
106 | `endif | |
107 | ||
108 | always @(negedge link_clk_int) | |
109 | begin | |
110 | required_delay = required_delay + 1; | |
111 | if(reinit_count > 0) reinit_count = reinit_count - 1; | |
112 | if(dtm_en == 1'b1 && required_delay == 10'd840 && reinit_count == 0) | |
113 | begin | |
114 | if(rst_reg_cnt > 0) | |
115 | begin | |
116 | rst_reg_cnt = rst_reg_cnt - 1; | |
117 | rst_reg = 1; | |
118 | end | |
119 | else rst_reg = 0; | |
120 | dtm_ps_reg = {10{dtm_ts0_pattern[pattern_counter]}}; | |
121 | dtm_ps_bar_reg = ~dtm_ps_reg; | |
122 | dtm_sb_dummy_reg = ps; | |
123 | if(pattern_counter == 0) | |
124 | num_ts0 = num_ts0+1; | |
125 | pattern_counter = (pattern_counter + 1)%144; | |
126 | if(num_ts0 == dtm_ts0_pattern_num) | |
127 | begin | |
128 | required_delay = 10'd500; | |
129 | end | |
130 | else | |
131 | required_delay = 10'd839; | |
132 | end | |
133 | else if(dtm_en == 1'b1 && required_delay !== 10'd840 && reinit_count == 0) | |
134 | begin | |
135 | dtm_ps_reg = 10'h0; | |
136 | dtm_ps_bar_reg = 10'h3ff; | |
137 | dtm_sb_dummy_reg = ps; | |
138 | if(required_delay == 10'd572 && (num_ts0 == dtm_ts0_pattern_num)) | |
139 | begin | |
140 | dtm_en = 1'b0; | |
141 | tr_complete_reg = 1; | |
142 | num_ts0 = 0; | |
143 | init_reg = 0; | |
144 | end | |
145 | else tr_complete_reg = 0; | |
146 | end | |
147 | else if(dtm_en == 1'b0 || reinit_count > 0) | |
148 | begin | |
149 | if(init) | |
150 | begin | |
151 | //dtm_en = 1; | |
152 | init_reg = 1; | |
153 | required_delay = 10'd813; | |
154 | tr_complete_reg = 0; | |
155 | num_ts0 = 0; | |
156 | pattern_counter = 8'h00; | |
157 | if(reinit_count == 0) reinit_count = 4'd12; | |
158 | end | |
159 | dtm_ps_reg = ps; | |
160 | dtm_ps_bar_reg = ps_bar; | |
161 | dtm_sb_dummy_reg = ps; | |
162 | if(dtm_ps_reg === dtm_ps_bar_reg) //Even X's will be considered equal | |
163 | begin | |
164 | rst_reg = 1; | |
165 | rst_reg_cnt = 1; | |
166 | end | |
167 | if(reinit_count > 0) reinit_count = reinit_count - 1; | |
168 | end | |
169 | end | |
170 | ||
171 | ||
172 | shifter_p #(1) delay_tr_complete1 (.signal_in ( tr_complete_reg ), | |
173 | .signal_out ( tr_complete_reg_d1 ), | |
174 | .delay_cycles ( 10'd48), | |
175 | .clk ( link_clk )); | |
176 | shifter_p #(1) delay_tr_complete2 (.signal_in ( tr_complete_reg_d1 ), | |
177 | .signal_out ( tr_complete_reg_d2 ), | |
178 | .delay_cycles ( 10'd108), | |
179 | .clk ( link_clk )); | |
180 | endmodule |