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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fbdimm_nb_fsr.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module fbdimm_nb_fsr(reset, | |
36 | pn0_in, | |
37 | pn1_in, | |
38 | pn2_in, | |
39 | pn3_in, | |
40 | pn4_in, | |
41 | pn5_in, | |
42 | pn6_in, | |
43 | pn7_in, | |
44 | pn8_in, | |
45 | pn9_in, | |
46 | pn10_in, | |
47 | pn11_in, | |
48 | pn_out, | |
49 | serdes_data_rdy, | |
50 | link_clk, | |
51 | ref_clk); | |
52 | parameter DS = 0; | |
53 | input reset; | |
54 | input [13:0] pn0_in,pn1_in,pn2_in,pn3_in,pn4_in,pn5_in,pn6_in,pn7_in,pn8_in,pn9_in,pn10_in,pn11_in; | |
55 | output [13:0] pn_out; | |
56 | input link_clk; | |
57 | input ref_clk; | |
58 | input serdes_data_rdy; | |
59 | ||
60 | reg [3:0] curr_state; | |
61 | reg [13:0] pn_out_reg; | |
62 | wire [13:0] pn_out_reg_d,pn_out_reg_idle; | |
63 | reg [3:0] fsr_counter; | |
64 | wire [13:0] pn_out_reg_shft; | |
65 | wire serdes_data_rdy_d; | |
66 | reg serdes_data_rdy_d1; | |
67 | reg [11:0] pn_shift_reg3,pn_shift_reg2,pn_shift_reg1,pn_shift_reg0; | |
68 | ||
69 | assign pn_out = pn_out_reg ; | |
70 | ||
71 | reg [11:0] pn_in_reg; | |
72 | reg [3:0] LastAMB_ID; | |
73 | ||
74 | ||
75 | initial begin | |
76 | curr_state = 0; | |
77 | ||
78 | if ($test$plusargs("1_FBDIMM")) | |
79 | LastAMB_ID=0; | |
80 | else if ($test$plusargs("2_FBDIMMS")) | |
81 | LastAMB_ID=1; | |
82 | else if ($test$plusargs("3_FBDIMMS")) | |
83 | LastAMB_ID=2; | |
84 | else if ($test$plusargs("4_FBDIMMS")) | |
85 | LastAMB_ID=3; | |
86 | else if ($test$plusargs("5_FBDIMMS")) | |
87 | LastAMB_ID=4; | |
88 | else if ($test$plusargs("6_FBDIMMS")) | |
89 | LastAMB_ID=5; | |
90 | else if ($test$plusargs("7_FBDIMMS")) | |
91 | LastAMB_ID=6; | |
92 | else if ($test$plusargs("8_FBDIMMS")) | |
93 | LastAMB_ID=7; | |
94 | else | |
95 | LastAMB_ID=0; | |
96 | ||
97 | ||
98 | end | |
99 | ||
100 | ||
101 | always@(posedge link_clk) | |
102 | begin | |
103 | case ( curr_state) | |
104 | 4'h0 : begin pn_out_reg <= pn11_in; end | |
105 | 4'h1 : begin pn_out_reg <= pn0_in; end | |
106 | 4'h2 : begin pn_out_reg <= pn1_in; end | |
107 | 4'h3 : begin pn_out_reg <= pn2_in; end | |
108 | 4'h4 : begin pn_out_reg <= pn3_in; end | |
109 | 4'h5 : begin pn_out_reg <= pn4_in; end | |
110 | 4'h6 : begin pn_out_reg <= pn5_in; end | |
111 | 4'h7 : begin pn_out_reg <= pn6_in; end | |
112 | 4'h8 : begin pn_out_reg <= pn7_in; end | |
113 | 4'h9 : begin pn_out_reg <= pn8_in; end | |
114 | 4'ha: begin pn_out_reg <= pn9_in; end | |
115 | 4'hb: begin pn_out_reg <= pn10_in; end | |
116 | endcase | |
117 | ||
118 | end | |
119 | ||
120 | ||
121 | always@(negedge link_clk ) | |
122 | begin | |
123 | case ( curr_state ) | |
124 | 4'h0: begin | |
125 | if ( ref_clk ) | |
126 | curr_state <= 4'h1; | |
127 | end | |
128 | 4'h1: begin | |
129 | curr_state <= 4'h2; | |
130 | end | |
131 | 4'h2: begin | |
132 | curr_state <= 4'h3; | |
133 | end | |
134 | 4'h3: begin | |
135 | curr_state <= 4'h4; | |
136 | end | |
137 | 4'h4: begin | |
138 | curr_state <= 4'h5; | |
139 | end | |
140 | 4'h5: begin | |
141 | curr_state <= 4'h6; | |
142 | end | |
143 | 4'h6: begin | |
144 | curr_state <= 4'h7; | |
145 | end | |
146 | 4'h7: begin | |
147 | curr_state <= 4'h8; | |
148 | end | |
149 | 4'h8: begin | |
150 | curr_state <= 4'h9; | |
151 | end | |
152 | 4'h9: begin | |
153 | curr_state <= 4'ha; | |
154 | end | |
155 | 4'ha: begin | |
156 | curr_state <= 4'hb; | |
157 | end | |
158 | 4'hb: begin | |
159 | curr_state <= 4'h0; | |
160 | end | |
161 | endcase | |
162 | ||
163 | end | |
164 | ||
165 | endmodule | |
166 |