Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: sb_decode_crc.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module sb_decode_crc ( ps_in , ps_bar_in, ss , ss_bar , | |
36 | rbuffer_rd,rbuffer_rd_data,rbuffer_empty, | |
37 | config_reg_rd,config_reg_data, | |
38 | send_status_frm,sync_cmd, | |
39 | fbdreg_dcalcsr,fbdreg_dcaladdr,fbdreg_drc, | |
40 | fbdreg_dareftc,fbdreg_synctrainint,fbdreg_mtr, | |
41 | fbdreg_curr_cmd_to_data,fbdreg_curr_cmd_to_data_inc, | |
42 | fbdreg_next_cmd_to_data,fbdreg_next_cmd_to_data_inc, | |
43 | fbds0,fbds1,fbds2,fbds3, | |
44 | fbdreg_emask,fbdreg_ferr,fbdreg_nerr, | |
45 | `ifdef AXIS_FBDIMM_NO_FSR | |
46 | `else | |
47 | link_clk, link_clk_bar, | |
48 | `endif | |
49 | dram_clk,dram_2x_clk,init, write_fifo_empty, | |
50 | soft_channel_reset, sb_crc_error,ref_2x_clk, | |
51 | sb_config, nop_frame_detected, | |
52 | command_in,command_type,command_rdy,data_in,data_out,reset, | |
53 | get_wbuffer_data,put_rbuffer_data, | |
54 | l0sdur_reg, recalibdur_reg,frm_begin,frm_boundary, clear_dcalcsr31, | |
55 | dram_cmd_vld_delayed,cke_reg_delayed, | |
56 | enter_recalibrate,enter_los,clk_int, | |
57 | ps0_in,ps1_in,ps2_in,ps3_in,ps4_in,ps5_in,ps6_in,ps7_in,ps8_in,ps9_in,ps10_in,ps11_in | |
58 | ); | |
59 | // Parameters | |
60 | parameter SB_LINK = 10; | |
61 | parameter DS = 0; | |
62 | ||
63 | `define SB_IDLE 0 | |
64 | `define SB_STATE1 1 | |
65 | `define SB_STATE2 2 | |
66 | `define SB_STATE3 3 | |
67 | ||
68 | ||
69 | input [SB_LINK-1:0] ps_in,ps_bar_in; // primary southbound | |
70 | output [SB_LINK-1:0] ss,ss_bar; // secondary southbound | |
71 | input [SB_LINK-1:0] ps0_in,ps1_in,ps2_in,ps3_in,ps4_in,ps5_in,ps6_in,ps7_in,ps8_in,ps9_in,ps10_in,ps11_in; | |
72 | output [23:0] command_in; | |
73 | output [71:0] data_in; | |
74 | input [71:0] data_out; | |
75 | inout [31:0] fbdreg_dcalcsr,fbdreg_dcaladdr,fbdreg_drc; | |
76 | output [31:0] fbdreg_emask,fbdreg_ferr,fbdreg_nerr; | |
77 | output [31:0] l0sdur_reg; | |
78 | output [31:0] recalibdur_reg; | |
79 | output [31:0] fbdreg_dareftc,fbdreg_synctrainint; | |
80 | output [71:0] rbuffer_rd_data; | |
81 | output [31:0] config_reg_data; | |
82 | output [23:0] sync_cmd; | |
83 | output [7:0] fbdreg_curr_cmd_to_data,fbdreg_curr_cmd_to_data_inc; | |
84 | output [7:0] fbdreg_next_cmd_to_data,fbdreg_next_cmd_to_data_inc; | |
85 | input [7:0] fbds0,fbds1,fbds2,fbds3; | |
86 | output [7:0] fbdreg_mtr; | |
87 | input [3:0] sb_config; | |
88 | input nop_frame_detected; | |
89 | output write_fifo_empty; // = write_fifo.rempty; | |
90 | output enter_recalibrate,enter_los; | |
91 | `ifdef AXIS_FBDIMM_NO_FSR | |
92 | `else | |
93 | input link_clk,link_clk_bar; | |
94 | `endif | |
95 | input dram_clk,dram_2x_clk; | |
96 | input rbuffer_rd; | |
97 | input dram_cmd_vld_delayed; | |
98 | input ref_2x_clk; | |
99 | input cke_reg_delayed; | |
100 | output rbuffer_empty; | |
101 | input init; // =1 if we are in initialization | |
102 | output config_reg_rd; | |
103 | output send_status_frm; | |
104 | output soft_channel_reset; | |
105 | output sb_crc_error; | |
106 | output command_rdy; | |
107 | output [1:0] command_type; | |
108 | input get_wbuffer_data; | |
109 | input put_rbuffer_data; | |
110 | input reset; | |
111 | input clk_int; | |
112 | input frm_begin; | |
113 | input frm_boundary; | |
114 | input clear_dcalcsr31; | |
115 | ||
116 | wire [SB_LINK-1:0] ps,ps_bar; | |
117 | wire [SB_LINK-1:0] ps0,ps1,ps2,ps3,ps4,ps5,ps6,ps7,ps8,ps9,ps10,ps11; | |
118 | wire [31:0] fbdreg_reccfg_wire; | |
119 | wire [15:0] fbdreg_recfbd0_wire; | |
120 | wire [15:0] fbdreg_recfbd1_wire; | |
121 | wire [15:0] fbdreg_recfbd2_wire; | |
122 | wire [15:0] fbdreg_recfbd3_wire; | |
123 | wire [15:0] fbdreg_recfbd4_wire; | |
124 | wire [15:0] fbdreg_recfbd5_wire; | |
125 | wire [15:0] fbdreg_recfbd6_wire; | |
126 | wire [15:0] fbdreg_recfbd7_wire; | |
127 | wire [15:0] fbdreg_recfbd8_wire; | |
128 | wire [15:0] fbdreg_recfbd9_wire; | |
129 | wire [13:0] CRC14; | |
130 | wire [21:0] CRC22; | |
131 | wire [9:0] CRC10_cmd_failover,CRC10_data_failover; | |
132 | wire [13:0] Write_Frame_Wire_d; | |
133 | wire [23:0] command_select; | |
134 | wire [71:0] RDATA; | |
135 | wire [71:0] wdata; | |
136 | wire [71:0] wfifo_rd_data; | |
137 | wire [71:0] dram_io_data_out; | |
138 | wire [71:0] wbuffer_rd_data; | |
139 | wire [71:0] wbuffer_wr_data; | |
140 | wire [21:0] calc_FE; | |
141 | wire [13:0] calc_aE; | |
142 | wire [31:0] cmd2data_reg; | |
143 | wire [31:0] fn3_off74_reg; | |
144 | wire [9:0] sync_detected; | |
145 | wire [31:0] wcfg_data; | |
146 | wire disable_state; | |
147 | wire fewedges_wire; | |
148 | wire wfifo_full; | |
149 | wire wbuffer_full; | |
150 | wire wbuffer_empty; | |
151 | wire dram_io_put_rbuffer_data; | |
152 | wire inv_wr,inv_rd; | |
153 | wire Write_Config_reg_d1,Write_Config_reg_d2,Write_Config_reg_d3,Write_Config_reg_d4; | |
154 | ||
155 | ||
156 | //internal registers | |
157 | reg [SB_LINK-1:0] trans_3,trans_2,trans_1,trans_0; | |
158 | reg [23:0] aC,bC,cC; | |
159 | reg [71:0] aData; | |
160 | reg [21:0] FE; | |
161 | reg [31:0] D; | |
162 | reg [71:0] WDATA; | |
163 | reg [4:0] curr_state,next_state; | |
164 | reg [2:0] WS; | |
165 | reg [3:0] WS_tmp,BE; | |
166 | reg [13:0] FE_latch,aE; | |
167 | reg [1:0] Write_Frame_Count,F; | |
168 | reg [12:0] sync_counter_reg; | |
169 | reg [13:0] Test_aE,Test_FE,calc_aE_reg,Test1_FE; | |
170 | reg [21:0] calc_FE_latch_reg,calc_FE_reg; | |
171 | reg [71:0] Data_72; | |
172 | reg [25:0] Command_26; | |
173 | reg [31:0] cfg_data; | |
174 | reg [11:0] frmdata_0,frmdata_1,frmdata_2,frmdata_3,frmdata_4,frmdata_5; | |
175 | reg [11:0] frmdata_6,frmdata_7,frmdata_8,frmdata_9; | |
176 | reg [10:0] Write_Config_addr_reg; | |
177 | reg Curr_Command_A_is_Sync,Prev_Command_A_is_Sync; | |
178 | reg Curr_Command_A_is_SoftReset,Prev_Command_A_is_SoftReset; | |
179 | reg command_A_rdy,command_B_rdy,command_C_rdy; | |
180 | reg Write_Frame_Reg; | |
181 | reg invalidate_Write_FIFO_reg; | |
182 | reg sb_crc_error_reg,sb_crc_error_reg_d; | |
183 | reg cfg_rd,reset_sync; | |
184 | reg [23:0] sync_cmd_data; | |
185 | reg [2:0] cmd_B[3:0], cmd_C[3:0]; | |
186 | reg sync_detected_reg; | |
187 | reg sync_cmd_rdy; | |
188 | reg Last_TID; | |
189 | wire failover_sb; | |
190 | reg bypass_init; | |
191 | reg sng_channel; | |
192 | reg Write_Config_reg; | |
193 | reg sb_fsm_start,sb_fsm_start_1; | |
194 | reg [2:0] sb_fsm_curr_state; | |
195 | reg data_crc_err,cmd_crc_err; | |
196 | reg [3:0] wf_counter; | |
197 | reg write_buffer_fifo_reg; | |
198 | ||
199 | // integers | |
200 | integer index; | |
201 | ||
202 | ||
203 | `ifdef AXIS_FBDIMM_HW | |
204 | wire [31:0] axis_rdata; | |
205 | wire [31:0] axis_wdata= wcfg_data; | |
206 | wire [10:0] axis_raddr= command_select[10:0]; | |
207 | wire [10:0] axis_waddr = Write_Config_addr_reg; | |
208 | wire axis_wen = Write_Config_reg_d4; | |
209 | ||
210 | ||
211 | `ifdef PALLADIUM | |
212 | reg [31:0] register_memory [0:2047]; | |
213 | reg [31:0] axis_rdata_reg; | |
214 | ||
215 | assign axis_rdata = axis_rdata_reg; | |
216 | ||
217 | always @ (axis_raddr) | |
218 | begin | |
219 | axis_rdata_reg = register_memory[axis_raddr]; | |
220 | end | |
221 | ||
222 | always @ (axis_wen or axis_wdata or axis_waddr) | |
223 | begin | |
224 | if(axis_wen) | |
225 | register_memory[axis_waddr] = axis_wdata; | |
226 | end | |
227 | ||
228 | `else | |
229 | ||
230 | axis_smem #(11,32,2,0) register_memory ( {axis_rdata,32'bz}, // output port | |
231 | {32'bz,axis_wdata}, // input port | |
232 | {axis_raddr,axis_waddr}, //address port | |
233 | {1'b0 ,axis_wen}, // write enable | |
234 | {1'b1,1'b1}, // chip enable | |
235 | {1'bz,1'bz}, // clock | |
236 | {32'bz,32'bz}); | |
237 | `endif | |
238 | ||
239 | ||
240 | `else | |
241 | reg [31:0] register_memory[0:2048]; | |
242 | `endif | |
243 | ||
244 | ||
245 | // Assignments | |
246 | ||
247 | ||
248 | wire [71:0] dq_out; | |
249 | wire [2:0] ws_fifo_data; | |
250 | wire write_buffer_fifo = write_buffer_fifo_reg; | |
251 | ||
252 | ||
253 | assign command_in = command_select; | |
254 | assign command_rdy = ( command_A_rdy | command_B_rdy | command_C_rdy) & ~sb_crc_error_reg; | |
255 | assign command_type = ( command_A_rdy ) ? 2'h3: | |
256 | ( command_B_rdy ) ? 2'h1: | |
257 | ( command_C_rdy ) ? 2'h2: 2'h0; | |
258 | ||
259 | assign data_in = wfifo_rd_data; | |
260 | assign dram_io_data_out = data_out; | |
261 | assign dram_io_put_rbuffer_data = put_rbuffer_data; | |
262 | ||
263 | assign failover_sb = ( sb_config !== 4'b1111 ); | |
264 | ||
265 | assign ps0 = ( sb_config == 4'b1111 ) ? ps0_in : // all lanes are good | |
266 | ( sb_config == 4'b1001 ) ? {1'b0,ps0_in[8:0]} : // map out lane 9 | |
267 | ( sb_config == 4'b1000 ) ? {1'b0,ps0_in[9],ps0_in[7:0]} : // map out lane 8 | |
268 | ( sb_config == 4'b0111 ) ? {1'b0,ps0_in[9:8],ps0_in[6:0]} : // map out lane 7 | |
269 | ( sb_config == 4'b0110 ) ? {1'b0,ps0_in[9:7],ps0_in[5:0]} : // map out lane 6 | |
270 | ( sb_config == 4'b0101 ) ? {1'b0,ps0_in[9:6],ps0_in[4:0]} : // map out lane 5 | |
271 | ( sb_config == 4'b0100 ) ? {1'b0,ps0_in[9:5],ps0_in[3:0]} : // map out lane 4 | |
272 | ( sb_config == 4'b0011 ) ? {1'b0,ps0_in[9:4],ps0_in[2:0]} : // map out lane 3 | |
273 | ( sb_config == 4'b0010 ) ? {1'b0,ps0_in[9:3],ps0_in[1:0]} : // map out lane 2 | |
274 | ( sb_config == 4'b0001 ) ? {1'b0,ps0_in[9:2],ps0_in[0]} : // map out lane 1 | |
275 | ( sb_config == 4'b0000 ) ? {1'b0,ps0_in[9:1]} : ps0_in ; // map out lane 0 | |
276 | ||
277 | assign ps1 = ( sb_config == 4'b1111 ) ? ps1_in : // all lanes are good | |
278 | ( sb_config == 4'b1001 ) ? {1'b0,ps1_in[8:0]} : // map out lane 9 | |
279 | ( sb_config == 4'b1000 ) ? {1'b0,ps1_in[9],ps1_in[7:0]} : // map out lane 8 | |
280 | ( sb_config == 4'b0111 ) ? {1'b0,ps1_in[9:8],ps1_in[6:0]} : // map out lane 7 | |
281 | ( sb_config == 4'b0110 ) ? {1'b0,ps1_in[9:7],ps1_in[5:0]} : // map out lane 6 | |
282 | ( sb_config == 4'b0101 ) ? {1'b0,ps1_in[9:6],ps1_in[4:0]} : // map out lane 5 | |
283 | ( sb_config == 4'b0100 ) ? {1'b0,ps1_in[9:5],ps1_in[3:0]} : // map out lane 4 | |
284 | ( sb_config == 4'b0011 ) ? {1'b0,ps1_in[9:4],ps1_in[2:0]} : // map out lane 3 | |
285 | ( sb_config == 4'b0010 ) ? {1'b0,ps1_in[9:3],ps1_in[1:0]} : // map out lane 2 | |
286 | ( sb_config == 4'b0001 ) ? {1'b0,ps1_in[9:2],ps1_in[0]} : // map out lane 1 | |
287 | ( sb_config == 4'b0000 ) ? {1'b0,ps1_in[9:1]} : ps1_in ; // map out lane 0 | |
288 | assign ps2 = ( sb_config == 4'b1111 ) ? ps2_in : // all lanes are good | |
289 | ( sb_config == 4'b1001 ) ? {1'b0,ps2_in[8:0]} : // map out lane 9 | |
290 | ( sb_config == 4'b1000 ) ? {1'b0,ps2_in[9],ps2_in[7:0]} : // map out lane 8 | |
291 | ( sb_config == 4'b0111 ) ? {1'b0,ps2_in[9:8],ps2_in[6:0]} : // map out lane 7 | |
292 | ( sb_config == 4'b0110 ) ? {1'b0,ps2_in[9:7],ps2_in[5:0]} : // map out lane 6 | |
293 | ( sb_config == 4'b0101 ) ? {1'b0,ps2_in[9:6],ps2_in[4:0]} : // map out lane 5 | |
294 | ( sb_config == 4'b0100 ) ? {1'b0,ps2_in[9:5],ps2_in[3:0]} : // map out lane 4 | |
295 | ( sb_config == 4'b0011 ) ? {1'b0,ps2_in[9:4],ps2_in[2:0]} : // map out lane 3 | |
296 | ( sb_config == 4'b0010 ) ? {1'b0,ps2_in[9:3],ps2_in[1:0]} : // map out lane 2 | |
297 | ( sb_config == 4'b0001 ) ? {1'b0,ps2_in[9:2],ps2_in[0]} : // map out lane 1 | |
298 | ( sb_config == 4'b0000 ) ? {1'b0,ps2_in[9:1]} : ps2_in ; // map out lane 0 | |
299 | assign ps3 = ( sb_config == 4'b1111 ) ? ps3_in : // all lanes are good | |
300 | ( sb_config == 4'b1001 ) ? {1'b0,ps3_in[8:0]} : // map out lane 9 | |
301 | ( sb_config == 4'b1000 ) ? {1'b0,ps3_in[9],ps3_in[7:0]} : // map out lane 8 | |
302 | ( sb_config == 4'b0111 ) ? {1'b0,ps3_in[9:8],ps3_in[6:0]} : // map out lane 7 | |
303 | ( sb_config == 4'b0110 ) ? {1'b0,ps3_in[9:7],ps3_in[5:0]} : // map out lane 6 | |
304 | ( sb_config == 4'b0101 ) ? {1'b0,ps3_in[9:6],ps3_in[4:0]} : // map out lane 5 | |
305 | ( sb_config == 4'b0100 ) ? {1'b0,ps3_in[9:5],ps3_in[3:0]} : // map out lane 4 | |
306 | ( sb_config == 4'b0011 ) ? {1'b0,ps3_in[9:4],ps3_in[2:0]} : // map out lane 3 | |
307 | ( sb_config == 4'b0010 ) ? {1'b0,ps3_in[9:3],ps3_in[1:0]} : // map out lane 2 | |
308 | ( sb_config == 4'b0001 ) ? {1'b0,ps3_in[9:2],ps3_in[0]} : // map out lane 1 | |
309 | ( sb_config == 4'b0000 ) ? {1'b0,ps3_in[9:1]} : ps3_in ; // map out lane 0 | |
310 | assign ps4 = ( sb_config == 4'b1111 ) ? ps4_in : // all lanes are good | |
311 | ( sb_config == 4'b1001 ) ? {1'b0,ps4_in[8:0]} : // map out lane 9 | |
312 | ( sb_config == 4'b1000 ) ? {1'b0,ps4_in[9],ps4_in[7:0]} : // map out lane 8 | |
313 | ( sb_config == 4'b0111 ) ? {1'b0,ps4_in[9:8],ps4_in[6:0]} : // map out lane 7 | |
314 | ( sb_config == 4'b0110 ) ? {1'b0,ps4_in[9:7],ps4_in[5:0]} : // map out lane 6 | |
315 | ( sb_config == 4'b0101 ) ? {1'b0,ps4_in[9:6],ps4_in[4:0]} : // map out lane 5 | |
316 | ( sb_config == 4'b0100 ) ? {1'b0,ps4_in[9:5],ps4_in[3:0]} : // map out lane 4 | |
317 | ( sb_config == 4'b0011 ) ? {1'b0,ps4_in[9:4],ps4_in[2:0]} : // map out lane 3 | |
318 | ( sb_config == 4'b0010 ) ? {1'b0,ps4_in[9:3],ps4_in[1:0]} : // map out lane 2 | |
319 | ( sb_config == 4'b0001 ) ? {1'b0,ps4_in[9:2],ps4_in[0]} : // map out lane 1 | |
320 | ( sb_config == 4'b0000 ) ? {1'b0,ps4_in[9:1]} : ps4_in ; // map out lane 0 | |
321 | assign ps5 = ( sb_config == 4'b1111 ) ? ps5_in : // all lanes are good | |
322 | ( sb_config == 4'b1001 ) ? {1'b0,ps5_in[8:0]} : // map out lane 9 | |
323 | ( sb_config == 4'b1000 ) ? {1'b0,ps5_in[9],ps5_in[7:0]} : // map out lane 8 | |
324 | ( sb_config == 4'b0111 ) ? {1'b0,ps5_in[9:8],ps5_in[6:0]} : // map out lane 7 | |
325 | ( sb_config == 4'b0110 ) ? {1'b0,ps5_in[9:7],ps5_in[5:0]} : // map out lane 6 | |
326 | ( sb_config == 4'b0101 ) ? {1'b0,ps5_in[9:6],ps5_in[4:0]} : // map out lane 5 | |
327 | ( sb_config == 4'b0100 ) ? {1'b0,ps5_in[9:5],ps5_in[3:0]} : // map out lane 4 | |
328 | ( sb_config == 4'b0011 ) ? {1'b0,ps5_in[9:4],ps5_in[2:0]} : // map out lane 3 | |
329 | ( sb_config == 4'b0010 ) ? {1'b0,ps5_in[9:3],ps5_in[1:0]} : // map out lane 2 | |
330 | ( sb_config == 4'b0001 ) ? {1'b0,ps5_in[9:2],ps5_in[0]} : // map out lane 1 | |
331 | ( sb_config == 4'b0000 ) ? {1'b0,ps5_in[9:1]} : ps5_in ; // map out lane 0 | |
332 | assign ps6 = ( sb_config == 4'b1111 ) ? ps6_in : // all lanes are good | |
333 | ( sb_config == 4'b1001 ) ? {1'b0,ps6_in[8:0]} : // map out lane 9 | |
334 | ( sb_config == 4'b1000 ) ? {1'b0,ps6_in[9],ps6_in[7:0]} : // map out lane 8 | |
335 | ( sb_config == 4'b0111 ) ? {1'b0,ps6_in[9:8],ps6_in[6:0]} : // map out lane 7 | |
336 | ( sb_config == 4'b0110 ) ? {1'b0,ps6_in[9:7],ps6_in[5:0]} : // map out lane 6 | |
337 | ( sb_config == 4'b0101 ) ? {1'b0,ps6_in[9:6],ps6_in[4:0]} : // map out lane 5 | |
338 | ( sb_config == 4'b0100 ) ? {1'b0,ps6_in[9:5],ps6_in[3:0]} : // map out lane 4 | |
339 | ( sb_config == 4'b0011 ) ? {1'b0,ps6_in[9:4],ps6_in[2:0]} : // map out lane 3 | |
340 | ( sb_config == 4'b0010 ) ? {1'b0,ps6_in[9:3],ps6_in[1:0]} : // map out lane 2 | |
341 | ( sb_config == 4'b0001 ) ? {1'b0,ps6_in[9:2],ps6_in[0]} : // map out lane 1 | |
342 | ( sb_config == 4'b0000 ) ? {1'b0,ps6_in[9:1]} : ps6_in ; // map out lane 0 | |
343 | assign ps7 = ( sb_config == 4'b1111 ) ? ps7_in : // all lanes are good | |
344 | ( sb_config == 4'b1001 ) ? {1'b0,ps7_in[8:0]} : // map out lane 9 | |
345 | ( sb_config == 4'b1000 ) ? {1'b0,ps7_in[9],ps7_in[7:0]} : // map out lane 8 | |
346 | ( sb_config == 4'b0111 ) ? {1'b0,ps7_in[9:8],ps7_in[6:0]} : // map out lane 7 | |
347 | ( sb_config == 4'b0110 ) ? {1'b0,ps7_in[9:7],ps7_in[5:0]} : // map out lane 6 | |
348 | ( sb_config == 4'b0101 ) ? {1'b0,ps7_in[9:6],ps7_in[4:0]} : // map out lane 5 | |
349 | ( sb_config == 4'b0100 ) ? {1'b0,ps7_in[9:5],ps7_in[3:0]} : // map out lane 4 | |
350 | ( sb_config == 4'b0011 ) ? {1'b0,ps7_in[9:4],ps7_in[2:0]} : // map out lane 3 | |
351 | ( sb_config == 4'b0010 ) ? {1'b0,ps7_in[9:3],ps7_in[1:0]} : // map out lane 2 | |
352 | ( sb_config == 4'b0001 ) ? {1'b0,ps7_in[9:2],ps7_in[0]} : // map out lane 1 | |
353 | ( sb_config == 4'b0000 ) ? {1'b0,ps7_in[9:1]} : ps7_in ; // map out lane 0 | |
354 | assign ps8 = ( sb_config == 4'b1111 ) ? ps8_in : // all lanes are good | |
355 | ( sb_config == 4'b1001 ) ? {1'b0,ps8_in[8:0]} : // map out lane 9 | |
356 | ( sb_config == 4'b1000 ) ? {1'b0,ps8_in[9],ps8_in[7:0]} : // map out lane 8 | |
357 | ( sb_config == 4'b0111 ) ? {1'b0,ps8_in[9:8],ps8_in[6:0]} : // map out lane 7 | |
358 | ( sb_config == 4'b0110 ) ? {1'b0,ps8_in[9:7],ps8_in[5:0]} : // map out lane 6 | |
359 | ( sb_config == 4'b0101 ) ? {1'b0,ps8_in[9:6],ps8_in[4:0]} : // map out lane 5 | |
360 | ( sb_config == 4'b0100 ) ? {1'b0,ps8_in[9:5],ps8_in[3:0]} : // map out lane 4 | |
361 | ( sb_config == 4'b0011 ) ? {1'b0,ps8_in[9:4],ps8_in[2:0]} : // map out lane 3 | |
362 | ( sb_config == 4'b0010 ) ? {1'b0,ps8_in[9:3],ps8_in[1:0]} : // map out lane 2 | |
363 | ( sb_config == 4'b0001 ) ? {1'b0,ps8_in[9:2],ps8_in[0]} : // map out lane 1 | |
364 | ( sb_config == 4'b0000 ) ? {1'b0,ps8_in[9:1]} : ps8_in ; // map out lane 0 | |
365 | assign ps9 = ( sb_config == 4'b1111 ) ? ps9_in : // all lanes are good | |
366 | ( sb_config == 4'b1001 ) ? {1'b0,ps9_in[8:0]} : // map out lane 9 | |
367 | ( sb_config == 4'b1000 ) ? {1'b0,ps9_in[9],ps9_in[7:0]} : // map out lane 8 | |
368 | ( sb_config == 4'b0111 ) ? {1'b0,ps9_in[9:8],ps9_in[6:0]} : // map out lane 7 | |
369 | ( sb_config == 4'b0110 ) ? {1'b0,ps9_in[9:7],ps9_in[5:0]} : // map out lane 6 | |
370 | ( sb_config == 4'b0101 ) ? {1'b0,ps9_in[9:6],ps9_in[4:0]} : // map out lane 5 | |
371 | ( sb_config == 4'b0100 ) ? {1'b0,ps9_in[9:5],ps9_in[3:0]} : // map out lane 4 | |
372 | ( sb_config == 4'b0011 ) ? {1'b0,ps9_in[9:4],ps9_in[2:0]} : // map out lane 3 | |
373 | ( sb_config == 4'b0010 ) ? {1'b0,ps9_in[9:3],ps9_in[1:0]} : // map out lane 2 | |
374 | ( sb_config == 4'b0001 ) ? {1'b0,ps9_in[9:2],ps9_in[0]} : // map out lane 1 | |
375 | ( sb_config == 4'b0000 ) ? {1'b0,ps9_in[9:1]} : ps9_in ; // map out lane 0 | |
376 | assign ps10 = ( sb_config == 4'b1111 ) ? ps10_in : // all lanes are good | |
377 | ( sb_config == 4'b1001 ) ? {1'b0,ps10_in[8:0]} : // map out lane 9 | |
378 | ( sb_config == 4'b1000 ) ? {1'b0,ps10_in[9],ps10_in[7:0]} : // map out lane 8 | |
379 | ( sb_config == 4'b0111 ) ? {1'b0,ps10_in[9:8],ps10_in[6:0]} : // map out lane 7 | |
380 | ( sb_config == 4'b0110 ) ? {1'b0,ps10_in[9:7],ps10_in[5:0]} : // map out lane 6 | |
381 | ( sb_config == 4'b0101 ) ? {1'b0,ps10_in[9:6],ps10_in[4:0]} : // map out lane 5 | |
382 | ( sb_config == 4'b0100 ) ? {1'b0,ps10_in[9:5],ps10_in[3:0]} : // map out lane 4 | |
383 | ( sb_config == 4'b0011 ) ? {1'b0,ps10_in[9:4],ps10_in[2:0]} : // map out lane 3 | |
384 | ( sb_config == 4'b0010 ) ? {1'b0,ps10_in[9:3],ps10_in[1:0]} : // map out lane 2 | |
385 | ( sb_config == 4'b0001 ) ? {1'b0,ps10_in[9:2],ps10_in[0]} : // map out lane 1 | |
386 | ( sb_config == 4'b0000 ) ? {1'b0,ps10_in[9:1]} : ps10_in ; // map out lane 0 | |
387 | assign ps11 = ( sb_config == 4'b1111 ) ? ps11_in : // all lanes are good | |
388 | ( sb_config == 4'b1001 ) ? {1'b0,ps11_in[8:0]} : // map out lane 9 | |
389 | ( sb_config == 4'b1000 ) ? {1'b0,ps11_in[9],ps11_in[7:0]} : // map out lane 8 | |
390 | ( sb_config == 4'b0111 ) ? {1'b0,ps11_in[9:8],ps11_in[6:0]} : // map out lane 7 | |
391 | ( sb_config == 4'b0110 ) ? {1'b0,ps11_in[9:7],ps11_in[5:0]} : // map out lane 6 | |
392 | ( sb_config == 4'b0101 ) ? {1'b0,ps11_in[9:6],ps11_in[4:0]} : // map out lane 5 | |
393 | ( sb_config == 4'b0100 ) ? {1'b0,ps11_in[9:5],ps11_in[3:0]} : // map out lane 4 | |
394 | ( sb_config == 4'b0011 ) ? {1'b0,ps11_in[9:4],ps11_in[2:0]} : // map out lane 3 | |
395 | ( sb_config == 4'b0010 ) ? {1'b0,ps11_in[9:3],ps11_in[1:0]} : // map out lane 2 | |
396 | ( sb_config == 4'b0001 ) ? {1'b0,ps11_in[9:2],ps11_in[0]} : // map out lane 1 | |
397 | ( sb_config == 4'b0000 ) ? {1'b0,ps11_in[9:1]} : ps11_in ; // map out lane 0 | |
398 | ||
399 | ||
400 | ||
401 | assign ps = ( sb_config == 4'b1111 ) ? ps_in : // all lanes are good | |
402 | ( sb_config == 4'b1001 ) ? {1'b0,ps_in[8:0]} : // map out lane 9 | |
403 | ( sb_config == 4'b1000 ) ? {1'b0,ps_in[9],ps_in[7:0]} : // map out lane 8 | |
404 | ( sb_config == 4'b0111 ) ? {1'b0,ps_in[9:8],ps_in[6:0]} : // map out lane 7 | |
405 | ( sb_config == 4'b0110 ) ? {1'b0,ps_in[9:7],ps_in[5:0]} : // map out lane 6 | |
406 | ( sb_config == 4'b0101 ) ? {1'b0,ps_in[9:6],ps_in[4:0]} : // map out lane 5 | |
407 | ( sb_config == 4'b0100 ) ? {1'b0,ps_in[9:5],ps_in[3:0]} : // map out lane 4 | |
408 | ( sb_config == 4'b0011 ) ? {1'b0,ps_in[9:4],ps_in[2:0]} : // map out lane 3 | |
409 | ( sb_config == 4'b0010 ) ? {1'b0,ps_in[9:3],ps_in[1:0]} : // map out lane 2 | |
410 | ( sb_config == 4'b0001 ) ? {1'b0,ps_in[9:2],ps_in[0]} : // map out lane 1 | |
411 | ( sb_config == 4'b0000 ) ? {1'b0,ps_in[9:1]} : ps_in ; // map out lane 0 | |
412 | ||
413 | assign ps_bar = ( sb_config == 4'b1111 ) ? ps_bar_in : // all lanes are good | |
414 | ( sb_config == 4'b1001 ) ? {1'b0,ps_bar_in[8:0]} : // map out lane 9 | |
415 | ( sb_config == 4'b1000 ) ? {1'b0,ps_bar_in[9],ps_bar_in[7:0]} : // map out lane 8 | |
416 | ( sb_config == 4'b0111 ) ? {1'b0,ps_bar_in[9:8],ps_bar_in[6:0]} : // map out lane 7 | |
417 | ( sb_config == 4'b0110 ) ? {1'b0,ps_bar_in[9:7],ps_bar_in[5:0]} : // map out lane 6 | |
418 | ( sb_config == 4'b0101 ) ? {1'b0,ps_bar_in[9:6],ps_bar_in[4:0]} : // map out lane 5 | |
419 | ( sb_config == 4'b0100 ) ? {1'b0,ps_bar_in[9:5],ps_bar_in[3:0]} : // map out lane 4 | |
420 | ( sb_config == 4'b0011 ) ? {1'b0,ps_bar_in[9:4],ps_bar_in[2:0]} : // map out lane 3 | |
421 | ( sb_config == 4'b0010 ) ? {1'b0,ps_bar_in[9:3],ps_bar_in[1:0]} : // map out lane 2 | |
422 | ( sb_config == 4'b0001 ) ? {1'b0,ps_bar_in[9:2],ps_bar_in[0]} : // map out lane 1 | |
423 | ( sb_config == 4'b0000 ) ? {1'b0,ps_bar_in[9:1]} : ps_bar_in ; // map out lane | |
424 | ||
425 | ||
426 | ||
427 | assign disable_state = ( ps_in == ps_bar_in ) ? 1'b1 : 1'b0; | |
428 | assign sync_detected[0] = sync_detected_reg; | |
429 | assign ss = ps_in; | |
430 | assign ss_bar = ps_bar_in; | |
431 | assign config_reg_rd = cfg_rd; | |
432 | assign config_reg_data = cfg_data; | |
433 | assign send_status_frm = sync_detected[1]; | |
434 | assign sync_cmd = sync_cmd_data; | |
435 | assign write_fifo_empty = write_fifo.rempty; | |
436 | assign soft_channel_reset = invalidate_Write_FIFO_reg; | |
437 | assign sb_crc_error = sb_crc_error_reg_d; | |
438 | assign enter_recalibrate = sync_detected_reg & aC[5]; | |
439 | assign enter_los = sync_detected_reg & aC[4]; | |
440 | assign inv_wr = invalidate_Write_FIFO_reg; | |
441 | assign wdata = WDATA; | |
442 | assign wbuffer_wr_data = {WDATA[71],WDATA[62],WDATA[53],WDATA[44],WDATA[35],WDATA[26],WDATA[17],WDATA[8], | |
443 | WDATA[70],WDATA[61],WDATA[52],WDATA[43],WDATA[34],WDATA[25],WDATA[16],WDATA[7], | |
444 | WDATA[69],WDATA[60],WDATA[51],WDATA[42],WDATA[33],WDATA[24],WDATA[15],WDATA[6], | |
445 | WDATA[68],WDATA[59],WDATA[50],WDATA[41],WDATA[32],WDATA[23],WDATA[14],WDATA[5], | |
446 | WDATA[67],WDATA[58],WDATA[49],WDATA[40],WDATA[31],WDATA[22],WDATA[13],WDATA[4], | |
447 | WDATA[66],WDATA[57],WDATA[48],WDATA[39],WDATA[30],WDATA[21],WDATA[12],WDATA[3], | |
448 | WDATA[65],WDATA[56],WDATA[47],WDATA[38],WDATA[29],WDATA[20],WDATA[11],WDATA[2], | |
449 | WDATA[64],WDATA[55],WDATA[46],WDATA[37],WDATA[28],WDATA[19],WDATA[10],WDATA[1], | |
450 | WDATA[63],WDATA[54],WDATA[45],WDATA[36],WDATA[27],WDATA[18],WDATA[9],WDATA[0] | |
451 | }; | |
452 | `ifdef AXIS_FBDIMM_1AMB | |
453 | assign command_select = (command_A_rdy ) ? aC[23:0] : | |
454 | (command_B_rdy ) ? bC[23:0] : | |
455 | (command_C_rdy ) ? cC[23:0] : 24'h0; | |
456 | `else | |
457 | assign command_select = (command_A_rdy && ( aC[23:21] == DS) ) ? aC[23:0] : | |
458 | (command_B_rdy && ( bC[23:21] == DS) ) ? bC[23:0] : | |
459 | (command_C_rdy && ( cC[23:21] == DS) ) ? cC[23:0] : 24'h0; | |
460 | `endif | |
461 | ||
462 | `ifdef AXIS_FBDIMM_HW | |
463 | assign fbdreg_dcalcsr = 32'h0; | |
464 | assign fbdreg_dcaladdr = 32'h0; | |
465 | //assign fbdreg_drc = 32'h33; | |
466 | reg [31:0] fbdreg_drc_tmp; | |
467 | `ifndef AL_DEFAULT | |
468 | `define AL_DEFAULT 3 | |
469 | `endif | |
470 | `ifndef CL_DEFAULT | |
471 | `define CL_DEFAULT 3 | |
472 | `endif | |
473 | ||
474 | initial fbdreg_drc_tmp <= { `AL_DEFAULT, `CL_DEFAULT }; | |
475 | assign fbdreg_drc = fbdreg_drc_tmp; | |
476 | assign fbdreg_emask = 32'h0; | |
477 | assign fbdreg_ferr = 32'h0; | |
478 | assign fbdreg_nerr = 32'h0; | |
479 | assign fbdreg_reccfg_wire = 32'h0; | |
480 | assign fbdreg_recfbd0_wire = 16'h0; | |
481 | assign fbdreg_recfbd1_wire = 16'h0; | |
482 | assign fbdreg_recfbd2_wire = 16'h0; | |
483 | assign fbdreg_recfbd3_wire = 16'h0; | |
484 | assign fbdreg_recfbd4_wire = 16'h0; | |
485 | assign fbdreg_recfbd5_wire = 16'h0; | |
486 | assign fbdreg_recfbd6_wire = 16'h0; | |
487 | assign fbdreg_recfbd7_wire = 16'h0; | |
488 | assign fbdreg_recfbd8_wire = 16'h0; | |
489 | assign fbdreg_recfbd9_wire = 16'h0; | |
490 | assign fbdreg_next_cmd_to_data = 8'h0; | |
491 | assign fbdreg_curr_cmd_to_data = 8'h0; | |
492 | assign fbdreg_next_cmd_to_data_inc = 8'h0; | |
493 | assign fbdreg_curr_cmd_to_data_inc = 8'h0; | |
494 | assign fbdreg_mtr = 8'h0; | |
495 | assign fbdreg_dareftc = 32'h004ec30; | |
496 | assign fbdreg_synctrainint = 32'h0; | |
497 | assign l0sdur_reg = 32'h043; | |
498 | `else | |
499 | assign fbdreg_dcalcsr = register_memory[{3'b100,8'h40}]; // function 4, offset 40h pg 97 | |
500 | assign fbdreg_dcaladdr = register_memory[{3'b100,8'h44}]; // function 4, offset 44h pg 97 | |
501 | assign fbdreg_drc = register_memory[{3'b011,8'h7c}]; // function 3, offset 7ch pg 97 | |
502 | assign fbdreg_emask = register_memory[{3'b001,8'h8c}]; // function 1 , offset 8ch pg 86 | |
503 | assign fbdreg_ferr = register_memory[{3'b001,8'h90}]; // function 1 , offset 90h pg 86 | |
504 | assign fbdreg_nerr = register_memory[{3'b001,8'h94}]; // function 1 , offset 94h pg 87 | |
505 | assign fbdreg_reccfg_wire = register_memory[{3'b001,8'h98}]; // function 1 , offset 98h pg 88 | |
506 | assign fbdreg_dareftc = register_memory[{3'b011,8'h70}]; // function 3 , offset 70h pg 119 | |
507 | assign fbdreg_synctrainint = register_memory[{3'b001,8'h78}]; // function 1 , offset 78h pg 103 | |
508 | assign cmd2data_reg = register_memory[{3'b001,8'he8}]; // function 1, offset e8 pg 90 | |
509 | assign fbdreg_next_cmd_to_data = cmd2data_reg[7:0]; | |
510 | assign fbdreg_curr_cmd_to_data = cmd2data_reg[15:8]; | |
511 | assign fbdreg_next_cmd_to_data_inc = cmd2data_reg[23:16]; | |
512 | assign fbdreg_curr_cmd_to_data_inc = cmd2data_reg[31:24]; | |
513 | assign l0sdur_reg = register_memory[{3'b001,8'h74}]; | |
514 | assign recalibdur_reg = register_memory[{3'b001,8'h70}]; | |
515 | assign fn3_off74_reg = register_memory[{3'b011,8'h74}]; | |
516 | assign fbdreg_mtr = fn3_off74_reg[7:0]; | |
517 | assign fewedges_wire = ( sync_counter_reg == 13'd1009 ) ? 1'b1 : 1'b0; | |
518 | ||
519 | // First ERROR | |
520 | always@(fewedges_wire or sb_crc_error) | |
521 | register_memory[{3'b001,8'h90}] <= {26'h0,1'b0,1'b0,fewedges_wire,1'b0,1'b0,sb_crc_error}; | |
522 | ||
523 | // Next ERROR | |
524 | always@(fewedges_wire or sb_crc_error) | |
525 | register_memory[{3'b001,8'h94}] <= {26'h0,1'b0,1'b0,fewedges_wire,1'b0,1'b0,sb_crc_error}; | |
526 | ||
527 | ||
528 | `endif | |
529 | ||
530 | ||
531 | ||
532 | ||
533 | // Initialization | |
534 | // Note: For now, generate a dummy reset signal | |
535 | initial begin | |
536 | ||
537 | sb_fsm_start = 0; | |
538 | sb_fsm_curr_state=`SB_IDLE; | |
539 | sb_crc_error_reg_d =0; | |
540 | Write_Frame_Reg = 0; | |
541 | wf_counter=1; | |
542 | Data_72=0; | |
543 | FE=0; | |
544 | ||
545 | `ifdef AXIS_FBDIMM_HW | |
546 | `else | |
547 | for(index=0; index <= 2047; index = index+1) | |
548 | begin | |
549 | register_memory[index]=32'h0; | |
550 | end | |
551 | ||
552 | `ifdef STINGRAY | |
553 | `else | |
554 | $readmemh("fbdimm_register.data",register_memory); | |
555 | `endif | |
556 | ||
557 | if ( $test$plusargs("fbdimm_dbg")) | |
558 | $ch_dispmon("sb_decode",`DBG_0,1); | |
559 | ||
560 | if ( $test$plusargs("fbdimm_dbg_1")) | |
561 | $ch_dispmon("sb_decode",`DBG_1,1); | |
562 | ||
563 | if ( $test$plusargs("fbdimm_dbg_2")) | |
564 | $ch_dispmon("sb_decode",`DBG_2,1); | |
565 | ||
566 | if ( $test$plusargs("fbdimm_dbg_3")) | |
567 | $ch_dispmon("sb_decode",`DBG_3,1); | |
568 | ||
569 | if ( $test$plusargs("fbdimm_dbg_4")) | |
570 | $ch_dispmon("sb_decode",`DBG_4,1); | |
571 | ||
572 | `endif | |
573 | ||
574 | if ( $test$plusargs("bypass_init")) | |
575 | bypass_init = 1; | |
576 | else | |
577 | bypass_init = 0; | |
578 | ||
579 | if ( $test$plusargs("SNG_CHANNEL")) | |
580 | sng_channel = 1; | |
581 | else | |
582 | sng_channel = 0; | |
583 | ||
584 | invalidate_Write_FIFO_reg=1; | |
585 | curr_state = `TRANSFER_0; | |
586 | next_state = `TRANSFER_0; | |
587 | Write_Frame_Count =0; | |
588 | sync_detected_reg=0; | |
589 | sb_crc_error_reg=0; | |
590 | calc_aE_reg=0; | |
591 | calc_FE_reg=0; | |
592 | reset_sync=1'b1; | |
593 | WS=0; | |
594 | WS_tmp=0; | |
595 | Last_TID=0; | |
596 | ||
597 | ||
598 | end | |
599 | ||
600 | ||
601 | `ifdef AXIS_FBDIMM_NO_FSR | |
602 | `else | |
603 | `ifdef AXIS_FBDIMM_HW | |
604 | `else | |
605 | always@(link_clk) | |
606 | begin | |
607 | register_memory[{3'b001,8'h40}]<= {24'h0,fbds0}; // fbds0 register from nb | |
608 | register_memory[{3'b001,8'h41}]<= {24'h0,fbds1}; // fbds1 register from nb | |
609 | register_memory[{3'b001,8'h42}]<= {24'h0,fbds2}; // fbds2 register from nb | |
610 | register_memory[{3'b001,8'h43}]<= {24'h0,fbds3}; // fbds3 register from nb | |
611 | end | |
612 | `endif // AXIS_FBDIMM_HW | |
613 | `endif // AXIS_FBDIMM_NO_FSR | |
614 | ||
615 | // Main state machine to sample data bus | |
616 | ||
617 | ||
618 | always@(posedge frm_boundary ) | |
619 | sb_crc_error_reg_d <= sb_crc_error_reg; | |
620 | ||
621 | ||
622 | ||
623 | always@(negedge clk_int) | |
624 | sb_fsm_start <= 1; | |
625 | ||
626 | always@(posedge frm_begin) if ( sb_fsm_start ) | |
627 | sb_fsm_start_1 <= 1; | |
628 | ||
629 | ||
630 | // CRC checking mechanism to generate alert frames | |
631 | ||
632 | always@(posedge clk_int) | |
633 | begin | |
634 | ||
635 | if ( soft_channel_reset | disable_state ) | |
636 | sb_crc_error_reg<=0; | |
637 | ||
638 | if ( sb_fsm_curr_state == `SB_STATE1 ) | |
639 | begin | |
640 | if ( failover_sb ) | |
641 | FE_latch <= {CRC10_data_failover[9:0],4'h0}; | |
642 | else | |
643 | FE_latch <= CRC22[13:0]; | |
644 | end | |
645 | ||
646 | ||
647 | if ( sb_fsm_curr_state == `SB_STATE2 ) | |
648 | begin | |
649 | if (!failover_sb) | |
650 | begin | |
651 | if(Prev_Command_A_is_SoftReset && (aE !== 14'h0)) | |
652 | begin | |
653 | `ifdef AXIS_FBDIMM_NO_FSR | |
654 | sb_crc_error_reg<=1; | |
655 | cmd_crc_err = 1; | |
656 | `else | |
657 | if ( {ps3[5],ps2[5],ps1[5]} == DS ) begin// if the frame was meant for this AMB\ | |
658 | sb_crc_error_reg<=1; | |
659 | cmd_crc_err = 1; | |
660 | end | |
661 | `endif | |
662 | end | |
663 | if ( !Prev_Command_A_is_Sync & !Prev_Command_A_is_SoftReset ) | |
664 | if ( ((FE_latch[13] ^ aE[13]) !== CRC14[13] ) || | |
665 | ((FE_latch[12] ^ aE[12]) !== CRC14[12] ) || | |
666 | ((FE_latch[11] ^ aE[11]) !== CRC14[11] ) || | |
667 | ((FE_latch[10] ^ aE[10]) !== CRC14[10] ) || | |
668 | ((FE_latch[09] ^ aE[09]) !== CRC14[09] ) || | |
669 | ((FE_latch[08] ^ aE[08]) !== CRC14[08] ) || | |
670 | ((FE_latch[07] ^ aE[07]) !== CRC14[07] ) || | |
671 | ((FE_latch[06] ^ aE[06]) !== CRC14[06] ) || | |
672 | ((FE_latch[05] ^ aE[05]) !== CRC14[05] ) || | |
673 | ((FE_latch[04] ^ aE[04]) !== CRC14[04] ) || | |
674 | ((FE_latch[03] ^ aE[03]) !== CRC14[03] ) || | |
675 | ((FE_latch[02] ^ aE[02]) !== CRC14[02] ) || | |
676 | ((FE_latch[01] ^ aE[01]) !== CRC14[01] ) || | |
677 | ((FE_latch[00] ^ aE[00]) !== CRC14[00] ) | |
678 | ) | |
679 | begin | |
680 | `ifdef AXIS_FBDIMM_NO_FSR | |
681 | sb_crc_error_reg<=1; | |
682 | cmd_crc_err = 1; | |
683 | `else | |
684 | if ( {ps3[5],ps2[5],ps1[5]} == DS ) begin// if the frame was meant for this AMB | |
685 | sb_crc_error_reg<=1; | |
686 | cmd_crc_err = 1; | |
687 | end | |
688 | `endif | |
689 | end | |
690 | else if ( /*sync_detected_reg |*/ soft_channel_reset | disable_state ) | |
691 | sb_crc_error_reg<=0; | |
692 | ||
693 | end | |
694 | ||
695 | ||
696 | if (failover_sb) | |
697 | begin | |
698 | if(Prev_Command_A_is_SoftReset && aE[9:0] !== 10'h0) | |
699 | begin | |
700 | `ifdef AXIS_FBDIMM_NO_FSR | |
701 | sb_crc_error_reg<=1; | |
702 | cmd_crc_err = 1; | |
703 | `else | |
704 | if ( {ps3[5],ps2[5],ps1[5]} == DS ) begin// if the frame was meant for this AMB\ | |
705 | sb_crc_error_reg<=1; | |
706 | cmd_crc_err = 1; | |
707 | end | |
708 | `endif | |
709 | end | |
710 | if ( !Prev_Command_A_is_Sync & !Prev_Command_A_is_SoftReset ) | |
711 | if ( ((FE_latch[13] ^ aE[09]) !== CRC10_cmd_failover[09] ) || | |
712 | ((FE_latch[12] ^ aE[08]) !== CRC10_cmd_failover[08] ) || | |
713 | ((FE_latch[11] ^ aE[07]) !== CRC10_cmd_failover[07] ) || | |
714 | ((FE_latch[10] ^ aE[06]) !== CRC10_cmd_failover[06] ) || | |
715 | ((FE_latch[09] ^ aE[05]) !== CRC10_cmd_failover[05] ) || | |
716 | ((FE_latch[08] ^ aE[04]) !== CRC10_cmd_failover[04] ) || | |
717 | ((FE_latch[07] ^ aE[03]) !== CRC10_cmd_failover[03] ) || | |
718 | ((FE_latch[06] ^ aE[02]) !== CRC10_cmd_failover[02] ) || | |
719 | ((FE_latch[05] ^ aE[01]) !== CRC10_cmd_failover[01] ) || | |
720 | ((FE_latch[04] ^ aE[00]) !== CRC10_cmd_failover[00] ) | |
721 | ) | |
722 | begin | |
723 | `ifdef AXIS_FBDIMM_NO_FSR | |
724 | sb_crc_error_reg<=1; | |
725 | `PR_ALWAYS ("sb_decode",`DBG_1,"ERROR: Command has CRC mismatch => Test_aE %h != aE %h \n",FE_latch[13:4] ^ aE[9:0], CRC10_cmd_failover[9:0]); | |
726 | `else | |
727 | ||
728 | if ( {ps3[5],ps2[5],ps1[5]} == DS ) // if the frame was meant for this AMB | |
729 | sb_crc_error_reg<=1; | |
730 | `endif | |
731 | ||
732 | end | |
733 | else if ( /*sync_detected_reg*/ | soft_channel_reset | disable_state) | |
734 | sb_crc_error_reg<=0; | |
735 | ||
736 | end | |
737 | ||
738 | end | |
739 | ||
740 | if ( sb_fsm_curr_state == `SB_STATE3 ) | |
741 | begin | |
742 | ||
743 | if ( failover_sb ) | |
744 | Test1_FE[13:0] = {CRC10_cmd_failover[09] ^ aE[09], | |
745 | CRC10_cmd_failover[08] ^ aE[08], | |
746 | CRC10_cmd_failover[07] ^ aE[07], | |
747 | CRC10_cmd_failover[06] ^ aE[06], | |
748 | CRC10_cmd_failover[05] ^ aE[05], | |
749 | CRC10_cmd_failover[04] ^ aE[04], | |
750 | CRC10_cmd_failover[03] ^ aE[03], | |
751 | CRC10_cmd_failover[02] ^ aE[02], | |
752 | CRC10_cmd_failover[01] ^ aE[01], | |
753 | CRC10_cmd_failover[00] ^ aE[00], | |
754 | 1'b0, | |
755 | 1'b0, | |
756 | 1'b0, | |
757 | 1'b0}; | |
758 | else | |
759 | Test1_FE[13:0] = {CRC14[13] ^ aE[13], | |
760 | CRC14[12] ^ aE[12], | |
761 | CRC14[11] ^ aE[11], | |
762 | CRC14[10] ^ aE[10], | |
763 | CRC14[09] ^ aE[09], | |
764 | CRC14[08] ^ aE[08], | |
765 | CRC14[07] ^ aE[07], | |
766 | CRC14[06] ^ aE[06], | |
767 | CRC14[05] ^ aE[05], | |
768 | CRC14[04] ^ aE[04], | |
769 | CRC14[03] ^ aE[03], | |
770 | CRC14[02] ^ aE[02], | |
771 | CRC14[01] ^ aE[01], | |
772 | CRC14[00] ^ aE[00]}; | |
773 | ||
774 | ||
775 | if ( !failover_sb ) | |
776 | if ( !Prev_Command_A_is_Sync & !Prev_Command_A_is_SoftReset ) | |
777 | if ( ((CRC14[13] ^ aE[13]) !== FE_latch[13] ) || | |
778 | ((CRC14[12] ^ aE[12]) !== FE_latch[12] ) || | |
779 | ((CRC14[11] ^ aE[11]) !== FE_latch[11] ) || | |
780 | ((CRC14[10] ^ aE[10]) !== FE_latch[10] ) || | |
781 | ((CRC14[09] ^ aE[09]) !== FE_latch[09] ) || | |
782 | ((CRC14[08] ^ aE[08]) !== FE_latch[08] ) || | |
783 | ((CRC14[07] ^ aE[07]) !== FE_latch[07] ) || | |
784 | ((CRC14[06] ^ aE[06]) !== FE_latch[06] ) || | |
785 | ((CRC14[05] ^ aE[05]) !== FE_latch[05] ) || | |
786 | ((CRC14[04] ^ aE[04]) !== FE_latch[04] ) || | |
787 | ((CRC14[03] ^ aE[03]) !== FE_latch[03] ) || | |
788 | ((CRC14[02] ^ aE[02]) !== FE_latch[02] ) || | |
789 | ((CRC14[01] ^ aE[01]) !== FE_latch[01] ) || | |
790 | ((CRC14[00] ^ aE[00]) !== FE_latch[00] )) | |
791 | begin | |
792 | `ifdef AXIS_FBDIMM_NO_FSR | |
793 | sb_crc_error_reg<=1; | |
794 | `PR_ALWAYS ("sb_decode",`DBG_1,"ERROR: Data has CRC mismatch Test1_FE = %h != FE = %h\n",Test1_FE,FE_latch); | |
795 | `else | |
796 | if ( {ps3[5],ps2[5],ps1[5]} == DS ) // if the frame was meant for this AMB | |
797 | sb_crc_error_reg<=1; | |
798 | `endif | |
799 | ||
800 | end | |
801 | else if ( /*sync_detected_reg |*/ soft_channel_reset | disable_state) | |
802 | sb_crc_error_reg<=1'b0; | |
803 | ||
804 | ||
805 | ||
806 | if ( failover_sb ) | |
807 | if ( !Prev_Command_A_is_Sync & !Prev_Command_A_is_SoftReset ) | |
808 | if ( ((CRC10_cmd_failover[09] ^ aE[09]) !== FE_latch[13] ) || | |
809 | ((CRC10_cmd_failover[08] ^ aE[08]) !== FE_latch[12] ) || | |
810 | ((CRC10_cmd_failover[07] ^ aE[07]) !== FE_latch[11] ) || | |
811 | ((CRC10_cmd_failover[06] ^ aE[06]) !== FE_latch[10] ) || | |
812 | ((CRC10_cmd_failover[05] ^ aE[05]) !== FE_latch[09] ) || | |
813 | ((CRC10_cmd_failover[04] ^ aE[04]) !== FE_latch[08] ) || | |
814 | ((CRC10_cmd_failover[03] ^ aE[03]) !== FE_latch[07] ) || | |
815 | ((CRC10_cmd_failover[02] ^ aE[02]) !== FE_latch[06] ) || | |
816 | ((CRC10_cmd_failover[01] ^ aE[01]) !== FE_latch[05] ) || | |
817 | ((CRC10_cmd_failover[00] ^ aE[00]) !== FE_latch[04] )) | |
818 | begin | |
819 | `ifdef AXIS_FBDIMM_NO_FSR | |
820 | sb_crc_error_reg<=1'b1; | |
821 | `else | |
822 | if ( {ps3[5],ps2[5],ps1[5]} == DS ) // if the frame was meant for this AMB | |
823 | sb_crc_error_reg<=1'b1; | |
824 | `endif | |
825 | end | |
826 | else if ( /*sync_detected_reg |*/ soft_channel_reset | disable_state) | |
827 | sb_crc_error_reg<=1'b0; | |
828 | ||
829 | end // if sb_fsm_curr_state == sb_state3 | |
830 | ||
831 | ||
832 | if ( sb_fsm_curr_state == `SB_STATE1 ) | |
833 | begin | |
834 | ||
835 | // 10th bit lane carries pattern info for sync frames so we will not do this check for sycn frames | |
836 | ||
837 | ||
838 | if ( !failover_sb ) | |
839 | if ( !Curr_Command_A_is_Sync & !Curr_Command_A_is_SoftReset ) | |
840 | if ( FE[21:14] !== CRC22[21:14] ) begin | |
841 | `ifdef AXIS_FBDIMM_NO_FSR | |
842 | sb_crc_error_reg<=1'b1; | |
843 | data_crc_err = 1; | |
844 | `else | |
845 | `ifdef AXIS_FBDIMM_HW | |
846 | `else | |
847 | `PR_ALWAYS ("sb_decode",`DBG_1,"ERROR: Data has CRC mismatch Test2_FE[21:14] = %h != CRC[21:14] = %h\n",FE[21:14], CRC22[21:14]); | |
848 | `endif | |
849 | if ( {ps3[5],ps2[5],ps1[5]} == DS ) begin// if the frame was meant for this AMB | |
850 | sb_crc_error_reg<=1'b1; | |
851 | data_crc_err = 1; | |
852 | end | |
853 | `endif | |
854 | end | |
855 | else if ( /*sync_detected_reg |*/ soft_channel_reset | disable_state) | |
856 | sb_crc_error_reg<=1'b0; | |
857 | ||
858 | ||
859 | end // if sb_fsm_curr_state == sb_state1 | |
860 | ||
861 | ||
862 | end | |
863 | ||
864 | wire ts0_pattern_start; | |
865 | ||
866 | voting_logic check_LSB3 (.a ( {ps0[0],ps1[0],ps2[0],ps3[0],ps4[0],ps5[0],ps6[0],ps7[0],ps8[0],ps9[0],ps10[0],ps11[0]} == 12'h7fd ), | |
867 | .b ( {ps0[1],ps1[1],ps2[1],ps3[1],ps4[1],ps5[1],ps6[1],ps7[1],ps8[1],ps9[1],ps10[1],ps11[1]} == 12'h7fd ), | |
868 | .c ( {ps0[2],ps1[2],ps2[2],ps3[2],ps4[2],ps5[2],ps6[2],ps7[2],ps8[2],ps9[2],ps10[2],ps11[2]} == 12'h7fd ), | |
869 | .out ( ts0_pattern_start ) ); | |
870 | ||
871 | ||
872 | `ifdef DTM_ENABLED | |
873 | ||
874 | reg init_d1; | |
875 | always@(posedge frm_boundary) | |
876 | init_d1 <= ~nop_frame_detected ; | |
877 | ||
878 | `else | |
879 | wire init_d1; | |
880 | assign init_d1 = init; | |
881 | `endif | |
882 | ||
883 | always@(negedge clk_int) | |
884 | begin | |
885 | if ( ~init) | |
886 | reset_sync=0; | |
887 | ||
888 | case ( sb_fsm_curr_state ) | |
889 | `SB_IDLE: begin | |
890 | if ( bypass_init && sb_fsm_start_1 ) | |
891 | sb_fsm_curr_state <= `SB_STATE1; | |
892 | ||
893 | if ( ts0_pattern_start ) | |
894 | sb_fsm_curr_state <= `SB_STATE1; | |
895 | end | |
896 | `SB_STATE1: if ( disable_state ) sb_fsm_curr_state <= `SB_IDLE; | |
897 | else if ( ~init_d1 ) begin | |
898 | // Latch FE | |
899 | calc_FE_latch_reg <= FE; | |
900 | Prev_Command_A_is_Sync <= Curr_Command_A_is_Sync; | |
901 | Prev_Command_A_is_SoftReset <= Curr_Command_A_is_SoftReset; | |
902 | ||
903 | if ( sb_config == 4'hf ) begin | |
904 | {aE[0],aE[7],aE[08], F[00],aC[20],aC[16],aC[12],aC[08],aC[4],aC[0]} = ps0[9:0]; | |
905 | {aE[1],aE[6],aE[09], F[01],aC[21],aC[17],aC[13],aC[09],aC[5],aC[1]} = ps1[9:0]; | |
906 | {aE[2],aE[5],aE[10],aE[13],aC[22],aC[18],aC[14],aC[10],aC[6],aC[2]} = ps2[9:0]; | |
907 | {aE[3],aE[4],aE[11],aE[12],aC[23],aC[19],aC[15],aC[11],aC[7],aC[3]} = ps3[9:0]; | |
908 | ||
909 | {Command_26[20],Command_26[19],Command_26[12],Command_26[11],Command_26[4],Command_26[3]}=ps3[5:0]; | |
910 | {Command_26[21],Command_26[18],Command_26[13],Command_26[10],Command_26[5],Command_26[2]}=ps2[5:0]; | |
911 | {Command_26[25],Command_26[22],Command_26[17],Command_26[14],Command_26[09],Command_26[6],Command_26[1]}=ps1[6:0]; | |
912 | {Command_26[24],Command_26[23],Command_26[16],Command_26[15],Command_26[08],Command_26[7],Command_26[0]}=ps0[6:0]; | |
913 | ||
914 | {FE[0],FE[7],FE[8]}={ps0[9],ps0[8],ps0[7]}; | |
915 | {FE[1],FE[6],FE[9]}={ps1[9],ps1[8],ps1[7]}; | |
916 | {FE[2],FE[5],FE[10],FE[13]}={ps2[9],ps2[8],ps2[7],ps2[6]}; | |
917 | {FE[3],FE[4],FE[11],FE[12]}={ps3[9],ps3[8],ps3[7],ps3[6]}; | |
918 | ||
919 | ||
920 | if ( ( ps0 == 10'h0 ) && | |
921 | ( ps1 == 10'h0 ) && | |
922 | ( ps2 == 10'h0 ) && | |
923 | ( ps3 == 10'h8 ) && | |
924 | ( ps4 == 10'h2aa ) && | |
925 | ( ps5 == 10'h155 ) && | |
926 | ( ps6 == 10'h2aa ) && | |
927 | ( ps7 == 10'h155 ) && | |
928 | ( ps8 == 10'h2aa ) && | |
929 | ( ps9 == 10'h155 ) && | |
930 | ( ps10 == 10'h2aa ) && | |
931 | ( ps11 == 10'h155 ) ) | |
932 | begin | |
933 | // Since soft channel reset is detected, invalidate all Write fifos | |
934 | invalidate_Write_FIFO_reg = 1'b1; | |
935 | end | |
936 | else | |
937 | invalidate_Write_FIFO_reg = 1'b0; | |
938 | `ifdef AXIS_FBDIMM_1AMB | |
939 | command_A_rdy <= 1; | |
940 | `else | |
941 | if ( { ps3[5],ps2[5],ps1[5]} == DS ) begin | |
942 | command_A_rdy <= 1; | |
943 | end | |
944 | `endif | |
945 | if ( {ps0[5],ps3[4],ps2[4],ps1[4],ps0[4],ps3[3],ps2[3]} == 6'h1 /* aC[20:14] == 6'h1*/) | |
946 | begin | |
947 | `ifdef AXIS_FBDIMM_HW | |
948 | `else | |
949 | sync_detected_reg <= 1; | |
950 | `endif | |
951 | Curr_Command_A_is_Sync<=1; | |
952 | end | |
953 | else | |
954 | Curr_Command_A_is_Sync<=0; | |
955 | ||
956 | if ( {ps0[5],ps3[4],ps2[4],ps1[4],ps0[4],ps3[3],ps2[3]} == 6'h2 ) | |
957 | begin | |
958 | Curr_Command_A_is_SoftReset <=1; | |
959 | end | |
960 | else | |
961 | Curr_Command_A_is_SoftReset <=0; | |
962 | ||
963 | ||
964 | sync_cmd_rdy<=1; | |
965 | ||
966 | ||
967 | command_C_rdy <= 0; | |
968 | if ( ps1[6] == 1 ) begin // if f1=1 | |
969 | WS_tmp[3:0] <= {ps0[6],WS_tmp[3:1]}; | |
970 | Write_Frame_Reg <= 1; | |
971 | end | |
972 | else | |
973 | Write_Frame_Reg <= 0; | |
974 | ||
975 | end else begin // failover sb mode | |
976 | ||
977 | {aE[03],aE[04], F[00],aC[20],aC[16],aC[12],aC[08],aC[4],aC[0]} = ps0[8:0]; | |
978 | {aE[02],aE[05], F[01],aC[21],aC[17],aC[13],aC[09],aC[5],aC[1]} = ps1[8:0]; | |
979 | {aE[01],aE[06],aE[09],aC[22],aC[18],aC[14],aC[10],aC[6],aC[2]} = ps2[8:0]; | |
980 | {aE[00],aE[07],aE[08],aC[23],aC[19],aC[15],aC[11],aC[7],aC[3]} = ps3[8:0]; | |
981 | ||
982 | {Command_26[24],Command_26[23],Command_26[16],Command_26[15],Command_26[08],Command_26[7],Command_26[0]}=ps0[6:0]; | |
983 | {Command_26[25],Command_26[22],Command_26[17],Command_26[14],Command_26[09],Command_26[6],Command_26[1]}=ps1[6:0]; | |
984 | {Command_26[21],Command_26[18],Command_26[13],Command_26[10],Command_26[5],Command_26[2]}=ps2[5:0]; | |
985 | {Command_26[20],Command_26[19],Command_26[12],Command_26[11],Command_26[4],Command_26[3]}=ps3[5:0]; | |
986 | ||
987 | {FE[3],FE[4]}={ps0[8],ps0[7]}; | |
988 | {FE[2],FE[5]}={ps1[8],ps1[7]}; | |
989 | {FE[1],FE[6],FE[9]}={ps2[8],ps2[7],ps2[6]}; | |
990 | {FE[0],FE[7],FE[8]}={ps3[8],ps3[7],ps3[6]}; | |
991 | ||
992 | ||
993 | if ( ( ps0 == 10'h0 ) && | |
994 | ( ps1 == 10'h0 ) && | |
995 | ( ps2 == 10'h0 ) && | |
996 | ( ps3 == 10'h8 ) && | |
997 | ( ps4 == 10'h2aa ) && | |
998 | ( ps5 == 10'h155 ) && | |
999 | ( ps6 == 10'h2aa ) && | |
1000 | ( ps7 == 10'h155 ) && | |
1001 | ( ps8 == 10'h2aa ) && | |
1002 | ( ps9 == 10'h155 ) && | |
1003 | ( ps10 == 10'h2aa ) && | |
1004 | ( ps11 == 10'h155 ) ) | |
1005 | begin | |
1006 | invalidate_Write_FIFO_reg = 1'b1; | |
1007 | end | |
1008 | else | |
1009 | invalidate_Write_FIFO_reg = 1'b0; | |
1010 | `ifdef AXIS_FBDIMM_1AMB | |
1011 | command_A_rdy <= 1; | |
1012 | `else | |
1013 | if ( { ps3[5],ps2[5],ps1[5]} == DS ) begin | |
1014 | command_A_rdy <= 1; | |
1015 | end | |
1016 | `endif | |
1017 | if ( {ps0[5],ps3[4],ps2[4],ps1[4],ps0[4],ps3[3],ps2[3]} == 6'h1 /* aC[20:14] == 6'h1*/) | |
1018 | Curr_Command_A_is_Sync<=1; | |
1019 | else | |
1020 | Curr_Command_A_is_Sync<=0; | |
1021 | ||
1022 | if ( {ps0[5],ps3[4],ps2[4],ps1[4],ps0[4],ps3[3],ps2[3]} == 6'h2 /* aC[20:14] == 6'h1*/) | |
1023 | Curr_Command_A_is_SoftReset<=1; | |
1024 | else | |
1025 | Curr_Command_A_is_SoftReset<=0; | |
1026 | ||
1027 | sync_cmd_rdy<=1; | |
1028 | ||
1029 | command_C_rdy <= 0; | |
1030 | if ( ps1[6] == 1 ) begin // if f1=1 | |
1031 | WS_tmp[3:0] <= {ps0[6],WS_tmp[3:1]}; | |
1032 | Write_Frame_Reg <= 1; | |
1033 | end | |
1034 | else | |
1035 | Write_Frame_Reg <= 0; | |
1036 | ||
1037 | end | |
1038 | ||
1039 | ||
1040 | sb_fsm_curr_state <= `SB_STATE2; | |
1041 | end | |
1042 | `SB_STATE2: begin | |
1043 | ||
1044 | if ( disable_state ) sb_fsm_curr_state <= `SB_IDLE; | |
1045 | else begin | |
1046 | Write_Frame_Reg <= 0; | |
1047 | ||
1048 | ||
1049 | if ( sb_config == 4'hf ) begin | |
1050 | FE[21]=ps4[9]; | |
1051 | FE[20]=ps5[9]; | |
1052 | FE[19]=ps6[9]; | |
1053 | FE[18]=ps7[9]; | |
1054 | end | |
1055 | ||
1056 | {bC[20],bC[16],bC[12],bC[08],bC[4],bC[0]}=ps4[5:0]; | |
1057 | {bC[21],bC[17],bC[13],bC[09],bC[5],bC[1]}=ps5[5:0]; | |
1058 | {bC[22],bC[18],bC[14],bC[10],bC[6],bC[2]}=ps6[5:0]; | |
1059 | {bC[23],bC[19],bC[15],bC[11],bC[7],bC[3]}=ps7[5:0]; | |
1060 | ||
1061 | WDATA[08:00]=ps4[8:0]; | |
1062 | WDATA[17:09]=ps5[8:0]; | |
1063 | WDATA[26:18]=ps6[8:0]; | |
1064 | WDATA[35:27]=ps7[8:0]; | |
1065 | ||
1066 | Data_72[8:0]=ps4[8:0]; | |
1067 | Data_72[17:9]={ps5[0],ps5[1],ps5[2],ps5[3],ps5[4],ps5[5],ps5[6],ps5[7],ps5[8]}; | |
1068 | Data_72[26:18]=ps6[8:0]; | |
1069 | Data_72[35:27]={ps7[0],ps7[1],ps7[2],ps7[3],ps7[4],ps7[5],ps7[6],ps7[7],ps7[8]}; | |
1070 | ||
1071 | command_A_rdy <= 0; | |
1072 | sync_cmd_rdy<=0; | |
1073 | calc_aE_reg<=calc_aE; | |
1074 | ||
1075 | ||
1076 | `ifdef AXIS_FBDIMM_1AMB | |
1077 | if ( (ps4[8:6] == 3'h0 ) && | |
1078 | (ps5[8:6] == 3'h0 ) && | |
1079 | (ps6[8:6] == 3'h0 ) && | |
1080 | (ps7[8:6] == 3'h0 ) && ({ps1[6],ps0[6]} == 2'h0 )) begin | |
1081 | command_B_rdy <= 1; | |
1082 | end | |
1083 | `else | |
1084 | if ( (ps4[8:6] == 3'h0 ) && | |
1085 | (ps5[8:6] == 3'h0 ) && | |
1086 | (ps6[8:6] == 3'h0 ) && | |
1087 | (ps7[8:6] == 3'h0 ) && ({ps7[5],ps6[5],ps5[5]} == DS) && ({ps1[6],ps0[6]} == 2'h0 )) begin | |
1088 | command_B_rdy <= 1; | |
1089 | end | |
1090 | `endif | |
1091 | ||
1092 | sb_fsm_curr_state <= `SB_STATE3; | |
1093 | end // if ( disable_state ) | |
1094 | ||
1095 | end | |
1096 | `SB_STATE3: begin | |
1097 | ||
1098 | if ( disable_state ) sb_fsm_curr_state <= `SB_IDLE; | |
1099 | else begin | |
1100 | ||
1101 | if ( sb_config == 4'hf ) begin | |
1102 | FE[17]=ps8[9]; | |
1103 | FE[16]=ps9[9]; | |
1104 | FE[15]=ps10[9]; | |
1105 | FE[14]=ps11[9]; | |
1106 | end | |
1107 | ||
1108 | command_B_rdy <= 0; | |
1109 | {cC[20],cC[16],cC[12],cC[8],cC[4],cC[0]}=ps8[5:0]; | |
1110 | {cC[21],cC[17],cC[13],cC[9],cC[5],cC[1]}=ps9[5:0]; | |
1111 | {cC[22],cC[18],cC[14],cC[10],cC[6],cC[2]}=ps10[5:0]; | |
1112 | {cC[23],cC[19],cC[15],cC[11],cC[7],cC[3]}=ps11[5:0]; | |
1113 | ||
1114 | ||
1115 | {BE[0],D[28],D[24],D[20],D[16],D[12],D[8],D[4],D[0]}=ps8[8:0]; | |
1116 | {BE[1],D[29],D[25],D[21],D[17],D[13],D[9],D[5],D[1]}=ps9[8:0]; | |
1117 | {BE[2],D[30],D[26],D[22],D[18],D[14],D[10],D[6],D[2]}=ps10[8:0]; | |
1118 | {BE[3],D[31],D[27],D[23],D[19],D[15],D[11],D[7],D[3]}=ps11[8:0]; | |
1119 | ||
1120 | cmd_C[0]=ps8[8:6]; | |
1121 | cmd_C[1]=ps[8:6]; | |
1122 | cmd_C[2]=ps[8:6]; | |
1123 | ||
1124 | WDATA[44:36]=ps8[8:0]; | |
1125 | WDATA[53:45]=ps9[8:0]; | |
1126 | WDATA[62:54]=ps10[8:0]; | |
1127 | WDATA[71:63]=ps11[8:0]; | |
1128 | ||
1129 | Data_72[44:36]=ps8[8:0]; | |
1130 | Data_72[53:45]={ps9[0],ps9[1],ps9[2],ps9[3],ps9[4],ps9[5],ps9[6],ps9[7],ps9[8]}; | |
1131 | Data_72[62:54]=ps10[8:0]; | |
1132 | Data_72[71:63]={ps11[0],ps11[1],ps11[2],ps11[3],ps11[4],ps11[5],ps11[6],ps11[7],ps11[8]}; | |
1133 | ||
1134 | ||
1135 | Write_Frame_Reg <= 0; | |
1136 | ||
1137 | `ifdef AXIS_FBDIMM_1AMB | |
1138 | if ( (ps8[8:6] == 3'h0 ) && | |
1139 | (ps9[8:6] == 3'h0 ) && | |
1140 | (ps10[8:6] == 3'h0 ) && | |
1141 | (ps11[8:6] == 3'h0 ) && ({ps0[6],ps1[6]} == 2'h0) ) begin | |
1142 | command_C_rdy <= 1; | |
1143 | end | |
1144 | `else | |
1145 | if ( (ps8[8:6] == 3'h0 ) && | |
1146 | (ps9[8:6] == 3'h0 ) && | |
1147 | (ps10[8:6] == 3'h0 ) && | |
1148 | (ps11[8:6] == 3'h0 ) && ({ps11[5],ps10[5],ps9[5]} == DS) && ({ps0[6],ps1[6]} == 2'h0) ) begin | |
1149 | command_C_rdy <= 1; | |
1150 | end | |
1151 | `endif | |
1152 | WS <=WS_tmp[2:0]; | |
1153 | Write_Frame_Count[1:0] <= Write_Frame_Count[1:0] + 2'b1; | |
1154 | ||
1155 | if ( ps == ps_bar ) | |
1156 | sb_fsm_curr_state <= `SB_IDLE; | |
1157 | else | |
1158 | sb_fsm_curr_state <= `SB_STATE1; | |
1159 | ||
1160 | end | |
1161 | end // if ( disable_state) | |
1162 | ||
1163 | endcase | |
1164 | ||
1165 | end | |
1166 | ||
1167 | ||
1168 | // Channel Commands | |
1169 | ||
1170 | `ifdef AXIS_FBDIMM_NO_FSR | |
1171 | always@(posedge clk_int) | |
1172 | `else | |
1173 | always@(posedge link_clk) | |
1174 | `endif | |
1175 | begin | |
1176 | // channel reset command | |
1177 | ||
1178 | ||
1179 | // write config command | |
1180 | if ( command_B_rdy && ( bC[20:14] == 7'b0000101 ) && ( bC[12] == ~Last_TID ) ) | |
1181 | begin | |
1182 | `ifdef AXIS_FBDIMM_HW | |
1183 | `else | |
1184 | `PR_ALWAYS ("sb_decode",`DBG_0,"FBDIMM: Write config register received : Function number %h Register Address %h",bC[10:8],bC[10:0]); | |
1185 | `endif | |
1186 | ||
1187 | Last_TID<=bC[12]; // update last tid | |
1188 | Write_Config_reg<=1; | |
1189 | Write_Config_addr_reg<=bC[10:0]; | |
1190 | end | |
1191 | else | |
1192 | Write_Config_reg<=0; | |
1193 | ||
1194 | ||
1195 | // read config command | |
1196 | if ( (command_A_rdy || command_B_rdy || command_C_rdy) && ( command_select[20:14] == 7'b0000100 ) ) | |
1197 | begin | |
1198 | `ifdef AXIS_FBDIMM_HW | |
1199 | cfg_data <= axis_rdata; | |
1200 | `else | |
1201 | `PR_ALWAYS ("sb_decode",`DBG_0,"FBDIMM: Read config register received : Function number %h Register Address %h Register data %h",command_select[10:8],command_select[7:2],register_memory[command_select[10:0]]); | |
1202 | cfg_data<=register_memory[command_select[10:0]]; | |
1203 | `endif | |
1204 | cfg_rd<=1; | |
1205 | end | |
1206 | else | |
1207 | cfg_rd<=0; | |
1208 | ||
1209 | // sync command | |
1210 | if ( sync_cmd_rdy && ( aC[20:18] == 3'b000 ) && ( aC[17:14] == 4'b0001) ) | |
1211 | begin | |
1212 | `ifdef AXIS_FBDIMM_HW | |
1213 | `else | |
1214 | `PR_ALWAYS ("sb_decode",`DBG_0,"FBDIMM: Sync detected. sd=%h ier=%b erc=%b el0s=%b r1,r0=%h",aC[12:11],aC[6],aC[5],aC[4],aC[1:0]); | |
1215 | `endif | |
1216 | sync_detected_reg<=1'b1; | |
1217 | sync_cmd_data<=aC; | |
1218 | sync_counter_reg <= 13'h0; | |
1219 | end | |
1220 | else begin | |
1221 | sync_detected_reg<= 1'b0; | |
1222 | sync_counter_reg <= sync_counter_reg + 13'h1; | |
1223 | end | |
1224 | ||
1225 | end | |
1226 | ||
1227 | `ifdef AXIS_FBDIMM_HW | |
1228 | assign wcfg_data ={WDATA[70],WDATA[61],WDATA[52],WDATA[43],WDATA[69],WDATA[60],WDATA[51],WDATA[42],WDATA[68],WDATA[59],WDATA[50],WDATA[41],WDATA[67],WDATA[58],WDATA[49],WDATA[40],WDATA[66],WDATA[57],WDATA[48],WDATA[39],WDATA[65],WDATA[56],WDATA[47],WDATA[38],WDATA[64],WDATA[55],WDATA[46],WDATA[37],WDATA[63],WDATA[54],WDATA[45],WDATA[36]}; | |
1229 | `else | |
1230 | ||
1231 | assign wcfg_data ={WDATA[70],WDATA[61],WDATA[52],WDATA[43],WDATA[69],WDATA[60],WDATA[51],WDATA[42],WDATA[68],WDATA[59],WDATA[50],WDATA[41],WDATA[67],WDATA[58],WDATA[49],WDATA[40],WDATA[66],WDATA[57],WDATA[48],WDATA[39],WDATA[65],WDATA[56],WDATA[47],WDATA[38],WDATA[64],WDATA[55],WDATA[46],WDATA[37],WDATA[63],WDATA[54],WDATA[45],WDATA[36]}; | |
1232 | ||
1233 | wire [31:0] tmp_dcalcsr = register_memory[{3'b100,8'h40}]; | |
1234 | ||
1235 | `ifdef AXIS_FBDIMM_NO_FSR | |
1236 | always@(posedge clk_int) | |
1237 | `else | |
1238 | always@(posedge link_clk) | |
1239 | `endif | |
1240 | begin | |
1241 | if ( clear_dcalcsr31 ) | |
1242 | register_memory[{3'b100,8'h40}] <= {1'b0,tmp_dcalcsr[30:0]}; | |
1243 | ||
1244 | ||
1245 | if ( Write_Config_reg_d4 ) | |
1246 | begin | |
1247 | register_memory[Write_Config_addr_reg]<= wcfg_data; | |
1248 | `PR_ALWAYS ("sb_decode",`DBG_0,"FBDIMM: Write config data: %h", wcfg_data); | |
1249 | end | |
1250 | if(dram_cmd_vld_delayed) | |
1251 | begin | |
1252 | register_memory[{3'b011,8'h7c}]<={22'b0,cke_reg_delayed,9'b0} | register_memory[{3'b011,8'h7c}]; | |
1253 | end | |
1254 | end | |
1255 | ||
1256 | `endif | |
1257 | ||
1258 | // DDR2 DRAM I/O module | |
1259 | ||
1260 | ||
1261 | ||
1262 | always@(posedge clk_int) | |
1263 | begin | |
1264 | if ( init | soft_channel_reset ) | |
1265 | wf_counter<=1; | |
1266 | else if ( Write_Frame_Wire_d[12] & ~init) | |
1267 | begin | |
1268 | if ( wf_counter == 4'h8 ) | |
1269 | wf_counter <= 1 ; | |
1270 | else | |
1271 | wf_counter <= wf_counter + 3'h1; | |
1272 | end | |
1273 | ||
1274 | end | |
1275 | ||
1276 | ||
1277 | reg first_write_vld; | |
1278 | ||
1279 | always@(posedge clk_int) | |
1280 | begin | |
1281 | if ( init || soft_channel_reset ) | |
1282 | first_write_vld <=0; | |
1283 | else if ( Write_Frame_Reg) | |
1284 | first_write_vld <=1; | |
1285 | end | |
1286 | ||
1287 | wire enable_buffer_fifo0 = ( wf_counter == 3'h1 ) | ( wf_counter == 3'h2 ) | ( wf_counter == 3'h3 ) | ( wf_counter == 3'h4 ); | |
1288 | wire enable_buffer_fifo1 = ( wf_counter == 3'h5 ) | ( wf_counter == 3'h6 ) | ( wf_counter == 3'h7 ) | ( wf_counter == 4'h8 ); | |
1289 | ||
1290 | wire wbuffer_full0,wbuffer_full1,wbuffer_empty0,wbuffer_empty1; | |
1291 | assign wbuffer_full = wbuffer_full0 | wbuffer_full1; | |
1292 | assign wbuffer_empty = wbuffer_empty0 | wbuffer_empty1; | |
1293 | reg [2:0] fifo0_rd,fifo1_rd; | |
1294 | ||
1295 | wire [71:0] wbuffer_rd_data0,wbuffer_rd_data1; | |
1296 | ||
1297 | assign wbuffer_rd_data = ( (fifo0_rd == 3'h4 ) | (fifo0_rd == 2'h1 ) | (fifo0_rd == 2'h2) | (fifo0_rd == 2'h3) ) ? wbuffer_rd_data0 : wbuffer_rd_data1; | |
1298 | ||
1299 | ||
1300 | always@(negedge clk_int) | |
1301 | begin | |
1302 | if ( init || soft_channel_reset) | |
1303 | fifo0_rd <= 2'b00; | |
1304 | else if ( enable_buffer_fifo1 && ( fifo0_rd !== 3'b101)) | |
1305 | fifo0_rd <= fifo0_rd + 2'b1; | |
1306 | else if ( enable_buffer_fifo0 ) | |
1307 | fifo0_rd <= 2'b00; | |
1308 | ||
1309 | ||
1310 | if ( init || soft_channel_reset) | |
1311 | fifo1_rd <= 3'b101; | |
1312 | else if ( enable_buffer_fifo0 && ( fifo1_rd !== 3'b101)) | |
1313 | fifo1_rd <= fifo1_rd + 2'b1; | |
1314 | else if ( enable_buffer_fifo1 ) | |
1315 | fifo1_rd <= 2'b00; | |
1316 | ||
1317 | ||
1318 | end | |
1319 | ||
1320 | // Buffer to hold Write data before it is enqueud in Write Buffer | |
1321 | beh_fifo #(72,2) buffer_fifo0 (.rdata (wbuffer_rd_data0), | |
1322 | .wfull (wbuffer_full0), | |
1323 | .rempty (wbuffer_empty0), | |
1324 | .wdata (wbuffer_wr_data), | |
1325 | .winc (Write_Frame_Wire_d[11] & enable_buffer_fifo0 ), | |
1326 | .wclk (clk_int ), | |
1327 | .wrst_n (~reset), | |
1328 | .inv (inv_wr | disable_state), | |
1329 | .rinc ( ((fifo0_rd == 3'h4 ) | (fifo0_rd == 2'h1 ) | (fifo0_rd == 2'h2) | (fifo0_rd == 2'h3)) & first_write_vld ), | |
1330 | .rclk (clk_int ), | |
1331 | .rrst_n(~reset) | |
1332 | ); | |
1333 | ||
1334 | // Buffer to hold Write data before it is enqueud in Write Buffer | |
1335 | beh_fifo #(72,2) buffer_fifo1 (.rdata (wbuffer_rd_data1), | |
1336 | .wfull (wbuffer_full1), | |
1337 | .rempty (wbuffer_empty1), | |
1338 | .wdata (wbuffer_wr_data), | |
1339 | .winc (Write_Frame_Wire_d[11] & enable_buffer_fifo1), | |
1340 | .wclk (clk_int ), | |
1341 | .wrst_n (~reset), | |
1342 | .inv (inv_wr | disable_state ), | |
1343 | .rinc ( ((fifo1_rd == 3'h4 ) | (fifo1_rd == 2'h1 ) | (fifo1_rd == 2'h2) | (fifo1_rd == 2'h3)) & first_write_vld ), | |
1344 | .rclk (clk_int ), | |
1345 | .rrst_n(~reset) | |
1346 | ); | |
1347 | ||
1348 | ||
1349 | ||
1350 | reg write_amb_ok; | |
1351 | reg [2:0] WS_d1,WS_d2; | |
1352 | ||
1353 | ||
1354 | ||
1355 | `ifdef AXIS_FBDIMM_1AMB | |
1356 | assign write_fifo_winc = ( fifo0_rd == 3'h4 ) || (fifo0_rd == 3'h2 ) || ( fifo0_rd == 3'h3) || (fifo0_rd == 3'h1) || | |
1357 | ( fifo1_rd == 3'h4 ) || (fifo1_rd == 3'h2 ) || ( fifo1_rd == 3'h3) || (fifo1_rd == 3'h1 ) ; | |
1358 | ||
1359 | `else | |
1360 | ||
1361 | reg [2:0] WS_latch0,WS_latch1; | |
1362 | ||
1363 | always@(negedge enable_buffer_fifo0) | |
1364 | WS_latch0 <= WS; | |
1365 | ||
1366 | always@(negedge enable_buffer_fifo1) | |
1367 | WS_latch1 <= WS; | |
1368 | ||
1369 | ||
1370 | wire write_fifo_winc = (( ((fifo0_rd == 3'h4 ) | (fifo0_rd == 2'h1 ) | (fifo0_rd == 2'h2) | (fifo0_rd == 2'h3) ) & (WS_latch0 == DS )) | | |
1371 | ( ((fifo1_rd == 3'h4 ) | (fifo1_rd == 2'h1 ) | (fifo1_rd == 2'h2) | (fifo1_rd == 2'h3) ) & (WS_latch1 == DS))) & first_write_vld ; | |
1372 | ||
1373 | `endif | |
1374 | ||
1375 | ||
1376 | ||
1377 | // Write Buffer | |
1378 | beh_fifo #(72,6) write_fifo (.rdata (wfifo_rd_data), | |
1379 | .wfull (wfifo_full), | |
1380 | .rempty (wfifo_empty), | |
1381 | .wdata (wbuffer_rd_data), | |
1382 | .winc ( write_fifo_winc ), | |
1383 | .wclk (clk_int), | |
1384 | .wrst_n (~reset), | |
1385 | .rinc ( get_wbuffer_data ), | |
1386 | .rclk (dram_2x_clk), | |
1387 | .inv (inv_wr | disable_state), | |
1388 | .rrst_n(~reset) | |
1389 | ); | |
1390 | ||
1391 | ||
1392 | ||
1393 | `ifdef FBDIMM_FAST_NB | |
1394 | // Read Buffer | |
1395 | beh_fifo #(72,6) read_fifo (.rdata (rbuffer_rd_data), | |
1396 | .wfull (), | |
1397 | .rempty ( rbuffer_empty ), | |
1398 | .wdata (dram_io_data_out), | |
1399 | .winc (dram_io_put_rbuffer_data), | |
1400 | .wclk (dram_2x_clk), | |
1401 | .wrst_n (~reset), | |
1402 | `ifdef AXIS_FBDIMM_NO_FSR | |
1403 | .rinc ( rbuffer_rd ), | |
1404 | .rclk ( dram_2x_clk ), | |
1405 | `else | |
1406 | .rinc ( rbuffer_rd ), | |
1407 | .rclk ( frm_begin ), | |
1408 | `endif | |
1409 | .inv ( disable_state ), | |
1410 | .rrst_n(~reset_sync) | |
1411 | ); | |
1412 | ||
1413 | `else | |
1414 | // Read Buffer | |
1415 | beh_fifo #(72,6) read_fifo (.rdata (rbuffer_rd_data), | |
1416 | .wfull (), | |
1417 | .rempty ( rbuffer_empty ), | |
1418 | .wdata (dram_io_data_out), | |
1419 | .winc (dram_io_put_rbuffer_data), | |
1420 | .wclk (dram_2x_clk), | |
1421 | .wrst_n (~reset), | |
1422 | .rinc ( rbuffer_rd ), | |
1423 | .rclk ( link_clk ), | |
1424 | .inv ( disable_state), | |
1425 | .rrst_n(~reset_sync) | |
1426 | ); | |
1427 | `endif | |
1428 | ||
1429 | ||
1430 | ||
1431 | // shifter logic | |
1432 | ||
1433 | ||
1434 | dff_n #(1) WF0( .signal_in (Write_Frame_Reg), | |
1435 | .signal_out (Write_Frame_Wire_d[1]), | |
1436 | .clk (clk_int)); | |
1437 | ||
1438 | ||
1439 | ||
1440 | dff_n #(1) WF1( .signal_in (Write_Frame_Wire_d[1]), | |
1441 | .signal_out (Write_Frame_Wire_d[11]), | |
1442 | .clk (clk_int)); | |
1443 | ||
1444 | dff_n #(1) WF2( .signal_in (Write_Frame_Wire_d[11]), | |
1445 | .signal_out (Write_Frame_Wire_d[12]), | |
1446 | .clk (clk_int)); | |
1447 | ||
1448 | ||
1449 | ||
1450 | ||
1451 | `ifdef AXIS_FBDIMM_NO_FSR | |
1452 | ||
1453 | dff_fbd #(1) WCR1( .signal_in (Write_Config_reg), | |
1454 | .signal_out (Write_Config_reg_d1), | |
1455 | .clk (clk_int)); | |
1456 | ||
1457 | dff_fbd #(1) WCR2( .signal_in (Write_Config_reg_d1), | |
1458 | .signal_out (Write_Config_reg_d2), | |
1459 | .clk (clk_int)); | |
1460 | ||
1461 | dff_fbd #(1) WCR3( .signal_in (Write_Config_reg_d2), | |
1462 | .signal_out (Write_Config_reg_d3), | |
1463 | .clk (clk_int)); | |
1464 | ||
1465 | dff_fbd #(1) WCR4( .signal_in (Write_Config_reg_d3), | |
1466 | .signal_out (Write_Config_reg_d4), | |
1467 | .clk (clk_int)); | |
1468 | ||
1469 | ||
1470 | ||
1471 | dff_fbd #(1) sync1( .signal_in (sync_detected[0]), | |
1472 | .signal_out (sync_detected[1]), | |
1473 | .clk (clk_int)); | |
1474 | ||
1475 | dff_fbd #(1) sync2( .signal_in (sync_detected[1]), | |
1476 | .signal_out (sync_detected[2]), | |
1477 | .clk (clk_int)); | |
1478 | ||
1479 | dff_fbd #(1) sync3( .signal_in (sync_detected[2]), | |
1480 | .signal_out (sync_detected[3]), | |
1481 | .clk (clk_int)); | |
1482 | ||
1483 | dff_fbd #(1) sync4( .signal_in (sync_detected[3]), | |
1484 | .signal_out (sync_detected[4]), | |
1485 | .clk (clk_int)); | |
1486 | ||
1487 | dff_fbd #(1) sync5( .signal_in (sync_detected[4]), | |
1488 | .signal_out (sync_detected[5]), | |
1489 | .clk (clk_int)); | |
1490 | ||
1491 | dff_fbd #(1) sync6( .signal_in (sync_detected[5]), | |
1492 | .signal_out (sync_detected[6]), | |
1493 | .clk (clk_int)); | |
1494 | ||
1495 | dff_fbd #(1) sync7( .signal_in (sync_detected[6]), | |
1496 | .signal_out (sync_detected[7]), | |
1497 | .clk (clk_int)); | |
1498 | ||
1499 | `else | |
1500 | dff_fbd #(1) WCR1( .signal_in (Write_Config_reg), | |
1501 | .signal_out (Write_Config_reg_d1), | |
1502 | .clk (link_clk)); | |
1503 | ||
1504 | dff_fbd #(1) WCR2( .signal_in (Write_Config_reg_d1), | |
1505 | .signal_out (Write_Config_reg_d2), | |
1506 | .clk (link_clk)); | |
1507 | ||
1508 | dff_fbd #(1) WCR3( .signal_in (Write_Config_reg_d2), | |
1509 | .signal_out (Write_Config_reg_d3), | |
1510 | .clk (link_clk)); | |
1511 | ||
1512 | dff_fbd #(1) WCR4( .signal_in (Write_Config_reg_d3), | |
1513 | .signal_out (Write_Config_reg_d4), | |
1514 | .clk (link_clk)); | |
1515 | ||
1516 | ||
1517 | ||
1518 | dff_fbd #(1) sync1( .signal_in (sync_detected[0]), | |
1519 | .signal_out (sync_detected[1]), | |
1520 | .clk (link_clk)); | |
1521 | ||
1522 | dff_fbd #(1) sync2( .signal_in (sync_detected[1]), | |
1523 | .signal_out (sync_detected[2]), | |
1524 | .clk (link_clk)); | |
1525 | ||
1526 | dff_fbd #(1) sync3( .signal_in (sync_detected[2]), | |
1527 | .signal_out (sync_detected[3]), | |
1528 | .clk (link_clk)); | |
1529 | ||
1530 | dff_fbd #(1) sync4( .signal_in (sync_detected[3]), | |
1531 | .signal_out (sync_detected[4]), | |
1532 | .clk (link_clk)); | |
1533 | ||
1534 | dff_fbd #(1) sync5( .signal_in (sync_detected[4]), | |
1535 | .signal_out (sync_detected[5]), | |
1536 | .clk (link_clk)); | |
1537 | ||
1538 | dff_fbd #(1) sync6( .signal_in (sync_detected[5]), | |
1539 | .signal_out (sync_detected[6]), | |
1540 | .clk (link_clk)); | |
1541 | ||
1542 | dff_fbd #(1) sync7( .signal_in (sync_detected[6]), | |
1543 | .signal_out (sync_detected[7]), | |
1544 | .clk (link_clk)); | |
1545 | ||
1546 | `endif | |
1547 | ||
1548 | ||
1549 | crc_FE data_crc(.B(Data_72) , | |
1550 | .E (CRC22)); | |
1551 | ||
1552 | ||
1553 | crc_aE cmd_crc ( .B(Command_26), | |
1554 | .E (CRC14)); | |
1555 | ||
1556 | crc_FE_failover data_crc_failover (.B(Data_72) , | |
1557 | .E (CRC10_data_failover)); | |
1558 | ||
1559 | crc_aE_failover cmd_crc_failover ( .B(Command_26), | |
1560 | .E (CRC10_cmd_failover)); | |
1561 | ||
1562 | endmodule | |
1563 | ||
1564 |