Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / model / verilog / mem / fbdimm / design / sys_fbdimm4.v
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: sys_fbdimm4.v
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35module sys_fbdimm4 ( ps , ps_bar, sn , sn_bar, pn, pn_bar, ss , ss_bar , // channel interface
36 sclk);
37// Parameters
38parameter NB_LINK = 14;
39parameter SB_LINK = 10;
40
41// Inputs/Outputs
42output [NB_LINK-1:0] pn,pn_bar; // primary northbound
43input [NB_LINK-1:0] sn,sn_bar; // secondary northbound
44output [SB_LINK-1:0] ss,ss_bar; // secondary southbound
45input [SB_LINK-1:0] ps,ps_bar; // primary southbound
46input sclk;
47
48// internal registers/wires
49wire [NB_LINK-1:0] fbdimm0_sn,fbdimm1_sn,fbdimm2_sn,fbdimm3_sn;
50wire [SB_LINK-1:0] fbdimm0_ss,fbdimm1_ss,fbdimm2_ss,fbdimm3_ss;
51
52fbdimm #(NB_LINK,SB_LINK,0) fbdimm0 ( .ps (ps),
53 .sn (fbdimm0_sn),
54 .pn (pn),
55 .ss (fbdimm0_ss),
56 .sclk (sclk));
57
58fbdimm #(NB_LINK,SB_LINK,1) fbdimm1 ( .ps (fbdimm0_ss),
59 .sn (fbdimm1_sn),
60 .pn (fbdimm0_sn),
61 .ss (fbdimm1_ss),
62 .sclk (sclk));
63
64fbdimm #(NB_LINK,SB_LINK,2) fbdimm2 ( .ps (fbdimm1_ss),
65 .sn (fbdimm2_sn),
66 .pn (fbdimm1_sn),
67 .ss (fbdimm2_ss),
68 .sclk (sclk));
69
70fbdimm #(NB_LINK,SB_LINK,3) fbdimm3 ( .ps (fbdimm2_ss),
71 .sn (fbdimm3_sn),
72 .pn (fbdimm2_sn),
73 .ss (fbdimm3_ss),
74 .sclk (sclk));
75
76
77endmodule