Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / model / verilog / mem / fbdimm / library / fifo / sync_r2w.v

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// OpenSPARC T2 Processor File: sync_r2w.v
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module sync_r2w (wrptr2,rptr,wclk,wrst_n);
parameter ADDRSIZE=6;
output [ADDRSIZE:0] wrptr2;
input  [ADDRSIZE:0] rptr;
input              wclk,wrst_n;
reg [ADDRSIZE:0] wrptr2,wrptr1;

always @(posedge wclk or negedge wrst_n)
  if ( !wrst_n) 
   begin
    wrptr1 <= 1'b0;
    wrptr2 <= 1'b0;
   end
  else
   begin
    {wrptr2,wrptr1} <= {wrptr1,rptr};
   end
endmodule