Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / model / verilog / mem / fbdimm / library / library.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: library.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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module dff_l  (signal_in,signal_out,clk);

parameter SIZE = 1;
parameter INITIAL_VALUE=0;

input [SIZE-1:0] signal_in;
output [SIZE-1:0] signal_out;
input clk;
reg [SIZE-1:0] signal_out_reg;

assign signal_out = signal_out_reg;

always@(posedge clk)
begin
  signal_out_reg[SIZE-1:0] <= signal_in[SIZE-1:0];
end

initial begin
 signal_out_reg = INITIAL_VALUE;
end

endmodule


module dff_p  (signal_in,signal_out,clk);

parameter SIZE = 1;
parameter INITIAL_VALUE=0;

input [SIZE-1:0] signal_in;
output [SIZE-1:0] signal_out;
input clk;
reg [SIZE-1:0] signal_out_reg;

assign signal_out = signal_out_reg;

always@(posedge clk)
begin
  signal_out_reg[SIZE-1:0] <= signal_in[SIZE-1:0];
end

initial begin
 signal_out_reg = INITIAL_VALUE;
end

endmodule

module dff_n  (signal_in,signal_out,clk);

parameter SIZE = 1;
parameter INITIAL_VALUE=0;

input [SIZE-1:0] signal_in;
output [SIZE-1:0] signal_out;
input clk;
reg [SIZE-1:0] signal_out;

always@(negedge clk)
begin
  signal_out[SIZE-1:0] <= signal_in[SIZE-1:0];
end

initial begin
 signal_out = INITIAL_VALUE;
end


endmodule

module dff_fbd  (signal_in,signal_out,clk);

parameter SIZE = 1;

input [SIZE-1:0] signal_in;
output [SIZE-1:0] signal_out;
input clk;
reg [SIZE-1:0] signal_out;

always@(negedge clk)
begin
  signal_out[SIZE-1:0] <= signal_in[SIZE-1:0];
end


endmodule