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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: enet_models.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module enet_models ( | |
36 | ref_clk, // input (xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
37 | reset, // input (pcs_0_ENV,pcs_1_ENV,xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
38 | RGMII_TXCLK0, // input () <= () | |
39 | RGMII_TXCLK1, // input () <= () | |
40 | RGMII_TXCLK2, // input () <= () | |
41 | RGMII_TXCLK3, // input () <= () | |
42 | RXN0_p0, // input (serdes_P0) <= () | |
43 | RXN1_p0, // input (serdes_P0) <= () | |
44 | RXN2_p0, // input (serdes_P0) <= () | |
45 | RXN3_p0, // input (serdes_P0) <= () | |
46 | RXP0_p0, // input (serdes_P0) <= () | |
47 | RXP1_p0, // input (serdes_P0) <= () | |
48 | RXP2_p0, // input (serdes_P0) <= () | |
49 | RXP3_p0, // input (serdes_P0) <= () | |
50 | RXN0_p1, // input (serdes_P1) <= () | |
51 | RXN1_p1, // input (serdes_P1) <= () | |
52 | RXN2_p1, // input (serdes_P1) <= () | |
53 | RXN3_p1, // input (serdes_P1) <= () | |
54 | RXP0_p1, // input (serdes_P1) <= () | |
55 | RXP1_p1, // input (serdes_P1) <= () | |
56 | RXP2_p1, // input (serdes_P1) <= () | |
57 | RXP3_p1, // input (serdes_P1) <= () | |
58 | m0_rx_clk, // output (port0_clk) => (xgmii_if_P0) | |
59 | m0_tx_clk, // output () => (BW_CALC_P0) | |
60 | m0_tx_data, // output () => (BW_CALC_P0) | |
61 | m0_tx_en, // output () => (BW_CALC_P0) | |
62 | m0_tx_err, // output () => () | |
63 | m1_rx_clk, // output (port1_clk) => (xgmii_if_P1) | |
64 | m1_tx_clk, // output () => (BW_CALC_P1) | |
65 | m1_tx_data, // output () => (BW_CALC_P1) | |
66 | m1_tx_en, // output () => (BW_CALC_P1) | |
67 | m1_tx_err, // output () => () | |
68 | m2_rx_clk, // output (port2_clk) => () | |
69 | m2_tx_clk, // output () => () | |
70 | m2_tx_data, // output () => () | |
71 | m2_tx_en, // output () => () | |
72 | m2_tx_err, // output () => () | |
73 | m3_rx_clk, // output (port3_clk) => () | |
74 | m3_tx_clk, // output () => () | |
75 | m3_tx_data, // output () => () | |
76 | m3_tx_en, // output () => () | |
77 | m3_tx_err, // output () => () | |
78 | BSINITCLK, // input (serdes_P0,serdes_P1) <= () | |
79 | REFCLKN, // input (serdes_P0,serdes_P1) <= () | |
80 | REFCLKP, // input (serdes_P0,serdes_P1) <= () | |
81 | core_clk, // input (pcs_0_ENV,pcs_1_ENV) <= () | |
82 | m0_rx_config, // input (port0_clk) <= () | |
83 | m0_rx_data, // input (pcs_0_ENV,xgmii_if_P0) <= () | |
84 | m0_rx_dv, // input (pcs_0_ENV,xgmii_if_P0) <= () | |
85 | m0_rx_err, // input (pcs_0_ENV) <= () | |
86 | m0_tx_config, // input (port0_clk) <= () | |
87 | m1_rx_config, // input (port1_clk) <= () | |
88 | m1_rx_data, // input (pcs_1_ENV,xgmii_if_P1) <= () | |
89 | m1_rx_dv, // input (pcs_1_ENV,xgmii_if_P1) <= () | |
90 | m1_rx_err, // input (pcs_1_ENV) <= () | |
91 | m1_tx_config, // input (port1_clk) <= () | |
92 | m2_rx_config, // input (port2_clk) <= () | |
93 | m2_tx_config, // input (port2_clk) <= () | |
94 | m3_rx_config, // input (port3_clk) <= () | |
95 | m3_tx_config, // input (port3_clk) <= () | |
96 | AMUX_p0, // output (serdes_P0) => () | |
97 | AMUX_p1, // output (serdes_P1) => () | |
98 | STCIQ_p0, // output (serdes_P0) => () | |
99 | STCIQ_p1, // output (serdes_P1) => () | |
100 | TXN0_p0, // output (serdes_P0) => () | |
101 | TXN0_p1, // output (serdes_P1) => () | |
102 | TXN1_p0, // output (serdes_P0) => () | |
103 | TXN1_p1, // output (serdes_P1) => () | |
104 | TXN2_p0, // output (serdes_P0) => () | |
105 | TXN2_p1, // output (serdes_P1) => () | |
106 | TXN3_p0, // output (serdes_P0) => () | |
107 | TXN3_p1, // output (serdes_P1) => () | |
108 | TXP0_p0, // output (serdes_P0) => () | |
109 | TXP0_p1, // output (serdes_P1) => () | |
110 | TXP1_p0, // output (serdes_P0) => () | |
111 | TXP1_p1, // output (serdes_P1) => () | |
112 | TXP2_p0, // output (serdes_P0) => () | |
113 | TXP2_p1, // output (serdes_P1) => () | |
114 | TXP3_p0, // output (serdes_P0) => () | |
115 | TXP3_p1, // output (serdes_P1) => () | |
116 | m0_rx_col, // output (pcs_0_ENV) => () | |
117 | m0_rx_crs, // output (pcs_0_ENV) => () | |
118 | m0_tx_clk_port, // output (port0_clk) => () | |
119 | m1_rx_col, // output (pcs_1_ENV) => () | |
120 | m1_rx_crs, // output (pcs_1_ENV) => () | |
121 | m1_tx_clk_port, // output (port1_clk) => () | |
122 | m2_tx_clk_port, // output (port2_clk) => () | |
123 | m3_tx_clk_port, // output (port3_clk) => () | |
124 | rx_clk_xgmii // output (xgmii_if_P0,xgmii_if_P1) => () | |
125 | ); | |
126 | ||
127 | input BSINITCLK; | |
128 | input REFCLKN; | |
129 | input REFCLKP; | |
130 | input core_clk; | |
131 | input [3:0] m0_rx_config; | |
132 | input [7:0] m0_rx_data; | |
133 | input m0_rx_dv; | |
134 | input m0_rx_err; | |
135 | input [3:0] m0_tx_config; | |
136 | input [3:0] m1_rx_config; | |
137 | input [7:0] m1_rx_data; | |
138 | input m1_rx_dv; | |
139 | input m1_rx_err; | |
140 | input [3:0] m1_tx_config; | |
141 | input [3:0] m2_rx_config; | |
142 | input [3:0] m2_tx_config; | |
143 | input [3:0] m3_rx_config; | |
144 | input [3:0] m3_tx_config; | |
145 | output AMUX_p0; | |
146 | output AMUX_p1; | |
147 | output STCIQ_p0; | |
148 | output STCIQ_p1; | |
149 | output TXN0_p0; | |
150 | output TXN0_p1; | |
151 | output TXN1_p0; | |
152 | output TXN1_p1; | |
153 | output TXN2_p0; | |
154 | output TXN2_p1; | |
155 | output TXN3_p0; | |
156 | output TXN3_p1; | |
157 | output TXP0_p0; | |
158 | output TXP0_p1; | |
159 | output TXP1_p0; | |
160 | output TXP1_p1; | |
161 | output TXP2_p0; | |
162 | output TXP2_p1; | |
163 | output TXP3_p0; | |
164 | output TXP3_p1; | |
165 | output m0_rx_col; | |
166 | output m0_rx_crs; | |
167 | output m0_tx_clk_port; | |
168 | output m1_rx_col; | |
169 | output m1_rx_crs; | |
170 | output m1_tx_clk_port; | |
171 | output m2_tx_clk_port; | |
172 | output m3_tx_clk_port; | |
173 | output rx_clk_xgmii; | |
174 | ||
175 | wire [31:0] xgmii_rxd0; | |
176 | wire [31:0] xgmii_rxd1; | |
177 | wire [3:0] xgmii_rxc0; | |
178 | wire [3:0] xgmii_rxc1; | |
179 | supply0 VLO; | |
180 | supply0 GND; | |
181 | supply1 VDD; | |
182 | supply0 LV_TM; | |
183 | input ref_clk; | |
184 | input reset; | |
185 | input RGMII_TXCLK0; | |
186 | input RGMII_TXCLK1; | |
187 | input RGMII_TXCLK2; | |
188 | input RGMII_TXCLK3; | |
189 | input RXN0_p0; | |
190 | input RXN1_p0; | |
191 | input RXN2_p0; | |
192 | input RXN3_p0; | |
193 | input RXP0_p0; | |
194 | input RXP1_p0; | |
195 | input RXP2_p0; | |
196 | input RXP3_p0; | |
197 | input RXN0_p1; | |
198 | input RXN1_p1; | |
199 | input RXN2_p1; | |
200 | input RXN3_p1; | |
201 | input RXP0_p1; | |
202 | input RXP1_p1; | |
203 | input RXP2_p1; | |
204 | input RXP3_p1; | |
205 | output m0_rx_clk; | |
206 | output m0_tx_clk; | |
207 | output [7:0] m0_tx_data; | |
208 | output m0_tx_en; | |
209 | output m0_tx_err; | |
210 | output m1_rx_clk; | |
211 | output m1_tx_clk; | |
212 | output [7:0] m1_tx_data; | |
213 | output m1_tx_en; | |
214 | output m1_tx_err; | |
215 | output m2_rx_clk; | |
216 | output m2_tx_clk; | |
217 | output [7:0] m2_tx_data; | |
218 | output m2_tx_en; | |
219 | output m2_tx_err; | |
220 | output m3_rx_clk; | |
221 | output m3_tx_clk; | |
222 | output [7:0] m3_tx_data; | |
223 | output m3_tx_en; | |
224 | output m3_tx_err; | |
225 | wire ENV_RO_MONI; | |
226 | wire w_BT_EN; | |
227 | wire w_RO_EN; | |
228 | wire w_TEST_EN; | |
229 | wire w_BS_MODE; | |
230 | wire w_FORCE_DRV_DIS; | |
231 | wire w_TX_BS_SEL; | |
232 | wire DRV_BSOUT_A; | |
233 | wire DRV_BSOUT_B; | |
234 | wire DRV_BSOUT_C; | |
235 | wire DRV_BSOUT_D; | |
236 | wire ENV_PLL_LOCK; | |
237 | wire ENV_RES_EXT; | |
238 | wire RX_BSOUT_A; | |
239 | wire RX_BSOUT_B; | |
240 | wire RX_BSOUT_C; | |
241 | wire RX_BSOUT_D; | |
242 | wire TX_BSOUT_A; | |
243 | wire TX_BSOUT_B; | |
244 | wire TX_BSOUT_C; | |
245 | wire TX_BSOUT_D; | |
246 | wire [3:0] RDreg; | |
247 | wire odd_rx_pcs0_ENV; | |
248 | wire odd_rx_pcs1_ENV; | |
249 | wire odd_rx_pcs2_ENV; | |
250 | wire odd_rx_pcs3_ENV; | |
251 | wire pio_core_sel_pcs_ENV; | |
252 | wire pio_rd_wr__pcs_ENV; | |
253 | wire [6:0] pio_addr_pcs_ENV; | |
254 | wire [17:0] pio_wr_data_pcs_ENV; | |
255 | wire [1:0] slink_state_pcs_ENV; | |
256 | wire signal_detect_pcs_ENV; | |
257 | wire serdes_rdy_pcs_ENV; | |
258 | wire pio_err_pcs_0_ENV; | |
259 | wire pio_err_pcs_1_ENV; | |
260 | wire an_loss_sync_pcs_ENV; | |
261 | wire ewrap_pcs_ENV; | |
262 | wire pcs_int_pcs_ENV; | |
263 | wire phy_mode_pcs_ENV; | |
264 | wire pio_core_ack_pcs_ENV; | |
265 | wire [31:0] pio_rd_data_pcs_ENV; | |
266 | wire [31:0] xgmii_txd0_in; | |
267 | wire [3:0] xgmii_txc0_in; | |
268 | wire [31:0] xgmii_txd1_in; | |
269 | wire [3:0] xgmii_txc1_in; | |
270 | wire eser_env_bit_byte_sync_a; | |
271 | wire eser_env_bit_byte_sync_b; | |
272 | wire eser_env_bit_byte_sync_c; | |
273 | wire eser_env_bit_byte_sync_d; | |
274 | wire link_up_tx_pcs_0_ENV; | |
275 | wire link_up_tx_pcs_1_ENV; | |
276 | wire rx_clkn; | |
277 | wire [2:0] shared_sel_pcs_ENV; | |
278 | wire sw_ensyncdet_pcs_ENV; | |
279 | wire sw_lockref_pcs_ENV; | |
280 | wire tx_clk_xgmii0; | |
281 | wire tx_clk_xgmii1; | |
282 | wire tx_clkn; | |
283 | wire rx_clk_pcs0_ENV; | |
284 | wire rx_clk_pcs1_ENV; | |
285 | wire [9:0] xgmii_env_eser_rxd_a_del; | |
286 | wire [9:0] xgmii_env_eser_rxd_b_del; | |
287 | wire [9:0] xgmii_env_eser_rxd_c_del; | |
288 | wire [9:0] xgmii_env_eser_rxd_d_del; | |
289 | wire [9:0] env_eser_rxd_a_del; | |
290 | wire [9:0] env_eser_rxd_b_del; | |
291 | wire [9:0] env_eser_rxd_c_del; | |
292 | wire [9:0] env_eser_rxd_d_del; | |
293 | wire [9:0] env_eser_rxd_a_del1; | |
294 | wire [9:0] env_eser_rxd_b_del1; | |
295 | wire [9:0] env_eser_rxd_c_del1; | |
296 | wire [9:0] env_eser_rxd_d_del1; | |
297 | wire [9:0] env_eser_rxd_a; | |
298 | wire [9:0] env_eser_rxd_b; | |
299 | wire [9:0] env_eser_rxd_c; | |
300 | wire [9:0] env_eser_rxd_d; | |
301 | wire env_eser_pll_en; | |
302 | wire env_eser_bias_en; | |
303 | wire [1:0] env_eser_ser_sel; | |
304 | wire env_eser_refclk_sel; | |
305 | wire env_eser_trd_sel; | |
306 | wire env_eser_tclk_sel; | |
307 | wire env_eser_low_latency; | |
308 | wire env_eser_sync_dual_pol; | |
309 | wire [5:0] env_eser_tubi; | |
310 | wire env_eser_tx_en_a; | |
311 | wire env_eser_tx_en_b; | |
312 | wire env_eser_tx_en_c; | |
313 | wire env_eser_tx_en_d; | |
314 | wire env_eser_tx_clk_en_a; | |
315 | wire env_eser_tx_clk_en_b; | |
316 | wire env_eser_tx_clk_en_c; | |
317 | wire env_eser_tx_clk_en_d; | |
318 | wire env_eser_drv_en_a; | |
319 | wire env_eser_drv_en_b; | |
320 | wire env_eser_drv_en_c; | |
321 | wire env_eser_drv_en_d; | |
322 | wire [1:0] env_eser_lev_sel_a; | |
323 | wire [1:0] env_eser_lev_sel_b; | |
324 | wire [1:0] env_eser_lev_sel_c; | |
325 | wire [1:0] env_eser_lev_sel_d; | |
326 | wire [1:0] env_eser_drv_emp_lvl_a; | |
327 | wire [1:0] env_eser_drv_emp_lvl_b; | |
328 | wire [1:0] env_eser_drv_emp_lvl_c; | |
329 | wire [1:0] env_eser_drv_emp_lvl_d; | |
330 | wire env_eser_tx_lpb_en_a; | |
331 | wire env_eser_tx_lpb_en_b; | |
332 | wire env_eser_tx_lpb_en_c; | |
333 | wire env_eser_tx_lpb_en_d; | |
334 | wire env_eser_rx_lpb_en_a; | |
335 | wire env_eser_rx_lpb_en_b; | |
336 | wire env_eser_rx_lpb_en_c; | |
337 | wire env_eser_rx_lpb_en_d; | |
338 | wire env_eser_rx_en_a; | |
339 | wire env_eser_rx_en_b; | |
340 | wire env_eser_rx_en_c; | |
341 | wire env_eser_rx_en_d; | |
342 | wire env_eser_rx_clk_en_a; | |
343 | wire env_eser_rx_clk_en_b; | |
344 | wire env_eser_rx_clk_en_c; | |
345 | wire env_eser_rx_clk_en_d; | |
346 | wire env_eser_rx_sleep_en_a; | |
347 | wire env_eser_rx_sleep_en_b; | |
348 | wire env_eser_rx_sleep_en_c; | |
349 | wire env_eser_rx_sleep_en_d; | |
350 | wire env_eser_rbc_sel_a; | |
351 | wire env_eser_rbc_sel_b; | |
352 | wire env_eser_rbc_sel_c; | |
353 | wire env_eser_rbc_sel_d; | |
354 | wire env_eser_byte_sync_en_a; | |
355 | wire env_eser_byte_sync_en_b; | |
356 | wire env_eser_byte_sync_en_c; | |
357 | wire env_eser_byte_sync_en_d; | |
358 | wire env_eser_sync_sel_a; | |
359 | wire env_eser_sync_sel_b; | |
360 | wire env_eser_sync_sel_c; | |
361 | wire env_eser_sync_sel_d; | |
362 | wire env_eser_rx_reset_a; | |
363 | wire env_eser_rx_reset_b; | |
364 | wire env_eser_rx_reset_c; | |
365 | wire env_eser_rx_reset_d; | |
366 | wire [9:0] eser_env_txd_a; | |
367 | wire [9:0] eser_env_txd_b; | |
368 | wire [9:0] eser_env_txd_c; | |
369 | wire [9:0] eser_env_txd_d; | |
370 | wire eser_env_rbc0_a; | |
371 | wire eser_env_rbc0_b; | |
372 | wire eser_env_rbc0_c; | |
373 | wire eser_env_rbc0_d; | |
374 | wire eser_env_rbc1_a; | |
375 | wire eser_env_rbc1_b; | |
376 | wire eser_env_rbc1_c; | |
377 | wire eser_env_rbc1_d; | |
378 | wire eser_env_tclk0; | |
379 | wire eser_env_tclk1; | |
380 | wire eser_env_common_ready; | |
381 | wire eser_env_cchk_dmy; | |
382 | wire [2:0] eser_env_tubo; | |
383 | wire [3:0] eser_env_tbo; | |
384 | wire eser_env_fraq_a; | |
385 | wire eser_env_fraq_b; | |
386 | wire eser_env_fraq_c; | |
387 | wire eser_env_fraq_d; | |
388 | wire eser_env_sigdet_a; | |
389 | wire eser_env_sigdet_b; | |
390 | wire eser_env_sigdet_c; | |
391 | wire eser_env_sigdet_d; | |
392 | wire eser_env_rx_ready_a; | |
393 | wire eser_env_rx_ready_b; | |
394 | wire eser_env_rx_ready_c; | |
395 | wire eser_env_rx_ready_d; | |
396 | wire [9:0] w_SYNC_CHAR; | |
397 | wire [4:0] w_SYNC_MASK; | |
398 | wire m0_gmii_tx_en0; | |
399 | wire m0_xgmii_tx_en; | |
400 | wire [7:0] m0_xgmii_txdata; | |
401 | wire m1_xgmii_tx_en; | |
402 | wire [7:0] m1_xgmii_txdata; | |
403 | wire [7:0] m0_gmii_txd0; | |
404 | wire rxclk_mux0; | |
405 | wire rxclk_mux1; | |
406 | wire txclk_mux0; | |
407 | wire txclk_mux1; | |
408 | wire [7:0] pcs0_tx_data; | |
409 | wire [7:0] pcs1_tx_data; | |
410 | wire [7:0] pcs2_tx_data; | |
411 | wire [7:0] pcs3_tx_data; | |
412 | wire pcs0_tx_en; | |
413 | wire pcs1_tx_en; | |
414 | wire pcs2_tx_en; | |
415 | wire pcs3_tx_en; | |
416 | wire pcs0_tx_err; | |
417 | wire pcs1_tx_err; | |
418 | wire pcs2_tx_err; | |
419 | wire pcs3_tx_err; | |
420 | wire [7:0] rgmii0_tx_data; | |
421 | wire [7:0] rgmii1_tx_data; | |
422 | wire [7:0] rgmii2_tx_data; | |
423 | wire [7:0] rgmii3_tx_data; | |
424 | wire rgmii0_tx_en; | |
425 | wire rgmii1_tx_en; | |
426 | wire rgmii2_tx_en; | |
427 | wire rgmii3_tx_en; | |
428 | wire rgmii0_tx_err; | |
429 | wire rgmii1_tx_err; | |
430 | wire rgmii2_tx_err; | |
431 | wire rgmii3_tx_err; | |
432 | wire [9:0] temp_enc_ch0_p0; | |
433 | wire [9:0] temp_enc_ch1_p0; | |
434 | wire [9:0] temp_enc_ch2_p0; | |
435 | wire [9:0] temp_enc_ch3_p0; | |
436 | wire [9:0] temp_enc_ch0_p1; | |
437 | wire [9:0] temp_enc_ch1_p1; | |
438 | wire [9:0] temp_enc_ch2_p1; | |
439 | wire [9:0] temp_enc_ch3_p1; | |
440 | wire [9:0] TD0_p0; | |
441 | wire [9:0] TD1_p0; | |
442 | wire [9:0] TD2_p0; | |
443 | wire [9:0] TD3_p0; | |
444 | wire [9:0] TD0_r_p0; | |
445 | wire [9:0] TD1_r_p0; | |
446 | wire [9:0] TD2_r_p0; | |
447 | wire [9:0] TD3_r_p0; | |
448 | wire [9:0] TD1_r_p0_mux; | |
449 | wire [9:0] TD0_r_p0_mux; | |
450 | wire [9:0] TD0_r_p1_mux; | |
451 | wire [9:0] RD0_p0; | |
452 | wire [9:0] RD1_p0; | |
453 | wire [9:0] RD2_p0; | |
454 | wire [9:0] RD3_p0; | |
455 | wire [9:0] RD0_r_p0; | |
456 | wire [9:0] RD1_r_p0; | |
457 | wire [9:0] RD2_r_p0; | |
458 | wire [9:0] RD3_r_p0; | |
459 | wire [3:0] STSPLL_p0; | |
460 | wire [7:0] STSRX0_p0; | |
461 | wire [7:0] STSRX1_p0; | |
462 | wire [7:0] STSRX2_p0; | |
463 | wire [7:0] STSRX3_p0; | |
464 | wire [3:0] STSTX0_p0; | |
465 | wire [3:0] STSTX1_p0; | |
466 | wire [3:0] STSTX2_p0; | |
467 | wire [3:0] STSTX3_p0; | |
468 | wire [3:0] TXBCLK_p0; | |
469 | wire [1:0] RDLL0_p0; | |
470 | wire [1:0] RDLL1_p0; | |
471 | wire [1:0] RDLL2_p0; | |
472 | wire [1:0] RDLL3_p0; | |
473 | wire [3:0] RXBCLKLLN_p0; | |
474 | wire [3:0] RXBCLKLLP_p0; | |
475 | wire [3:0] RXBCLK_p0; | |
476 | wire [3:0] RXBCLKIN_p0; | |
477 | wire AMX_p0; | |
478 | wire FDO_p0; | |
479 | wire BSINITCLK_p0; | |
480 | wire [11:0] CFGPLL_p0; | |
481 | wire [27:0] CFGRX0_p0; | |
482 | wire [27:0] CFGRX1_p0; | |
483 | wire [27:0] CFGRX2_p0; | |
484 | wire [27:0] CFGRX3_p0; | |
485 | wire [19:0] CFGTX0_p0; | |
486 | wire [19:0] CFGTX1_p0; | |
487 | wire [19:0] CFGTX2_p0; | |
488 | wire [19:0] CFGTX3_p0; | |
489 | wire [19:0] TESTCFG_p0; | |
490 | wire FCLK_p0; | |
491 | wire FCLRZ_p0; | |
492 | wire FDI_p0; | |
493 | wire [1:0] STCICFG_p0; | |
494 | wire STCICLK_p0; | |
495 | wire STCID_p0; | |
496 | wire TESTCLKR_p0; | |
497 | wire TESTCLKT_p0; | |
498 | wire [3:0] TXBCLKIN_p0; | |
499 | wire [9:0] TD0_p1; | |
500 | wire [9:0] TD1_p1; | |
501 | wire [9:0] TD2_p1; | |
502 | wire [9:0] TD3_p1; | |
503 | wire [9:0] TD0_r_p1; | |
504 | wire [9:0] TD1_r_p1; | |
505 | wire [9:0] TD2_r_p1; | |
506 | wire [9:0] TD3_r_p1; | |
507 | wire [9:0] TD1_r_p1_mux; | |
508 | wire [9:0] RD0_p1; | |
509 | wire [9:0] RD1_p1; | |
510 | wire [9:0] RD2_p1; | |
511 | wire [9:0] RD3_p1; | |
512 | wire [9:0] RD0_r_p1; | |
513 | wire [9:0] RD1_r_p1; | |
514 | wire [9:0] RD2_r_p1; | |
515 | wire [9:0] RD3_r_p1; | |
516 | wire [3:0] STSPLL_p1; | |
517 | wire [7:0] STSRX0_p1; | |
518 | wire [7:0] STSRX1_p1; | |
519 | wire [7:0] STSRX2_p1; | |
520 | wire [7:0] STSRX3_p1; | |
521 | wire [3:0] STSTX0_p1; | |
522 | wire [3:0] STSTX1_p1; | |
523 | wire [3:0] STSTX2_p1; | |
524 | wire [3:0] STSTX3_p1; | |
525 | wire [3:0] TXBCLK_p1; | |
526 | wire [1:0] RDLL0_p1; | |
527 | wire [1:0] RDLL1_p1; | |
528 | wire [1:0] RDLL2_p1; | |
529 | wire [1:0] RDLL3_p1; | |
530 | wire [3:0] RXBCLKLLN_p1; | |
531 | wire [3:0] RXBCLKLLP_p1; | |
532 | wire [3:0] RXBCLK_p1; | |
533 | wire [3:0] RXBCLKIN_p1; | |
534 | wire AMX_p1; | |
535 | wire FDO_p1; | |
536 | wire BSINITCLK_p1; | |
537 | wire [11:0] CFGPLL_p1; | |
538 | wire [27:0] CFGRX0_p1; | |
539 | wire [27:0] CFGRX1_p1; | |
540 | wire [27:0] CFGRX2_p1; | |
541 | wire [27:0] CFGRX3_p1; | |
542 | wire [19:0] CFGTX0_p1; | |
543 | wire [19:0] CFGTX1_p1; | |
544 | wire [19:0] CFGTX2_p1; | |
545 | wire [19:0] CFGTX3_p1; | |
546 | wire [19:0] TESTCFG_p1; | |
547 | wire FCLK_p1; | |
548 | wire FCLRZ_p1; | |
549 | wire FDI_p1; | |
550 | wire [1:0] STCICFG_p1; | |
551 | wire STCICLK_p1; | |
552 | wire STCID_p1; | |
553 | wire TESTCLKR_p1; | |
554 | wire TESTCLKT_p1; | |
555 | wire [3:0] TXBCLKIN_p1; | |
556 | wire [15:0] no_of_txpkts_r; | |
557 | wire [15:0] tx_pkt_len_r; | |
558 | wire enb_bwcal_r; | |
559 | wire speed_10G_w; | |
560 | ||
561 | serdes_wrapper serdes_P0 ( | |
562 | .BSINITCLK (BSINITCLK), // input (serdes_P0,serdes_P1) <= () | |
563 | .CFGPLL (CFGPLL_p0[11:0]), // input (serdes_P0) <= () | |
564 | .CFGRX0 (CFGRX0_p0[27:0]), // input (serdes_P0) <= () | |
565 | .CFGRX1 (CFGRX1_p0[27:0]), // input (serdes_P0) <= () | |
566 | .CFGRX2 (CFGRX2_p0[27:0]), // input (serdes_P0) <= () | |
567 | .CFGRX3 (CFGRX3_p0[27:0]), // input (serdes_P0) <= () | |
568 | .CFGTX0 (CFGTX0_p0[19:0]), // input (serdes_P0) <= () | |
569 | .CFGTX1 (CFGTX1_p0[19:0]), // input (serdes_P0) <= () | |
570 | .CFGTX2 (CFGTX2_p0[19:0]), // input (serdes_P0) <= () | |
571 | .CFGTX3 (CFGTX3_p0[19:0]), // input (serdes_P0) <= () | |
572 | .FCLK (FCLK_p0), // input (serdes_P0) <= () | |
573 | .FCLRZ (FCLRZ_p0), // input (serdes_P0) <= () | |
574 | .FDI (FDI_p0), // input (serdes_P0) <= () | |
575 | .REFCLKN (REFCLKN), // input (serdes_P0,serdes_P1) <= () | |
576 | .REFCLKP (REFCLKP), // input (serdes_P0,serdes_P1) <= () | |
577 | .RXBCLKIN (RXBCLKIN_p0[3:0]), // input (serdes_P0) <= () | |
578 | .RXN0 (RXN0_p0), // input (serdes_P0) <= () | |
579 | .RXN1 (RXN1_p0), // input (serdes_P0) <= () | |
580 | .RXN2 (RXN2_p0), // input (serdes_P0) <= () | |
581 | .RXN3 (RXN3_p0), // input (serdes_P0) <= () | |
582 | .RXP0 (RXP0_p0), // input (serdes_P0) <= () | |
583 | .RXP1 (RXP1_p0), // input (serdes_P0) <= () | |
584 | .RXP2 (RXP2_p0), // input (serdes_P0) <= () | |
585 | .RXP3 (RXP3_p0), // input (serdes_P0) <= () | |
586 | .STCICFG (STCICFG_p0[1:0]), // input (serdes_P0) <= () | |
587 | .STCICLK (STCICLK_p0), // input (serdes_P0) <= () | |
588 | .STCID (STCID_p0), // input (serdes_P0) <= () | |
589 | .TD0 (TD0_r_p0[9:0]), // input (serdes_P0) <= () | |
590 | .TD1 (TD1_r_p0[9:0]), // input (serdes_P0) <= () | |
591 | .TD2 (TD2_r_p0[9:0]), // input (serdes_P0) <= () | |
592 | .TD3 (TD3_r_p0[9:0]), // input (serdes_P0) <= () | |
593 | .TESTCFG (TESTCFG_p0[19:0]), // input (serdes_P0) <= () | |
594 | .TESTCLKR (TESTCLKR_p0), // input (serdes_P0) <= () | |
595 | .TESTCLKT (TESTCLKT_p0), // input (serdes_P0) <= () | |
596 | .TXBCLKIN (TXBCLKIN_p0[3:0]), // input (serdes_P0) <= () | |
597 | .AMUX (AMUX_p0), // output (serdes_P0) => () | |
598 | .FDO (FDO_p0), // output (serdes_P0) => () | |
599 | .RD0 (RD0_p0[9:0]), // output (serdes_P0) => () | |
600 | .RD1 (RD1_p0[9:0]), // output (serdes_P0) => () | |
601 | .RD2 (RD2_p0[9:0]), // output (serdes_P0) => () | |
602 | .RD3 (RD3_p0[9:0]), // output (serdes_P0) => () | |
603 | .RDLL0 (RDLL0_p0), // output (serdes_P0) => () | |
604 | .RDLL1 (RDLL1_p0), // output (serdes_P0) => () | |
605 | .RDLL2 (RDLL2_p0), // output (serdes_P0) => () | |
606 | .RDLL3 (RDLL3_p0), // output (serdes_P0) => () | |
607 | .RXBCLK (RXBCLK_p0), // output (serdes_P0) => () | |
608 | .RXBCLKLLN (RXBCLKLLN_p0), // output (serdes_P0) => () | |
609 | .RXBCLKLLP (RXBCLKLLP_p0), // output (serdes_P0) => () | |
610 | .STCIQ (STCIQ_p0), // output (serdes_P0) => () | |
611 | .STSPLL (STSPLL_p0), // output (serdes_P0) => () | |
612 | .STSRX0 (STSRX0_p0), // output (serdes_P0) => (pcs_0_ENV) | |
613 | .STSRX1 (STSRX1_p0), // output (serdes_P0) => () | |
614 | .STSRX2 (STSRX2_p0), // output (serdes_P0) => () | |
615 | .STSRX3 (STSRX3_p0), // output (serdes_P0) => () | |
616 | .STSTX0 (STSTX0_p0), // output (serdes_P0) => () | |
617 | .STSTX1 (STSTX1_p0), // output (serdes_P0) => () | |
618 | .STSTX2 (STSTX2_p0), // output (serdes_P0) => () | |
619 | .STSTX3 (STSTX3_p0), // output (serdes_P0) => () | |
620 | .TXBCLK (TXBCLK_p0), // output (serdes_P0) => () | |
621 | .TXN0 (TXN0_p0), // output (serdes_P0) => () | |
622 | .TXN1 (TXN1_p0), // output (serdes_P0) => () | |
623 | .TXN2 (TXN2_p0), // output (serdes_P0) => () | |
624 | .TXN3 (TXN3_p0), // output (serdes_P0) => () | |
625 | .TXP0 (TXP0_p0), // output (serdes_P0) => () | |
626 | .TXP1 (TXP1_p0), // output (serdes_P0) => () | |
627 | .TXP2 (TXP2_p0), // output (serdes_P0) => () | |
628 | .TXP3 (TXP3_p0) // output (serdes_P0) => () | |
629 | ); | |
630 | ||
631 | serdes_wrapper serdes_P1 ( | |
632 | .BSINITCLK (BSINITCLK), // input (serdes_P0,serdes_P1) <= () | |
633 | .CFGPLL (CFGPLL_p1[11:0]), // input (serdes_P1) <= () | |
634 | .CFGRX0 (CFGRX0_p1[27:0]), // input (serdes_P1) <= () | |
635 | .CFGRX1 (CFGRX1_p1[27:0]), // input (serdes_P1) <= () | |
636 | .CFGRX2 (CFGRX2_p1[27:0]), // input (serdes_P1) <= () | |
637 | .CFGRX3 (CFGRX3_p1[27:0]), // input (serdes_P1) <= () | |
638 | .CFGTX0 (CFGTX0_p1[19:0]), // input (serdes_P1) <= () | |
639 | .CFGTX1 (CFGTX1_p1[19:0]), // input (serdes_P1) <= () | |
640 | .CFGTX2 (CFGTX2_p1[19:0]), // input (serdes_P1) <= () | |
641 | .CFGTX3 (CFGTX3_p1[19:0]), // input (serdes_P1) <= () | |
642 | .FCLK (FCLK_p1), // input (serdes_P1) <= () | |
643 | .FCLRZ (FCLRZ_p1), // input (serdes_P1) <= () | |
644 | .FDI (FDI_p1), // input (serdes_P1) <= () | |
645 | .REFCLKN (REFCLKN), // input (serdes_P0,serdes_P1) <= () | |
646 | .REFCLKP (REFCLKP), // input (serdes_P0,serdes_P1) <= () | |
647 | .RXBCLKIN (RXBCLKIN_p1[3:0]), // input (serdes_P1) <= () | |
648 | .RXN0 (RXN0_p1), // input (serdes_P1) <= () | |
649 | .RXN1 (RXN1_p1), // input (serdes_P1) <= () | |
650 | .RXN2 (RXN2_p1), // input (serdes_P1) <= () | |
651 | .RXN3 (RXN3_p1), // input (serdes_P1) <= () | |
652 | .RXP0 (RXP0_p1), // input (serdes_P1) <= () | |
653 | .RXP1 (RXP1_p1), // input (serdes_P1) <= () | |
654 | .RXP2 (RXP2_p1), // input (serdes_P1) <= () | |
655 | .RXP3 (RXP3_p1), // input (serdes_P1) <= () | |
656 | .STCICFG (STCICFG_p1[1:0]), // input (serdes_P1) <= () | |
657 | .STCICLK (STCICLK_p1), // input (serdes_P1) <= () | |
658 | .STCID (STCID_p1), // input (serdes_P1) <= () | |
659 | .TD0 (TD0_r_p1[9:0]), // input (serdes_P1) <= () | |
660 | .TD1 (TD1_r_p1[9:0]), // input (serdes_P1) <= () | |
661 | .TD2 (TD2_r_p1[9:0]), // input (serdes_P1) <= () | |
662 | .TD3 (TD3_r_p1[9:0]), // input (serdes_P1) <= () | |
663 | .TESTCFG (TESTCFG_p1[19:0]), // input (serdes_P1) <= () | |
664 | .TESTCLKR (TESTCLKR_p1), // input (serdes_P1) <= () | |
665 | .TESTCLKT (TESTCLKT_p1), // input (serdes_P1) <= () | |
666 | .TXBCLKIN (TXBCLKIN_p1[3:0]), // input (serdes_P1) <= () | |
667 | .AMUX (AMUX_p1), // output (serdes_P1) => () | |
668 | .FDO (FDO_p1), // output (serdes_P1) => () | |
669 | .RD0 (RD0_p1[9:0]), // output (serdes_P1) => () | |
670 | .RD1 (RD1_p1[9:0]), // output (serdes_P1) => () | |
671 | .RD2 (RD2_p1[9:0]), // output (serdes_P1) => () | |
672 | .RD3 (RD3_p1[9:0]), // output (serdes_P1) => () | |
673 | .RDLL0 (RDLL0_p1), // output (serdes_P1) => () | |
674 | .RDLL1 (RDLL1_p1), // output (serdes_P1) => () | |
675 | .RDLL2 (RDLL2_p1), // output (serdes_P1) => () | |
676 | .RDLL3 (RDLL3_p1), // output (serdes_P1) => () | |
677 | .RXBCLK (RXBCLK_p1), // output (serdes_P1) => () | |
678 | .RXBCLKLLN (RXBCLKLLN_p1), // output (serdes_P1) => () | |
679 | .RXBCLKLLP (RXBCLKLLP_p1), // output (serdes_P1) => () | |
680 | .STCIQ (STCIQ_p1), // output (serdes_P1) => () | |
681 | .STSPLL (STSPLL_p1), // output (serdes_P1) => () | |
682 | .STSRX0 (STSRX0_p1), // output (serdes_P1) => (pcs_1_ENV) | |
683 | .STSRX1 (STSRX1_p1), // output (serdes_P1) => () | |
684 | .STSRX2 (STSRX2_p1), // output (serdes_P1) => () | |
685 | .STSRX3 (STSRX3_p1), // output (serdes_P1) => () | |
686 | .STSTX0 (STSTX0_p1), // output (serdes_P1) => () | |
687 | .STSTX1 (STSTX1_p1), // output (serdes_P1) => () | |
688 | .STSTX2 (STSTX2_p1), // output (serdes_P1) => () | |
689 | .STSTX3 (STSTX3_p1), // output (serdes_P1) => () | |
690 | .TXBCLK (TXBCLK_p1), // output (serdes_P1) => () | |
691 | .TXN0 (TXN0_p1), // output (serdes_P1) => () | |
692 | .TXN1 (TXN1_p1), // output (serdes_P1) => () | |
693 | .TXN2 (TXN2_p1), // output (serdes_P1) => () | |
694 | .TXN3 (TXN3_p1), // output (serdes_P1) => () | |
695 | .TXP0 (TXP0_p1), // output (serdes_P1) => () | |
696 | .TXP1 (TXP1_p1), // output (serdes_P1) => () | |
697 | .TXP2 (TXP2_p1), // output (serdes_P1) => () | |
698 | .TXP3 (TXP3_p1) // output (serdes_P1) => () | |
699 | ); | |
700 | ||
701 | pcs pcs_0_ENV ( | |
702 | .rxclk (rxclk_mux0), // input (pcs_0_ENV) <= () | |
703 | .rx_10bdata (RD0_r_p0), // input (pcs_0_ENV,xgmii_A_dec_P0) <= () | |
704 | .rxd (pcs0_tx_data[7:0]), // output (pcs_0_ENV) => () | |
705 | .rx_dv (pcs0_tx_en), // output (pcs_0_ENV) => () | |
706 | .rx_er (pcs0_tx_err), // output (pcs_0_ENV) => () | |
707 | .serdes_rdy (serdes_rdy_pcs_ENV), // input (pcs_0_ENV,pcs_1_ENV) <= () | |
708 | .link_up_tx (link_up_tx_pcs_0_ENV), // output (pcs_0_ENV) => () | |
709 | .odd_rx (STSRX0_p0[2]), // input (pcs_0_ENV) <= (serdes_P0) | |
710 | .signal_detect (signal_detect_pcs_ENV), // input (pcs_0_ENV,pcs_1_ENV) <= () | |
711 | .an_loss_sync (an_loss_sync_pcs_ENV), // output (pcs_0_ENV,pcs_1_ENV) => () | |
712 | .txclk (txclk_mux0), // input (pcs_0_ENV) <= () | |
713 | .tx_en (m0_rx_dv), // input (pcs_0_ENV,xgmii_if_P0) <= () | |
714 | .tx_er (m0_rx_err), // input (pcs_0_ENV) <= () | |
715 | .crs (m0_rx_crs), // output (pcs_0_ENV) => () | |
716 | .col (m0_rx_col), // output (pcs_0_ENV) => () | |
717 | .txd (m0_rx_data[7:0]), // input (pcs_0_ENV,xgmii_if_P0) <= () | |
718 | .tx_10bdata (env_eser_rxd_a[9:0]), // output (pcs_0_ENV) => () | |
719 | .clk (core_clk), // input (pcs_0_ENV,pcs_1_ENV) <= () | |
720 | .pio_core_reset (reset), // input (pcs_0_ENV,pcs_1_ENV,xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
721 | .pio_core_sel (pio_core_sel_pcs_ENV), // input (pcs_0_ENV,pcs_1_ENV) <= () | |
722 | .pio_rd_wr (pio_rd_wr__pcs_ENV), // input (pcs_0_ENV,pcs_1_ENV) <= () | |
723 | .pio_addr (pio_addr_pcs_ENV), // input (pcs_0_ENV,pcs_1_ENV) <= () | |
724 | .pio_wr_data (pio_wr_data_pcs_ENV), // input (pcs_0_ENV,pcs_1_ENV) <= () | |
725 | .slink_state (slink_state_pcs_ENV), // input (pcs_0_ENV,pcs_1_ENV) <= () | |
726 | .pio_err (pio_err_pcs_0_ENV), // output (pcs_0_ENV) => () | |
727 | .pio_core_ack (pio_core_ack_pcs_ENV), // output (pcs_0_ENV,pcs_1_ENV) => () | |
728 | .pio_rd_data (pio_rd_data_pcs_ENV), // output (pcs_0_ENV,pcs_1_ENV) => () | |
729 | .sw_ensyncdet (sw_ensyncdet_pcs_ENV), // output (pcs_0_ENV,pcs_1_ENV) => () | |
730 | .sw_lockref (sw_lockref_pcs_ENV), // output (pcs_0_ENV,pcs_1_ENV) => () | |
731 | .phy_mode (phy_mode_pcs_ENV), // output (pcs_0_ENV,pcs_1_ENV) => () | |
732 | .shared_sel (shared_sel_pcs_ENV), // output (pcs_0_ENV,pcs_1_ENV) => () | |
733 | .pcs_int (pcs_int_pcs_ENV), // output (pcs_0_ENV,pcs_1_ENV) => () | |
734 | .ewrap (ewrap_pcs_ENV) // output (pcs_0_ENV,pcs_1_ENV) => () | |
735 | ); | |
736 | ||
737 | pcs pcs_1_ENV ( | |
738 | .rxclk (rxclk_mux1), // input (pcs_1_ENV) <= () | |
739 | .rx_10bdata (RD0_r_p1), // input (pcs_1_ENV,xgmii_A_dec_P1) <= () | |
740 | .rxd (pcs1_tx_data[7:0]), // output (pcs_1_ENV) => () | |
741 | .rx_dv (pcs1_tx_en), // output (pcs_1_ENV) => () | |
742 | .rx_er (pcs1_tx_err), // output (pcs_1_ENV) => () | |
743 | .serdes_rdy (serdes_rdy_pcs_ENV), // input (pcs_0_ENV,pcs_1_ENV) <= () | |
744 | .link_up_tx (link_up_tx_pcs_1_ENV), // output (pcs_1_ENV) => () | |
745 | .odd_rx (STSRX0_p1[2]), // input (pcs_1_ENV) <= (serdes_P1) | |
746 | .signal_detect (signal_detect_pcs_ENV), // input (pcs_0_ENV,pcs_1_ENV) <= () | |
747 | .an_loss_sync (an_loss_sync_pcs_ENV), // output (pcs_0_ENV,pcs_1_ENV) => () | |
748 | .txclk (txclk_mux1), // input (pcs_1_ENV) <= () | |
749 | .tx_en (m1_rx_dv), // input (pcs_1_ENV,xgmii_if_P1) <= () | |
750 | .tx_er (m1_rx_err), // input (pcs_1_ENV) <= () | |
751 | .crs (m1_rx_crs), // output (pcs_1_ENV) => () | |
752 | .col (m1_rx_col), // output (pcs_1_ENV) => () | |
753 | .txd (m1_rx_data[7:0]), // input (pcs_1_ENV,xgmii_if_P1) <= () | |
754 | .tx_10bdata (env_eser_rxd_b[9:0]), // output (pcs_1_ENV) => () | |
755 | .clk (core_clk), // input (pcs_0_ENV,pcs_1_ENV) <= () | |
756 | .pio_core_reset (reset), // input (pcs_0_ENV,pcs_1_ENV,xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
757 | .pio_core_sel (pio_core_sel_pcs_ENV), // input (pcs_0_ENV,pcs_1_ENV) <= () | |
758 | .pio_rd_wr (pio_rd_wr__pcs_ENV), // input (pcs_0_ENV,pcs_1_ENV) <= () | |
759 | .pio_addr (pio_addr_pcs_ENV), // input (pcs_0_ENV,pcs_1_ENV) <= () | |
760 | .pio_wr_data (pio_wr_data_pcs_ENV), // input (pcs_0_ENV,pcs_1_ENV) <= () | |
761 | .slink_state (slink_state_pcs_ENV), // input (pcs_0_ENV,pcs_1_ENV) <= () | |
762 | .pio_err (pio_err_pcs_1_ENV), // output (pcs_1_ENV) => () | |
763 | .pio_core_ack (pio_core_ack_pcs_ENV), // output (pcs_0_ENV,pcs_1_ENV) => () | |
764 | .pio_rd_data (pio_rd_data_pcs_ENV), // output (pcs_0_ENV,pcs_1_ENV) => () | |
765 | .sw_ensyncdet (sw_ensyncdet_pcs_ENV), // output (pcs_0_ENV,pcs_1_ENV) => () | |
766 | .sw_lockref (sw_lockref_pcs_ENV), // output (pcs_0_ENV,pcs_1_ENV) => () | |
767 | .phy_mode (phy_mode_pcs_ENV), // output (pcs_0_ENV,pcs_1_ENV) => () | |
768 | .shared_sel (shared_sel_pcs_ENV), // output (pcs_0_ENV,pcs_1_ENV) => () | |
769 | .pcs_int (pcs_int_pcs_ENV), // output (pcs_0_ENV,pcs_1_ENV) => () | |
770 | .ewrap (ewrap_pcs_ENV) // output (pcs_0_ENV,pcs_1_ENV) => () | |
771 | ); | |
772 | ||
773 | phy_clock_doubler_env phy_clk_doubler_0_ENV ( | |
774 | .rbc0 (eser_env_rbc0_a), // input (phy_clk_doubler_0_ENV) <= () | |
775 | .rbc1 (eser_env_rbc1_a), // input (phy_clk_doubler_0_ENV) <= () | |
776 | .rbcx2 (rx_clk_pcs0_ENV) // output (phy_clk_doubler_0_ENV) => () | |
777 | ); | |
778 | ||
779 | phy_clock_doubler_env phy_clk_doubler_1_ENV ( | |
780 | .rbc0 (eser_env_rbc0_b), // input (phy_clk_doubler_1_ENV) <= () | |
781 | .rbc1 (eser_env_rbc1_b), // input (phy_clk_doubler_1_ENV) <= () | |
782 | .rbcx2 (rx_clk_pcs1_ENV) // output (phy_clk_doubler_1_ENV) => () | |
783 | ); | |
784 | ||
785 | xgmii_tx_encoder_top xgmii_tx_enc_top_P0 ( | |
786 | .tx_clk (ref_clk), // input (xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
787 | .tx_rst (reset), // input (pcs_0_ENV,pcs_1_ENV,xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
788 | .tx_enc_in (xgmii_rxd0[31:0]), // input (xgmii_tx_enc_top_P0) <= (xgmii_if_P0) | |
789 | .tx_ctrl_in (xgmii_rxc0[3:0]), // input (xgmii_tx_enc_top_P0) <= (xgmii_if_P0) | |
790 | .RDreg (RDreg[0]), // output (xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) => () | |
791 | .tx_10b_enc_out_a (temp_enc_ch0_p0[9:0]), // output (xgmii_tx_enc_top_P0) => () | |
792 | .tx_10b_enc_out_b (temp_enc_ch1_p0[9:0]), // output (xgmii_tx_enc_top_P0) => () | |
793 | .tx_10b_enc_out_c (temp_enc_ch2_p0[9:0]), // output (xgmii_tx_enc_top_P0) => () | |
794 | .tx_10b_enc_out_d (temp_enc_ch3_p0[9:0]) // output (xgmii_tx_enc_top_P0) => () | |
795 | ); | |
796 | ||
797 | xgmii_tx_encoder_top xgmii_tx_enc_top_P1 ( | |
798 | .tx_clk (ref_clk), // input (xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
799 | .tx_rst (reset), // input (pcs_0_ENV,pcs_1_ENV,xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
800 | .tx_enc_in (xgmii_rxd1[31:0]), // input (xgmii_tx_enc_top_P1) <= (xgmii_if_P1) | |
801 | .tx_ctrl_in (xgmii_rxc1[3:0]), // input (xgmii_tx_enc_top_P1) <= (xgmii_if_P1) | |
802 | .RDreg (RDreg[0]), // output (xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) => () | |
803 | .tx_10b_enc_out_a (temp_enc_ch0_p1[9:0]), // output (xgmii_tx_enc_top_P1) => () | |
804 | .tx_10b_enc_out_b (temp_enc_ch1_p1[9:0]), // output (xgmii_tx_enc_top_P1) => () | |
805 | .tx_10b_enc_out_c (temp_enc_ch2_p1[9:0]), // output (xgmii_tx_enc_top_P1) => () | |
806 | .tx_10b_enc_out_d (temp_enc_ch3_p1[9:0]) // output (xgmii_tx_enc_top_P1) => () | |
807 | ); | |
808 | ||
809 | xgmii_rx_decoder xgmii_A_dec_P0 ( | |
810 | .rx_clk (ref_clk), // input (xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
811 | .rst (reset), // input (pcs_0_ENV,pcs_1_ENV,xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
812 | .rx_10bdec_in (RD0_r_p0[9:0]), // input (pcs_0_ENV,xgmii_A_dec_P0) <= () | |
813 | .rx_8bdec_out (xgmii_txd0_in[7:0]), // output (xgmii_A_dec_P0,xgmii_B_dec_P0,xgmii_C_dec_P0,xgmii_D_dec_P0) => (xgmii_if_P0) | |
814 | .special (xgmii_txc0_in[0]) // output (xgmii_A_dec_P0,xgmii_B_dec_P0,xgmii_C_dec_P0,xgmii_D_dec_P0) => (xgmii_if_P0) | |
815 | ); | |
816 | ||
817 | xgmii_rx_decoder xgmii_B_dec_P0 ( | |
818 | .rx_clk (ref_clk), // input (xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
819 | .rst (reset), // input (pcs_0_ENV,pcs_1_ENV,xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
820 | .rx_10bdec_in (RD1_r_p0[9:0]), // input (xgmii_B_dec_P0) <= () | |
821 | .rx_8bdec_out (xgmii_txd0_in[15:8]), // output (xgmii_A_dec_P0,xgmii_B_dec_P0,xgmii_C_dec_P0,xgmii_D_dec_P0) => (xgmii_if_P0) | |
822 | .special (xgmii_txc0_in[1]) // output (xgmii_A_dec_P0,xgmii_B_dec_P0,xgmii_C_dec_P0,xgmii_D_dec_P0) => (xgmii_if_P0) | |
823 | ); | |
824 | ||
825 | xgmii_rx_decoder xgmii_C_dec_P0 ( | |
826 | .rx_clk (ref_clk), // input (xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
827 | .rst (reset), // input (pcs_0_ENV,pcs_1_ENV,xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
828 | .rx_10bdec_in (RD2_r_p0[9:0]), // input (xgmii_C_dec_P0) <= () | |
829 | .rx_8bdec_out (xgmii_txd0_in[23:16]), // output (xgmii_A_dec_P0,xgmii_B_dec_P0,xgmii_C_dec_P0,xgmii_D_dec_P0) => (xgmii_if_P0) | |
830 | .special (xgmii_txc0_in[2]) // output (xgmii_A_dec_P0,xgmii_B_dec_P0,xgmii_C_dec_P0,xgmii_D_dec_P0) => (xgmii_if_P0) | |
831 | ); | |
832 | ||
833 | xgmii_rx_decoder xgmii_D_dec_P0 ( | |
834 | .rx_clk (ref_clk), // input (xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
835 | .rst (reset), // input (pcs_0_ENV,pcs_1_ENV,xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
836 | .rx_10bdec_in (RD3_r_p0[9:0]), // input (xgmii_D_dec_P0) <= () | |
837 | .rx_8bdec_out (xgmii_txd0_in[31:24]), // output (xgmii_A_dec_P0,xgmii_B_dec_P0,xgmii_C_dec_P0,xgmii_D_dec_P0) => (xgmii_if_P0) | |
838 | .special (xgmii_txc0_in[3]) // output (xgmii_A_dec_P0,xgmii_B_dec_P0,xgmii_C_dec_P0,xgmii_D_dec_P0) => (xgmii_if_P0) | |
839 | ); | |
840 | ||
841 | xgmii_rx_decoder xgmii_A_dec_P1 ( | |
842 | .rx_clk (ref_clk), // input (xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
843 | .rst (reset), // input (pcs_0_ENV,pcs_1_ENV,xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
844 | .rx_10bdec_in (RD0_r_p1[9:0]), // input (pcs_1_ENV,xgmii_A_dec_P1) <= () | |
845 | .rx_8bdec_out (xgmii_txd1_in[7:0]), // output (xgmii_A_dec_P1,xgmii_B_dec_P1,xgmii_C_dec_P1,xgmii_D_dec_P1) => (xgmii_if_P1) | |
846 | .special (xgmii_txc1_in[0]) // output (xgmii_A_dec_P1,xgmii_B_dec_P1,xgmii_C_dec_P1,xgmii_D_dec_P1) => (xgmii_if_P1) | |
847 | ); | |
848 | ||
849 | xgmii_rx_decoder xgmii_B_dec_P1 ( | |
850 | .rx_clk (ref_clk), // input (xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
851 | .rst (reset), // input (pcs_0_ENV,pcs_1_ENV,xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
852 | .rx_10bdec_in (RD1_r_p1[9:0]), // input (xgmii_B_dec_P1) <= () | |
853 | .rx_8bdec_out (xgmii_txd1_in[15:8]), // output (xgmii_A_dec_P1,xgmii_B_dec_P1,xgmii_C_dec_P1,xgmii_D_dec_P1) => (xgmii_if_P1) | |
854 | .special (xgmii_txc1_in[1]) // output (xgmii_A_dec_P1,xgmii_B_dec_P1,xgmii_C_dec_P1,xgmii_D_dec_P1) => (xgmii_if_P1) | |
855 | ); | |
856 | ||
857 | xgmii_rx_decoder xgmii_C_dec_P1 ( | |
858 | .rx_clk (ref_clk), // input (xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
859 | .rst (reset), // input (pcs_0_ENV,pcs_1_ENV,xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
860 | .rx_10bdec_in (RD2_r_p1[9:0]), // input (xgmii_C_dec_P1) <= () | |
861 | .rx_8bdec_out (xgmii_txd1_in[23:16]), // output (xgmii_A_dec_P1,xgmii_B_dec_P1,xgmii_C_dec_P1,xgmii_D_dec_P1) => (xgmii_if_P1) | |
862 | .special (xgmii_txc1_in[2]) // output (xgmii_A_dec_P1,xgmii_B_dec_P1,xgmii_C_dec_P1,xgmii_D_dec_P1) => (xgmii_if_P1) | |
863 | ); | |
864 | ||
865 | xgmii_rx_decoder xgmii_D_dec_P1 ( | |
866 | .rx_clk (ref_clk), // input (xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
867 | .rst (reset), // input (pcs_0_ENV,pcs_1_ENV,xgmii_A_dec_P0,xgmii_A_dec_P1,xgmii_B_dec_P0,xgmii_B_dec_P1,xgmii_C_dec_P0,xgmii_C_dec_P1,xgmii_D_dec_P0,xgmii_D_dec_P1,xgmii_tx_enc_top_P0,xgmii_tx_enc_top_P1) <= () | |
868 | .rx_10bdec_in (RD3_r_p1[9:0]), // input (xgmii_D_dec_P1) <= () | |
869 | .rx_8bdec_out (xgmii_txd1_in[31:24]), // output (xgmii_A_dec_P1,xgmii_B_dec_P1,xgmii_C_dec_P1,xgmii_D_dec_P1) => (xgmii_if_P1) | |
870 | .special (xgmii_txc1_in[3]) // output (xgmii_A_dec_P1,xgmii_B_dec_P1,xgmii_C_dec_P1,xgmii_D_dec_P1) => (xgmii_if_P1) | |
871 | ); | |
872 | ||
873 | xgmii_if xgmii_if_P0 ( | |
874 | .rxd (m0_rx_data), // input (pcs_0_ENV,xgmii_if_P0) <= () | |
875 | .rxdv (m0_rx_dv), // input (pcs_0_ENV,xgmii_if_P0) <= () | |
876 | .rx_clk (m0_rx_clk), // input (xgmii_if_P0) <= (port0_clk) | |
877 | .txd_xgmii (xgmii_txd0_in[31:0]), // input (xgmii_if_P0) <= (xgmii_A_dec_P0,xgmii_B_dec_P0,xgmii_C_dec_P0,xgmii_D_dec_P0) | |
878 | .txctrl_xgmii (xgmii_txc0_in[3:0]), // input (xgmii_if_P0) <= (xgmii_A_dec_P0,xgmii_B_dec_P0,xgmii_C_dec_P0,xgmii_D_dec_P0) | |
879 | .tx_clk (m0_rx_clk), // input (xgmii_if_P0) <= (port0_clk) | |
880 | .rx_clk_xgmii (rx_clk_xgmii), // output (xgmii_if_P0,xgmii_if_P1) => () | |
881 | .rxd_xgmii (xgmii_rxd0), // output (xgmii_if_P0) => (xgmii_tx_enc_top_P0) | |
882 | .rxctrl_xgmii (xgmii_rxc0), // output (xgmii_if_P0) => (xgmii_tx_enc_top_P0) | |
883 | .tx_clk_xgmii (tx_clk_xgmii0), // output (xgmii_if_P0) => () | |
884 | .txd (m0_xgmii_txdata), // output (xgmii_if_P0) => () | |
885 | .txen (m0_xgmii_tx_en) // output (xgmii_if_P0) => () | |
886 | ); | |
887 | ||
888 | xgmii_if xgmii_if_P1 ( | |
889 | .rxd (m1_rx_data), // input (pcs_1_ENV,xgmii_if_P1) <= () | |
890 | .rxdv (m1_rx_dv), // input (pcs_1_ENV,xgmii_if_P1) <= () | |
891 | .rx_clk (m1_rx_clk), // input (xgmii_if_P1) <= (port1_clk) | |
892 | .txd_xgmii (xgmii_txd1_in[31:0]), // input (xgmii_if_P1) <= (xgmii_A_dec_P1,xgmii_B_dec_P1,xgmii_C_dec_P1,xgmii_D_dec_P1) | |
893 | .txctrl_xgmii (xgmii_txc1_in[3:0]), // input (xgmii_if_P1) <= (xgmii_A_dec_P1,xgmii_B_dec_P1,xgmii_C_dec_P1,xgmii_D_dec_P1) | |
894 | .tx_clk (m1_rx_clk), // input (xgmii_if_P1) <= (port1_clk) | |
895 | .rx_clk_xgmii (rx_clk_xgmii), // output (xgmii_if_P0,xgmii_if_P1) => () | |
896 | .rxd_xgmii (xgmii_rxd1), // output (xgmii_if_P1) => (xgmii_tx_enc_top_P1) | |
897 | .rxctrl_xgmii (xgmii_rxc1), // output (xgmii_if_P1) => (xgmii_tx_enc_top_P1) | |
898 | .tx_clk_xgmii (tx_clk_xgmii1), // output (xgmii_if_P1) => () | |
899 | .txd (m1_xgmii_txdata), // output (xgmii_if_P1) => () | |
900 | .txen (m1_xgmii_tx_en) // output (xgmii_if_P1) => () | |
901 | ); | |
902 | ||
903 | port_clk port0_clk ( | |
904 | .tx_clkp (m0_tx_clk_port), // output (port0_clk) => () | |
905 | .tx_clkn (tx_clkn), // output (port0_clk,port1_clk,port2_clk,port3_clk) => () | |
906 | .rx_clkp (m0_rx_clk), // output (port0_clk) => (xgmii_if_P0) | |
907 | .rx_clkn (rx_clkn), // output (port0_clk,port1_clk,port2_clk,port3_clk) => () | |
908 | .tx_config (m0_tx_config[3:0]), // input (port0_clk) <= () | |
909 | .rx_config (m0_rx_config[3:0]) // input (port0_clk) <= () | |
910 | ); | |
911 | ||
912 | port_clk port1_clk ( | |
913 | .tx_clkp (m1_tx_clk_port), // output (port1_clk) => () | |
914 | .tx_clkn (tx_clkn), // output (port0_clk,port1_clk,port2_clk,port3_clk) => () | |
915 | .rx_clkp (m1_rx_clk), // output (port1_clk) => (xgmii_if_P1) | |
916 | .rx_clkn (rx_clkn), // output (port0_clk,port1_clk,port2_clk,port3_clk) => () | |
917 | .tx_config (m1_tx_config[3:0]), // input (port1_clk) <= () | |
918 | .rx_config (m1_rx_config[3:0]) // input (port1_clk) <= () | |
919 | ); | |
920 | ||
921 | port_clk port2_clk ( | |
922 | .tx_clkp (m2_tx_clk_port), // output (port2_clk) => () | |
923 | .tx_clkn (tx_clkn), // output (port0_clk,port1_clk,port2_clk,port3_clk) => () | |
924 | .rx_clkp (m2_rx_clk), // output (port2_clk) => () | |
925 | .rx_clkn (rx_clkn), // output (port0_clk,port1_clk,port2_clk,port3_clk) => () | |
926 | .tx_config (m2_tx_config[3:0]), // input (port2_clk) <= () | |
927 | .rx_config (m2_rx_config[3:0]) // input (port2_clk) <= () | |
928 | ); | |
929 | ||
930 | port_clk port3_clk ( | |
931 | .tx_clkp (m3_tx_clk_port), // output (port3_clk) => () | |
932 | .tx_clkn (tx_clkn), // output (port0_clk,port1_clk,port2_clk,port3_clk) => () | |
933 | .rx_clkp (m3_rx_clk), // output (port3_clk) => () | |
934 | .rx_clkn (rx_clkn), // output (port0_clk,port1_clk,port2_clk,port3_clk) => () | |
935 | .tx_config (m3_tx_config[3:0]), // input (port3_clk) <= () | |
936 | .rx_config (m3_rx_config[3:0]) // input (port3_clk) <= () | |
937 | ); | |
938 | ||
939 | bw_calc BW_CALC_P0 ( | |
940 | .clk (m0_tx_clk), // input (BW_CALC_P0) <= () | |
941 | .data (m0_tx_data), // input (BW_CALC_P0) <= () | |
942 | .enb (m0_tx_en), // input (BW_CALC_P0) <= () | |
943 | .cal_enb (enb_bwcal_r), // input (BW_CALC_P0,BW_CALC_P1) <= () | |
944 | .speed_10G (speed_10G_w), // input (BW_CALC_P0,BW_CALC_P1) <= () | |
945 | .port_num ({VLO,VLO}), // input (BW_CALC_P0,BW_CALC_P1) <= () | |
946 | .no_of_pkts (no_of_txpkts_r), // input (BW_CALC_P0,BW_CALC_P1) <= () | |
947 | .pkt_len (tx_pkt_len_r) // input (BW_CALC_P0,BW_CALC_P1) <= () | |
948 | ); | |
949 | ||
950 | bw_calc BW_CALC_P1 ( | |
951 | .clk (m1_tx_clk), // input (BW_CALC_P1) <= () | |
952 | .data (m1_tx_data), // input (BW_CALC_P1) <= () | |
953 | .enb (m1_tx_en), // input (BW_CALC_P1) <= () | |
954 | .cal_enb (enb_bwcal_r), // input (BW_CALC_P0,BW_CALC_P1) <= () | |
955 | .speed_10G (speed_10G_w), // input (BW_CALC_P0,BW_CALC_P1) <= () | |
956 | .port_num ({VLO,VDD}), // input (BW_CALC_P0,BW_CALC_P1) <= () | |
957 | .no_of_pkts (no_of_txpkts_r), // input (BW_CALC_P0,BW_CALC_P1) <= () | |
958 | .pkt_len (tx_pkt_len_r) // input (BW_CALC_P0,BW_CALC_P1) <= () | |
959 | ); | |
960 | // VPERL: GENERATED_END | |
961 | ||
962 | //------------------------------------------------------------ | |
963 | // SerDes_ENV initialization | |
964 | //------------------------------------------------------------ | |
965 | ||
966 | assign w_BT_EN = 1'b0; | |
967 | assign w_RO_EN = 1'b0; | |
968 | assign w_SYNC_CHAR = 10'b0101111100; | |
969 | assign w_SYNC_MASK = 5'b00000; | |
970 | ||
971 | ||
972 | assign w_TEST_EN = 1'b0; | |
973 | assign w_BS_MODE = 1'b0; | |
974 | assign w_FORCE_DRV_DIS = 1'b0; | |
975 | assign w_TX_BS_SEL = 1'b0; | |
976 | ||
977 | ||
978 | assign env_eser_pll_en = 1; | |
979 | assign env_eser_bias_en = 1; | |
980 | assign env_eser_tclk_sel = 1; | |
981 | assign env_eser_drv_emp_lvl_a[1] = 0; | |
982 | assign env_eser_drv_emp_lvl_a[0] = 0; | |
983 | assign env_eser_drv_emp_lvl_b[1] = 0; | |
984 | assign env_eser_drv_emp_lvl_b[0] = 0; | |
985 | assign env_eser_drv_emp_lvl_c[1] = 0; | |
986 | assign env_eser_drv_emp_lvl_c[0] = 0; | |
987 | assign env_eser_drv_emp_lvl_d[1] = 0; | |
988 | assign env_eser_drv_emp_lvl_d[0] = 0; | |
989 | /** | |
990 | assign env_eser_ser_sel[1] = 0; | |
991 | assign env_eser_ser_sel[0] = 0; | |
992 | assign env_eser_refclk_sel = 0; | |
993 | **/ | |
994 | assign env_eser_trd_sel = 0; | |
995 | assign env_eser_low_latency = 0; | |
996 | assign env_eser_sync_dual_pol = 1; | |
997 | assign env_eser_tubi[5] = 0; | |
998 | assign env_eser_tubi[4] = 0; | |
999 | assign env_eser_tubi[3] = 0; | |
1000 | assign env_eser_tubi[2] = 0; | |
1001 | assign env_eser_tubi[1] = 0; | |
1002 | assign env_eser_tubi[0] = 0; | |
1003 | assign env_eser_tx_en_a = 1; | |
1004 | assign env_eser_tx_en_b = 1; | |
1005 | assign env_eser_tx_en_c = 1; | |
1006 | assign env_eser_tx_en_d = 1; | |
1007 | assign env_eser_tx_clk_en_a = 1; | |
1008 | assign env_eser_tx_clk_en_b = 1; | |
1009 | assign env_eser_tx_clk_en_c = 1; | |
1010 | assign env_eser_tx_clk_en_d = 1; | |
1011 | assign env_eser_drv_en_a = 1; | |
1012 | assign env_eser_drv_en_b = 1; | |
1013 | assign env_eser_drv_en_c = 1; | |
1014 | assign env_eser_drv_en_d = 1; | |
1015 | assign env_eser_lev_sel_a[1] = 0; | |
1016 | assign env_eser_lev_sel_b[1] = 0; | |
1017 | assign env_eser_lev_sel_c[1] = 0; | |
1018 | assign env_eser_lev_sel_d[1] = 0; | |
1019 | assign env_eser_lev_sel_a[0] = 0; | |
1020 | assign env_eser_lev_sel_b[0] = 0; | |
1021 | assign env_eser_lev_sel_c[0] = 0; | |
1022 | assign env_eser_lev_sel_d[0] = 0; | |
1023 | assign env_eser_tx_lpb_en_a = 0; | |
1024 | assign env_eser_tx_lpb_en_b = 0; | |
1025 | assign env_eser_tx_lpb_en_c = 0; | |
1026 | assign env_eser_tx_lpb_en_d = 0; | |
1027 | assign env_eser_rx_lpb_en_a = 0; | |
1028 | assign env_eser_rx_lpb_en_b = 0; | |
1029 | assign env_eser_rx_lpb_en_c = 0; | |
1030 | assign env_eser_rx_lpb_en_d = 0; | |
1031 | assign env_eser_rx_en_a = 1; | |
1032 | assign env_eser_rx_en_b = 1; | |
1033 | assign env_eser_rx_en_c = 1; | |
1034 | assign env_eser_rx_en_d = 1; | |
1035 | assign env_eser_rx_clk_en_a = 1; | |
1036 | assign env_eser_rx_clk_en_b = 1; | |
1037 | assign env_eser_rx_clk_en_c = 1; | |
1038 | assign env_eser_rx_clk_en_d = 1; | |
1039 | assign env_eser_rx_sleep_en_a = 1; | |
1040 | assign env_eser_rx_sleep_en_b = 1; | |
1041 | assign env_eser_rx_sleep_en_c = 1; | |
1042 | assign env_eser_rx_sleep_en_d = 1; | |
1043 | assign env_eser_rbc_sel_a = 0; | |
1044 | assign env_eser_rbc_sel_b = 0; | |
1045 | assign env_eser_rbc_sel_c = 0; | |
1046 | assign env_eser_rbc_sel_d = 0; | |
1047 | assign env_eser_byte_sync_en_a = 1; | |
1048 | assign env_eser_byte_sync_en_b = 1; | |
1049 | assign env_eser_byte_sync_en_c = 1; | |
1050 | assign env_eser_byte_sync_en_d = 1; | |
1051 | assign env_eser_sync_sel_a = 0; | |
1052 | assign env_eser_sync_sel_b = 0; | |
1053 | assign env_eser_sync_sel_c = 0; | |
1054 | assign env_eser_sync_sel_d = 0; | |
1055 | assign env_eser_rx_reset_a = 0; | |
1056 | assign env_eser_rx_reset_b = 0; | |
1057 | assign env_eser_rx_reset_c = 0; | |
1058 | assign env_eser_rx_reset_d = 0; | |
1059 | ||
1060 | ||
1061 | ||
1062 | ||
1063 | //------------------------------------------------------------ | |
1064 | // pcs_ENV initialization | |
1065 | //------------------------------------------------------------ | |
1066 | ||
1067 | assign signal_detect_pcs_ENV = 1; | |
1068 | assign serdes_rdy_pcs_ENV = 1; | |
1069 | assign #2 odd_rx_pcs0_ENV = eser_env_rbc1_a; | |
1070 | assign #2 odd_rx_pcs1_ENV = eser_env_rbc1_b; | |
1071 | //assign #2 odd_rx_pcs2_ENV = eser_env_rbc1_c; | |
1072 | //assign #2 odd_rx_pcs3_ENV = eser_env_rbc1_d; | |
1073 | assign pio_core_sel_pcs_ENV = 1; | |
1074 | assign pio_rd_wr__pcs_ENV = 0; | |
1075 | assign pio_addr_pcs_ENV = 0; | |
1076 | assign pio_wr_data_pcs_ENV = 0; | |
1077 | assign slink_state_pcs_ENV = 0; | |
1078 | ||
1079 | // asign TD and xgmii_env_esr | |
1080 | ||
1081 | assign TD0_p0 = temp_enc_ch0_p0; | |
1082 | assign TD1_p0 = temp_enc_ch1_p0; | |
1083 | assign TD2_p0 = temp_enc_ch2_p0; | |
1084 | assign TD3_p0 = temp_enc_ch3_p0; | |
1085 | ||
1086 | assign TD0_p1 = temp_enc_ch0_p1; | |
1087 | assign TD1_p1 = temp_enc_ch1_p1; | |
1088 | assign TD2_p1 = temp_enc_ch2_p1; | |
1089 | assign TD3_p1 = temp_enc_ch3_p1; | |
1090 | ||
1091 | ||
1092 | initial begin | |
1093 | force enet_models.pcs_0_ENV.pcs_slave.phy_mode_ext_xREG2.qout=2'b10; | |
1094 | force enet_models.pcs_0_ENV.pcs_slave.pcs_config_xREG2.qout=7'h21; | |
1095 | force enet_models.pcs_1_ENV.pcs_slave.phy_mode_ext_xREG2.qout=2'b10; | |
1096 | force enet_models.pcs_1_ENV.pcs_slave.pcs_config_xREG2.qout=7'h21; | |
1097 | //force enet_models.pcs_2_ENV.pcs_slave.phy_mode_ext_xREG2.qout=2'b10; | |
1098 | //force enet_models.pcs_2_ENV.pcs_slave.pcs_config_xREG2.qout=7'h21; | |
1099 | //force enet_models.pcs_3_ENV.pcs_slave.phy_mode_ext_xREG2.qout=2'b10; | |
1100 | //force enet_models.pcs_3_ENV.pcs_slave.pcs_config_xREG2.qout=7'h21; | |
1101 | end | |
1102 | ||
1103 | ||
1104 | reg sel_gmii; | |
1105 | integer speed0,speed1; | |
1106 | integer mac_port; | |
1107 | reg speed_10G; | |
1108 | reg[8*60:1] arg,arg0,arg1,arg2,arg3; | |
1109 | reg enb_bwcal; | |
1110 | integer no_of_txpkts,tx_pkt_len; | |
1111 | integer tb_time_out; | |
1112 | reg [31:0] CycleCounter; | |
1113 | ||
1114 | `ifdef TEST_UNH_VECTORS | |
1115 | initial begin | |
1116 | ||
1117 | if ($value$plusargs ("tb_time_out=%d", tb_time_out)) begin | |
1118 | $display("SET tb_time_out = %d", tb_time_out); | |
1119 | end // if ($value$plusargs ("tb_time_out=%d", tb_time_out)) | |
1120 | else | |
1121 | begin | |
1122 | tb_time_out = 1999999; | |
1123 | $display("SET tb_time_out = %d", tb_time_out); | |
1124 | end // else: !if($value$plusargs ("tb_time_out=%d", tb_time_out)) | |
1125 | end // initial begin | |
1126 | ||
1127 | initial CycleCounter = 0; | |
1128 | ||
1129 | always @(posedge core_clk) | |
1130 | begin | |
1131 | CycleCounter = CycleCounter+1; | |
1132 | if(CycleCounter % 100000 == 0) | |
1133 | $display("INFO Simulation CycleCounter = %d", CycleCounter); | |
1134 | end | |
1135 | ||
1136 | always @(posedge core_clk) | |
1137 | begin | |
1138 | if(CycleCounter > tb_time_out) | |
1139 | begin | |
1140 | $display("INFO Simulation is quitting at CycleCounter = %d for UNH TESTS", CycleCounter); | |
1141 | $finish; | |
1142 | end // if (CycleCounter == 32'h5_4000) | |
1143 | end // always @ (posedge SystemClock) | |
1144 | `else | |
1145 | `endif | |
1146 | ||
1147 | /* reg [9:0] xgmii_env_eser_rxd_a; | |
1148 | reg [9:0] xgmii_env_eser_rxd_b; | |
1149 | reg [9:0] xgmii_env_eser_rxd_c; | |
1150 | reg [9:0] xgmii_env_eser_rxd_d; */ | |
1151 | ||
1152 | wire [9:0] xgmii_env_eser_rxd_a; | |
1153 | wire [9:0] xgmii_env_eser_rxd_b; | |
1154 | wire [9:0] xgmii_env_eser_rxd_c; | |
1155 | wire [9:0] xgmii_env_eser_rxd_d; | |
1156 | ||
1157 | ||
1158 | initial | |
1159 | begin | |
1160 | arg = "GET_MAC_PORTS="; | |
1161 | ||
1162 | if ($test$plusargs("GET_MAC_PORTS=")) | |
1163 | mac_port = $util_get_plus_args_num(arg); | |
1164 | $display("mc_core : Ethernet Port is %0d \n",mac_port); | |
1165 | end | |
1166 | ||
1167 | /* if (mac_port == 0) | |
1168 | begin | |
1169 | xgmii_env_eser_rxd_a = temp_enc_ch0_p0; | |
1170 | xgmii_env_eser_rxd_b = temp_enc_ch1_p0; | |
1171 | xgmii_env_eser_rxd_c = temp_enc_ch2_p0; | |
1172 | xgmii_env_eser_rxd_d = temp_enc_ch3_p0; | |
1173 | end | |
1174 | else if (mac_port == 1) | |
1175 | begin | |
1176 | xgmii_env_eser_rxd_a = temp_enc_ch0_p1; | |
1177 | xgmii_env_eser_rxd_b = temp_enc_ch1_p1; | |
1178 | xgmii_env_eser_rxd_c = temp_enc_ch2_p1; | |
1179 | xgmii_env_eser_rxd_d = temp_enc_ch3_p1; | |
1180 | end | |
1181 | end */ | |
1182 | ||
1183 | assign xgmii_env_eser_rxd_a = mac_port ? temp_enc_ch0_p1 : temp_enc_ch0_p0; | |
1184 | assign xgmii_env_eser_rxd_b = mac_port ? temp_enc_ch1_p1 : temp_enc_ch1_p0; | |
1185 | assign xgmii_env_eser_rxd_c = mac_port ? temp_enc_ch2_p1 : temp_enc_ch2_p0; | |
1186 | assign xgmii_env_eser_rxd_d = mac_port ? temp_enc_ch3_p1 : temp_enc_ch3_p0; | |
1187 | ||
1188 | ||
1189 | initial | |
1190 | begin | |
1191 | ||
1192 | /* Check MAC_SPEED0 */ | |
1193 | ||
1194 | arg0 = "MAC_SPEED0="; | |
1195 | if ($test$plusargs("MAC_SPEED0=")) | |
1196 | speed0 = $util_get_plus_args_num(arg0); | |
1197 | else speed0 = 1000; | |
1198 | ||
1199 | /* Check MAC_SPEED1 */ | |
1200 | ||
1201 | arg1 = "MAC_SPEED1="; | |
1202 | if ($test$plusargs("MAC_SPEED1=")) | |
1203 | speed1 = $util_get_plus_args_num(arg1); | |
1204 | else speed1 = 1000; | |
1205 | ||
1206 | arg2 = "TX_PKT_CNT="; | |
1207 | /* check for no_of_pkts */ | |
1208 | if ($test$plusargs("TX_PKT_CNT=")) begin | |
1209 | no_of_txpkts = $util_get_plus_args_num(arg2); | |
1210 | $display("Number of tx_pkts %0d\n",no_of_txpkts); | |
1211 | end | |
1212 | ||
1213 | arg3 = "TX_PKT_LEN="; | |
1214 | /* check for no_of_pkts */ | |
1215 | if ($test$plusargs("TX_PKT_LEN=")) begin | |
1216 | tx_pkt_len = $util_get_plus_args_num(arg3); | |
1217 | $display("Tx_pkt_len %0d\n",tx_pkt_len); | |
1218 | end | |
1219 | ||
1220 | ||
1221 | if ((speed0 == 10000) ||(speed1 == 10000)) | |
1222 | begin | |
1223 | $display("mc_core : Ethernet Speed 10G\n"); | |
1224 | speed_10G = 1; | |
1225 | end | |
1226 | else | |
1227 | begin | |
1228 | $display("mac_core : Ethernet Speed0 Speed1 %0d, %0d\n",speed0, speed1); | |
1229 | speed_10G = 0; | |
1230 | end | |
1231 | ||
1232 | /* Check PCS_SERDES */ | |
1233 | ||
1234 | if ($test$plusargs("PCS_SERDES")) | |
1235 | begin | |
1236 | $display("mac_core : Ethernet SerDes Mode\n"); | |
1237 | sel_gmii = 0; | |
1238 | end | |
1239 | else | |
1240 | begin | |
1241 | $display("mac_core : Ethernet RGMII Mode\n"); | |
1242 | sel_gmii = 1; | |
1243 | end | |
1244 | ||
1245 | /* check if perf test */ | |
1246 | ||
1247 | if($test$plusargs("PERF_TEST")) | |
1248 | begin | |
1249 | $display("BANDW_CAL_ON\n"); | |
1250 | enb_bwcal = 1; | |
1251 | end | |
1252 | else | |
1253 | enb_bwcal = 0; | |
1254 | ||
1255 | end | |
1256 | ||
1257 | assign no_of_txpkts_r = no_of_txpkts; | |
1258 | assign tx_pkt_len_r = tx_pkt_len; | |
1259 | assign enb_bwcal_r = enb_bwcal; | |
1260 | assign speed_10G_w = speed_10G; | |
1261 | ||
1262 | //////////////////////////////////////////////////// | |
1263 | // INJECT_10b_ERRORS //port0 only | |
1264 | // test specific, only sends corrupt pattern for `corrupt_time_limit | |
1265 | `define corrupt_time_limit 160000 | |
1266 | `define corrupt_limit_min 300 | |
1267 | `define corrupt_limit_max 600 | |
1268 | ||
1269 | reg [9:0] txd_corrupt; | |
1270 | integer corrupt_cnt=0; | |
1271 | integer corrupt_limit=`corrupt_limit_min; | |
1272 | reg corrupt; | |
1273 | reg inject_10b_errors=0; | |
1274 | ||
1275 | initial begin | |
1276 | corrupt=0; | |
1277 | txd_corrupt='h17c; | |
1278 | if($test$plusargs("INJECT_10b_ERRORS")) begin | |
1279 | repeat(2000) @(posedge ref_clk); // wait for link up | |
1280 | inject_10b_errors=1; | |
1281 | end | |
1282 | else inject_10b_errors=0; | |
1283 | end | |
1284 | ||
1285 | always@(posedge TXBCLK_p0[0] & inject_10b_errors) begin | |
1286 | if($time>`corrupt_time_limit) begin | |
1287 | corrupt=0; // stop corrupting and let link up remain | |
1288 | end | |
1289 | else if(corrupt_cnt==corrupt_limit) begin | |
1290 | corrupt_cnt = 0; | |
1291 | corrupt=~corrupt; | |
1292 | if(corrupt==1) begin | |
1293 | if(corrupt_limit==`corrupt_limit_max) corrupt_limit=`corrupt_limit_min; | |
1294 | else corrupt_limit=corrupt_limit+3; | |
1295 | end | |
1296 | end | |
1297 | else corrupt_cnt = corrupt_cnt +1; | |
1298 | end | |
1299 | ||
1300 | always@(posedge TXBCLK_p0[0]) begin | |
1301 | if(corrupt_cnt<5) txd_corrupt=$random; | |
1302 | else txd_corrupt = (txd_corrupt=='h17c) ? 9'h00 : 9'h17c; //17c==fa | |
1303 | end | |
1304 | //////////////////////////////////////////////////// | |
1305 | ||
1306 | assign TD0_r_p0_mux = speed_10G ? {TD0_p0[0],TD0_p0[1],TD0_p0[2],TD0_p0[3],TD0_p0[4], | |
1307 | TD0_p0[5],TD0_p0[6],TD0_p0[7],TD0_p0[8],TD0_p0[9]} : | |
1308 | {env_eser_rxd_a[0],env_eser_rxd_a[1],env_eser_rxd_a[2], | |
1309 | env_eser_rxd_a[3],env_eser_rxd_a[4],env_eser_rxd_a[5], | |
1310 | env_eser_rxd_a[6],env_eser_rxd_a[7],env_eser_rxd_a[8], | |
1311 | env_eser_rxd_a[9]}; | |
1312 | assign TD0_r_p1_mux = speed_10G ? {TD0_p1[0],TD0_p1[1],TD0_p1[2],TD0_p1[3],TD0_p1[4], | |
1313 | TD0_p1[5],TD0_p1[6],TD0_p1[7],TD0_p1[8],TD0_p1[9]} : | |
1314 | {env_eser_rxd_b[0],env_eser_rxd_b[1],env_eser_rxd_b[2], | |
1315 | env_eser_rxd_b[3],env_eser_rxd_b[4],env_eser_rxd_b[5], | |
1316 | env_eser_rxd_b[6],env_eser_rxd_b[7],env_eser_rxd_b[8], | |
1317 | env_eser_rxd_b[9]}; | |
1318 | ||
1319 | ||
1320 | //------------------------------------------------------- | |
1321 | //-- For ti serdes reverse the encoded data Port 0 ------ | |
1322 | //------------------------------------------------------- | |
1323 | ||
1324 | // assign TD0_r_p0 = {TD0_p0[0],TD0_p0[1],TD0_p0[2],TD0_p0[3],TD0_p0[4], | |
1325 | // TD0_p0[5],TD0_p0[6],TD0_p0[7],TD0_p0[8],TD0_p0[9]}; | |
1326 | ||
1327 | // assign TD1_r_p0 = TD1_r_p0_mux; // mux for 10G and 1G | |
1328 | ||
1329 | // assign TD0_r_p0 = TD0_r_p0_mux; // mux for 10G and 1G | |
1330 | ||
1331 | `ifdef TEST_UNH_VECTORS | |
1332 | assign TD0_r_p0 = {env_eser_rxd_a_del[0],env_eser_rxd_a_del[1],env_eser_rxd_a_del[2],env_eser_rxd_a_del[3], | |
1333 | env_eser_rxd_a_del[4],env_eser_rxd_a_del[5],env_eser_rxd_a_del[6],env_eser_rxd_a_del[7], | |
1334 | env_eser_rxd_a_del[8],env_eser_rxd_a_del[9]}; | |
1335 | `else | |
1336 | //assign TD0_r_p0 = TD0_r_p0_mux; | |
1337 | assign TD0_r_p0 = (corrupt) ? {txd_corrupt[0],txd_corrupt[1],txd_corrupt[2], | |
1338 | txd_corrupt[3],txd_corrupt[4],txd_corrupt[5], | |
1339 | txd_corrupt[6],txd_corrupt[7],txd_corrupt[8], | |
1340 | txd_corrupt[9]} | |
1341 | : TD0_r_p0_mux; | |
1342 | `endif | |
1343 | ||
1344 | `ifdef TEST_UNH_VECTORS | |
1345 | assign TD1_r_p0 = {env_eser_rxd_b_del[0],env_eser_rxd_b_del[1],env_eser_rxd_b_del[2],env_eser_rxd_b_del[3], | |
1346 | env_eser_rxd_b_del[4],env_eser_rxd_b_del[5],env_eser_rxd_b_del[6],env_eser_rxd_b_del[7], | |
1347 | env_eser_rxd_b_del[8],env_eser_rxd_b_del[9]}; | |
1348 | `else | |
1349 | assign TD1_r_p0 = {TD1_p0[0],TD1_p0[1],TD1_p0[2],TD1_p0[3],TD1_p0[4], | |
1350 | TD1_p0[5],TD1_p0[6],TD1_p0[7],TD1_p0[8],TD1_p0[9]}; | |
1351 | `endif | |
1352 | ||
1353 | `ifdef TEST_UNH_VECTORS | |
1354 | assign TD2_r_p0 = {env_eser_rxd_c_del[0],env_eser_rxd_c_del[1],env_eser_rxd_c_del[2],env_eser_rxd_c_del[3], | |
1355 | env_eser_rxd_c_del[4],env_eser_rxd_c_del[5],env_eser_rxd_c_del[6],env_eser_rxd_c_del[7], | |
1356 | env_eser_rxd_c_del[8],env_eser_rxd_c_del[9]}; | |
1357 | `else | |
1358 | assign TD2_r_p0 = {TD2_p0[0],TD2_p0[1],TD2_p0[2],TD2_p0[3],TD2_p0[4], | |
1359 | TD2_p0[5],TD2_p0[6],TD2_p0[7],TD2_p0[8],TD2_p0[9]}; | |
1360 | `endif | |
1361 | ||
1362 | `ifdef TEST_UNH_VECTORS | |
1363 | // assign TD3_r_p0 = env_eser_rxd_d_del[9:0]; | |
1364 | assign TD3_r_p0 = {env_eser_rxd_d_del[0],env_eser_rxd_d_del[1],env_eser_rxd_d_del[2],env_eser_rxd_d_del[3], | |
1365 | env_eser_rxd_d_del[4],env_eser_rxd_d_del[5],env_eser_rxd_d_del[6],env_eser_rxd_d_del[7], | |
1366 | env_eser_rxd_d_del[8],env_eser_rxd_d_del[9]}; | |
1367 | `else | |
1368 | assign TD3_r_p0 = {TD3_p0[0],TD3_p0[1],TD3_p0[2],TD3_p0[3],TD3_p0[4], | |
1369 | TD3_p0[5],TD3_p0[6],TD3_p0[7],TD3_p0[8],TD3_p0[9]}; | |
1370 | `endif | |
1371 | ||
1372 | assign RD0_r_p0 = {RD0_p0[0],RD0_p0[1],RD0_p0[2],RD0_p0[3],RD0_p0[4], | |
1373 | RD0_p0[5],RD0_p0[6],RD0_p0[7],RD0_p0[8],RD0_p0[9]}; | |
1374 | ||
1375 | assign RD1_r_p0 = {RD1_p0[0],RD1_p0[1],RD1_p0[2],RD1_p0[3],RD1_p0[4], | |
1376 | RD1_p0[5],RD1_p0[6],RD1_p0[7],RD1_p0[8],RD1_p0[9]}; | |
1377 | ||
1378 | assign RD2_r_p0 = {RD2_p0[0],RD2_p0[1],RD2_p0[2],RD2_p0[3],RD2_p0[4], | |
1379 | RD2_p0[5],RD2_p0[6],RD2_p0[7],RD2_p0[8],RD2_p0[9]}; | |
1380 | ||
1381 | assign RD3_r_p0 = {RD3_p0[0],RD3_p0[1],RD3_p0[2],RD3_p0[3],RD3_p0[4], | |
1382 | RD3_p0[5],RD3_p0[6],RD3_p0[7],RD3_p0[8],RD3_p0[9]}; | |
1383 | ||
1384 | ||
1385 | //------------------------------------------------------- | |
1386 | //-- For ti serdes reverse the encoded data Port 1 ------ | |
1387 | //------------------------------------------------------- | |
1388 | ||
1389 | // assign TD0_r_p1 = {TD0_p1[0],TD0_p1[1],TD0_p1[2],TD0_p1[3],TD0_p1[4], | |
1390 | // TD0_p1[5],TD0_p1[6],TD0_p1[7],TD0_p1[8],TD0_p1[9]}; | |
1391 | ||
1392 | // assign TD0_r_p1 = TD0_r_p1_mux; // mux for 10G and 1G | |
1393 | ||
1394 | `ifdef TEST_UNH_VECTORS | |
1395 | assign TD0_r_p1 = {env_eser_rxd_a_del[0],env_eser_rxd_a_del[1],env_eser_rxd_a_del[2],env_eser_rxd_a_del[3], | |
1396 | env_eser_rxd_a_del[4],env_eser_rxd_a_del[5],env_eser_rxd_a_del[6],env_eser_rxd_a_del[7], | |
1397 | env_eser_rxd_a_del[8],env_eser_rxd_a_del[9]}; | |
1398 | `else | |
1399 | assign TD0_r_p1 = TD0_r_p1_mux; // mux for 10G and 1G | |
1400 | `endif | |
1401 | ||
1402 | `ifdef TEST_UNH_VECTORS | |
1403 | assign TD1_r_p1 = {env_eser_rxd_b_del[0],env_eser_rxd_b_del[1],env_eser_rxd_b_del[2],env_eser_rxd_b_del[3], | |
1404 | env_eser_rxd_b_del[4],env_eser_rxd_b_del[5],env_eser_rxd_b_del[6],env_eser_rxd_b_del[7], | |
1405 | env_eser_rxd_b_del[8],env_eser_rxd_b_del[9]}; | |
1406 | `else | |
1407 | assign TD1_r_p1 = {TD1_p1[0],TD1_p1[1],TD1_p1[2],TD1_p1[3],TD1_p1[4], | |
1408 | TD1_p1[5],TD1_p1[6],TD1_p1[7],TD1_p1[8],TD1_p1[9]}; | |
1409 | `endif | |
1410 | ||
1411 | `ifdef TEST_UNH_VECTORS | |
1412 | assign TD2_r_p1 = {env_eser_rxd_c_del[0],env_eser_rxd_c_del[1],env_eser_rxd_c_del[2],env_eser_rxd_c_del[3], | |
1413 | env_eser_rxd_c_del[4],env_eser_rxd_c_del[5],env_eser_rxd_c_del[6],env_eser_rxd_c_del[7], | |
1414 | env_eser_rxd_c_del[8],env_eser_rxd_c_del[9]}; | |
1415 | `else | |
1416 | assign TD2_r_p1 = {TD2_p1[0],TD2_p1[1],TD2_p1[2],TD2_p1[3],TD2_p1[4], | |
1417 | TD2_p1[5],TD2_p1[6],TD2_p1[7],TD2_p1[8],TD2_p1[9]}; | |
1418 | `endif | |
1419 | ||
1420 | `ifdef TEST_UNH_VECTORS | |
1421 | assign TD3_r_p1 = {env_eser_rxd_d_del[0],env_eser_rxd_d_del[1],env_eser_rxd_d_del[2],env_eser_rxd_d_del[3], | |
1422 | env_eser_rxd_d_del[4],env_eser_rxd_d_del[5],env_eser_rxd_d_del[6],env_eser_rxd_d_del[7], | |
1423 | env_eser_rxd_d_del[8],env_eser_rxd_d_del[9]}; | |
1424 | `else | |
1425 | assign TD3_r_p1 = {TD3_p1[0],TD3_p1[1],TD3_p1[2],TD3_p1[3],TD3_p1[4], | |
1426 | TD3_p1[5],TD3_p1[6],TD3_p1[7],TD3_p1[8],TD3_p1[9]}; | |
1427 | `endif | |
1428 | ||
1429 | assign RD0_r_p1 = {RD0_p1[0],RD0_p1[1],RD0_p1[2],RD0_p1[3],RD0_p1[4], | |
1430 | RD0_p1[5],RD0_p1[6],RD0_p1[7],RD0_p1[8],RD0_p1[9]}; | |
1431 | ||
1432 | assign RD1_r_p1 = {RD1_p1[0],RD1_p1[1],RD1_p1[2],RD1_p1[3],RD1_p1[4], | |
1433 | RD1_p1[5],RD1_p1[6],RD1_p1[7],RD1_p1[8],RD1_p1[9]}; | |
1434 | ||
1435 | assign RD2_r_p1 = {RD2_p1[0],RD2_p1[1],RD2_p1[2],RD2_p1[3],RD2_p1[4], | |
1436 | RD2_p1[5],RD2_p1[6],RD2_p1[7],RD2_p1[8],RD2_p1[9]}; | |
1437 | ||
1438 | assign RD3_r_p1 = {RD3_p1[0],RD3_p1[1],RD3_p1[2],RD3_p1[3],RD3_p1[4], | |
1439 | RD3_p1[5],RD3_p1[6],RD3_p1[7],RD3_p1[8],RD3_p1[9]}; | |
1440 | ||
1441 | ||
1442 | assign env_eser_ser_sel[1] = speed_10G ? 1'b1 : 1'b0; | |
1443 | assign env_eser_ser_sel[0] = speed_10G ? 1'b0 : 1'b0; | |
1444 | assign env_eser_refclk_sel = speed_10G ? 1'b1 : 1'b0; | |
1445 | ||
1446 | assign rxclk_mux0 = speed_10G ? 1'b0 : RXBCLK_p0[0]; | |
1447 | assign rxclk_mux1 = speed_10G ? 1'b0 : RXBCLK_p1[0]; | |
1448 | assign txclk_mux0 = speed_10G ? 1'b0 : TXBCLK_p0[0]; | |
1449 | assign txclk_mux1 = speed_10G ? 1'b0 : TXBCLK_p1[0]; | |
1450 | ||
1451 | assign m0_tx_clk = speed_10G ? tx_clk_xgmii0 : (sel_gmii ? RGMII_TXCLK0 : eser_env_tclk0); | |
1452 | assign m1_tx_clk = speed_10G ? tx_clk_xgmii1 : (sel_gmii ? RGMII_TXCLK1 : eser_env_tclk1); | |
1453 | assign m2_tx_clk = sel_gmii ? RGMII_TXCLK2 : eser_env_tclk0; | |
1454 | assign m3_tx_clk = sel_gmii ? RGMII_TXCLK3 : eser_env_tclk0; | |
1455 | ||
1456 | assign eser_env_tclk0 = TXBCLK_p0[0]; | |
1457 | assign eser_env_tclk1 = TXBCLK_p1[0]; | |
1458 | ||
1459 | assign m0_tx_data = speed_10G ? m0_xgmii_txdata : (sel_gmii ? rgmii0_tx_data : pcs0_tx_data); | |
1460 | assign m0_tx_en = speed_10G ? m0_xgmii_tx_en : (sel_gmii ? rgmii0_tx_en : pcs0_tx_en); | |
1461 | assign m0_tx_err = speed_10G ? 0 : (sel_gmii ? rgmii0_tx_err : pcs0_tx_err); | |
1462 | ||
1463 | assign m1_tx_data = speed_10G ? m1_xgmii_txdata : (sel_gmii ? rgmii1_tx_data : pcs1_tx_data); | |
1464 | assign m1_tx_en = speed_10G ? m1_xgmii_tx_en : (sel_gmii ? rgmii1_tx_en : pcs1_tx_en); | |
1465 | assign m1_tx_err = speed_10G ? 0 : ( sel_gmii ? rgmii1_tx_err : pcs1_tx_err); | |
1466 | ||
1467 | ||
1468 | assign m2_tx_data = sel_gmii ? rgmii2_tx_data : pcs2_tx_data; | |
1469 | assign m2_tx_en = sel_gmii ? rgmii2_tx_en : pcs2_tx_en; | |
1470 | assign m2_tx_err = sel_gmii ? rgmii2_tx_err : pcs2_tx_err; | |
1471 | ||
1472 | assign m3_tx_data = sel_gmii ? rgmii3_tx_data : pcs3_tx_data; | |
1473 | assign m3_tx_en = sel_gmii ? rgmii3_tx_en : pcs3_tx_en; | |
1474 | assign m3_tx_err = sel_gmii ? rgmii3_tx_err : pcs3_tx_err; | |
1475 | ||
1476 | assign #0.9 xgmii_env_eser_rxd_a_del[9:0] = xgmii_env_eser_rxd_a[9:0]; | |
1477 | assign #0.9 xgmii_env_eser_rxd_b_del[9:0] = xgmii_env_eser_rxd_b[9:0]; | |
1478 | assign #0.9 xgmii_env_eser_rxd_c_del[9:0] = xgmii_env_eser_rxd_c[9:0]; | |
1479 | assign #0.9 xgmii_env_eser_rxd_d_del[9:0] = xgmii_env_eser_rxd_d[9:0]; | |
1480 | ||
1481 | ||
1482 | ||
1483 | assign #0.9 env_eser_rxd_a_del1[9:0] = env_eser_rxd_a[9:0]; | |
1484 | assign #0.9 env_eser_rxd_b_del1[9:0] = env_eser_rxd_b[9:0]; | |
1485 | assign #0.9 env_eser_rxd_c_del1[9:0] = env_eser_rxd_c[9:0]; | |
1486 | assign #0.9 env_eser_rxd_d_del1[9:0] = env_eser_rxd_d[9:0]; | |
1487 | ||
1488 | ||
1489 | `ifdef TEST_UNH_VECTORS | |
1490 | reg [9:0] unh_rxd_a,unh_rxd_b,unh_rxd_c,unh_rxd_d; | |
1491 | wire [9:0] unh_rxd_a_del,unh_rxd_b_del,unh_rxd_c_del,unh_rxd_d_del; | |
1492 | reg [9:0] vectors[20000:0]; | |
1493 | reg [15:0] vector_loc; | |
1494 | reg start_playing_vectors; | |
1495 | reg USE_UNH_VECTOR; | |
1496 | wire USE_UNH_VECTOR_del; | |
1497 | reg [31:0] start_time; | |
1498 | reg[8*60:1] unh_arg; | |
1499 | integer plus_args_ok; | |
1500 | reg [400*8:0] unh_vector_filename; | |
1501 | wire env_eop; | |
1502 | reg [3:0] env_pkt_cnt; | |
1503 | reg new_start_time,new_start_time_d; | |
1504 | reg check_serdes_output; | |
1505 | ||
1506 | initial begin | |
1507 | USE_UNH_VECTOR =0; | |
1508 | env_pkt_cnt = 4'h0; | |
1509 | new_start_time =0; | |
1510 | new_start_time_d =0; | |
1511 | start_playing_vectors =0; | |
1512 | unh_rxd_a = 0; | |
1513 | unh_rxd_b = 0; | |
1514 | unh_rxd_c = 0; | |
1515 | unh_rxd_d = 0; | |
1516 | for(vector_loc =0;vector_loc < 18096; vector_loc = vector_loc +1) | |
1517 | vectors[vector_loc] = 0; | |
1518 | ||
1519 | unh_vector_filename = "unh_vectors.txt"; | |
1520 | ||
1521 | //plus_args_ok = $util_get_plus_args_str("UNH_VECTOR_FILE_",unh_vector_filename); | |
1522 | plus_args_ok = $value$plusargs("UNH_VECTOR_FILE=%s", unh_vector_filename); | |
1523 | ||
1524 | if(plus_args_ok) | |
1525 | $display("UNH_DEBUG: UNH Vector Files -- %s",unh_vector_filename); | |
1526 | else begin | |
1527 | unh_vector_filename = "unh_vectors.txt"; | |
1528 | $display("UNH_DEBUG: No Vector File Specified Using Default FileName-- %s",unh_vector_filename); | |
1529 | $display("UNH_DEBUG: UNH Vector Files -- %s",unh_vector_filename); | |
1530 | end | |
1531 | ||
1532 | $readmemb(unh_vector_filename,vectors); | |
1533 | $display(" UNH Vectors Read into Buffer \n"); | |
1534 | ||
1535 | vector_loc =0; | |
1536 | ||
1537 | unh_arg = "UNH_START_TIME="; | |
1538 | if ($test$plusargs("UNH_START_TIME=")) | |
1539 | start_time = $util_get_plus_args_num(unh_arg); | |
1540 | else start_time = 1277; | |
1541 | $display("%m:UNH start time set to %d \n",start_time); | |
1542 | // $display("%m:UNH start time set to %d \n",start_time); | |
1543 | // repeat(1633) @(posedge ref_clk); | |
1544 | // repeat(1347) @(posedge ref_clk); | |
1545 | // repeat(1277) @(posedge ref_clk); | |
1546 | // repeat(start_time) @(posedge ref_clk); | |
1547 | // start_playing_vectors =1; | |
1548 | // $display(" UNH VECTORS STARTED Time = %t ",$time); | |
1549 | ||
1550 | ||
1551 | end | |
1552 | assign env_eop = (xgmii_env_eser_rxd_a[9:0] == 10'h3a2 /* 0x117*/ ) | ( xgmii_env_eser_rxd_a[9:0] == 10'h05d /* 0x2e8*/ ); | |
1553 | always@(posedge ref_clk) begin | |
1554 | if(env_eop) | |
1555 | env_pkt_cnt <= env_pkt_cnt +1; | |
1556 | if(env_pkt_cnt ==1) begin | |
1557 | start_playing_vectors <= 1; | |
1558 | end // if (env_pkt_cnt ==1) | |
1559 | new_start_time_d <= start_playing_vectors; | |
1560 | if(~start_playing_vectors & new_start_time_d) | |
1561 | $display(" UNH VECTORS STARTED Time = %t ",$time); | |
1562 | ||
1563 | end | |
1564 | ||
1565 | ||
1566 | ||
1567 | always@(posedge ref_clk) begin | |
1568 | if(start_playing_vectors) begin | |
1569 | USE_UNH_VECTOR <=1; | |
1570 | unh_rxd_a <= vectors[vector_loc +0 ] ; | |
1571 | unh_rxd_b <= vectors[vector_loc +1 ] ; | |
1572 | unh_rxd_c <= vectors[vector_loc +2 ] ; | |
1573 | unh_rxd_d <= vectors[vector_loc +3 ] ; | |
1574 | vector_loc <= vector_loc +4; | |
1575 | if(vector_loc >= 18096) begin | |
1576 | USE_UNH_VECTOR <=0; | |
1577 | start_playing_vectors <= 1'b0; | |
1578 | end | |
1579 | end else // if (start_playing_vectors) | |
1580 | USE_UNH_VECTOR <=0; | |
1581 | ||
1582 | end | |
1583 | ||
1584 | // assign #0.9 USE_UNH_VECTOR_del = USE_UNH_VECTOR; | |
1585 | assign #0.9 USE_UNH_VECTOR_del = new_start_time_d; | |
1586 | ||
1587 | assign #0.9 unh_rxd_a_del = {unh_rxd_a[0],unh_rxd_a[1],unh_rxd_a[2],unh_rxd_a[3],unh_rxd_a[4],unh_rxd_a[5],unh_rxd_a[6],unh_rxd_a[7],unh_rxd_a[8],unh_rxd_a[9]} ; | |
1588 | assign #0.9 unh_rxd_b_del = {unh_rxd_b[0],unh_rxd_b[1],unh_rxd_b[2],unh_rxd_b[3],unh_rxd_b[4],unh_rxd_b[5],unh_rxd_b[6],unh_rxd_b[7],unh_rxd_b[8],unh_rxd_b[9]} ; | |
1589 | assign #0.9 unh_rxd_c_del = {unh_rxd_c[0],unh_rxd_c[1],unh_rxd_c[2],unh_rxd_c[3],unh_rxd_c[4],unh_rxd_c[5],unh_rxd_c[6],unh_rxd_c[7],unh_rxd_c[8],unh_rxd_c[9]} ; | |
1590 | assign #0.9 unh_rxd_d_del = {unh_rxd_d[0],unh_rxd_d[1],unh_rxd_d[2],unh_rxd_d[3],unh_rxd_d[4],unh_rxd_d[5],unh_rxd_d[6],unh_rxd_d[7],unh_rxd_d[8],unh_rxd_d[9]} ; | |
1591 | ||
1592 | ||
1593 | assign env_eser_rxd_a_del[9:0] = USE_UNH_VECTOR_del? unh_rxd_a_del : (speed_10G ? | |
1594 | xgmii_env_eser_rxd_a_del[9:0] : env_eser_rxd_a_del1[9:0]); | |
1595 | assign env_eser_rxd_b_del[9:0] = USE_UNH_VECTOR_del? unh_rxd_b_del : (speed_10G ? | |
1596 | xgmii_env_eser_rxd_b_del[9:0] : env_eser_rxd_b_del1[9:0]); | |
1597 | assign env_eser_rxd_c_del[9:0] = USE_UNH_VECTOR_del? unh_rxd_c_del : (speed_10G ? | |
1598 | xgmii_env_eser_rxd_c_del[9:0] : env_eser_rxd_c_del1[9:0]); | |
1599 | assign env_eser_rxd_d_del[9:0] = USE_UNH_VECTOR_del? unh_rxd_d_del : (speed_10G ? | |
1600 | xgmii_env_eser_rxd_d_del[9:0] : env_eser_rxd_d_del1[9:0]); | |
1601 | ||
1602 | xaui_decode unh_rxda ( .data(unh_rxd_a), .clk(ref_clk),.decode(start_playing_vectors), .bit_reverse(1'b0)); | |
1603 | xaui_decode unh_rxdb ( .data(unh_rxd_b), .clk(ref_clk),.decode(start_playing_vectors), .bit_reverse(1'b0)); | |
1604 | xaui_decode unh_rxdc ( .data(unh_rxd_c), .clk(ref_clk),.decode(start_playing_vectors), .bit_reverse(1'b0)); | |
1605 | xaui_decode unh_rxdd ( .data(unh_rxd_d), .clk(ref_clk),.decode(start_playing_vectors), .bit_reverse(1'b0)); | |
1606 | unh_checks unh_checks(.ref_clk(core_clk)); | |
1607 | ||
1608 | reg [9:0] serdesout_lane0,serdesout_lane1,serdesout_lane2,serdesout_lane3; | |
1609 | reg [4:0] start_checking_serdesdata; | |
1610 | reg [15:0] check_loc; | |
1611 | reg [9:0] lane0_exp,lane1_exp,lane2_exp,lane3_exp; | |
1612 | ||
1613 | initial begin | |
1614 | start_checking_serdesdata =0; | |
1615 | check_loc =0; | |
1616 | if($test$plusargs("CHECK_SERDES")) | |
1617 | check_serdes_output = 1; | |
1618 | else | |
1619 | check_serdes_output =0; | |
1620 | end | |
1621 | ||
1622 | always@(posedge ref_clk) begin | |
1623 | start_checking_serdesdata <= {start_checking_serdesdata[3:0],USE_UNH_VECTOR}; | |
1624 | end | |
1625 | ||
1626 | always@(posedge ref_clk) begin | |
1627 | if(start_checking_serdesdata[4] & check_serdes_output) begin | |
1628 | lane0_exp <= vectors[check_loc + 0]; | |
1629 | lane1_exp <= vectors[check_loc + 1]; | |
1630 | lane2_exp <= vectors[check_loc + 2]; | |
1631 | lane3_exp <= vectors[check_loc + 3]; | |
1632 | check_loc <= check_loc +4; | |
1633 | ||
1634 | serdesout_lane0 <= tb_top.cpu.mac.mac_core.esr_mac_rxd0_0[9:0]; | |
1635 | serdesout_lane1 <= tb_top.cpu.mac.mac_core.esr_mac_rxd1_0[9:0]; | |
1636 | serdesout_lane2 <= tb_top.cpu.mac.mac_core.esr_mac_rxd2_0[9:0]; | |
1637 | serdesout_lane3 <= tb_top.cpu.mac.mac_core.esr_mac_rxd3_0[9:0]; | |
1638 | ||
1639 | check_serdesout(lane0_exp,serdesout_lane0,2'h0,check_loc); | |
1640 | check_serdesout(lane1_exp,serdesout_lane1,2'h1,check_loc); | |
1641 | check_serdesout(lane2_exp,serdesout_lane2,2'h2,check_loc); | |
1642 | check_serdesout(lane3_exp,serdesout_lane3,2'h3,check_loc); | |
1643 | ||
1644 | end | |
1645 | end | |
1646 | ||
1647 | `else // !ifdef TEST_UNH_VECTORS | |
1648 | ||
1649 | assign env_eser_rxd_a_del[9:0] = speed_10G ? | |
1650 | xgmii_env_eser_rxd_a_del[9:0] : env_eser_rxd_a_del1[9:0]; | |
1651 | assign env_eser_rxd_b_del[9:0] = speed_10G ? | |
1652 | xgmii_env_eser_rxd_b_del[9:0] : env_eser_rxd_b_del1[9:0]; | |
1653 | assign env_eser_rxd_c_del[9:0] = speed_10G ? | |
1654 | xgmii_env_eser_rxd_c_del[9:0] : env_eser_rxd_c_del1[9:0]; | |
1655 | assign env_eser_rxd_d_del[9:0] = speed_10G ? | |
1656 | xgmii_env_eser_rxd_d_del[9:0] : env_eser_rxd_d_del1[9:0]; | |
1657 | `endif | |
1658 | ||
1659 | // Code for dumping Tx signals into file for easy debug | |
1660 | ||
1661 | reg dump_tx_debug,start_tx_dump; | |
1662 | reg [31:0] tx_dump_start_time; | |
1663 | reg [8*60:1] tx_dump_arg,tx_start_arg; | |
1664 | ||
1665 | reg [80*6:0] fp; | |
1666 | ||
1667 | initial begin | |
1668 | ||
1669 | fp = $fopen("xaui_tx_debug.txt","w"); | |
1670 | start_tx_dump =0; | |
1671 | ||
1672 | tx_dump_arg = "TX_DEBUG_ENABLE"; | |
1673 | if ($test$plusargs("TX_DEBUG_ENABLE")) | |
1674 | dump_tx_debug = 1; | |
1675 | else dump_tx_debug = 0; | |
1676 | tx_start_arg = "TX_DEBUG_START="; | |
1677 | if ($test$plusargs("TX_DEBUG_START=")) | |
1678 | tx_dump_start_time = $util_get_plus_args_num(tx_start_arg); | |
1679 | else tx_dump_start_time = 10; | |
1680 | ||
1681 | if(dump_tx_debug) begin | |
1682 | $display("%m:TX Debug Dump start clock set to %d \n",tx_dump_start_time); | |
1683 | repeat(tx_dump_start_time) @(posedge ref_clk); | |
1684 | $display(" enabling Tx Debug Dumps at Time =%t",$time); | |
1685 | start_tx_dump =1; | |
1686 | end // if (dump_tx_debug) | |
1687 | ||
1688 | ||
1689 | end | |
1690 | ||
1691 | always@(posedge ref_clk) begin | |
1692 | if(start_tx_dump & dump_tx_debug ) | |
1693 | $fdisplay(fp,"%b %b %b %b",eser_env_txd_a[9:0],eser_env_txd_b[9:0],eser_env_txd_c[9:0],eser_env_txd_d[9:0]); | |
1694 | end | |
1695 | ||
1696 | ||
1697 | xaui_decode rxda ( .data(env_eser_rxd_a_del), .clk(ref_clk), .decode(1'b1), .bit_reverse(1'b1)); | |
1698 | xaui_decode rxdb ( .data(env_eser_rxd_b_del), .clk(ref_clk), .decode(1'b1), .bit_reverse(1'b1)); | |
1699 | xaui_decode rxdc ( .data(env_eser_rxd_c_del), .clk(ref_clk), .decode(1'b1), .bit_reverse(1'b1)); | |
1700 | xaui_decode rxdd ( .data(env_eser_rxd_d_del), .clk(ref_clk), .decode(1'b1), .bit_reverse(1'b1)); | |
1701 | ||
1702 | ||
1703 | `ifdef TEST_UNH_VECTORS | |
1704 | ||
1705 | task check_serdesout; | |
1706 | input [9:0] lane_exp; | |
1707 | input [9:0] serdesout; | |
1708 | input [1:0] lane_num; | |
1709 | input [15:0] check_loc; | |
1710 | reg [9:0] serdes_out_tmp; | |
1711 | begin | |
1712 | serdes_out_tmp = { serdesout[0],serdesout[1],serdesout[2],serdesout[3],serdesout[4], | |
1713 | serdesout[5],serdesout[6],serdesout[7],serdesout[8],serdesout[9] }; | |
1714 | ||
1715 | if(serdes_out_tmp!== lane_exp) begin | |
1716 | $display("Time =%t: ERROR Serdes Output Mismatch!! LaneNumber = %d, Expected = %h Received = %h VectorIndex = %d ",$time,lane_num,lane_exp,serdes_out_tmp,check_loc); | |
1717 | end | |
1718 | ||
1719 | end | |
1720 | endtask | |
1721 | `endif | |
1722 | ||
1723 | //----------------------------------------------------------------------- | |
1724 | //------------- PORT0 reg declarations and init ------------------------- | |
1725 | // register declarations and initialization code of ti-serdes for port 0 | |
1726 | //------------------------------------------------------------------------ | |
1727 | ||
1728 | reg [11:0] reg_CFGPLL_p0; | |
1729 | reg [27:0] reg_CFGRX0_p0; // Receive configuration bus - channel 0 | |
1730 | reg [27:0] reg_CFGRX1_p0; // Receive configuration bus - channel 1 | |
1731 | reg [27:0] reg_CFGRX2_p0; // Receive configuration bus - channel 2 | |
1732 | reg [27:0] reg_CFGRX3_p0; // Receive configuration bus - channel 3 | |
1733 | ||
1734 | reg [19:0] reg_CFGTX0_p0; // Transmit configuration bus - channel 0 | |
1735 | reg [19:0] reg_CFGTX1_p0; // Transmit configuration bus - channel 1 | |
1736 | reg [19:0] reg_CFGTX2_p0; // Transmit configuration bus - channel 2 | |
1737 | reg [19:0] reg_CFGTX3_p0; // Transmit configuration bus - channel 3 | |
1738 | reg [19:0] reg_TESTCFG_p0; // Test configuration bus. | |
1739 | reg reg_FCLK_p0; // eFuse clock | |
1740 | reg reg_FCLRZ_p0; // eFuse clear | |
1741 | reg reg_FDI_p0; // eFuse input data | |
1742 | reg [1:0] reg_STCICFG_p0; // STCI Mode. | |
1743 | reg reg_STCICLK_p0; // STCI clock. | |
1744 | reg reg_STCID_p0; // STCI input data | |
1745 | reg reg_TESTCLKR_p0; // Receive test clock | |
1746 | reg reg_TESTCLKT_p0; // Receive test clock | |
1747 | reg reg_BSINITCLK_p0; | |
1748 | ||
1749 | ||
1750 | initial | |
1751 | if(speed_10G == 1) | |
1752 | begin | |
1753 | @(posedge ref_clk); | |
1754 | ||
1755 | reg_BSINITCLK_p0 = 1'b0; | |
1756 | // configure PLL | |
1757 | reg_CFGPLL_p0 = 0; | |
1758 | reg_CFGPLL_p0[0] = 1'b1; | |
1759 | reg_CFGPLL_p0[4:1] = 4'h1; | |
1760 | reg_CFGPLL_p0[9:8] = 2'b11; | |
1761 | reg_CFGPLL_p0[11:10] = 2'b10; | |
1762 | ||
1763 | // RX Configuration | |
1764 | reg_CFGRX0_p0 = 0; | |
1765 | reg_CFGRX1_p0 = reg_CFGRX0_p0; | |
1766 | reg_CFGRX2_p0 = reg_CFGRX0_p0; | |
1767 | reg_CFGRX3_p0 = reg_CFGRX0_p0; | |
1768 | ||
1769 | // TX Configuration | |
1770 | reg_CFGTX0_p0 = 0; | |
1771 | reg_CFGTX1_p0 = reg_CFGTX0_p0; | |
1772 | reg_CFGTX2_p0 = reg_CFGTX0_p0; | |
1773 | reg_CFGTX3_p0 = reg_CFGTX0_p0; | |
1774 | ||
1775 | // Test Configuration | |
1776 | reg_TESTCFG_p0 = 0; | |
1777 | ||
1778 | // misc | |
1779 | reg_FCLK_p0 = 0; | |
1780 | reg_FCLRZ_p0 = 1; // active low | |
1781 | reg_FDI_p0 = 0; | |
1782 | reg_STCICFG_p0 = 0; | |
1783 | reg_STCICLK_p0 = 0; | |
1784 | reg_STCID_p0 = 0; | |
1785 | reg_TESTCLKR_p0 = 0; | |
1786 | reg_TESTCLKT_p0 = 0; | |
1787 | ||
1788 | @(posedge STSPLL_p0[0]); | |
1789 | $display("PLL Lock for Port0 is %b", STSPLL_p0[0] ); | |
1790 | ||
1791 | @(posedge REFCLKP); | |
1792 | // TX Configuration | |
1793 | reg_CFGTX0_p0[0] = 1; | |
1794 | reg_CFGTX1_p0[0] = 1; | |
1795 | reg_CFGTX2_p0[0] = 1; | |
1796 | reg_CFGTX3_p0[0] = 1; | |
1797 | ||
1798 | // RX Configuration | |
1799 | reg_CFGRX0_p0[0] = 1; | |
1800 | reg_CFGRX0_p0[13:12] = 2'b01; | |
1801 | reg_CFGRX0_p0[15:14] = 2'b01; | |
1802 | ||
1803 | reg_CFGRX1_p0 = reg_CFGRX0_p0; | |
1804 | reg_CFGRX2_p0 = reg_CFGRX0_p0; | |
1805 | reg_CFGRX3_p0 = reg_CFGRX0_p0; | |
1806 | end | |
1807 | else | |
1808 | begin | |
1809 | @(posedge ref_clk); | |
1810 | ||
1811 | reg_BSINITCLK_p0 = 1'b0; | |
1812 | // configure PLL | |
1813 | reg_CFGPLL_p0 = 0; | |
1814 | reg_CFGPLL_p0[0] = 1'b1; | |
1815 | reg_CFGPLL_p0[4:1] = 4'h5; | |
1816 | reg_CFGPLL_p0[9:8] = 2'b00; | |
1817 | reg_CFGPLL_p0[11:10] = 2'b00; | |
1818 | ||
1819 | // RX Configuration | |
1820 | reg_CFGRX0_p0 = 0; | |
1821 | reg_CFGRX1_p0 = reg_CFGRX0_p0; | |
1822 | reg_CFGRX2_p0 = reg_CFGRX0_p0; | |
1823 | reg_CFGRX3_p0 = reg_CFGRX0_p0; | |
1824 | ||
1825 | // TX Configuration | |
1826 | reg_CFGTX0_p0 = 0; | |
1827 | reg_CFGTX1_p0 = reg_CFGTX0_p0; | |
1828 | reg_CFGTX2_p0 = reg_CFGTX0_p0; | |
1829 | reg_CFGTX3_p0 = reg_CFGTX0_p0; | |
1830 | ||
1831 | // Test Configuration | |
1832 | reg_TESTCFG_p0 = 0; | |
1833 | ||
1834 | // misc | |
1835 | reg_FCLK_p0 = 0; | |
1836 | reg_FCLRZ_p0 = 1; // active low | |
1837 | reg_FDI_p0 = 0; | |
1838 | reg_STCICFG_p0 = 0; | |
1839 | reg_STCICLK_p0 = 0; | |
1840 | reg_STCID_p0 = 0; | |
1841 | reg_TESTCLKR_p0 = 0; | |
1842 | reg_TESTCLKT_p0 = 0; | |
1843 | ||
1844 | @(posedge STSPLL_p0[0]); | |
1845 | $display("PLL Lock for Port0 is %b", STSPLL_p0[0] ); | |
1846 | ||
1847 | @(posedge REFCLKP); | |
1848 | // TX Configuration | |
1849 | reg_CFGTX0_p0[0] = 1; | |
1850 | reg_CFGTX0_p0[6:5] = 2'b01; | |
1851 | reg_CFGTX1_p0[0] = 0; | |
1852 | reg_CFGTX2_p0[0] = 0; | |
1853 | reg_CFGTX3_p0[0] = 0; | |
1854 | ||
1855 | // RX Configuration | |
1856 | reg_CFGRX0_p0[0] = 1; | |
1857 | reg_CFGRX0_p0[6:5] = 2'b01; | |
1858 | reg_CFGRX0_p0[13:12] = 2'b01; | |
1859 | reg_CFGRX0_p0[15:14] = 2'b01; | |
1860 | ||
1861 | end | |
1862 | ||
1863 | assign TXBCLKIN_p0 = {4{REFCLKP}}; | |
1864 | assign RXBCLKIN_p0 = RXBCLK_p0; | |
1865 | ||
1866 | assign CFGPLL_p0 = reg_CFGPLL_p0; | |
1867 | assign CFGRX0_p0 = reg_CFGRX0_p0; | |
1868 | assign CFGRX1_p0 = reg_CFGRX1_p0; | |
1869 | assign CFGRX2_p0 = reg_CFGRX2_p0; | |
1870 | assign CFGRX3_p0 = reg_CFGRX3_p0; | |
1871 | ||
1872 | assign CFGTX0_p0 = reg_CFGTX0_p0; | |
1873 | assign CFGTX1_p0 = reg_CFGTX1_p0; | |
1874 | assign CFGTX2_p0 = reg_CFGTX2_p0; | |
1875 | assign CFGTX3_p0 = reg_CFGTX3_p0; | |
1876 | assign TESTCFG_p0 = reg_TESTCFG_p0; | |
1877 | assign FCLK_p0 = reg_FCLK_p0; | |
1878 | assign FCLRZ_p0 = reg_FCLRZ_p0; // eFuse clear | |
1879 | assign FDI_p0 = reg_FDI_p0; // eFuse input data | |
1880 | assign STCICFG_p0 = reg_STCICFG_p0; // STCI Mode. | |
1881 | assign STCICLK_p0 = reg_STCICLK_p0; // STCI clock. | |
1882 | assign STCID_p0 = reg_STCID_p0; // STCI input data | |
1883 | assign TESTCFG_p0 = reg_TESTCFG_p0; // Test configuration bus. | |
1884 | assign TESTCLKR_p0 = reg_TESTCLKR_p0; // Receive test clock | |
1885 | assign TESTCLKT_p0 = reg_TESTCLKT_p0; // Tx test clock | |
1886 | assign BSINITCLK_p0 = reg_BSINITCLK_p0; | |
1887 | ||
1888 | //----------------------------------------------------------------------- | |
1889 | //------------- PORT1 reg declarations and init ------------------------- | |
1890 | // register declarations and initialization code of ti-serdes for port 1 | |
1891 | //------------------------------------------------------------------------ | |
1892 | ||
1893 | reg [11:0] reg_CFGPLL_p1; | |
1894 | reg [27:0] reg_CFGRX0_p1; // Receive configuration bus - channel 0 | |
1895 | reg [27:0] reg_CFGRX1_p1; // Receive configuration bus - channel 1 | |
1896 | reg [27:0] reg_CFGRX2_p1; // Receive configuration bus - channel 2 | |
1897 | reg [27:0] reg_CFGRX3_p1; // Receive configuration bus - channel 3 | |
1898 | ||
1899 | reg [19:0] reg_CFGTX0_p1; // Transmit configuration bus - channel 0 | |
1900 | reg [19:0] reg_CFGTX1_p1; // Transmit configuration bus - channel 1 | |
1901 | reg [19:0] reg_CFGTX2_p1; // Transmit configuration bus - channel 2 | |
1902 | reg [19:0] reg_CFGTX3_p1; // Transmit configuration bus - channel 3 | |
1903 | reg [19:0] reg_TESTCFG_p1; // Test configuration bus. | |
1904 | reg reg_FCLK_p1; // eFuse clock | |
1905 | reg reg_FCLRZ_p1; // eFuse clear | |
1906 | reg reg_FDI_p1; // eFuse input data | |
1907 | reg [1:0] reg_STCICFG_p1; // STCI Mode. | |
1908 | reg reg_STCICLK_p1; // STCI clock. | |
1909 | reg reg_STCID_p1; // STCI input data | |
1910 | reg reg_TESTCLKR_p1; // Receive test clock | |
1911 | reg reg_TESTCLKT_p1; // Receive test clock | |
1912 | reg reg_BSINITCLK_p1; | |
1913 | ||
1914 | //---------------------------------------------------------- | |
1915 | //------ declarations for BW Cal ----------------------- | |
1916 | //---------------------------------------------------------- | |
1917 | ||
1918 | // integer data_byte_cnt; | |
1919 | // integer ipg_byte_cnt; | |
1920 | // real BW; | |
1921 | // real avg_ipg_byte_cnt; | |
1922 | // time bw_start_time; | |
1923 | // time bw_end_time; | |
1924 | // integer pkt_cnt; | |
1925 | ||
1926 | // reg [1:0] bw_state; | |
1927 | // reg [1:0] nxt_state; | |
1928 | // reg [1:0] bw_state1; | |
1929 | // reg [1:0] nxt_state1; | |
1930 | ||
1931 | ||
1932 | initial | |
1933 | if (speed_10G == 1) | |
1934 | begin | |
1935 | @(posedge ref_clk); | |
1936 | ||
1937 | reg_BSINITCLK_p1 = 1'b0; | |
1938 | // configure PLL | |
1939 | reg_CFGPLL_p1 = 0; | |
1940 | reg_CFGPLL_p1[0] = 1'b1; | |
1941 | reg_CFGPLL_p1[4:1] = 4'h1; | |
1942 | reg_CFGPLL_p1[9:8] = 2'b11; | |
1943 | reg_CFGPLL_p1[11:10] = 2'b10; | |
1944 | ||
1945 | // RX Configuration | |
1946 | reg_CFGRX0_p1 = 0; | |
1947 | reg_CFGRX1_p1 = reg_CFGRX0_p1; | |
1948 | reg_CFGRX2_p1 = reg_CFGRX0_p1; | |
1949 | reg_CFGRX3_p1 = reg_CFGRX0_p1; | |
1950 | ||
1951 | // TX Configuration | |
1952 | reg_CFGTX0_p1 = 0; | |
1953 | reg_CFGTX1_p1 = reg_CFGTX0_p1; | |
1954 | reg_CFGTX2_p1 = reg_CFGTX0_p1; | |
1955 | reg_CFGTX3_p1 = reg_CFGTX0_p1; | |
1956 | ||
1957 | // Test Configuration | |
1958 | reg_TESTCFG_p1 = 0; | |
1959 | ||
1960 | // misc | |
1961 | reg_FCLK_p1 = 0; | |
1962 | reg_FCLRZ_p1 = 1; // active low | |
1963 | reg_FDI_p1 = 0; | |
1964 | reg_STCICFG_p1 = 0; | |
1965 | reg_STCICLK_p1 = 0; | |
1966 | reg_STCID_p1 = 0; | |
1967 | reg_TESTCLKR_p1 = 0; | |
1968 | reg_TESTCLKT_p1 = 0; | |
1969 | ||
1970 | @(posedge STSPLL_p1[0]); | |
1971 | $display("PLL Lock for Port1 is %b", STSPLL_p1[0] ); | |
1972 | ||
1973 | @(posedge REFCLKP); | |
1974 | // TX Configuration | |
1975 | reg_CFGTX0_p1[0] = 1; | |
1976 | reg_CFGTX1_p1[0] = 1; | |
1977 | reg_CFGTX2_p1[0] = 1; | |
1978 | reg_CFGTX3_p1[0] = 1; | |
1979 | ||
1980 | // RX Configuration | |
1981 | reg_CFGRX0_p1[0] = 1; | |
1982 | reg_CFGRX0_p1[13:12] = 2'b01; | |
1983 | reg_CFGRX0_p1[15:14] = 2'b01; | |
1984 | ||
1985 | reg_CFGRX1_p1 = reg_CFGRX0_p1; | |
1986 | reg_CFGRX2_p1 = reg_CFGRX0_p1; | |
1987 | reg_CFGRX3_p1 = reg_CFGRX0_p1; | |
1988 | end | |
1989 | else | |
1990 | begin | |
1991 | @(posedge ref_clk); | |
1992 | ||
1993 | reg_BSINITCLK_p1 = 1'b0; | |
1994 | // configure PLL | |
1995 | reg_CFGPLL_p1 = 0; | |
1996 | reg_CFGPLL_p1[0] = 1'b1; | |
1997 | reg_CFGPLL_p1[4:1] = 4'h5; | |
1998 | reg_CFGPLL_p1[9:8] = 2'b00; | |
1999 | reg_CFGPLL_p1[11:10] = 2'b00; | |
2000 | ||
2001 | // RX Configuration | |
2002 | reg_CFGRX0_p1 = 0; | |
2003 | reg_CFGRX1_p1 = reg_CFGRX0_p1; | |
2004 | reg_CFGRX2_p1 = reg_CFGRX0_p1; | |
2005 | reg_CFGRX3_p1 = reg_CFGRX0_p1; | |
2006 | ||
2007 | // TX Configuration | |
2008 | reg_CFGTX0_p1 = 0; | |
2009 | reg_CFGTX1_p1 = reg_CFGTX0_p1; | |
2010 | reg_CFGTX2_p1 = reg_CFGTX0_p1; | |
2011 | reg_CFGTX3_p1 = reg_CFGTX0_p1; | |
2012 | ||
2013 | // Test Configuration | |
2014 | reg_TESTCFG_p1 = 0; | |
2015 | ||
2016 | // misc | |
2017 | reg_FCLK_p1 = 0; | |
2018 | reg_FCLRZ_p1 = 1; // active low | |
2019 | reg_FDI_p1 = 0; | |
2020 | reg_STCICFG_p1 = 0; | |
2021 | reg_STCICLK_p1 = 0; | |
2022 | reg_STCID_p1 = 0; | |
2023 | reg_TESTCLKR_p1 = 0; | |
2024 | reg_TESTCLKT_p1 = 0; | |
2025 | ||
2026 | @(posedge STSPLL_p1[0]); | |
2027 | $display("PLL Lock for Port1 is %b", STSPLL_p1[0] ); | |
2028 | ||
2029 | @(posedge REFCLKP); | |
2030 | // TX Configuration | |
2031 | reg_CFGTX0_p1[0] = 1; | |
2032 | reg_CFGTX0_p1[6:5] = 2'b01; | |
2033 | reg_CFGTX1_p1[0] = 0; | |
2034 | reg_CFGTX2_p1[0] = 0; | |
2035 | reg_CFGTX3_p1[0] = 0; | |
2036 | ||
2037 | // RX Configuration | |
2038 | //reg_CFGRX0_p1[0] = 0; | |
2039 | //reg_CFGRX0_p1[13:12] = 2'b01; | |
2040 | //reg_CFGRX0_p1[15:14] = 2'b01; | |
2041 | ||
2042 | // reg_CFGRX1_p1 = reg_CFGRX0_p1; | |
2043 | reg_CFGRX0_p1[0] = 1; | |
2044 | reg_CFGRX0_p1[6:5] = 2'b01; | |
2045 | reg_CFGRX0_p1[13:12] = 2'b01; | |
2046 | reg_CFGRX0_p1[15:14] = 2'b01; | |
2047 | ||
2048 | //reg_CFGRX2_p1 = reg_CFGRX0_p1; | |
2049 | //reg_CFGRX3_p1 = reg_CFGRX0_p1; | |
2050 | ||
2051 | end | |
2052 | ||
2053 | assign TXBCLKIN_p1 = {4{REFCLKP}}; | |
2054 | assign RXBCLKIN_p1 = RXBCLK_p1; | |
2055 | ||
2056 | assign CFGPLL_p1 = reg_CFGPLL_p1; | |
2057 | assign CFGRX0_p1 = reg_CFGRX0_p1; | |
2058 | assign CFGRX1_p1 = reg_CFGRX1_p1; | |
2059 | assign CFGRX2_p1 = reg_CFGRX2_p1; | |
2060 | assign CFGRX3_p1 = reg_CFGRX3_p1; | |
2061 | ||
2062 | assign CFGTX0_p1 = reg_CFGTX0_p1; | |
2063 | assign CFGTX1_p1 = reg_CFGTX1_p1; | |
2064 | assign CFGTX2_p1 = reg_CFGTX2_p1; | |
2065 | assign CFGTX3_p1 = reg_CFGTX3_p1; | |
2066 | assign TESTCFG_p1 = reg_TESTCFG_p1; | |
2067 | assign FCLK_p1 = reg_FCLK_p1; | |
2068 | assign FCLRZ_p1 = reg_FCLRZ_p1; // eFuse clear | |
2069 | assign FDI_p1 = reg_FDI_p1; // eFuse input data | |
2070 | assign STCICFG_p1 = reg_STCICFG_p1; // STCI Mode. | |
2071 | assign STCICLK_p1 = reg_STCICLK_p1; // STCI clock. | |
2072 | assign STCID_p1 = reg_STCID_p1; // STCI input data | |
2073 | assign TESTCFG_p1 = reg_TESTCFG_p1; // Test configuration bus. | |
2074 | assign TESTCLKR_p1 = reg_TESTCLKR_p1; // Receive test clock | |
2075 | assign TESTCLKT_p1 = reg_TESTCLKT_p1; // Tx test clock | |
2076 | assign BSINITCLK_p1 = reg_BSINITCLK_p1; | |
2077 | ||
2078 | endmodule |