Commit | Line | Data |
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86530b38 AT |
1 | |
2 | module clock_multiplier_10x(refclk, clk); | |
3 | input refclk; | |
4 | output clk; | |
5 | reg clk; | |
6 | ||
7 | reg clk_; | |
8 | ||
9 | integer old_time; | |
10 | integer count; | |
11 | ||
12 | always @(clk_) | |
13 | clk = #1 clk_; | |
14 | ||
15 | integer period, first_half, second_half; | |
16 | initial begin | |
17 | period = 10000; | |
18 | first_half = 5000; | |
19 | second_half = 5000; | |
20 | end | |
21 | ||
22 | initial clk_ = 0; | |
23 | initial count = 0; | |
24 | ||
25 | always @(posedge clk_) begin | |
26 | clk_ = #first_half ~clk_; | |
27 | end | |
28 | ||
29 | always @(negedge clk_) begin | |
30 | if(count == 2) | |
31 | clk_ = #second_half ~clk_; | |
32 | end | |
33 | ||
34 | always @(period) begin | |
35 | first_half = period / 2; | |
36 | second_half = period - first_half; | |
37 | end | |
38 | ||
39 | always @(posedge refclk) begin | |
40 | if(count < 2) count = count + 1; | |
41 | if(count == 2) begin | |
42 | period = ($time - old_time) / 10; | |
43 | clk_ = 1; | |
44 | end | |
45 | old_time = $time; | |
46 | end | |
47 | ||
48 | endmodule | |
49 | ||
50 | ||
51 | module xaui_port ( | |
52 | XAUI_RX_N, | |
53 | XAUI_RX_P, | |
54 | xaui_clk, | |
55 | mac_clk, | |
56 | reset, | |
57 | XAUI_AMUX, | |
58 | XAUI_TX_N, | |
59 | XAUI_TX_P, | |
60 | esr_mac_rxd0, | |
61 | esr_mac_rxd1, | |
62 | esr_mac_rxd2, | |
63 | esr_mac_rxd3, | |
64 | mac_esr_txd0, | |
65 | mac_esr_txd1, | |
66 | mac_esr_txd2, | |
67 | mac_esr_txd3); | |
68 | ||
69 | input [3:0] XAUI_RX_N; | |
70 | input [3:0] XAUI_RX_P; | |
71 | ||
72 | input xaui_clk; | |
73 | input mac_clk; | |
74 | input reset; | |
75 | ||
76 | output XAUI_AMUX; | |
77 | output [3:0] XAUI_TX_N; | |
78 | output [3:0] XAUI_TX_P; | |
79 | ||
80 | output [9:0] esr_mac_rxd0; | |
81 | output [9:0] esr_mac_rxd1; | |
82 | output [9:0] esr_mac_rxd2; | |
83 | output [9:0] esr_mac_rxd3; | |
84 | ||
85 | input [9:0] mac_esr_txd0; | |
86 | input [9:0] mac_esr_txd1; | |
87 | input [9:0] mac_esr_txd2; | |
88 | input [9:0] mac_esr_txd3; | |
89 | ||
90 | ||
91 | reg XAUI_AMUX; | |
92 | reg [3:0] XAUI_TX_N; | |
93 | reg [3:0] XAUI_TX_P; | |
94 | ||
95 | reg [9:0] esr_mac_rxd0; | |
96 | reg [9:0] esr_mac_rxd1; | |
97 | reg [9:0] esr_mac_rxd2; | |
98 | reg [9:0] esr_mac_rxd3; | |
99 | ||
100 | reg [6:0] xaui_comma0; | |
101 | reg [6:0] xaui_comma1; | |
102 | reg [6:0] xaui_comma2; | |
103 | reg [6:0] xaui_comma3; | |
104 | ||
105 | reg [3:0] xaui_count0, xaui_count1, xaui_count2, xaui_count3; | |
106 | reg [3:0] xaui_serdes_count; | |
107 | ||
108 | reg [9:0] mac_esr_tx0, mac_esr_tx1, mac_esr_tx2, mac_esr_tx3; | |
109 | reg [9:0] esr_mac_rx_l0, esr_mac_rx_l1, esr_mac_rx_l2, esr_mac_rx_l3; | |
110 | reg [9:0] esr_mac_rx0, esr_mac_rx1, esr_mac_rx2, esr_mac_rx3; | |
111 | reg reset_sync; | |
112 | ||
113 | wire [3:0] tx; | |
114 | ||
115 | initial begin | |
116 | xaui_count0 = 0; | |
117 | xaui_count1 = 0; | |
118 | xaui_count2 = 0; | |
119 | xaui_count3 = 0; | |
120 | end | |
121 | ||
122 | always @(posedge mac_clk) begin | |
123 | mac_esr_tx0 <= mac_esr_txd0; | |
124 | mac_esr_tx1 <= mac_esr_txd1; | |
125 | mac_esr_tx2 <= mac_esr_txd2; | |
126 | mac_esr_tx3 <= mac_esr_txd3; | |
127 | reset_sync <= reset; | |
128 | end | |
129 | ||
130 | always @(posedge mac_clk) begin | |
131 | esr_mac_rxd0 <= esr_mac_rx_l0; | |
132 | esr_mac_rxd1 <= esr_mac_rx_l1; | |
133 | esr_mac_rxd2 <= esr_mac_rx_l2; | |
134 | esr_mac_rxd3 <= esr_mac_rx_l3; | |
135 | end | |
136 | ||
137 | assign tx[0] = mac_esr_tx0[9 - xaui_serdes_count]; | |
138 | assign tx[1] = mac_esr_tx1[9 - xaui_serdes_count]; | |
139 | assign tx[2] = mac_esr_tx2[9 - xaui_serdes_count]; | |
140 | assign tx[3] = mac_esr_tx3[9 - xaui_serdes_count]; | |
141 | ||
142 | always @(posedge xaui_clk) begin | |
143 | XAUI_AMUX <= 1'b0; | |
144 | if(reset_sync) begin | |
145 | XAUI_TX_P <= 4'b0000; | |
146 | XAUI_TX_N <= 4'b1111; | |
147 | xaui_serdes_count = 0; | |
148 | end else begin | |
149 | XAUI_TX_P <= tx; | |
150 | XAUI_TX_N <= ~tx; | |
151 | xaui_serdes_count <= (xaui_serdes_count + 1) % 10; | |
152 | end | |
153 | end | |
154 | ||
155 | ||
156 | always @(negedge xaui_clk) begin | |
157 | if(reset_sync) begin | |
158 | xaui_comma0 <= 7'b0; | |
159 | xaui_comma1 <= 7'b0; | |
160 | xaui_comma2 <= 7'b0; | |
161 | xaui_comma3 <= 7'b0; | |
162 | xaui_count0 <= 0; | |
163 | xaui_count1 <= 0; | |
164 | xaui_count2 <= 0; | |
165 | xaui_count3 <= 0; | |
166 | end else begin | |
167 | ||
168 | xaui_comma0[6:0] <= {xaui_comma0[5:0], XAUI_RX_P[0]}; | |
169 | xaui_comma1[6:0] <= {xaui_comma1[5:0], XAUI_RX_P[1]}; | |
170 | xaui_comma2[6:0] <= {xaui_comma2[5:0], XAUI_RX_P[2]}; | |
171 | xaui_comma3[6:0] <= {xaui_comma3[5:0], XAUI_RX_P[3]}; | |
172 | ||
173 | esr_mac_rx0[9 - xaui_count0] <= XAUI_RX_P[0]; | |
174 | esr_mac_rx1[9 - xaui_count1] <= XAUI_RX_P[1]; | |
175 | esr_mac_rx2[9 - xaui_count2] <= XAUI_RX_P[2]; | |
176 | esr_mac_rx3[9 - xaui_count3] <= XAUI_RX_P[3]; | |
177 | ||
178 | if(xaui_count0 == 9) esr_mac_rx_l0 <= {esr_mac_rx0[9:1],XAUI_RX_P[0]}; | |
179 | if(xaui_count1 == 9) esr_mac_rx_l1 <= {esr_mac_rx1[9:1],XAUI_RX_P[1]}; | |
180 | if(xaui_count2 == 9) esr_mac_rx_l2 <= {esr_mac_rx2[9:1],XAUI_RX_P[2]}; | |
181 | if(xaui_count3 == 9) esr_mac_rx_l3 <= {esr_mac_rx3[9:1],XAUI_RX_P[3]}; | |
182 | ||
183 | if(xaui_comma0 == 7'b0011111) begin | |
184 | xaui_count0 <= 8; | |
185 | end else begin | |
186 | xaui_count0 <= (xaui_count0 + 1) % 10; | |
187 | end | |
188 | if(xaui_comma1 == 7'b0011111) begin | |
189 | xaui_count1 <= 8; | |
190 | end else begin | |
191 | xaui_count1 <= (xaui_count1 + 1) % 10; | |
192 | end | |
193 | if(xaui_comma2 == 7'b0011111) begin | |
194 | xaui_count2 <= 8; | |
195 | end else begin | |
196 | xaui_count2 <= (xaui_count2 + 1) % 10; | |
197 | end | |
198 | if(xaui_comma3 == 7'b0011111) begin | |
199 | xaui_count3 <= 8; | |
200 | end else begin | |
201 | xaui_count3 <= (xaui_count3 + 1) % 10; | |
202 | end | |
203 | end | |
204 | end | |
205 | ||
206 | endmodule | |
207 |