Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: xgmii_if.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `timescale 1ps/1ps | |
36 | module xgmii_if ( rxd, | |
37 | rxdv, | |
38 | rx_clk, | |
39 | rx_clk_xgmii, | |
40 | rxd_xgmii, | |
41 | rxctrl_xgmii, | |
42 | txd_xgmii, | |
43 | txctrl_xgmii, | |
44 | tx_clk, | |
45 | tx_clk_xgmii, | |
46 | txd, | |
47 | txen | |
48 | ); | |
49 | ||
50 | input [7:0] rxd; | |
51 | input rxdv; | |
52 | ||
53 | input rx_clk; | |
54 | ||
55 | input [31:0] txd_xgmii; | |
56 | input [3:0] txctrl_xgmii; | |
57 | ||
58 | input tx_clk; | |
59 | ||
60 | output rx_clk_xgmii; | |
61 | output [31:0] rxd_xgmii; | |
62 | output [3:0] rxctrl_xgmii; | |
63 | ||
64 | output tx_clk_xgmii; | |
65 | output [7:0] txd; | |
66 | output txen; | |
67 | ||
68 | reg [31:0] rxd_int; | |
69 | reg [31:0] rxd_xgmii_reg; | |
70 | reg [31:0] rxd_xgmii_int; | |
71 | ||
72 | ||
73 | reg[3:0] rx_ctrl_int; | |
74 | reg[3:0] rx_ctrl_xgmii_reg; | |
75 | reg[3:0] rx_ctrl_xgmii_int; | |
76 | ||
77 | reg rx_clk_xgmii_int; | |
78 | reg tx_clk_xgmii_int; | |
79 | ||
80 | wire rx_clk_int; | |
81 | wire rx_clk_xgmii_reg; | |
82 | ||
83 | wire FB_DETECT; | |
84 | ||
85 | ||
86 | reg tx_clk_int; | |
87 | ||
88 | reg [31:0] txd_xgmii_d; | |
89 | reg [3:0] txctrl_xgmii_d; | |
90 | reg [31:0] txd_xgmii_d1; | |
91 | reg [3:0] txctrl_xgmii_d1; | |
92 | ||
93 | parameter term_cnttx =3; | |
94 | parameter term_cntrx =3; | |
95 | ||
96 | reg [3:0] cntrx; | |
97 | ||
98 | reg [3:0] cnttx; | |
99 | ||
100 | reg [7:0] txd; | |
101 | reg txen; | |
102 | reg trig; | |
103 | reg trig1; | |
104 | ||
105 | reg [7:0] rxd_d; | |
106 | reg rxdv_d; | |
107 | reg [7:0] rxd_d1; | |
108 | reg rxdv_d1; | |
109 | ||
110 | reg reset_cnttx; | |
111 | reg reset_cnttx_d; | |
112 | reg reset_cntrx; | |
113 | reg reset_cntrx_d; | |
114 | reg start_cnt; | |
115 | ||
116 | initial | |
117 | begin | |
118 | rx_clk_xgmii_int = 1'b1; | |
119 | tx_clk_xgmii_int = 1'b0; | |
120 | cntrx = 4'b0001; | |
121 | cnttx = 4'b0001; | |
122 | rxd_int = 32'h0000_0000; | |
123 | rxd_xgmii_int = 32'h0000_0000; | |
124 | rx_ctrl_xgmii_int = 4'hF; | |
125 | rx_ctrl_int = 4'hF; | |
126 | reset_cntrx = 0; | |
127 | reset_cntrx_d = 0; | |
128 | start_cnt=0; | |
129 | end | |
130 | ||
131 | assign tx_clk_xgmii = tx_clk_int; | |
132 | assign #300 rx_clk_int = rx_clk; | |
133 | assign #150 rx_clk_xgmii = rx_clk_xgmii_int; | |
134 | assign #170 rx_clk_xgmii_reg = rx_clk_xgmii_int; | |
135 | ||
136 | assign #0.0 rxd_xgmii = rxd_xgmii_reg; | |
137 | assign #0.0 rxctrl_xgmii = rx_ctrl_xgmii_reg; | |
138 | ||
139 | always #400 rx_clk_xgmii_int = ~rx_clk_xgmii_int; | |
140 | always #400 tx_clk_xgmii_int = ~tx_clk_xgmii_int; | |
141 | ||
142 | always @(posedge rx_clk) | |
143 | begin | |
144 | if (FB_DETECT) | |
145 | start_cnt <= 1'b1; | |
146 | else | |
147 | start_cnt <= start_cnt; | |
148 | end | |
149 | ||
150 | always @(posedge rx_clk ) | |
151 | begin | |
152 | if((FB_DETECT) && (start_cnt==0)) | |
153 | cnttx[3:0] <= 4'b1000; | |
154 | else | |
155 | cnttx[3:0] <= {cnttx[2:0],cnttx[3]}; | |
156 | //else | |
157 | // cnttx[3:0] <= cnttx[3:0]; | |
158 | end | |
159 | ||
160 | always @(posedge rx_clk_xgmii_reg) | |
161 | begin | |
162 | rxd_xgmii_reg <= rxd_xgmii_int; | |
163 | rx_ctrl_xgmii_reg <= rx_ctrl_xgmii_int; | |
164 | end | |
165 | ||
166 | always @ (posedge rx_clk ) | |
167 | begin | |
168 | rxd_d <= rxd; | |
169 | rxdv_d <= rxdv; | |
170 | rxd_d1 <= rxd_d; | |
171 | rxdv_d1 <= rxdv_d; | |
172 | end | |
173 | ||
174 | assign FB_DETECT = (rxd == 8'hFB)? 1'b1:1'b0; | |
175 | ||
176 | always @ (posedge rx_clk ) | |
177 | begin | |
178 | case (cnttx) | |
179 | 4'b0001 : | |
180 | begin | |
181 | rxd_int[7:0] <= rxd_d1; | |
182 | rx_ctrl_int[0] <= rxdv_d1; | |
183 | end | |
184 | 4'b0010 : | |
185 | begin | |
186 | rxd_int[15:8] <= rxd_d1; | |
187 | rx_ctrl_int[1] <= rxdv_d1; | |
188 | end | |
189 | 4'b0100 : | |
190 | begin | |
191 | rxd_int[23:16] <= rxd_d1; | |
192 | rx_ctrl_int[2] <= rxdv_d1; | |
193 | end | |
194 | 4'b1000 : | |
195 | begin | |
196 | rxd_int[31:24] <= rxd_d1; | |
197 | rx_ctrl_int[3] <= rxdv_d1; | |
198 | end | |
199 | endcase | |
200 | ||
201 | if(cnttx== 4'b0001) begin | |
202 | rxd_xgmii_int <= rxd_int; | |
203 | rx_ctrl_xgmii_int <= rx_ctrl_int; | |
204 | ||
205 | end | |
206 | ||
207 | end | |
208 | ||
209 | /*----------------------------------------------------------------------- */ | |
210 | ||
211 | always@(tx_clk) | |
212 | #1 tx_clk_int = tx_clk; | |
213 | ||
214 | reg [1:0] cur_state; | |
215 | reg [1:0] nxt_state; | |
216 | reg trig2; | |
217 | ||
218 | parameter | |
219 | SFD = 2'b00, | |
220 | CNT1 = 2'b01, | |
221 | CNT2 = 2'b10, | |
222 | CNT3 = 2'b11; | |
223 | ||
224 | ||
225 | always @(cur_state or trig1) | |
226 | begin | |
227 | trig2 =1'b0; | |
228 | case(cur_state) | |
229 | SFD: | |
230 | if (trig1 ==1'b1) | |
231 | begin | |
232 | trig2 =1'b1; | |
233 | nxt_state = CNT1; | |
234 | end | |
235 | CNT1: | |
236 | begin | |
237 | trig2 =1'b0; | |
238 | nxt_state = CNT2; | |
239 | end | |
240 | CNT2: | |
241 | begin | |
242 | trig2 =1'b0; | |
243 | nxt_state = CNT3; | |
244 | end | |
245 | CNT3: | |
246 | begin | |
247 | trig2 =1'b0; | |
248 | nxt_state = SFD; | |
249 | end | |
250 | default: nxt_state = SFD; | |
251 | ||
252 | endcase | |
253 | end | |
254 | ||
255 | always @(posedge tx_clk) | |
256 | cur_state <= nxt_state; | |
257 | ||
258 | always @(posedge tx_clk) | |
259 | begin | |
260 | if ( (txd_xgmii == 32'h5555_55FB) && (txctrl_xgmii == 1'h1) ) | |
261 | begin | |
262 | trig1 = 1; | |
263 | #700 trig1 = 0; | |
264 | end | |
265 | else | |
266 | trig1 = 0; | |
267 | end | |
268 | ||
269 | always @(posedge tx_clk ) | |
270 | begin | |
271 | txctrl_xgmii_d <= txctrl_xgmii; | |
272 | txctrl_xgmii_d1 <= txctrl_xgmii_d; | |
273 | txd_xgmii_d <= txd_xgmii; | |
274 | txd_xgmii_d1 <= txd_xgmii_d; | |
275 | ||
276 | end | |
277 | always @(posedge tx_clk ) | |
278 | begin | |
279 | reset_cntrx <= (txd_xgmii == 32'h5555_55FB) && (txctrl_xgmii == 1'h1); | |
280 | reset_cntrx_d <= reset_cntrx; | |
281 | if(reset_cntrx &~ reset_cntrx_d) | |
282 | cntrx[3:0] <= 4'h1; | |
283 | else | |
284 | cntrx[3:0] <= {cntrx[2:0],cntrx[3]}; | |
285 | end | |
286 | always @(posedge tx_clk ) | |
287 | begin | |
288 | case(cntrx) | |
289 | 4'b0001: begin txd <= txd_xgmii_d1[7:0]; txen <= txctrl_xgmii_d1[0]; end | |
290 | 4'b0010: begin txd <= txd_xgmii_d1[15:8]; txen <= txctrl_xgmii_d1[1]; end | |
291 | 4'b0100: begin txd <= txd_xgmii_d1[23:16]; txen <= txctrl_xgmii_d1[2]; end | |
292 | 4'b1000: begin txd <= txd_xgmii_d1[31:24]; txen <= txctrl_xgmii_d1[3]; end | |
293 | ||
294 | endcase | |
295 | end | |
296 | ||
297 | endmodule | |
298 |