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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / model / verilog / niu / niu_enet_models / xgmii_rx_decoder.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: xgmii_rx_decoder.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module xgmii_rx_decoder (
36 rx_clk,
37 rst,
38
39 rx_10bdec_in,
40
41 rx_8bdec_out,
42 special);
43
44input rx_clk; // rx clk, 250 MHz
45input rst; // synchronous active low reset
46
47input [9:0] rx_10bdec_in; // receive encoded 10 bit data
48
49output [7:0] rx_8bdec_out; // decoded data byte
50output special; // decoded special characters & errors
51
52
53wire [9:0] rx_10bdec_int; // receive encoded 10 bit data
54
55
56//reg special; // running disparity register
57
58reg RDreg; // running disparity register
59wire noneof6,
60 oneof6,
61 twoof6,
62 threeof6,
63 fourof6,
64 fiveof6,
65 sixof6; //no. of 1#s in data[9:4]
66wire noneof4,
67 oneof4,
68 twoof4,
69 threeof4,
70 fourof4; //no. of 1#s in data[3:0]
71wire control;
72wire pos_disp, RD, newRD; // running disparity signals
73reg [7:0] deco1_fcn;
74reg [4:0] deco2_fcn;
75
76// decode data
77
78assign rx_10bdec_int[9:0] = {rx_10bdec_in[0],rx_10bdec_in[1], rx_10bdec_in[2],
79 rx_10bdec_in[3],rx_10bdec_in[4], rx_10bdec_in[5],
80 rx_10bdec_in[6],rx_10bdec_in[7], rx_10bdec_in[8],
81 rx_10bdec_in[9]};
82
83assign rx_8bdec_out = {deco2_fcn[4:2],deco1_fcn[7:3]};
84assign special = deco1_fcn[0];
85
86// Register to hold running disparity
87
88always @ (posedge rx_clk)
89 if (rst)
90 RDreg <= 1'b0;
91 else
92 RDreg <= pos_disp;
93
94// Running disparity calculator
95
96assign noneof4 = ~(rx_10bdec_int[0] | rx_10bdec_int[1] | rx_10bdec_int[2] | rx_10bdec_int[3]);
97
98assign fourof4 = (rx_10bdec_int[0] & rx_10bdec_int[1] & rx_10bdec_int[2] & rx_10bdec_int[3]);
99
100assign threeof4 = ((rx_10bdec_int[0]^rx_10bdec_int[1]) & (~(rx_10bdec_int[2]^rx_10bdec_int[3]) &
101 (rx_10bdec_int[2]&rx_10bdec_int[3]))) | ((rx_10bdec_int[2]^rx_10bdec_int[3]) &
102 (~(rx_10bdec_int[0]^rx_10bdec_int[1]) & (rx_10bdec_int[0]&rx_10bdec_int[1])));
103
104assign oneof4 = ((~rx_10bdec_int[0]^~rx_10bdec_int[1]) & (~(~rx_10bdec_int[2]^~rx_10bdec_int[3]) &
105 (~rx_10bdec_int[2]&~rx_10bdec_int[3]))) | ((~rx_10bdec_int[2]^~rx_10bdec_int[3]) &
106 (~(~rx_10bdec_int[0]^~rx_10bdec_int[1]) & (~rx_10bdec_int[0]&~rx_10bdec_int[1])));
107
108assign twoof4 = ((rx_10bdec_int[0]^rx_10bdec_int[1]) & (rx_10bdec_int[2]^rx_10bdec_int[3])) | ((rx_10bdec_int[0]&rx_10bdec_int[1]) ^ (rx_10bdec_int[2]&rx_10bdec_int[3]));
109
110assign noneof6 = ~(rx_10bdec_int[4] | rx_10bdec_int[5] | rx_10bdec_int[6] | rx_10bdec_int[7] | rx_10bdec_int[8] | rx_10bdec_int[9]);
111
112assign sixof6 = (rx_10bdec_int[4] & rx_10bdec_int[5] & rx_10bdec_int[6] & rx_10bdec_int[7] & rx_10bdec_int[8] & rx_10bdec_int[9]);
113
114assign fiveof6 = ( (((rx_10bdec_int[4]^rx_10bdec_int[5]) & (~(rx_10bdec_int[6]^rx_10bdec_int[7]) &
115 (rx_10bdec_int[6]&rx_10bdec_int[7]))) | ((rx_10bdec_int[6]^rx_10bdec_int[7]) &
116 (~(rx_10bdec_int[4]^rx_10bdec_int[5]) & (rx_10bdec_int[4]&rx_10bdec_int[5])))) &
117 (rx_10bdec_int[8] & rx_10bdec_int[9]) ) | ((rx_10bdec_int[4] & rx_10bdec_int[5] &
118 rx_10bdec_int[6] & rx_10bdec_int[7]) & (rx_10bdec_int[8] ^ rx_10bdec_int[9]));
119
120assign oneof6 = ( (((~rx_10bdec_int[4]^~rx_10bdec_int[5]) & (~(~rx_10bdec_int[6]^~rx_10bdec_int[7]) &
121 (~rx_10bdec_int[6]&~rx_10bdec_int[7]))) | ((~rx_10bdec_int[6]^~rx_10bdec_int[7]) &
122 (~(~rx_10bdec_int[4]^~rx_10bdec_int[5]) & (~rx_10bdec_int[4]&~rx_10bdec_int[5])))) &
123 (~rx_10bdec_int[8] & ~rx_10bdec_int[9]) ) |
124 ((~rx_10bdec_int[4] & ~rx_10bdec_int[5] & ~rx_10bdec_int[6] & ~rx_10bdec_int[7]) & (~rx_10bdec_int[8] ^ ~rx_10bdec_int[9]));
125
126assign fourof6 = ( (((rx_10bdec_int[4]^rx_10bdec_int[5]) & (rx_10bdec_int[6]^rx_10bdec_int[7])) |
127 ((rx_10bdec_int[4]&rx_10bdec_int[5]) ^ (rx_10bdec_int[6]&rx_10bdec_int[7]))) &
128 (rx_10bdec_int[8] & rx_10bdec_int[9]) ) | ( (((rx_10bdec_int[4]^rx_10bdec_int[5]) &
129 (~(rx_10bdec_int[6]^rx_10bdec_int[7]) & (rx_10bdec_int[6]&rx_10bdec_int[7]))) |
130 ((rx_10bdec_int[6]^rx_10bdec_int[7]) & (~(rx_10bdec_int[4]^rx_10bdec_int[5]) &
131 (rx_10bdec_int[4]&rx_10bdec_int[5])))) & (rx_10bdec_int[8] ^ rx_10bdec_int[9]) ) |
132 ( (rx_10bdec_int[4] & rx_10bdec_int[5] & rx_10bdec_int[6] & rx_10bdec_int[7]) &
133 (~(rx_10bdec_int[8]|rx_10bdec_int[9])) );
134
135assign twoof6 = ( (((~rx_10bdec_int[4]^~rx_10bdec_int[5]) & (~rx_10bdec_int[6]^~rx_10bdec_int[7])) |
136 ((~rx_10bdec_int[4]&~rx_10bdec_int[5]) ^ (~rx_10bdec_int[6]&~rx_10bdec_int[7]))) &
137 (~rx_10bdec_int[8] & ~rx_10bdec_int[9]) ) | ( (((~rx_10bdec_int[4]^~rx_10bdec_int[5]) &
138 (~(~rx_10bdec_int[6]^~rx_10bdec_int[7]) & (~rx_10bdec_int[6]&~rx_10bdec_int[7])))
139 | ((~rx_10bdec_int[6]^~rx_10bdec_int[7]) & (~(~rx_10bdec_int[4]^~rx_10bdec_int[5]) &
140 (~rx_10bdec_int[4]&~rx_10bdec_int[5])))) & (~rx_10bdec_int[8] ^ ~rx_10bdec_int[9]) ) |
141 ( (~rx_10bdec_int[4] & ~rx_10bdec_int[5] & ~rx_10bdec_int[6] & ~rx_10bdec_int[7]) &
142 (~(~rx_10bdec_int[8]|~rx_10bdec_int[9])) );
143
144assign threeof6 = ( (((~rx_10bdec_int[4]^~rx_10bdec_int[5]) & (~(~rx_10bdec_int[6]^~rx_10bdec_int[7]) &
145 (~rx_10bdec_int[6]&~rx_10bdec_int[7]))) | ((~rx_10bdec_int[6]^~rx_10bdec_int[7]) &
146 (~(~rx_10bdec_int[4]^~rx_10bdec_int[5]) & (~rx_10bdec_int[4]&~rx_10bdec_int[5])))) &
147 (rx_10bdec_int[8] & rx_10bdec_int[9]) ) | ( (((rx_10bdec_int[4]^rx_10bdec_int[5]) &
148 (rx_10bdec_int[6]^rx_10bdec_int[7])) |
149 ((rx_10bdec_int[4]&rx_10bdec_int[5]) ^ (rx_10bdec_int[6]&rx_10bdec_int[7]))) &
150 (rx_10bdec_int[8] ^ rx_10bdec_int[9]) ) | ( (((rx_10bdec_int[4]^rx_10bdec_int[5]) &
151 (~(rx_10bdec_int[6]^rx_10bdec_int[7]) & (rx_10bdec_int[6]&rx_10bdec_int[7])))
152 | ((rx_10bdec_int[6]^rx_10bdec_int[7]) & (~(rx_10bdec_int[4]^rx_10bdec_int[5]) &
153 (rx_10bdec_int[6]&rx_10bdec_int[7])))) & ( ~(rx_10bdec_int[8] | rx_10bdec_int[9])) );
154
155assign newRD = ((noneof6 | oneof6 | twoof6) |
156 (threeof6 & (rx_10bdec_int[9:4]==6'b111000))) ? 1'b0 :
157 ((fourof6 | fiveof6 | sixof6) | (threeof6 &
158 (rx_10bdec_int[9:4]==6'b000111))) ? 1'b1 : RDreg;
159
160assign pos_disp = ((noneof4 | oneof4) | (twoof4 &
161 (rx_10bdec_int[3:0]==4'b1100))) ? 1'b0 : ((threeof4 | fourof4)
162 | (twoof4 & (rx_10bdec_int[3:0]==4'b0011))) ? 1'b1 : newRD;
163
164// 6b5b decode on most significant bits of rx_10bdata
165// ~RDreg means that you can only get this code if the beginning
166// running disparity is one. So if zero, error is flagged.
167// RDreg means that you can only get this code if the beginning
168// running disparity is zero. So if one, error is flagged.
169// 1'b0 means that this code can be received whether the
170// running disparity is zero or one. So no check is done.
171//
172// The function output is:
173// deco1_fcn = {decodata[4:0], dec_err1, rderr, Kchar}
174
175always @ (rx_10bdec_int or RDreg)
176 case (rx_10bdec_int[9:4]) //####synopsys parallel_case full_case
177 /* D0 + */ 6'b011000: deco1_fcn = {5'b00000, 1'b0, !RDreg, 1'b0};
178 /* D0 - */ 6'b100111: deco1_fcn = {5'b00000, 1'b0, RDreg, 1'b0};
179 /* D1 + */ 6'b100010: deco1_fcn = {5'b00001, 1'b0, !RDreg, 1'b0};
180 /* D1 - */ 6'b011101: deco1_fcn = {5'b00001, 1'b0, RDreg, 1'b0};
181 /* D2 + */ 6'b010010: deco1_fcn = {5'b00010, 1'b0, !RDreg, 1'b0};
182 /* D2 - */ 6'b101101: deco1_fcn = {5'b00010, 1'b0, RDreg, 1'b0};
183 /* D3 0 */ 6'b110001: deco1_fcn = {5'b00011, 1'b0, 1'b0, 1'b0};
184 /* D4 + */ 6'b001010: deco1_fcn = {5'b00100, 1'b0, !RDreg, 1'b0};
185 /* D4 - */ 6'b110101: deco1_fcn = {5'b00100, 1'b0, RDreg, 1'b0};
186 /* D5 0 */ 6'b101001: deco1_fcn = {5'b00101, 1'b0, 1'b0, 1'b0};
187 /* D6 0 */ 6'b011001: deco1_fcn = {5'b00110, 1'b0, 1'b0, 1'b0};
188 /* D7 + */ 6'b000111: deco1_fcn = {5'b00111, 1'b0, !RDreg, 1'b0};
189 /* D7 - */ 6'b111000: deco1_fcn = {5'b00111, 1'b0, RDreg, 1'b0};
190 /* D8 + */ 6'b000110: deco1_fcn = {5'b01000, 1'b0, !RDreg, 1'b0};
191 /* D8 - */ 6'b111001: deco1_fcn = {5'b01000, 1'b0, RDreg, 1'b0};
192 /* D9 0 */ 6'b100101: deco1_fcn = {5'b01001, 1'b0, 1'b0, 1'b0};
193 /* D10 0 */ 6'b010101: deco1_fcn = {5'b01010, 1'b0, 1'b0, 1'b0};
194 /* D11 0 */ 6'b110100: deco1_fcn = {5'b01011, 1'b0, 1'b0, 1'b0};
195 /* D12 0 */ 6'b001101: deco1_fcn = {5'b01100, 1'b0, 1'b0, 1'b0};
196 /* D13 0 */ 6'b101100: deco1_fcn = {5'b01101, 1'b0, 1'b0, 1'b0};
197 /* D14 0 */ 6'b011100: deco1_fcn = {5'b01110, 1'b0, 1'b0, 1'b0};
198 /* D15 + */ 6'b101000: deco1_fcn = {5'b01111, 1'b0, !RDreg, 1'b0};
199 /* D15 - */ 6'b010111: deco1_fcn = {5'b01111, 1'b0, RDreg, 1'b0};
200 /* D16 + */ 6'b100100: deco1_fcn = {5'b10000, 1'b0, !RDreg, 1'b0};
201 /* D16 - */ 6'b011011: deco1_fcn = {5'b10000, 1'b0, RDreg, 1'b0};
202 /* D17 0 */ 6'b100011: deco1_fcn = {5'b10001, 1'b0, 1'b0, 1'b0};
203 /* D18 0 */ 6'b010011: deco1_fcn = {5'b10010, 1'b0, 1'b0, 1'b0};
204 /* D19 0 */ 6'b110010: deco1_fcn = {5'b10011, 1'b0, 1'b0, 1'b0};
205 /* D20 0 */ 6'b001011: deco1_fcn = {5'b10100, 1'b0, 1'b0, 1'b0};
206 /* D21 0 */ 6'b101010: deco1_fcn = {5'b10101, 1'b0, 1'b0, 1'b0};
207 /* D22 0 */ 6'b011010: deco1_fcn = {5'b10110, 1'b0, 1'b0, 1'b0};
208 /* D23 + */ 6'b000101: deco1_fcn = {5'b10111, 1'b0, !RDreg, (rx_10bdec_int[3:0]==4'b0111)};
209 /* D23 - */ 6'b111010: deco1_fcn = {5'b10111, 1'b0, RDreg, (rx_10bdec_int[3:0]==4'b1000)};
210 /* D24 + */ 6'b001100: deco1_fcn = {5'b11000, 1'b0, !RDreg, 1'b0};
211 /* D24 - */ 6'b110011: deco1_fcn = {5'b11000, 1'b0, RDreg, 1'b0};
212 /* D25 0 */ 6'b100110: deco1_fcn = {5'b11001, 1'b0, 1'b0, 1'b0};
213 /* D26 0 */ 6'b010110: deco1_fcn = {5'b11010, 1'b0, 1'b0, 1'b0};
214 /* D27 + */ 6'b001001: deco1_fcn = {5'b11011, 1'b0, !RDreg, (rx_10bdec_int[3:0]==4'b0111)};
215 /* D27 - */ 6'b110110: deco1_fcn = {5'b11011, 1'b0, RDreg, (rx_10bdec_int[3:0]==4'b1000)};
216 /* D28 0 */ 6'b001110: deco1_fcn = {5'b11100, 1'b0, 1'b0, 1'b0};
217 /* D29 + */ 6'b010001: deco1_fcn = {5'b11101, 1'b0, !RDreg, (rx_10bdec_int[3:0]==4'b0111)};
218 /* D29 - */ 6'b101110: deco1_fcn = {5'b11101, 1'b0, RDreg, (rx_10bdec_int[3:0]==4'b1000)};
219 /* D30 + */ 6'b100001: deco1_fcn = {5'b11110, 1'b0, !RDreg, (rx_10bdec_int[3:0]==4'b0111)};
220 /* D30 - */ 6'b011110: deco1_fcn = {5'b11110, 1'b0, RDreg, (rx_10bdec_int[3:0]==4'b1000)};
221 /* D31 + */ 6'b010100: deco1_fcn = {5'b11111, 1'b0, !RDreg, 1'b0};
222 /* D31 - */ 6'b101011: deco1_fcn = {5'b11111, 1'b0, RDreg, 1'b0};
223 /* K28 + */ 6'b110000: deco1_fcn = {5'b11100, 1'b0, !RDreg, 1'b1};
224 /* K28 - */ 6'b001111: deco1_fcn = {5'b11100, 1'b0, RDreg, 1'b1};
225 /* K27.7+*/ 6'b001001: deco1_fcn = {5'b11011, 1'b0, !RDreg, (rx_10bdec_int[3:0]==4'b0111) };
226 /* K27.7-*/ 6'b110110: deco1_fcn = {5'b11011, 1'b0, RDreg, (rx_10bdec_int[3:0]==1000) };
227 /* K29.7+*/ 6'b010001: deco1_fcn = {5'b11101, 1'b0, !RDreg, (rx_10bdec_int[3:0]==4'b0111) };
228 /* K29.7-*/ 6'b101110: deco1_fcn = {5'b11101, 1'b0, !RDreg, (rx_10bdec_int[3:0]==4'b1000) };
229 /* K30.7+*/ 6'b100001: deco1_fcn = {5'b11110, 1'b0, !RDreg, (rx_10bdec_int[3:0]==4'b0111) };
230 /* K30.7-*/ 6'b011110: deco1_fcn = {5'b11110, 1'b0, !RDreg, (rx_10bdec_int[3:0]==4'b1000) };
231 default: deco1_fcn = {5'b00000, 1'b1, 1'b0, 1'b0}; // dec_err1
232 endcase
233
234// 4b3b decode on least significant bits of rx_10bdata
235// deco2_fcn = {decodata[7:5], dec_err2, rderr2, }
236
237always @ (rx_10bdec_int or newRD or deco1_fcn[0])
238 case (rx_10bdec_int[3:0]) //####synopsys parallel_case full_case
239 /* Dx.0 + */ 4'b0100: deco2_fcn = {3'b000, 1'b0, !newRD};
240 /* Dx.0 - */ 4'b1011: deco2_fcn = {3'b000, 1'b0, newRD};
241 /* Dx.1 0 */ 4'b1001: deco2_fcn = {3'b001, deco1_fcn[0], 1'b0};
242 /* Dx.2 0 */ 4'b0101: deco2_fcn = {3'b010, 1'b0, 1'b0};
243 /* Dx.3 + */ 4'b0011: deco2_fcn = {3'b011, deco1_fcn[0], !newRD};
244 /* Dx.3 - */ 4'b1100: deco2_fcn = {3'b011, deco1_fcn[0], newRD};
245 /* Dx.4 + */ 4'b0010: deco2_fcn = {3'b100, deco1_fcn[0], !newRD};
246 /* Dx.4 - */ 4'b1101: deco2_fcn = {3'b100, deco1_fcn[0], newRD};
247 /* Dx.5 0 */ 4'b1010: deco2_fcn = {3'b101, 1'b0, 1'b0};
248 /* Dx.6 0 */ 4'b0110: deco2_fcn = {3'b110, deco1_fcn[0], 1'b0};
249 /* Dx.7 + */ 4'b0001: deco2_fcn = {3'b111, deco1_fcn[0], !newRD};
250 /* Dx.7 - */ 4'b1110: deco2_fcn = {3'b111, deco1_fcn[0], newRD};
251 /* Ax.7 + */ 4'b1000: deco2_fcn = {3'b111, (rx_10bdec_int[9:4]==6'b110000), !newRD};
252 /* Ax.7 - */ 4'b0111: deco2_fcn = {3'b111, (rx_10bdec_int[9:4]==6'b001111), newRD};
253 default: deco2_fcn = {3'b000, 1'b1, 1'b0}; // dec_err2
254 endcase
255
256// decode of special characters
257
258
259/***
260 assign control = ((rx_10bdec_int[9:0] == 10'b0011111010) |
261 (rx_10bdec_int[9:0] == 10'b1100000101) |
262 (rx_10bdec_int[9:0] == 10'b1101101000) |
263 (rx_10bdec_int[9:0] == 10'b0010010111) |
264 (rx_10bdec_int[9:0] == 10'b1011101000) |
265 (rx_10bdec_int[9:0] == 10'b0100010111) |
266 (rx_10bdec_int[9:0] == 10'b0111101000) |
267 (rx_10bdec_int[9:0] == 10'b1000010111) |
268 (rx_10bdec_int[9:0] == 10'b0011110010) |
269 (rx_10bdec_int[9:0] == 10'b1100001101) |
270 (rx_10bdec_int[9:0] == 10'b0011110011) |
271 (rx_10bdec_int[9:0] == 10'b1100001100));
272 ***/
273
274 //assign special = (rst|control) ? 1'b1:1'b0;
275
276
277/***
278always @(rx_10bdec_int )
279 begin
280 if ((rx_10bdec_int[9:0] == 10'b0011111010)) {
281 special = 1'b1;
282 } else{
283 special = 1'b0;
284 }
285 end
286
287always @(rx_10bdec_int or rst)
288begin
289
290
291 if ( (rst) || (rx_10bdec_int[9:0] == 10'b0011111010) || (rx_10bdec_int[9:0] == 10'b1100000101) || (rx_10bdec_int[9:0] == 10'b1101101000) || (rx_10bdec_int[9:0] == 10'b0010010111) || (rx_10bdec_int[9:0] == 10'b1011101000) || (rx_10bdec_int[9:0] == 10'b0100010111) || (rx_10bdec_int[9:0] == 10'b0111101000) || (rx_10bdec_int[9:0] == 10'b1000010111) || (rx_10bdec_int[9:0] == 10'b0011110010) || (rx_10bdec_int[9:0] == 10'b1100001101) || (rx_10bdec_int[9:0] == 10'b0011110011) || (rx_10bdec_int[9:0] == 10'b1100001100) ) {
292
293 special = 1'b1;
294}
295 else {
296 special = 1'b0;
297}
298 end
299 **/
300
301
302endmodule //
303
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